Electronic apparatus

Abstract

Provided is a novel electronic apparatus. This electronic apparatus has a housing, a display device, a computing unit, a line-of-sight detection unit, and a motion detection unit. The display device has a display element, a pixel circuit, a drive circuit, and a functional circuit. The motion detection unit has a function of detecting a motion of the housing. The line-of-sight detection unit has a function of detecting a gaze point corresponding to a line of sight to the display device. The computing unit has a function of performing drawing processing corresponding to the motion of the housing and a function of dividing a display part of the display device into a plurality of regions according to the gaze point. The pixel circuit has a function of controlling light emission of the display element. The drive circuit has a function of controlling the pixel circuit. The functional circuit has a function of controlling the drive circuit according to the plurality of regions. The display device has a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are respectively provided in different layers. The first layer has the drive circuit and the functional circuit. The second layer has the pixel circuit. The third layer has the display element.

Description

electronic equipment

[0001] 1. Field of the Invention One aspect of the present invention relates to an electronic device. 1. Field of the Invention One aspect of the present invention relates to a wearable electronic device including a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, head-mounted display (HMD) type electronic devices suitable for applications such as virtual reality (VR), augmented reality (AR), etc. HMDs are capable of displaying images in a 360-degree area around a user in response to the user's head movements, line of sight, or operations, allowing the user to experience a highly immersive and realistic experience.

[0004] An HMD is configured to enlarge an image displayed on a display device using optical components or the like, and the user views the enlarged image. In this case, there is a risk that the inclusion of optical components will increase the size of the housing, or that the user will be more likely to see the pixels and perceive them as grainy, so there is a demand for high-definition and / or miniaturized display devices. For example, Patent Document 1 discloses an HMD with fine pixels achieved by using transistors capable of high-speed operation.

[0005] Japanese Patent Application Laid-Open No. 2000-2856

[0006] HMD-type electronic devices require high rendering capabilities that respond to the user's head movements, line of sight, and operations. Driving a high-resolution, compact display device with a computation circuit with high rendering capabilities can result in increased power consumption. Furthermore, a computation circuit with high rendering capabilities requires a heat dissipation mechanism to cool the computation circuit, which can lead to an increase in the size of the electronic device.

[0007] Alternatively, in a configuration in which a functional circuit such as an application processor for driving a display device is provided in an area overlapping with the display unit, there is a risk that the drawing processing capability will be insufficient in the case of a display device that is designed to have high definition and be compact.

[0008] An object of one embodiment of the present invention is to provide an electronic device with reduced power consumption.An object of one embodiment of the present invention is to provide an electronic device with reduced size and weight.An object of one embodiment of the present invention is to provide an electronic device with excellent drawing processing capability.An object of one embodiment of the present invention is to provide a novel electronic device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0010] One embodiment of the present invention is an electronic device having a housing, a display device, an arithmetic unit, a line-of-sight detection unit, and a motion detection unit. The display device has a display element, a pixel circuit, a driver circuit, and a functional circuit. The motion detection unit has a function of detecting movement of the housing. The line-of-sight detection unit has a function of detecting a gaze point according to the line of sight toward the display device. The arithmetic unit has a function of performing drawing processing according to movement of the housing and a function of dividing the display unit into multiple regions according to the gaze point. The pixel circuit has a function of controlling light emission of the display element. The driver circuit has a function of controlling the pixel circuit. The functional circuit has a function of controlling the driver circuit according to the multiple regions.

[0011] One embodiment of the present invention is an electronic device including a housing, a display device, an arithmetic unit, a line-of-sight detection unit, and a motion detection unit. The display device includes a display element, a pixel circuit, a driver circuit, and a functional circuit. The motion detection unit has a function of detecting movement of the housing. The line-of-sight detection unit has a function of detecting a gaze point according to a line of sight toward the display device. The arithmetic unit has a function of performing drawing processing according to movement of the housing and a function of dividing a display unit of the display device into a plurality of regions according to the gaze point. The pixel circuit has a function of controlling light emission of the display element. The driver circuit has a function of controlling the pixel circuit. The functional circuit has a function of controlling the driver circuit according to the plurality of regions. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and a functional circuit. The second layer includes a pixel circuit. The third layer includes a display element.

[0012] In one embodiment of the present invention, the electronic device preferably includes a first transistor having a semiconductor layer including silicon in a channel formation region, and a second transistor having a semiconductor layer including metal oxide in a channel formation region.

[0013] In one embodiment of the present invention, the electronic device preferably has a metal oxide containing In, an element M (M is Al, Ga, Y, or Sn), and Zn.

[0014] In one embodiment of the present invention, the electronic device preferably includes an organic EL element as the display element, and the organic EL element is a display element formed by processing using a photolithography method.

[0015] In one aspect of the present invention, the electronic device preferably has a driving circuit including a gate driver circuit and a source driver circuit.

[0016] In one aspect of the present invention, the electronic device is preferably such that the display unit is divided into a plurality of sections, one of the sections has a source driver circuit and a gate driver circuit, the source driver circuit is electrically connected to a plurality of source lines, and the gate driver circuit is electrically connected to a plurality of gate lines.

[0017] In one aspect of the present invention, the electronic device is preferably such that the control of the drive circuit according to the plurality of regions in the functional circuit is a control that varies the drive frequency for each section.

[0018] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0019] One embodiment of the present invention can provide an electronic device with reduced power consumption, a smaller and lighter electronic device, an electronic device with excellent drawing processing capability, or a novel electronic device.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0021] FIGS. 1A and 1B are diagrams illustrating an example of the configuration of an electronic device. FIGS. 2A and 2B are diagrams illustrating an example of the configuration of an electronic device. FIGS. 3A and 3B are diagrams illustrating an example of the configuration of a display device. FIG. 4 is a diagram illustrating an example of the configuration of a display device. FIG. 5 is a diagram illustrating an example of the operation of an electronic device. FIGS. 6A and 6B are diagrams illustrating an example of the configuration of an electronic device. FIGS. 7A and 7B are diagrams illustrating an example of the configuration of an electronic device. FIGS. 8A and 8B are diagrams illustrating an example of the configuration of an electronic device. FIGS. 9A and 9B are diagrams illustrating an example of the configuration of a display device. FIGS. 10A to 10D are diagrams illustrating an example of the configuration of a display device. FIGS. 11A to 11D are diagrams illustrating an example of the configuration of a display device. FIG. 12 is a diagram illustrating a method of driving a display device. FIGS. 13A and 13B are diagrams illustrating an example of the configuration of a display device. FIGS. 14A and 14B are diagrams illustrating an example of the configuration of a display device. FIGS. 15A and 15B are diagrams illustrating an example of the configuration of a display device. FIGS. 16A and 16B are diagrams illustrating an example of the configuration of a display device. Fig. 17 is a diagram illustrating a configuration example of a display device. Fig. 18 is a diagram illustrating a configuration example of a display device. Figs. 19A to 19C are diagrams illustrating a configuration example of a display device. Fig. 20A is a diagram illustrating a classification of crystal structures. Fig. 20B is a diagram illustrating an XRD spectrum of a CAAC-IGZO film. Fig. 20C is a diagram illustrating a microelectron beam diffraction pattern of a CAAC-IGZO film. Figs. 21A to 21D are diagrams illustrating a configuration example of a display element. Figs. 22A to 22D are diagrams illustrating a configuration example of a display element. Figs. 23A and 23B are diagrams illustrating a configuration example of a display element.

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0023] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0024] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0025] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0026] Embodiment 1 In one embodiment of the present invention, an electronic device according to one embodiment of the present invention will be described. The electronic device according to one embodiment of the present invention can also be suitably used as a wearable electronic device for VR and AR applications.

[0027] 1A is a perspective view of an example of a wearable electronic device, namely, a glasses-type (goggle-type) electronic device 100. The electronic device 100 shown in FIG. 1A includes a pair of display devices 10_L and 10_R, a motion detection unit 101, a line-of-sight detection unit 102, a calculation unit 103, and a communication unit 104 in a housing 105.

[0028] Fig. 1B is a block diagram of the electronic device 100 of Fig. 1A. As in Fig. 1A, the electronic device 100 includes display devices 10_L and 10_R, a motion detection unit 101, a line-of-sight detection unit 102, a calculation unit 103, and a communication unit 104, which transmit and receive various signals to and from each other via bus wiring BW. Each of the display devices 10_L and 10_R includes a display element 61, a pixel circuit 51, a drive circuit 30, and a function circuit 40.

[0029] The motion detection unit 101 has a function of detecting the movement of the housing 105, i.e., the movement of the head of the user wearing the electronic device 100. The motion detection unit 101 may use, for example, a motion sensor using MEMS technology. The motion sensor may be a three-axis motion sensor or a six-axis motion sensor. Information regarding the movement of the housing 105 detected by the motion detection unit 101 may be referred to as first information, first data, motion data, or the like.

[0030] The gaze detection unit 102 has a function of detecting the direction of the user's gaze, determining which object in the image displayed on the display devices 10_L and 10_R the user is gazing at (at the gaze point). Information regarding the gaze point detected by the gaze detection unit 102 may be referred to as second information, second data, or gaze data. The second information may be acquired using a known gaze measurement (eye tracking) method. For example, the second information may be acquired using the Pupil Center Corneal Reflection method, the Bright / Dark Pupil Effect method, or the like. For example, the second information may be acquired using a measurement method using a laser or ultrasound.

[0031] The calculation unit 103 has a function of performing drawing processing in accordance with the movement of the housing 105. The drawing processing in accordance with the movement of the housing 105 in the calculation unit 103 is performed using the first information and 360-degree omnidirectional image data input from the outside via the communication unit 104. The 360-degree omnidirectional image data is data generated by an omnidirectional camera (omnidirectional camera, 360° camera) or computer graphics, etc. Specifically, the calculation unit 103 performs drawing processing on the 360-degree omnidirectional image data in accordance with the first information, and generates image data that can be displayed on the display devices 10_L and 10_R.

[0032] The calculation unit 103 also has a function of dividing the display unit of the display device 10_L, 10_R into multiple regions according to the gaze point. The calculation unit 103 has a function of determining the size and shape of the multiple regions (described later) based on information about the gaze direction. Specifically, the calculation unit 103 determines the gaze point according to the second information, and determines first to third regions, etc. on the display unit of the display device centered on the gaze point.

[0033] As the calculation unit 103, in addition to a central processing unit (CPU), other microprocessors such as a digital signal processor (DSP) and a graphics processing unit (GPU) can be used alone or in combination. Furthermore, these microprocessors may be realized by a programmable logic device (PLD) such as a field programmable gate array (FPGA) or a field programmable analog array (FPAA).

[0034] The arithmetic unit 103 performs various data processing or program control by interpreting and executing instructions from various programs using a processor. The programs that can be executed by the processor may be stored in a memory area of ​​the processor or in a separately provided storage unit. The storage unit may be, for example, a storage device that uses a non-volatile storage element such as a flash memory, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase change RAM), ReRAM (Resistive RAM), or FeRAM (Ferroelectric RAM), or a storage device that uses a volatile storage element such as a DRAM (Dynamic RAM) or SRAM (Static RAM).

[0035] The communication unit 104 has a function of communicating with external devices wirelessly or via a wired connection to acquire various data such as image data. The communication unit 104 may be provided with, for example, a high-frequency circuit (RF circuit) for transmitting and receiving RF signals. The high-frequency circuit is a circuit that converts between electromagnetic signals and electric signals in a frequency band defined by the laws of each country, and uses the electromagnetic signals to communicate wirelessly with other communication devices. When wireless communication is performed, communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), and WCDMA (Wideband Code Division Multiple Access: registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBee (registered trademark), can be used as communication protocols or communication technologies. It is also possible to use the third generation mobile communication system (3G), fourth generation mobile communication system (4G), or fifth generation mobile communication system (5G) defined by the International Telecommunication Union (ITU).

[0036] The communication unit 104 may also have external ports such as a terminal for connecting to a LAN (Local Area Network), a terminal for receiving digital broadcasts, and a terminal for connecting an AC adapter.

[0037] Each of display devices 10_L and 10_R has a display element 61, a pixel circuit 51, a drive circuit 30, and a functional circuit 40. Pixel circuit 51 has a function of controlling the light emission of display element 61. Drive circuit 30 has a function of controlling pixel circuit 51. Functional circuit 40 has a function of controlling drive circuit 30 in accordance with the sizes and shapes of multiple regions in the display unit of the display device, which are determined by calculation unit 103 from information related to the direction of the line of sight.

[0038] The information on the multiple regions of the display unit of the display device determined by the calculation unit 103 based on the information on the gaze direction is used to drive the display unit with different drive frequencies and / or different resolutions for each region. For example, the information is used when the functional circuit 40 controls the drive circuit 30 to drive the display unit with different drive frequencies for each region. The functional circuit 40 controls the drive circuit 30 to increase the drive frequency or provide high-resolution display in regions close to the gaze point, and to decrease the drive frequency or provide low-resolution display in regions farther from the gaze point. The electronic device 100 can reduce the power consumption required for display by suppressing the update frequency of image data far from the gaze point. This allows the electronic device 100 to achieve low power consumption.

[0039] The functional circuit 40 is provided integrally with the drive circuit 30. This allows the length of the wiring between the functional circuit 40 and the drive circuit 30 to be shortened, and reduces the charging and discharging of the wiring that provides the control signal for the functional circuit 40 to control the drive circuit 30 in response to changes in the region.

[0040] Because the functional circuit 40 is provided in a region overlapping with the pixel circuit 51 and the display element 61, it is difficult for the functional circuit 40 to perform high-load arithmetic processing. In one embodiment of the present invention, the arithmetic unit 103 is provided separately from the functional circuit 40, allowing the arithmetic unit 103 to perform high-load arithmetic processing, such as drawing processing in response to movement of the housing 105 and dividing the display unit of the display device 10_L or 10_R into multiple regions in response to a gaze point. Furthermore, the arithmetic unit 103 can perform processing, such as controlling the driver circuit 30 in response to changes in the region, in the functional circuit, thereby achieving circuit miniaturization and low power consumption. In particular, wearable electronic devices consume a lot of power for drawing processing because the arithmetic processing is performed within a limited period, such as the movement of the user's head or gaze. On the other hand, in one embodiment of the present invention, a functional circuit that outputs a control signal to the driver circuit 30 in response to the region is separated and integrated with the display device 10, enabling distributed arithmetic processing. Therefore, the load on one arithmetic unit can be reduced, thereby reducing overall power consumption.

[0041] 2A is a perspective view showing the back, bottom, and right side of electronic device 100. FIG.

[0042] 2A , the housing 105 of the electronic device 100 includes, as an example, a mounting portion 106, a buffer member 107, a pair of lenses 108, and the like, in addition to the pair of display devices 10_L and 10_R and the calculation unit 103. The pair of display devices 10_L and 10_R are provided inside the housing 105 at positions that can be viewed through the lenses 108.

[0043] 2A is provided with an input terminal 109 and an output terminal 110. A cable can be connected to the input terminal 109 to supply an image signal (image data) from a video output device or the like, or power for charging a battery provided within the housing 105. The output terminal 110 functions as, for example, an audio output terminal, and can be connected to earphones, headphones, or the like.

[0044] The housing 105 preferably has a mechanism for adjusting the left-right positions of the lens 108 and the display devices 10_L and 10_R so that they are optimally positioned according to the position of the user's eyes. The housing 105 also preferably has a mechanism for adjusting the focus by changing the distance between the lens 108 and the display devices 10_L and 10_R.

[0045] The cushioning member 107 is a portion that comes into contact with the user's face (forehead, cheeks, etc.). The cushioning member 107 makes close contact with the user's face, preventing light leakage and enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 107 so that it can come into close contact with the user's face when the user wears the electronic device 100. Using such a material is preferable because it feels pleasant to the touch and prevents the user from feeling cold when worn in cold seasons. It is preferable to make the components that come into contact with the user's skin, such as the cushioning member 107 or the attachment portion 106, removable, for easier cleaning or replacement.

[0046] The electronic device according to one embodiment of the present invention may further include an earphone 106A. The earphone 106A includes a communication unit (not shown) and has a wireless communication function. The earphone 106A can output audio data using the wireless communication function. The earphone 106A may also have a vibration mechanism to function as a bone conduction earphone.

[0047] 2B, the earphone 106A can be directly connected to the attachment unit 106 or connected by wire. The earphone 106B and the attachment unit 106 may have a magnet. This allows the earphone 106B to be fixed to the attachment unit 106 by magnetic force, which is preferable as it makes storage easier.

[0048] <Configuration Example of Display Device> The configuration of a display device 10 applicable to the display devices 10_L and 10_R shown in FIGS. 1A and 1B will be described with reference to FIGS. 3A, 3B, and 4. FIG.

[0049] FIG. 3A is a perspective schematic diagram of a display device 10 applicable to the display devices 10_L and 10_R shown in FIGS. 1A and 1B.

[0050] The display device 10 has a substrate 11 and a substrate 12. The display device 10 has a display section 13 composed of elements provided between the substrate 11 and the substrate 12. The display section 13 is an area that displays an image in the display device 10. The display section 13 is an area where pixels composed of pixel circuits and display elements connected to the pixel circuits are provided.

[0051] In this specification and the like, the term “element” may be replaced with “device” in some cases. For example, a display element, a light-emitting element, and a liquid crystal element may be replaced with a display device, a light-emitting device, and a liquid crystal device, for example.

[0052] Display device 10 receives various signals and power supply potentials from the outside via terminal section 14, and can display on display section 13. A plurality of layers are provided between substrate 11 and substrate 12, and each layer is provided with a transistor for performing circuit operation or a display element for emitting light. The plurality of layers are provided with pixel circuits that have the function of controlling the light emission of the display elements, drive circuits that have the function of controlling the pixel circuits, functional circuits that have the function of controlling the drive circuits, etc.

[0053] FIG. 3B is a perspective view showing a schematic configuration of each layer provided between the substrate 11 and the substrate 12. As shown in FIG.

[0054] A layer 20 is provided on the substrate 11. A driver circuit 30 and a functional circuit 40 are provided in the layer 20. The layer 20 includes a transistor 21 (also referred to as a Si transistor) having silicon in a channel formation region 22. The substrate 11 is, for example, a silicon substrate. A silicon substrate is preferable because it has higher thermal conductivity than a glass substrate.

[0055] The transistor 21 can be, for example, a transistor having single crystal silicon in a channel formation region. In particular, when a transistor having single crystal silicon in a channel formation region is used as the transistor provided in the layer 20, the on-state current of the transistor can be increased. Therefore, it is preferable because the circuit included in the layer 20 can be driven at high speed. Furthermore, since a Si transistor can be formed by microfabrication so as to have a channel length of 3 nm to 10 nm, the display device 10 can be provided with an accelerator such as a CPU or GPU, an application processor, or the like, integrated with the display unit.

[0056] The driver circuit 30 includes, for example, a gate driver circuit, a source driver circuit, and the like. In addition, the driver circuit 30 may include an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Since the gate driver circuit, the source driver circuit, and other circuits can be arranged overlapping the display portion 13, the width of a non-display region (also referred to as a frame) around the periphery of the display portion 13 of the display device 10 can be made significantly narrower than when these circuits are arranged side by side with the display portion 13, thereby enabling a compact display device 10 to be realized. When the driver circuit 30 is arranged around the periphery of the display portion 13 of the display device 10, the gate driver circuit and the source driver circuit are arranged together around the periphery. However, the driver circuit 30 in one embodiment of the present invention can be divided into multiple parts and arranged in a region overlapping with the display portion 13.

[0057] The functional circuit 40 has, for example, the function of an application processor for controlling each circuit in the display device 10 and generating signals for controlling each circuit. The functional circuit 40 may also have a circuit for correcting image data, such as an accelerator, such as a CPU or GPU. The functional circuit 40 may also have an LVDS (Low Voltage Differential Signaling) circuit, a MIPI (Mobile Industry Processor Interface) circuit, and / or a D / A (Digital to Analog) conversion circuit, each of which functions as an interface for receiving image data, etc., from outside the display device 10. The functional circuit 40 may also have a circuit for compressing and decompressing image data, and / or a power supply circuit, etc.

[0058] As described above, the functional circuit 40 has the function of driving the driver circuit 30 at different drive frequencies for each of multiple regions in the display unit of the display device determined by the gaze point and / or driving the driver circuit 30 at different resolutions for each region. When the gate driver circuits and source driver circuits are arranged in multiple separate regions, the driver circuits can be individually driven at different drive frequencies and / or at different resolutions for each region. This reduces the drive frequency or image data volume in areas far from the gaze point, thereby achieving low power consumption. Because the functional circuit 40 is integrated with the driver circuit 30, the charging and discharging of the wiring that supplies the control signals used by the functional circuit 40 to control the driver circuit 30 in response to changes in the region can be reduced.

[0059] A layer 50 is provided over the layer 20. The layer 50 includes a plurality of pixel circuits 51. The layer 50 includes a transistor 52 (also referred to as an OS transistor) having a metal oxide (also referred to as an oxide semiconductor) in a channel formation region 54. The layer 50 can be stacked over the layer 20. The layer 50 can also be formed over a different substrate and then bonded to the other substrate.

[0060] The transistor 52, which is an OS transistor, is preferably a transistor including an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc in a channel formation region. Such an OS transistor has a characteristic of extremely low off-state current. Therefore, it is preferable to use an OS transistor, particularly as a transistor provided in a pixel circuit, because analog data written to the pixel circuit can be held for a long period of time.

[0061] A layer 60 is provided on the layer 50. A substrate 12 is provided on the layer 60. The substrate 12 is preferably a light-transmitting substrate or a layer made of a light-transmitting material. The layer 60 is provided with a plurality of display elements 61. The layer 60 can be configured to be stacked on the layer 50. The display elements 61 can be, for example, organic electroluminescence elements (also referred to as organic EL elements). However, the display elements 61 are not limited thereto, and inorganic EL elements made of inorganic materials can also be used. Note that "organic EL elements" and "inorganic EL elements" are sometimes collectively referred to as "EL elements." The display elements 61 may contain inorganic compounds such as quantum dots. For example, quantum dots can be used in the light-emitting layer of the display elements 61 to function as a light-emitting material.

[0062] As shown in FIG. 3B , the display device 10 of one embodiment of the present invention can have a stacked structure including the display element 61, the pixel circuit 51, the driver circuit 30, and the functional circuit 40. This allows for an extremely high pixel aperture ratio (effective display area ratio). For example, the pixel aperture ratio can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, pixels can be arranged at extremely high density, resulting in extremely high pixel resolution. For example, in the display portion of the display device 10 (a region where the pixel circuit 51 and the display element 61 are stacked), pixels can be arranged with a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and further preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0063] Because of its extremely high resolution, the display device 10 can be suitably used in VR devices such as head-mounted displays or in glasses-type AR devices. For example, even in a configuration in which the display unit of the display device 10 is viewed through an optical component such as a lens, the display device 10 has an extremely high-resolution display unit, so that pixels are not visible even when the display unit is enlarged with a lens, thereby providing a highly immersive display.

[0064] In the display device 10, when a material containing single crystal silicon is used for the transistor 21 included in the layer 20, the size of the display portion 13 can be set to a diagonal size of 0.1 to 5 inches, preferably 0.5 to 3 inches, and more preferably 1 to 2 inches. In the display device 10 of one embodiment of the present invention, the width of the frame can be made extremely narrow. For example, when the diagonal size of the substrate 11 on which the layer 20 is provided is 1 inch, about four times the amount of light can be extracted compared to a diagonal size of 0.5 inches, which is preferable.

[0065] A specific configuration example of the drive circuit 30 and the functional circuit 40 will be described with reference to Fig. 4. The display device 10 shown in Fig. 4 is a block diagram illustrating pixel circuits 51, a plurality of wirings connecting the drive circuit 30 and the functional circuit 40, bus wirings within the display device 10, and the like.

[0066] In the display device 10 shown in FIG. 4, a layer 50 has a plurality of pixel circuits 51 arranged in a matrix.

[0067] 4 , the layer 20 includes a drive circuit 30 and a functional circuit 40. The drive circuit 30 includes, for example, a source driver circuit 31, a digital-to-analog conversion circuit 32, a gate driver circuit 33, and a level shifter 34. The functional circuit 40 includes, for example, a memory device 41, a GPU (AI accelerator) 42, an EL correction circuit 43, a timing controller 44, a CPU 45, a sensor controller 46, and a power supply circuit 47. The functional circuit 40 has the function of an application processor.

[0068] In addition, in the display device 10 of FIG. 4, the circuits included in the drive circuit 30 and the circuits included in the function circuit 40 are electrically connected to bus lines BSL, for example.

[0069] As an example, the source driver circuit 31 has a function of transmitting image data to the pixel circuits 51. Therefore, the source driver circuit 31 is electrically connected to the pixel circuits 51 via wirings SL. It is preferable to provide a plurality of source driver circuits 31. By arranging the source driver circuit 31 in each section of the display unit in which the pixel circuits 51 are provided, it is possible to configure the display unit so that each section is driven at a different driving frequency.

[0070] The digital-analog conversion circuit 32 has a function of converting image data that has been digitally processed by a GPU, a correction circuit, etc., which will be described later, into analog data. The image data that has been converted into analog data is transmitted to the pixel circuits 51 via the source driver circuit 31. Note that the digital-analog conversion circuit 32 may be included in the source driver circuit 31, or the image data may be transmitted in the order of the source driver circuit 31, the digital-analog conversion circuit 32, and the pixel circuits 51.

[0071] For example, the gate driver circuit 33 has a function of selecting a pixel circuit 51 to which image data is to be sent. Therefore, the gate driver circuit 33 is electrically connected to the pixel circuit 51 via a wiring GL. Note that it is preferable to provide a plurality of gate driver circuits 33 corresponding to the source driver circuits 31. By arranging the plurality of gate driver circuits 33 for each section of the display unit in which the pixel circuits 51 are provided, it is possible to configure the display unit to be driven at different drive frequencies for each section.

[0072] The level shifter 34 has a function of converting the levels of signals input to the source driver circuit 31, the digital-to-analog conversion circuit 32, the gate driver circuit 33, and the like, into appropriate levels, for example.

[0073] For example, the storage device 41 has a function of storing image data to be displayed on the pixel circuits 51. The storage device 41 can be configured to store image data as digital data or analog data.

[0074] Furthermore, when image data is stored in the storage device 41, it is preferable that the storage device 41 is a nonvolatile memory. In this case, the storage device 41 may be, for example, a NAND memory.

[0075] Furthermore, when temporary data generated by the GPU 42, the EL correction circuit 43, the CPU 45, etc. is stored in the storage device 41, it is preferable that the storage device 41 be a volatile memory. In this case, for example, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), etc. can be used as the storage device 41.

[0076] As an example, the GPU 42 has a function of performing processing to output image data read from the storage device 41 to the pixel circuit 51. In particular, the GPU 42 is configured to perform pipeline processing in parallel, and therefore can quickly process image data to be output to the pixel circuit 51. The GPU 42 can also have a function as a decoder for restoring encoded images.

[0077] The functional circuit 40 may also include a plurality of circuits capable of improving the display quality of the display device 10. For example, such circuits may include a correction circuit (color adjustment, dimming) that detects color unevenness in the displayed image and corrects the color unevenness to produce an optimal image. Furthermore, when a light-emitting device using an organic EL is used as the display element, the functional circuit 40 may also include an EL correction circuit. As an example, the functional circuit 40 includes an EL correction circuit 43.

[0078] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through the pixel circuit (or the voltage applied to the pixel circuit) may be monitored and acquired, and the displayed image may be acquired by an image sensor or the like, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (e.g., an artificial neural network), and the output result may be used to determine whether or not the image should be corrected.

[0079] Furthermore, the AI ​​calculations can be applied not only to image correction but also to up-conversion (down-conversion) of image data. For example, the GPU 42 in Fig. 4 has blocks for performing various correction calculations (color unevenness correction 42a, up-conversion 42b, etc.).

[0080] The algorithm for performing the upconversion process of image data can be selected from the nearest neighbor method, the bilinear method, the bicubic method, the rapid and accurate image super-resolution (RAISR) method, the anchored neighborhood regression (ANR) method, the A+ method, the super-resolution convolutional neural network (SRCNN) method, and the like.

[0081] The upconversion process may be configured to change the algorithm used for upconversion for each section of the display unit of the display device 10 that corresponds to the area determined based on the point of gaze. By using this configuration, the upconversion processing time can be shortened.

[0082] As an example, the timing controller 44 has a function of arbitrarily setting the drive frequency for displaying an image. For example, when displaying a still image on the display device 10, the drive frequency can be lowered by the timing controller 44. Alternatively, for example, the source driver circuit 31 and the gate driver circuit 33 can be arranged for each section of the display unit in the display device 10, and the drive frequency can be controlled for each section of the display unit. In this case, the timing controller 44 can set different drive frequencies for the gate driver circuit 33 and the source driver circuit 31 in each section of the display unit, thereby driving each area at a different drive frequency.

[0083] The CPU 45 has a function of performing general-purpose processing such as, for example, running an operating system, controlling data, performing various calculations, or running programs. The CPU 45 has a role of issuing commands such as writing or reading image data to or from the storage device 41, correcting image data, and operating a sensor (described later). Furthermore, for example, the CPU 45 may have a function of transmitting a control signal to at least one of the circuits included in the functional circuit 40.

[0084] The sensor controller 46 has a function of controlling the sensor, for example. 4B also illustrates wiring SNCL as wiring for electrically connecting to the sensor.

[0085] The sensor may be, for example, a touch sensor that can be provided in the display unit, or may be, for example, an illuminance sensor.

[0086] For example, the power supply circuit 47 has a function of generating voltages to be supplied to the pixel circuits 51, the drive circuit 30, and the circuits included in the functional circuit 40. The power supply circuit 47 may also have a function of selecting the circuits to which the voltage is supplied. For example, the power supply circuit 47 can reduce the power consumption of the entire display device 10 by stopping the voltage supply to the CPU 45, the GPU 42, etc. during the period when a still image is being displayed.

[0087] As described above, the display device of one embodiment of the present invention can have a stacked structure including a display element, a pixel circuit, a driver circuit, and a functional circuit. The driver circuit and the functional circuit, which are peripheral circuits, can be arranged overlapping with the pixel circuit, and the width of the frame can be significantly reduced, resulting in a miniaturized display device. Furthermore, the display device of one embodiment of the present invention can be lightweight because the wiring connecting the circuits can be shortened by stacking the circuits. Furthermore, the display device of one embodiment of the present invention can have a display portion with improved pixel resolution, resulting in a display device with excellent display quality.

[0088] <Example of Operation of Electronic Device> An example of operation of the electronic device 100 will be described with reference to the drawings. FIG.

[0089] The motion detection unit 101 acquires first information (data) relating to the motion of the housing 105 (step S11).

[0090] The line-of-sight detection unit 102 acquires second information (data) relating to the gaze point G according to the line of sight (step S12).

[0091] The calculation unit 103 performs a rendering process of 360-degree omnidirectional image data based on the first information relating to the movement of the housing 105 (step S13).

[0092] Step S13 will be described with a specific example. The schematic diagram shown in Fig. 6A illustrates a user 112 positioned at the center of 360-degree omnidirectional image data 111. The user can view an image 114A in a direction 113A displayed on the display device 10 of the electronic device 100.

[0093] 6B shows a state in which user 112 moves his / her head from the schematic diagram of Fig. 6A to view image 114B in direction 113B. Image 114A changes to image 114B in accordance with the movement of the housing of electronic device 100, allowing user 112 to recognize the space represented by image data 111 in all 360-degree directions.

[0094] 6A and 6B, the user 112 moves the housing of the electronic device 100 in conjunction with the movement of his or her head. The higher the rendering processing capability used to process the images obtained from the 360-degree omnidirectional image data 111 that are displayed in accordance with the movement of the electronic device 100, the more the user 112 can recognize a virtual space that is more in line with the space in the real world.

[0095] The calculation unit 103 determines, based on the second information, a plurality of regions corresponding to the gaze point G for the display unit region of the display device (step S14). For example, a first region including the gaze point G is determined, a second region adjacent to the first region is determined, and the outside of the second region is determined as a third region.

[0096] Step S14 will be described using a specific example.

[0097] Generally, human visual fields are broadly classified into the following five categories, although there are individual differences. The discriminative visual field is the area where visual functions such as visual acuity and color discrimination are at their best, and refers to the area within approximately 5° of the center of the visual field. The effective visual field is the area where specific information can be instantly identified using eye movement alone, and refers to the area within approximately 30° horizontally and 20° vertically of the center of the visual field, but adjacent to the discriminative visual field. The stable fixation visual field is the area where specific information can be identified effortlessly with head movement, and refers to the area within approximately 90° horizontally and 70° vertically of the center of the visual field, but adjacent to the effective visual field. The induced visual field is the area where the presence of a specific object can be detected but the ability to identify it is low, and refers to the area within approximately 100° horizontally and 85° vertically of the center of the visual field, but adjacent to the stable fixation visual field. The auxiliary visual field is an area in which the ability to distinguish specific objects is significantly reduced, but the presence of stimuli can be detected. It is an area within approximately 100° to 200° horizontally and approximately 85° to 130° vertically from the center of the visual field, adjacent to the induced visual field.

[0098] From the above, it can be seen that the image quality from the discriminative visual field to the effective visual field is important for the image displayed by the electronic device. The image quality of the discriminative visual field is particularly crucial.

[0099] 7A is a schematic diagram showing a state in which a user 112 is observing an image 114 displayed on a display unit of the display device 10 of the electronic device 100 from the front (image display surface). The image 114 shown in FIG. 7A also corresponds to the display unit. A fixation point G at the end of the line of sight 113 of the user 112 is also shown on the image 114. In this specification, the area on the image 114 that includes the discriminative visual field is referred to as the "first area S1," and the area that includes the effective visual field is referred to as the "second area S2." Furthermore, the area that includes the stable fixation visual field, the induced visual field, and / or the auxiliary visual field is referred to as the "third area S3."

[0100] In FIG. 7A , the boundary (outline) between the first region S1 and the second region S2 is shown as a curve, but this is not limiting. As shown in FIG. 7B , the boundary (outline) between the first region S1 and the second region S2 may be rectangular or polygonal. It may also have a shape that combines straight lines and curves. The display unit of the display device 10 may also be divided into two regions, with the region that includes the discriminative visual field and the effective visual field designated as the first region S1 and the other region designated as the second region S2. In this case, the third region S3 is not formed.

[0101] 8A is a top view of image 114 displayed on the display unit of display device 10 of electronic device 100, and FIG. 8B is a side view of image 114 displayed on the display unit of display device 10 of electronic device 100. In this specification, the horizontal angle of first region S1 is referred to as "angle θx1," and the horizontal angle of second region S2 is referred to as "angle θx2" (see FIG. 8A). Also, in this specification, the vertical angle of first region S1 is referred to as "angle θy1," and the vertical angle of second region S2 is referred to as "angle θy2" (see FIG. 8B).

[0102] For example, by setting the angle θx1 to 10° and the angle θy1 to 10°, the area of ​​the first region S1 can be increased. In this case, part of the effective visual field is included in the first region S1. Furthermore, by setting the angle θx2 to 45° and the angle θy2 to 35°, the area of ​​the second region S2 can be increased. In this case, part of the stable visual field is included in the second region S2.

[0103] The position of the gaze point G fluctuates slightly due to the movement of the user 112. For this reason, it is preferable that the angles θx1 and θy1 are each greater than or equal to 5° and less than 20°. Setting the area of ​​the first region S1 to be larger than the discriminative field of view stabilizes the operation of the display device 10 and improves the visibility of the image.

[0104] When the line of sight 113 of the user 112 moves, the first area and the second area also move. For example, when the amount of change in the line of sight 113 exceeds a certain amount, it is determined that the line of sight 113 is moving. When the amount of change in the line of sight 113 becomes equal to or less than the certain amount, it is determined that the movement of the line of sight 113 has stopped, and the first area to the third area are determined.

[0105] The functional circuit 40 controls the drive circuit 30 according to the plurality of regions (first to third regions) (step S15). An example of the configuration of the drive circuit 30 that performs control according to the plurality of regions will be described later.

[0106] 9A and 9B show a configuration example of a pixel circuit 51 and a display element 61 connected to the pixel circuit 51. Fig. 9A is a diagram showing the connection of each element, and Fig. 9B is a diagram schematically showing the hierarchical relationship between a layer 20 including a driver circuit, a layer 50 including a plurality of transistors included in the pixel circuit, and a layer 60 including a light-emitting element.

[0107] 9A and 9B includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The transistors 52A, 52B, and 52C can be OS transistors. Each of the OS transistors 52A, 52B, and 52C preferably includes a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or a signal different from the gate electrode can be applied to the back gate electrode.

[0108] The transistor 52B includes a gate electrode electrically connected to the transistor 52A, a first terminal electrically connected to the display element 61, and a second terminal electrically connected to the wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the display element 61.

[0109] The transistor 52A has a first terminal electrically connected to the gate electrode of the transistor 52B, a second terminal electrically connected to the wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of the wiring GL1 that functions as a gate line.

[0110] The transistor 52C includes a first terminal electrically connected to the wiring V0, a ​​second terminal electrically connected to the display element 61, and a gate electrode having a function of controlling the conductive state or non-conductive state based on the potential of the wiring GL2 functioning as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 51 to the driver circuit 30 or the functional circuit 40.

[0111] The capacitor 53 has an electrode electrically connected to the gate electrode of the transistor 52B and an electrode electrically connected to the second terminal of the transistor 52C.

[0112] The display element 61 includes a first terminal electrically connected to the first terminal of the transistor 52B and a second terminal electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the display element 61.

[0113] This allows the intensity of light emitted from the display element 61 to be controlled in accordance with an image signal applied to the gate electrode of the transistor 52B. Furthermore, the reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source voltage of the transistor 52B.

[0114] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the display element 61 to the outside. The current output to the wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A / D converter or the like and output to the functional circuit 40 or the like.

[0115] Note that the display element described in one embodiment of the present invention refers to a self-luminous display element such as an organic light-emitting diode (OLED). Note that the display element electrically connected to the pixel circuit can be a self-luminous light-emitting element such as an LED (light-emitting diode), a micro LED, a quantum-dot light-emitting diode (QLED), or a semiconductor laser.

[0116] In the configuration shown in FIG. 9B as an example, the wiring electrically connecting the pixel circuits 51 and the drive circuit 30 can be shortened, thereby reducing the wiring resistance of the wiring. This allows data to be written at high speed, thereby enabling the display device 10 to be driven at high speed. This allows the display device 10 to have a sufficient frame period even if the display device 10 has a large number of pixel circuits 51, thereby increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 can increase the resolution of images displayed by the display device 10. For example, the pixel density of the display device 10 can be 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 10 can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices such as HMDs, in which the display unit is close to the user.

[0117] 9A and 9B show an example of the pixel circuit 51 including three transistors in total, but one embodiment of the present invention is not limited thereto. Below, examples of the configuration and driving method of a pixel circuit that can be applied to the pixel circuit 51 will be described.

[0118] 10A illustrates a pixel circuit 51A including a transistor 52A, a transistor 52B, and a capacitor 53. 10A also illustrates a display element 61 connected to the pixel circuit 51A. The pixel circuit 51A is electrically connected to a wiring SL, a wiring GL, a wiring ANO, and a wiring VCOM.

[0119] The transistor 52A has a gate electrically connected to a wiring GL, one of its source and drain electrically connected to a wiring SL, and the other electrically connected to the gate of the transistor 52B and one electrode of the capacitor 53. The transistor 52B has one of its source and drain electrically connected to a wiring ANO, and the other electrically connected to an anode of the display element 61. The capacitor 53 has the other electrode electrically connected to the anode of the display element 61. The display element 61 has a cathode electrically connected to a wiring VCOM.

[0120] 10B has a configuration in which a transistor 52C is added to the pixel circuit 51A. A wiring V0 is electrically connected to the pixel circuit 51B.

[0121] A pixel circuit 51C shown in FIG. 10C is an example in which transistors having a pair of gates electrically connected are used as the transistors 52A and 52B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 10D is an example in which the same transistors are used as the pixel circuit 51B. This can increase the current that the transistors can pass. Note that, although transistors having a pair of gates electrically connected are used as all the transistors here, this is not a limitation. Alternatively, a transistor having a pair of gates electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to a source.

[0122] 11A has a configuration in which a transistor 52D is added to the pixel circuit 51B. The pixel circuit 51E is electrically connected to three wirings (a wiring GL1, a wiring GL2, and a wiring GL3) that function as gate lines.

[0123] The gate of the transistor 52D is electrically connected to a wiring GL3, one of the source and drain of the transistor 52D is electrically connected to the gate of the transistor 52B, and the other is electrically connected to a wiring V0. The gate of the transistor 52A is electrically connected to a wiring GL1, and the gate of the transistor 52C is electrically connected to a wiring GL2.

[0124] By simultaneously turning on the transistors 52C and 52D, the source and gate of the transistor 52B have the same potential, and the transistor 52B can be turned off. This forcibly cuts off the current flowing through the display element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0125] 11B is an example in which a capacitor 53A is added to the pixel circuit 51E. The capacitor 53A functions as a storage capacitor.

[0126] 11C and 11D are examples in which transistors each having a pair of gates are applied to the pixel circuit 51E or 51F, respectively. Transistors each having a pair of gates electrically connected to each other are applied to the transistor 52A, the transistor 52C, and the transistor 52D, and a transistor each having one gate electrically connected to its source is applied to the transistor 52B.

[0127] Next, a description will be given of an example of a method for driving a display device to which the pixel circuit 51 E is applied. Note that the same driving method can also be applied to display devices to which the pixel circuits 51 F, 51 G, and 51 H are applied.

[0128] 12 is a timing chart illustrating a driving method of a display device using the pixel circuit 51E. The timing chart illustrates the transition of potentials of the wirings GL1[k], GL2[k], and GL3[k], which are gate lines in the kth row, and the wirings GL1[k+1], GL2[k+1], and GL3[k+1], which are gate lines in the k+1th row. The timing chart also illustrates the timing of signals applied to the wirings SL, which function as source lines.

[0129] Here, an example of a driving method is shown in which one horizontal period is divided into a light-on period and a light-off period. The horizontal period for the kth row and the horizontal period for the k+1th row are shifted by the selection period of the gate line.

[0130] During the lighting period of the kth row, a high-level potential is first applied to the wiring GL1[k] and the wiring GL2[k], and a source signal is applied to the wiring SL. As a result, the transistors 52A and 52C are turned on, and a potential corresponding to the source signal is written from the wiring SL to the gate of the transistor 52B. After that, a low-level potential is applied to the wiring GL1[k] and the wiring GL2[k], so that the transistors 52A and 52C are turned off, and the gate potential of the transistor 52B is maintained.

[0131] Subsequently, the lighting period of the k+1th row begins, and data is written in the same manner as above.

[0132] Next, the off-period will be described. During the off-period of the kth row, a high-level potential is applied to the wiring GL2[k] and the wiring GL3[k]. As a result, the transistors 52C and 52D are turned on, and the same potential is applied to the source and gate of the transistor 52B, causing almost no current to flow through the transistor 52B. This turns off the display element 61. All subpixels located on the kth row are turned off. The subpixels on the kth row remain off until the next light-on period.

[0133] Next, the process transitions to the off period of the k+1th row, and all the sub-pixels of the k+1th row are in the off state in the same manner as above.

[0134] This driving method, in which the display is not always on during one horizontal period but has an off period during one horizontal period, can also be called duty driving. Duty driving can reduce the afterimage phenomenon when displaying moving images, thereby realizing a display device with high moving image display performance. In particular, in VR devices, reducing afterimages can alleviate so-called VR sickness.

[0135] In duty driving, the ratio of the on period to one horizontal period can be called the duty ratio. For example, a duty ratio of 50% means that the on period and the off period are the same length. The duty ratio can be freely set and can be adjusted as appropriate within a range of, for example, more than 0% and less than 100%.

[0136] Furthermore, a configuration different from the pixel circuit described above will be described with reference to FIGS. 13A and 13B.

[0137] 13A is a block diagram of a pixel having elements included in a pixel circuit and a light-emitting element. The pixel shown in FIG. 13A has a memory in addition to a switching transistor (Switching Tr), a driving transistor (Driving Tr), and a light-emitting element (LED).

[0138] The memory is supplied with data Data_W. When the data Data_W is supplied to the pixel in addition to the display data Data, the current flowing through the light emitting element increases, and the display device can display high luminance.

[0139] FIG. 13B shows a specific circuit diagram of the pixel circuit.

[0140] 13B includes a transistor 52_w, a transistor 52A, a transistor 52B, a transistor 52C, a capacitor 53_s, and a capacitor 53_w. Also, FIG. 13B illustrates a display element 61 connected to the pixel circuit 52I.

[0141] One of the source or drain of the transistor 52_w is electrically connected to one electrode of the capacitor 53_w. The other electrode of the capacitor 53_w is electrically connected to one of the source or drain of the transistor 52A. One of the source or drain of the transistor 52A is electrically connected to the gate of the transistor 52B. The gate of the transistor 52B is electrically connected to one electrode of the capacitor 53_s. The other electrode of the capacitor 53_s is electrically connected to one of the source or drain of the transistor 52B. One of the source or drain of the transistor 52B is electrically connected to one of the source or drain of the transistor 52C. One of the source or drain of the transistor 52C is electrically connected to one electrode of the display element 61. Although each transistor shown in FIG. 13B has a backgate electrically connected to the gate, the connection of the backgate is not limited to this. Furthermore, the transistor does not necessarily have to have a backgate.

[0142] Here, a node NM is a node to which the other electrode of the capacitor 53_w, one of the source or drain of the transistor 52A, the gate of the transistor 52B, and one electrode of the capacitor 53_s are connected, and a node NA is a node to which the other electrode of the capacitor 53_s, one of the source or drain of the transistor 52B, one of the source or drain of the transistor 52C, and one electrode of the display element 61 are connected.

[0143] The gate of the transistor 52_w is electrically connected to the wiring GL1. The gate of the transistor 52C is electrically connected to the wiring GL1. The gate of the transistor 52A is electrically connected to the wiring GL2. The other of the source and the drain of the transistor 52_w is electrically connected to the wiring SL1. The other of the source and the drain of the transistor 52C is electrically connected to the wiring V0. The other of the source and the drain of the transistor 52A is electrically connected to the wiring SL2.

[0144] The other of the source and the drain of the transistor 52B is electrically connected to a wiring ANO. The other electrode of the display element 61 is electrically connected to a wiring VCOM.

[0145] The wiring GL1 and the wiring GL2 can function as signal lines for controlling the operation of the transistors. The wiring SL1 can function as a signal line for supplying an image signal to the pixel. The wiring SL2 can function as a signal line for writing data to the memory circuit MEM. The wiring SL2 can function as a signal line for supplying a correction signal to the pixel. The wiring V0 can function as a monitor line for acquiring electrical characteristics of the transistor 52B. Furthermore, by supplying a specific potential from the wiring V0 to the other electrode of the capacitor 53_s through the transistor 52C, writing of an image signal can also be stabilized.

[0146] The transistors 52A, 52B, and the capacitor 53_w constitute a memory circuit MEM. The node NM is a memory node, and a signal supplied to the wiring SL2 can be written to the node NM by turning on the transistor 52_w. By using an OS transistor with extremely low off-state current as the transistor 52A, the potential of the node NM can be held for a long time.

[0147] In the pixel, a signal written to the node NM is capacitively coupled to an image signal supplied from the wiring SL1 and can be output to the node NA. Note that the transistor 52_w can have a function of selecting a pixel.

[0148] 14A shows an example of a drive circuit 30 arranged to overlap a pixel circuit 51. A source driver circuit 31 and a gate driver circuit 33 are shown as circuits included in the drive circuit 30. A plurality of pixel circuits 51 (not shown) are divided into a plurality of sections 59. Each section 59 is provided in a section that overlaps with the source driver circuit 31 and the gate driver circuit 33. The source driver circuit 31 and the gate driver circuit 33 can be divided into any sections of the layer 20 and arranged to correspond to the sections 59.

[0149] Fig. 14B shows an enlarged view of the section 59. In Fig. 14B, a plurality of wirings SL and a plurality of wirings GL are indicated by dashed lines.

[0150] 14B , the multiple wirings SL extending in the vertical direction are each electrically connected to a source driver circuit 31. The multiple wirings GL extending in the horizontal direction are each electrically connected to a gate driver circuit 33. The wirings SL and GL are each electrically connected to a plurality of pixel circuits 51.

[0151] In this way, by providing a plurality of source driver circuits 31 and gate driver circuits 33 directly below the pixel circuits 51, the lengths of the wirings SL and GL can be made extremely short. As a result, the load on the wirings SL and GL is reduced, and the time and power required for charging and discharging can be made extremely short, thereby realizing high-speed driving. Furthermore, since the image can be rewritten for each section 59, it is possible to rewrite data only for parts of the image where changes have occurred and to retain data for images that remain unchanged, thereby reducing power consumption.

[0152] Furthermore, since the pixel circuit 51 is formed using an OS transistor with extremely low off-state current, data written to the pixel can be retained for a long period of time. Therefore, the display drive frequency can be arbitrarily set (variable). Furthermore, since the display device 10 can be driven for each section 59, the drive frequency can also be set for each section 59 in some cases.

[0153] The display device in the electronic device of one embodiment of the present invention has a structure in which pixel circuits and functional circuits are stacked, and by varying the drive frequency of the section 59 corresponding to the region (first region to third region) corresponding to the movement of the line of sight, it is possible to effectively reduce power consumption.

[0154] For example, as shown in Fig. 15A, a plurality of sections 59 (16 sections, 4 x 4 in the figure) corresponding to an image 114 are illustrated. Fig. 15A also illustrates a first region S1 to a third region S3 centered around a gaze point G. In this case, the sections are divided into a section 59A that overlaps with the first region S1 and the second region S2 near the user's gaze point G, and a section 59B that overlaps with the third region S3 that is far from the user's gaze point G (see Fig. 15B).

[0155] In the functional circuit 40, by controlling the drive frequency of the section 59A to be higher than the drive frequency of the section 59B, it is possible to reduce the power consumption required for displaying an area far from the gaze point G, thereby achieving low power consumption. The functional circuit 40 is provided integrally with the drive circuit 30. This allows the length of the wiring between the functional circuit 40 and the drive circuit 30 to be shortened, and reduces the charging and discharging of the wiring that provides the control signal for the functional circuit 40 to control the drive circuit 30 in accordance with changes in the area.

[0156] In addition, since the display device of one embodiment of the present invention can have a stacked structure of pixel circuits and functional circuits, defective pixels can be detected using the functional circuits provided below the screen circuits. By using information about the defective pixels, display defects due to the defective pixels can be corrected, and normal display can be achieved.

[0157] A part of the correction method exemplified below may be executed by a circuit provided outside the display device, or may be executed by the functional circuit 40 of the display device 10.

[0158] A more specific example of the correction method will be described below: Fig. 16A is a flowchart showing the correction method described below.

[0159] First, in step S1, the correction operation is started.

[0160] Next, in step S2, the pixel current is read out. For example, each pixel can be driven to output a current to a monitor line electrically connected to the pixel.

[0161] The current readout operation can be performed simultaneously in a plurality of sections 59. Because the screen is divided, the current readout operation for all pixels can be performed in an extremely short time.

[0162] Next, in step S3, the read current is converted into a voltage. At this time, if a digital signal is to be handled in subsequent processing, the voltage can be converted into digital data in step S3. For example, analog data can be converted into digital data by using an analog-to-digital converter (ADC).

[0163] Next, in step S4, pixel parameters for each pixel are obtained based on the obtained data, such as the threshold voltage or field effect mobility of the driving transistor, the threshold voltage of the light-emitting element, and the current value at a predetermined voltage.

[0164] Next, in step S5, each pixel is judged to be abnormal based on the pixel parameter. For example, if the value of the pixel parameter exceeds (or falls below) a predetermined threshold value, the pixel is recognized as an abnormal pixel.

[0165] The abnormalities include dark spot defects with significantly low brightness relative to the input data potential, and bright spot defects with significantly high brightness.

[0166] In step S5, the address of the abnormal pixel and the type of defect can be identified and acquired.

[0167] Subsequently, in step S6, a correction process is performed.

[0168] An example of the correction process will be described with reference to Fig. 16B. Fig. 16B schematically shows a pixel, each of which is a set of 3 x 3 pixel circuits 51 and display elements 61. Here, it is assumed that the central pixel is a pixel 151 that has a dark point defect. Fig. 16B schematically shows a state in which pixel 151 is turned off and the surrounding pixels 150 are turned on at a predetermined brightness.

[0169] A dark point defect is a defect in which the brightness of the pixel is unlikely to reach normal brightness even if a correction is made to increase the data potential input to the pixel. Therefore, as shown in Figure 16B, a correction is made to increase the brightness of pixels 150 surrounding a pixel 151 with a dark point defect. This makes it possible to display a normal image even if a dark point defect occurs.

[0170] In the case of a bright spot defect, the bright spot defect can be made less noticeable by lowering the brightness of the surrounding pixels.

[0171] In particular, in the case of high-resolution display devices (e.g., 1000 ppi or more), it is difficult to visually recognize each pixel separately, so it is particularly effective to use a correction method that compensates for abnormal pixels using surrounding pixels.

[0172] On the other hand, it is preferable to correct pixels in which an abnormality such as a dark spot defect or a bright spot defect has occurred so that no data potential is input.

[0173] In this way, correction parameters can be set for each pixel. By applying the correction parameters to input image data, corrected image data can be generated to display an optimal image on the display device 10.

[0174] Furthermore, since variations exist in pixel parameters not only for abnormal pixels and pixels surrounding the abnormal pixels but also for pixels not determined to be abnormal pixels, unevenness due to the variations may be visible when an image is displayed. Therefore, for pixels not determined to be abnormal pixels, correction parameters can be set to cancel (level out) the variations in pixel parameters. For example, a reference value based on the median or average value of pixel parameters for some or all pixels can be set, and a correction value for canceling the difference between the pixel parameters of a specific pixel and the reference value can be set as the correction parameter for that pixel.

[0175] Furthermore, for pixels surrounding an abnormal pixel, it is preferable to set correction data that takes into consideration both the amount of correction for compensating for the abnormal pixel and the amount of correction for canceling variations in pixel parameters.

[0176] Then, in step S7, the correction operation is completed.

[0177] Thereafter, an image can be displayed based on the correction parameters obtained in the above correction operation and the input image data.

[0178] A neural network may be used in one of the steps of the correction operation. In the neural network, correction parameters can be determined based on inference results obtained by machine learning, for example. For example, when the correction parameters are determined using a neural network, high-precision correction can be performed so that abnormal pixels are not noticeable, without using a detailed correction algorithm.

[0179] The above is the explanation of the correction method.

[0180] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0181] Embodiment 2 In this embodiment, an example of a cross-sectional structure of a display device 10 according to one embodiment of the present invention will be described.

[0182] 17 is a cross-sectional view showing an example of the configuration of the display device 10. The display device 10 has a substrate 11 and a substrate 12, and the substrates 11 and 12 are bonded together with a sealant 712.

[0183] A single crystal semiconductor substrate such as a single crystal silicon substrate can be used as the substrate 11. Note that a semiconductor substrate other than a single crystal semiconductor substrate may also be used as the substrate 11.

[0184] The transistor 441 and the transistor 601 are provided over a substrate 11. The transistor 441 and the transistor 601 can be the transistor 21 provided in the layer 20 described in Embodiment 1.

[0185] The transistor 441 includes a conductor 443 that functions as a gate electrode, an insulator 445 that functions as a gate insulator, and a part of the substrate 11, and includes a semiconductor region 447 including a channel formation region, a low-resistance region 449 a that functions as one of a source region and a drain region, and a low-resistance region 449 b that functions as the other of the source region and the drain region. The transistor 441 may be either a p-channel type or an n-channel type.

[0186] The transistor 441 is electrically isolated from other transistors by an element isolation layer 403. Fig. 17 shows a case where the transistor 441 and the transistor 601 are electrically isolated by the element isolation layer 403. The element isolation layer 403 can be formed by a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or the like.

[0187] 17, a semiconductor region 447 has a convex shape. A conductor 443 is provided to cover the side surface and the top surface of the semiconductor region 447 with an insulator 445 interposed therebetween. Note that the conductor 443 covering the side surface of the semiconductor region 447 is not shown in FIG. A material that adjusts the work function can be used for the conductor 443.

[0188] A transistor having a convex semiconductor region, such as the transistor 441, can be called a fin transistor because it utilizes a convex portion of a semiconductor substrate. Note that an insulator that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Also, although FIG. 17 shows a configuration in which the convex portion is formed by processing a part of the substrate 11, a semiconductor having a convex portion may be formed by processing an SOI substrate.

[0189] 17 is just an example, and the transistor 441 is not limited to this configuration and may have an appropriate configuration depending on the circuit configuration, the operation method of the circuit, etc. For example, the transistor 441 may be a planar transistor.

[0190] The transistor 601 can have a structure similar to that of the transistor 441 .

[0191] In addition to the element isolation layer 403, the transistor 441, and the transistor 601, insulators 405, 407, 409, and 411 are provided on the substrate 11. A conductor 451 is embedded in the insulator 405, the insulator 407, the insulator 409, and the insulator 411. Here, the height of the top surface of the conductor 451 and the height of the top surface of the insulator 411 can be made approximately the same.

[0192] The insulators 421 and 214 are provided over the conductor 451 and the insulator 411. The conductor 453 is embedded in the insulator 421 and the insulator 214. Here, the height of the top surface of the conductor 453 and the height of the top surface of the insulator 214 can be made approximately the same.

[0193] An insulator 216 is provided over the conductor 453 and the insulator 214. A conductor 455 is embedded in the insulator 216. Here, the height of the top surface of the conductor 455 and the height of the top surface of the insulator 216 can be made approximately the same.

[0194] Insulators 222, 224, 254, 280, 274, and 281 are provided on the conductor 455 and the insulator 216. A conductor 305 is embedded in the insulators 222, 224, 254, 280, 274, and 281. Here, the height of the top surface of the conductor 305 and the height of the top surface of the insulator 281 can be made approximately the same.

[0195] An insulator 361 is provided on the conductor 305 and the insulator 281. The conductor 317 and the conductor 337 are embedded in the insulator 361. Here, the height of the top surface of the conductor 337 and the height of the top surface of the insulator 361 can be made approximately the same.

[0196] An insulator 363 is provided on the conductor 337 and on the insulator 361. The conductors 347, 353, 355, and 357 are embedded in the insulator 363. Here, the height of the top surfaces of the conductors 353, 355, and 357 can be made approximately the same as the height of the top surface of the insulator 363.

[0197] A connection electrode 760 is provided on the conductor 353, the conductor 355, the conductor 357, and the insulator 363. An anisotropic conductor 780 is provided so as to be electrically connected to the connection electrode 760, and an FPC (Flexible Printed Circuit) 716 is provided so as to be electrically connected to the anisotropic conductor 780. Various signals and the like are supplied to the display device 10 from outside the display device 10 via the FPC 716.

[0198] 17 , the low-resistance region 449b serving as the other of the source and drain regions of the transistor 441 is electrically connected to the FPC 716 through the conductor 451, the conductor 453, the conductor 455, the conductor 305, the conductor 317, the conductor 337, the conductor 347, the conductor 353, the conductor 355, the conductor 357, the connection electrode 760, and the anisotropic conductor 780. Here, in FIG. 17 , three conductors, namely, the conductor 353, the conductor 355, and the conductor 357, are shown as conductors having a function of electrically connecting the connection electrode 760 and the conductor 347; however, one embodiment of the present invention is not limited thereto. The number of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347 may be one, two, or four or more. By providing a plurality of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347, contact resistance can be reduced.

[0199] A transistor 750 is provided over the insulator 214. The transistor 750 can be the transistor 52 provided in the layer 50 described in Embodiment 1. For example, the transistor 750 can be a transistor provided in the pixel circuit 51. An OS transistor can be suitably used as the transistor 750. An OS transistor has an extremely low off-state current. Therefore, the retention time of image data and the like can be extended, thereby reducing the frequency of a refresh operation. Therefore, the power consumption of the display device 10 can be reduced.

[0200] Conductors 301a and 301b are embedded in the insulators 254, 280, 274, and 281. The conductor 301a is electrically connected to one of the source and the drain of the transistor 750, and the conductor 301b is electrically connected to the other of the source and the drain of the transistor 750. Here, the height of the top surfaces of the conductors 301a and 301b can be made approximately the same as the height of the top surface of the insulator 281.

[0201] The conductors 311, 313, 331, a capacitor 790, a conductor 333, and a conductor 335 are embedded in the insulator 361. The conductors 311 and 313 are electrically connected to the transistor 750 and function as wirings. The conductors 333 and 335 are electrically connected to the capacitor 790. Here, the height of the top surfaces of the conductors 331, 333, and 335 can be made approximately the same as the height of the top surface of the insulator 361.

[0202] The conductors 341, 343, and 351 are embedded in the insulator 363. Here, the height of the top surface of the conductor 351 and the height of the top surface of the insulator 363 can be made to be approximately the same.

[0203] The insulators 405, 407, 409, 411, 421, 214, 280, 274, 281, 361, and 363 each function as an interlayer film and may also function as a planarizing film that covers uneven shapes below the insulators 405, 407, 409, 411, 421, 214, 280, 274, 281, 361, and 363. For example, the top surface of the insulator 363 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0204] 17 , the capacitor 790 has a lower electrode 321 and an upper electrode 325. An insulator 323 is provided between the lower electrode 321 and the upper electrode 325. That is, the capacitor 790 has a layered structure in which the insulator 323, which functions as a dielectric, is sandwiched between a pair of electrodes. Note that while FIG. 17 shows an example in which the capacitor 790 is provided on the insulator 281, the capacitor 790 may be provided on an insulator different from the insulator 281.

[0205] FIG. 17 shows an example in which conductors 301a, 301b, and 305 are formed in the same layer. It also shows an example in which conductors 311, 313, 317, and a lower electrode 321 are formed in the same layer. It also shows an example in which conductors 331, 333, 335, and 337 are formed in the same layer. It also shows an example in which conductors 341, 343, and 347 are formed in the same layer. It also shows an example in which conductors 351, 353, 355, and 357 are formed in the same layer. Forming multiple conductors in the same layer can simplify the manufacturing process of the display device 10, thereby reducing the manufacturing cost of the display device 10. These conductors may be formed in different layers and may contain different types of materials.

[0206] 17 includes a display element 61. The display element 61 includes a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0207] Materials that can be used for the organic compounds include fluorescent materials and phosphorescent materials, etc. Materials that can be used for the quantum dots include colloidal quantum dot materials, alloy quantum dot materials, core-shell quantum dot materials, core quantum dot materials, etc.

[0208] The conductor 772 is electrically connected to the other of the source and the drain of the transistor 750 through the conductors 351, 341, 331, 313, and 301b. The conductor 772 is formed over the insulator 363 and functions as a pixel electrode.

[0209] A material that transmits or reflects visible light can be used for the conductor 772. As a light-transmitting material, for example, an oxide material containing indium, zinc, tin, or the like can be used. As a reflective material, for example, a material containing aluminum, silver, or the like can be used.

[0210] Although not shown in FIG. 17, the display device 10 can be provided with optical members (optical substrates) such as a polarizing member, a phase difference member, an anti-reflection member, and the like.

[0211] A light-shielding layer 738 and an insulator 734 in contact with the light-shielding layer 738 are provided on the substrate 12 side. The light-shielding layer 738 has a function of blocking light emitted from an adjacent region. Alternatively, the light-shielding layer 738 has a function of blocking external light from reaching the transistor 750 and the like.

[0212] 17, an insulator 730 is provided over an insulator 363. Here, the insulator 730 can be configured to cover part of a conductor 772. The display element 61 includes a light-transmitting conductor 788 and can be a top-emission light-emitting element.

[0213] The light-shielding layer 738 is provided to have a region overlapping with the insulator 730. The light-shielding layer 738 is covered with the insulator 734. The sealing layer 732 is filled between the display element 61 and the insulator 734.

[0214] Furthermore, the structure 778 is provided between the insulator 730 and the EL layer 786. The structure 778 is also provided between the insulator 730 and the insulator 734.

[0215] FIG. 18 shows a modified example of the display device 10 shown in FIG. 17 . The display device 10 shown in FIG. 18 differs from the display device 10 shown in FIG. 17 in that a colored layer 736 is provided. The colored layer 736 is provided so as to have an area overlapping with the display element 61. By providing the colored layer 736, the color purity of the light extracted from the display element 61 can be increased. This allows the display device 10 to display a high-quality image. Furthermore, since, for example, all of the display elements 61 of the display device 10 can be light-emitting elements that emit white light, it is not necessary to form the EL layer 786 by different colors, and the display device 10 can have high definition.

[0216] The display element 61 can have a micro-optical resonator (microcavity) structure. This allows light of a predetermined color (e.g., RGB) to be extracted without providing a colored layer, and the display device 10 can perform color display. By configuring the display device 10 without providing a colored layer, it is possible to suppress light absorption by the colored layer. This allows the display device 10 to display high-brightness images and reduce power consumption of the display device 10. Note that even when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, i.e., formed by coloring, a configuration without providing a colored layer can be used. Note that the brightness of the display device 10 can be, for example, 500 cd / m ２ or more, preferably 1000 cd / m ２ More than 10000cd / m ２ or less, more preferably 2000 cd / m ２ More than 5000cd / m ２ It can be as follows:

[0217] 19A, 19B, and 19C are a top view and a cross-sectional view of a transistor 750 that can be used in a display device of one embodiment of the present invention and a periphery of the transistor 750. The transistor 750 can be applied to the display device of one embodiment of the present invention.

[0218] FIG. 19A is a top view of the transistor 750. FIGS. 19B and 19C are cross-sectional views of the transistor 750. FIG. 19B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 19A and is also a cross-sectional view of the transistor 750 in the channel length direction. FIG. 19C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 19A and is also a cross-sectional view of the transistor 750 in the channel width direction. Note that some elements are omitted from the top view in FIG. 19A for clarity.

[0219] As shown in FIG. 19 , the transistor 750 includes a metal oxide 230 a disposed on a substrate (not shown), a metal oxide 230 b disposed on the metal oxide 230 a, a conductor 242 a and a conductor 242 b disposed spaced apart from each other on the metal oxide 230 b, an insulator 280 disposed on the conductors 242 a and 242 b and having an opening formed between the conductors 242 a and 242 b, a conductor 260 disposed in the opening, an insulator 250 disposed among the metal oxide 230 b, the conductors 242 a, the conductors 242 b, the insulator 280, and the conductor 260, and a metal oxide 230 c disposed among the metal oxide 230 b, the conductors 242 a, the conductors 242 b, the insulator 280, and the insulator 250. 19B and 19C , it is preferable that the top surface of the conductor 260 approximately coincides with the top surfaces of the insulators 250, 254, metal oxide 230c, and 280. Note that, hereinafter, the metal oxides 230a, 230b, and 230c may be collectively referred to as the metal oxides 230. Furthermore, the conductors 242a and 242b may be collectively referred to as the conductors 242.

[0220] 19 , the side surfaces of the conductors 242a and 242b facing the conductor 260 have a substantially vertical shape. Note that the transistor 750 shown in FIG. 19 is not limited to this, and the angle formed between the side surface and the bottom surface of the conductors 242a and 242b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductors 242a and 242b may have multiple surfaces.

[0221] 19 , it is preferable that an insulator 254 be disposed between the insulator 224, the metal oxide 230a, the metal oxide 230b, the conductor 242a, the conductor 242b, and the metal oxide 230c and the insulator 280. Here, it is preferable that the insulator 254 be in contact with the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and the metal oxide 230b, and the top surface of the insulator 224, as shown in FIGS.

[0222] Although the transistor 750 has a three-layer structure including the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c in and around a region where a channel is formed (hereinafter also referred to as a channel formation region), the present invention is not limited to this structure. For example, a two-layer structure including the metal oxide 230b and the metal oxide 230c or a stacked structure of four or more layers may be provided. Although the transistor 750 has a two-layer structure including the conductor 260, the present invention is not limited to this structure. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Each of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may have a stacked structure of two or more layers.

[0223] For example, when metal oxide 230c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of metal oxide 230b, and the second metal oxide has a composition similar to that of metal oxide 230a.

[0224] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as source and drain electrodes, respectively. As described above, the conductor 260 is formed so as to be embedded in the opening of the insulator 280 and in the region sandwiched between the conductors 242a and 242b. Here, the arrangements of the conductors 260, 242a, and 242b are selected in a self-aligned manner with respect to the opening of the insulator 280. That is, in the transistor 750, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 260 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 750. This allows the display device to have high resolution. Furthermore, the display device can have a narrow frame.

[0225] As shown in FIG. 19, the conductor 260 preferably has a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be embedded inside the conductor 260a.

[0226] The transistor 750 preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, and an insulator 224 disposed on the insulator 222. A metal oxide 230a is preferably disposed on the insulator 224.

[0227] The insulator 274, which functions as an interlayer film, and the insulator 281 are preferably provided over the transistor 750. Here, the insulator 274 is preferably provided in contact with top surfaces of the conductor 260, the insulator 250, the insulator 254, the metal oxide 230c, and the insulator 280.

[0228] It is preferable that the insulators 222, 254, and 274 have the function of suppressing the diffusion of at least one of hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, it is preferable that the insulators 222, 254, and 274 have lower hydrogen permeability than the insulators 224, 250, and 280. It is also preferable that the insulators 222 and 254 have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, it is preferable that the insulators 222 and 254 have lower oxygen permeability than the insulators 224, 250, and 280.

[0229] Here, the insulator 224, the metal oxide 230, and the insulator 250 are separated by the insulators 280 and 281, and the insulators 254 and 274. Therefore, impurities such as hydrogen contained in the insulators 280 and 281, or excess oxygen, can be prevented from being mixed into the insulators 224, the metal oxide 230a, the metal oxide 230b, and the insulator 250.

[0230] It is preferable that a conductor 240 (conductor 240a and conductor 240b) electrically connected to the transistor 750 and functioning as a plug be provided. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 functioning as a plug. That is, the insulator 241 is provided in contact with the inner walls of the openings of the insulators 254, 280, 274, and 281. Alternatively, a first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 240 may be provided further inside. Here, the height of the top surface of the conductor 240 and the height of the insulator 281 can be made approximately the same. Note that, although the transistor 750 illustrates a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be configured to have a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, the layers may be distinguished by assigning ordinal numbers to indicate the order of formation.

[0231] In the transistor 750, a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide 230 (the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c) including the channel formation region. For example, a metal oxide that serves as the channel formation region of the metal oxide 230 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more.

[0232] The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). In addition to these, it is preferable that it contains element M. As element M, one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co) can be used. In particular, element M is preferably one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is more preferable that element M contains either one or both of Ga and Sn.

[0233] 19B , the film thickness of the metal oxide 230b in the region that does not overlap with the conductor 242 may be thinner than the film thickness of the region that overlaps with the conductor 242. This is formed by removing a portion of the upper surface of the metal oxide 230b when forming the conductors 242a and 242b. When a conductive film that will become the conductor 242 is formed on the upper surface of the metal oxide 230b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region located between the conductors 242a and 242b on the upper surface of the metal oxide 230b, it is possible to prevent a channel from being formed in that region.

[0234] According to one embodiment of the present invention, a display device having high definition and a small transistor can be provided. Alternatively, a display device having high luminance and a transistor with high on-state current can be provided. Alternatively, a display device having high-speed operation and a transistor with stable electrical characteristics can be provided. Alternatively, a display device having low power consumption and a transistor with low off-state current can be provided.

[0235] A detailed structure of a transistor 750 that can be used in a display device that is one embodiment of the present invention will be described.

[0236] The conductor 205 is arranged to have a region overlapping with the metal oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 216.

[0237] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and sidewall of an opening provided in the insulator 216. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the top surface of the conductor 205b is lower than the top surface of the conductor 205a and the top surface of the insulator 216. The conductor 205c is provided in contact with the top surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the top surface of the conductor 205c is approximately the same as the height of the top surface of the conductor 205a and the height of the top surface of the insulator 216. In other words, the conductor 205b is configured to be enclosed by the conductors 205a and 205c.

[0238] The conductors 205a and 205c are made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0239] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the metal oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be formed as a single layer or a stack of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0240] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0241] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the conductor 205 may be changed independently of the potential applied to the conductor 260, thereby controlling the V ｔｈ In particular, applying a negative potential to the conductor 205 can control the V ｔｈ Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when no negative potential is applied.

[0242] The conductor 205 is preferably provided to be larger than the channel formation region in the metal oxide 230. In particular, as shown in Fig. 19C, the conductor 205 preferably extends also in a region outside the end portion intersecting with the channel width direction of the metal oxide 230. In other words, the conductor 205 and the conductor 260 preferably overlap with each other with an insulator interposed therebetween on the outside of the side surface of the metal oxide 230 in the channel width direction.

[0243] With the above structure, the channel formation region of the metal oxide 230 can be electrically surrounded by the electric field of the conductor 260 that functions as a first gate electrode and the electric field of the conductor 205 that functions as a second gate electrode.

[0244] 19C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205.

[0245] The insulator 214 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 750 from the substrate side. Therefore, the insulator 214 prevents hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., copper atoms are less likely to penetrate the impurities), or that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is less likely to penetrate the insulating material).

[0246] For example, aluminum oxide, silicon nitride, or the like is preferably used as the insulator 214. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulator 214 to the transistor 750 side. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing to the substrate side of the insulator 214.

[0247] The insulators 216, 280, and 281, which function as interlayer films, preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 216, 280, and 281.

[0248] The insulators 222 and 224 function as gate insulators.

[0249] Here, the insulator 224 in contact with the metal oxide 230 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be reduced and the reliability of the transistor 750 can be improved.

[0250] Specifically, an oxide material from which some oxygen is released by heating is preferably used as the insulator 224. The oxide from which oxygen is released by heating is an oxide from which the amount of released oxygen converted into oxygen atoms is 1.0×10 in thermal desorption spectroscopy (TDS) analysis. １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0251] 19C , the thickness of the region of insulator 224 that does not overlap with insulator 254 and metal oxide 230b may be thinner than the thickness of the other region. It is preferable that the thickness of the region of insulator 224 that does not overlap with insulator 254 and metal oxide 230b is a thickness that allows sufficient diffusion of the oxygen.

[0252] Like the insulator 214 and the like, the insulator 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 750 from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the metal oxide 230, the insulator 250, and the like with the insulators 222, 254, and 274, impurities such as water or hydrogen can be prevented from entering the transistor 750 from the outside.

[0253] Furthermore, it is preferable that the insulator 222 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. The insulator 222 has a function of suppressing the diffusion of oxygen or impurities, etc., which is preferable because it can reduce the diffusion of oxygen contained in the metal oxide 230 toward the substrate side. Furthermore, it can suppress the reaction of the conductor 205 with the insulator 224 or oxygen contained in the metal oxide 230.

[0254] The insulator 222 may be an insulator containing an oxide of one or both of insulating materials, such as aluminum and hafnium. Examples of the insulator containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the metal oxide 230 or the intrusion of impurities such as hydrogen into the metal oxide 230 from the periphery of the transistor 750.

[0255] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0256] The insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ Insulators containing so-called high-k materials such as BST may be used in a single layer or a multilayer configuration. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0257] The insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. For example, an insulator similar to the insulator 224 may be provided below the insulator 222.

[0258] The metal oxide 230 includes a metal oxide 230a, a metal oxide 230b on the metal oxide 230a, and a metal oxide 230c on the metal oxide 230b. By providing the metal oxide 230a below the metal oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the metal oxide 230a to the metal oxide 230b. Furthermore, by providing the metal oxide 230c on the metal oxide 230b, it is possible to suppress the diffusion of impurities from structures formed above the metal oxide 230c to the metal oxide 230b.

[0259] The metal oxide 230 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, when the metal oxide 230 contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the metal oxide 230a to the number of atoms of all elements constituting the metal oxide 230a is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 230b to the number of atoms of all elements constituting the metal oxide 230b. Furthermore, the atomic ratio of the element M contained in the metal oxide 230a to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 230b to In. Here, the metal oxide 230c can be the same as the metal oxide 230a or the metal oxide 230b.

[0260] The energy of the conduction band minimum of the metal oxide 230a and the metal oxide 230c is preferably higher than the energy of the conduction band minimum of the metal oxide 230b. In other words, the electron affinity of the metal oxide 230a and the metal oxide 230c is preferably lower than the electron affinity of the metal oxide 230b. In this case, the metal oxide 230c is preferably a metal oxide that can be used for the metal oxide 230a. Specifically, the ratio of the number of atoms of the element M contained in the metal oxide 230c to the number of atoms of all elements constituting the metal oxide 230c is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 230b to the number of atoms of all elements constituting the metal oxide 230b. Furthermore, the atomic ratio of the element M contained in the metal oxide 230c to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 230c to In.

[0261] Here, the energy level of the conduction band minimum changes smoothly at the junction between the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c. In other words, the energy level of the conduction band minimum at the junction between the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c changes continuously or can be said to be a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the metal oxide 230a and the metal oxide 230b and the interface between the metal oxide 230b and the metal oxide 230c.

[0262] Specifically, the metal oxide 230a and the metal oxide 230b, and the metal oxide 230b and the metal oxide 230c, have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low defect level density. For example, when the metal oxide 230b is an In—Ga—Zn oxide, the metal oxide 230a and the metal oxide 230c may be made of an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like. The metal oxide 230c may also have a stacked structure. For example, a stacked structure of an In—Ga—Zn oxide and a Ga—Zn oxide on the In—Ga—Zn oxide, or a stacked structure of an In—Ga—Zn oxide and a gallium oxide on the In—Ga—Zn oxide, may be used. In other words, a stacked structure of an In—Ga—Zn oxide and an oxide not containing In may be used as the metal oxide 230c.

[0263] Specifically, the metal oxide 230a may have an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. The metal oxide 230b may have an atomic ratio of In:Ga:Zn=4:2:3 or 3:1:2. The metal oxide 230c may have an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the metal oxide 230c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0264] In this case, the main carrier path is the metal oxide 230b. By configuring the metal oxide 230a and the metal oxide 230c as described above, the defect state density at the interface between the metal oxide 230a and the metal oxide 230b and at the interface between the metal oxide 230b and the metal oxide 230c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 750 to achieve a high on-state current and high frequency characteristics. Note that when the metal oxide 230c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the metal oxide 230b and the metal oxide 230c, it is expected that the diffusion of constituent elements of the metal oxide 230c toward the insulator 250 can be suppressed. More specifically, since the metal oxide 230c has a stacked structure and an oxide not containing In is located above the stacked structure, it is possible to suppress In that may diffuse toward the insulator 250. The insulator 250 functions as a gate insulator, and diffusion of In causes poor transistor characteristics. Therefore, by forming the metal oxide 230c into a stacked structure, it is possible to provide a highly reliable display device.

[0265] Conductors 242 (conductors 242a and 242b) functioning as a source electrode and a drain electrode are provided on the metal oxide 230b. The conductor 242 is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when they absorb oxygen.

[0266] By providing the conductor 242 so as to be in contact with the metal oxide 230, the oxygen concentration may be reduced in the vicinity of the conductor 242 of the metal oxide 230. Furthermore, a metal compound layer containing the metal contained in the conductor 242 and components of the metal oxide 230 may be formed in the vicinity of the conductor 242 of the metal oxide 230. In such a case, the carrier density increases in the region of the metal oxide 230 in the vicinity of the conductor 242, and this region becomes a low-resistance region.

[0267] Here, the region between the conductor 242a and the conductor 242b is formed to overlap the opening of the insulator 280. This allows the conductor 260 to be arranged in a self-aligned manner between the conductor 242a and the conductor 242b.

[0268] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the metal oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0269] The insulator 250 preferably has a reduced concentration of impurities such as water or hydrogen, similar to the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0270] A metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. This makes it possible to suppress oxidation of the conductor 260 due to oxygen in the insulator 250.

[0271] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator into a stacked structure of the insulator 250 and the metal oxide, a stacked structure that is stable against heat and has a high dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0272] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0273] Although the conductor 260 is shown as having a two-layer structure in FIG. 19, it may have a single-layer structure or a laminated structure of three or more layers.

[0274] The conductor 260a is a material containing the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductor having a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0275] The conductor 260a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0276] The conductor 260b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 260b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0277] 19A and 19C , in a region of the metal oxide 230b that does not overlap with the conductor 242, in other words, in the channel formation region of the metal oxide 230, the side surface of the metal oxide 230 is arranged to be covered with the conductor 260. This makes it easier for the electric field of the conductor 260, which functions as the first gate electrode, to act on the side surface of the metal oxide 230. Therefore, the on-state current of the transistor 750 can be increased, and the frequency characteristics can be improved.

[0278] Like the insulator 214, the insulator 254 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 750 from the insulator 280 side. For example, the insulator 254 preferably has lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIGS. 19B and 19C , the insulator 254 preferably contacts the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and the metal oxide 230b, and the top surface of the insulator 224. This structure can prevent hydrogen contained in the insulator 280 from entering the metal oxide 230 from the top or side surfaces of the conductor 242a, the conductor 242b, the metal oxide 230a, the metal oxide 230b, and the insulator 224.

[0279] Furthermore, it is preferable that the insulator 254 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, it is preferable that the insulator 254 has lower oxygen permeability than the insulator 280 or the insulator 224.

[0280] The insulator 254 is preferably formed by a sputtering method. By forming the insulator 254 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulator 224 near a region in contact with the insulator 254. This allows oxygen to be supplied from this region into the metal oxide 230 through the insulator 224. The insulator 254 has a function of suppressing upward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 230 to the insulator 280. The insulator 222 has a function of suppressing downward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 230 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the metal oxide 230. This reduces oxygen vacancies in the metal oxide 230 and suppresses the transistor from becoming normally on.

[0281] For example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as the insulator 254. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.

[0282] The insulator 224, the insulator 250, and the metal oxide 230 are covered with the insulator 254, which has a barrier property against hydrogen, so that the insulator 280 is separated from the insulator 224, the metal oxide 230, and the insulator 250 by the insulator 254. This can prevent impurities such as hydrogen from penetrating from the outside of the transistor 750, thereby providing the transistor 750 with good electrical characteristics and reliability.

[0283] The insulator 280 is provided over the insulator 224, the metal oxide 230, and the conductor 242 with the insulator 254 interposed therebetween. For example, the insulator 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is released by heating.

[0284] It is preferable that the concentration of impurities such as water or hydrogen is reduced in the insulator 280. The top surface of the insulator 280 may be flattened.

[0285] Similar to the insulator 214, the insulator 274 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 280 from above. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 254, etc. may be used.

[0286] An insulator 281 functioning as an interlayer film is preferably provided over the insulator 274. Like the insulator 224, the insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen.

[0287] The conductor 240a and the conductor 240b are arranged in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductor 240a and the conductor 240b are provided opposite each other with the conductor 260 interposed therebetween. Note that the height of the top surfaces of the conductor 240a and the conductor 240b may be flush with the top surface of the insulator 281.

[0288] Note that insulator 241a is provided in contact with the inner walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240a is formed in contact with the side surface of insulator 241a. Conductor 242a is located on at least a portion of the bottom of the openings, and conductor 240a is in contact with conductor 242a. Similarly, insulator 241b is provided in contact with the inner walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240b is formed in contact with the side surface of insulator 241b. Conductor 242b is located on at least a portion of the bottom of the openings, and conductor 240b is in contact with conductor 242b.

[0289] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0290] When the conductor 240 has a layered structure, it is preferable to use the above-mentioned conductors having the function of suppressing the diffusion of impurities such as water or hydrogen for the conductors in contact with the metal oxide 230a, the metal oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material having the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a layered structure. By using such a conductive material, it is possible to suppress the absorption of oxygen added to the insulator 280 by the conductors 240a and 240b. It is also possible to suppress the intrusion of impurities such as water or hydrogen from layers above the insulator 281 into the metal oxide 230 through the conductors 240a and 240b.

[0291] The insulators 241a and 241b may be, for example, an insulator that can be used for the insulator 254. The insulators 241a and 241b are provided in contact with the insulator 254, and therefore can prevent impurities such as water or hydrogen from the insulator 280 from being mixed into the metal oxide 230 through the conductors 240a and 240b. Furthermore, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0292] Although not shown, a conductor functioning as wiring may be disposed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0293] <Constituent Materials of Transistor> Constituent materials that can be used for the transistor will be described.

[0294] [Substrate] For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used as a substrate on which a transistor is formed. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0295] [Insulator] Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0296] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0297] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0298] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0299] The electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator (such as the insulator 214, the insulator 222, the insulator 254, and the insulator 274) that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, a single-layer or stacked insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide; and metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0300] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be compensated for.

[0301] [Conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0302] A plurality of conductors formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0303] When a metal oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure of a combination of a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0304] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the above-mentioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0305] <Classification of Crystal Structures in Oxide Semiconductors> Classification of crystal structures in oxide semiconductors will be described with reference to Fig. 20A. Fig. 20A is a diagram illustrating the classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0306] As shown in FIG. 20A , oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." Furthermore, "amorphous" includes completely amorphous. Furthermore, "crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "crystalline" classification excludes single crystal, polycrystalline, and completely amorphous. Furthermore, "Crystal" includes single crystal and poly crystal.

[0307] The structure within the bold frame shown in Figure 20A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "Amorphous" or "Crystal."

[0308] The crystalline structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, FIG. 20B shows an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in FIG. 20B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 20B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 20B is 500 nm.

[0309] As shown in Figure 20B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 20B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0310] The crystalline structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 20C. FIG. 20C is a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 20C is near In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron beam diffraction is performed using a probe diameter of 1 nm.

[0311] As shown in FIG. 20C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0312] [Structure of Oxide Semiconductor] Note that oxide semiconductors may be classified differently from those shown in FIG. 20A when focusing on their crystal structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0313] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0314] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0315] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nanometers.

[0316] In an In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0317] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type, composition, and the like of the metal elements constituting the CAAC-OS.

[0318] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the spots are observed at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0319] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of a dense arrangement of oxygen atoms in the a-b plane direction or the change in interatomic bond distance caused by metal atom substitution.

[0320] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0321] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (oxygen vacancies, etc.). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0322] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0323] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0324] [Structure of Oxide Semiconductor] Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0325] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0326] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0327] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0328] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0329] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0330] For example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0331] When a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0332] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0333] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0334] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0335] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ Less than 1×10, more preferably 1×10 １１ cm −３ More preferably, 1×10 １０ cm −３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0336] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore, the density of trap states may also be low.

[0337] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0338] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0339] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0340] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by SIMS) are calculated to be 2×10 １８ atoms / cm ３ Below 2 × 10, preferably １７ atoms / cm ３ The following applies.

[0341] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0342] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0343] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0344] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0345] 21A , the EL layer 786 of the display element 61 can be composed of a plurality of layers, such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can include, for example, a layer containing a substance with a high electron injection property (electron injection layer) and a layer containing a substance with a high electron transport property (electron transport layer). The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 can include, for example, a layer containing a substance with a high hole injection property (hole injection layer) and a layer containing a substance with a high hole transport property (hole transport layer).

[0346] A structure having the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 21A is referred to as a single structure in this specification.

[0347] 21B shows a modified example of the EL layer 786 included in the display element 61 shown in Fig. 21A. Specifically, the display element 61 shown in Fig. 21B includes a layer 4430-1 on the conductor 772, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductor 788 on the layer 4420-2. For example, when the conductor 772 serves as an anode and the conductor 788 serves as a cathode, the layer 4430-1 functions as a hole-injection layer, the layer 4430-2 functions as a hole-transport layer, the layer 4420-1 functions as an electron-transport layer, and the layer 4420-2 functions as an electron-injection layer. Alternatively, when the conductor 772 is a cathode and the conductor 788 is an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. With such a layer structure, carriers can be efficiently injected into the light-emitting layer 4411, and the efficiency of carrier recombination in the light-emitting layer 4411 can be increased.

[0348] As shown in FIG. 21C, a configuration in which a plurality of light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0349] 21D, a configuration in which a plurality of light-emitting units (EL layers 786a, 786b) are connected in series via an intermediate layer (charge generating layer) 4440 is referred to as a tandem structure in this specification. Note that although the configuration shown in FIG. 21D is referred to as a tandem structure in this specification and the like, this is not limiting, and for example, the tandem structure may also be referred to as a stack structure. Note that by using a tandem structure, a light-emitting element capable of emitting light with high brightness can be obtained.

[0350] 21C and 21D, the layer 4420 and the layer 4430 may have a laminated structure consisting of two or more layers, as shown in FIG. 21B.

[0351] The emission color of the display element 61 can be red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material constituting the EL layer 786. Furthermore, by providing the display element 61 with a microcavity structure, the color purity can be further improved.

[0352] A light-emitting element that emits white light preferably has a structure in which two or more kinds of light-emitting substances are contained in the light-emitting layer. To obtain white light emission, light-emitting substances may be selected such that the respective emissions of the two or more light-emitting substances are in a complementary color relationship.

[0353] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0354] <Method of Forming Display Element 61> Hereinafter, a method of forming the display element 61 will be described.

[0355] FIG. 22A shows a schematic top view of display elements 61_R, 61_G, and 61_B applicable to the display element 61. The display element 61_R is a light-emitting element that emits red light, the display element 61_G is a light-emitting element that emits green light, and the display element 61_B is a light-emitting element that emits blue light. In FIG. 22A , the symbols R, G, and B are assigned within the light-emitting region of each light-emitting element to simplify the distinction between the light-emitting elements. Note that the configuration shown in FIG. 22A may also be referred to as an SBS (Side By Side) structure. Furthermore, the configuration shown in FIG. 22A illustrates a configuration having three colors, red (R), green (G), and blue (B), but is not limited to this. For example, a configuration having four or more colors may also be used.

[0356] The display elements 61_R, 61_G, and 61_B are arranged in a matrix. Fig. 22A shows a so-called stripe arrangement in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement of the light-emitting elements is not limited to this, and other arrangements such as a delta arrangement or a zigzag arrangement may also be used, or a pentile arrangement may also be used.

[0357] As the display elements 61_R, 61_G, and 61_B, it is preferable to use an organic EL device such as an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode). Examples of light-emitting materials that the EL elements have include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (TADF) materials.

[0358] FIG. 22B is a schematic cross-sectional view corresponding to the dashed dotted line A1-A2 in FIG. 22A.

[0359] 22B shows cross sections of the display elements 61_R, 61_G, and 61_B. Each of the display elements 61_R, 61_G, and 61_B is provided over a substrate 751 and includes a conductor 772 that functions as a pixel electrode and a conductor 788 that functions as a common electrode.

[0360] The display element 61_R includes an EL layer 786R between the conductor 772 and the conductor 788. The EL layer 786R includes a light-emitting organic compound that emits light having a peak in at least a red wavelength range. The EL layer 786G included in the display element 61_G includes a light-emitting organic compound that emits light having a peak in at least a green wavelength range. The EL layer 786B included in the display element 61_B includes a light-emitting organic compound that emits light having a peak in at least a blue wavelength range.

[0361] The EL layer 786R, the EL layer 786G, and the EL layer 786B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0362] The conductor 772 is provided for each light-emitting element. The conductor 788 is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductor 772 or the conductor 788 functioning as a common electrode, and a conductive film that is reflective is used for the other. By making the conductor 772 light-transmitting and the conductor 788 reflective, a bottom-emission display device can be obtained. Conversely, by making the conductor 772 reflective and the conductor 788 light-transmitting, a top-emission display device can be obtained. Note that by making both the conductor 772 and the conductor 788 light-transmitting, a dual-emission display device can also be obtained.

[0363] An insulating layer 755 is provided to cover the end portion of the conductor 772. The end portion of the insulating layer 755 preferably has a tapered shape.

[0364] The EL layer 786R, the EL layer 786G, and the EL layer 786B each have a region in contact with the top surface of the conductor 772 and a region in contact with the surface of the insulating layer 755. Ends of the EL layer 786R, the EL layer 786G, and the EL layer 786B are located over the insulating layer 755.

[0365] 22B , a gap is provided between two EL layers between light-emitting elements of different colors. In this manner, the EL layer 786R, the EL layer 786G, and the EL layer 786B are preferably provided so as not to be in contact with each other. This can suitably prevent current from flowing through two adjacent EL layers, thereby preventing unintended light emission (also known as crosstalk). Therefore, contrast can be increased, and a display device with high display quality can be realized.

[0366] The EL layers 786R, 786G, and 786B can be separately formed by vacuum deposition using a shadow mask such as a metal mask. Alternatively, they may be separately formed by photolithography. By using photolithography, a high-definition display device can be realized, which is difficult to achieve when a metal mask is used.

[0367] In addition, a protective layer 756 is provided over the conductor 788 to cover the display elements 61_R, 61_G, and 61_B. The protective layer 756 has a function of preventing impurities such as water from diffusing from above to each light-emitting element.

[0368] The protective layer 756 can have, for example, a single-layer structure or a stacked-layer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used for the protective layer 756. Note that the protective layer 756 may be formed by an ALD method, a CVD method, or a sputtering method. Note that, although the protective layer 756 includes an inorganic insulating film, this is not limiting. For example, the protective layer 756 may have a stacked-layer structure of an inorganic insulating film and an organic insulating film.

[0369] FIG. 22C shows a different example from the above.

[0370] 22C includes a display element 61_W that emits white light. The display element 61_W includes an EL layer 786W that emits white light between a conductor 772 and a conductor 788.

[0371] The EL layer 786W may be configured, for example, by stacking two or more light-emitting layers selected so that the emitted light colors are complementary to each other. Alternatively, a stacked EL layer having a charge generating layer sandwiched between light-emitting layers, i.e., a tandem structure EL layer, may be used. Note that the tandem structure allows for a light-emitting element capable of emitting light with high brightness.

[0372] 22C shows three display elements 61_W lined up. A colored layer 757R is provided on the top of the left display element 61_W. The colored layer 757R functions as a bandpass filter that transmits red light. Similarly, a colored layer 757G that transmits green light is provided on the top of the center display element 61_W, and a colored layer 757B that transmits blue light is provided on the top of the right display element 61_W. This allows the display device to display color images.

[0373] Here, the EL layer 786W and the conductor 788 are separated between two adjacent display elements 61_W. This effectively prevents current from flowing through the EL layer 786W between the two adjacent display elements 61_W, which would otherwise cause unintended light emission. In particular, when a stacked EL element in which a charge generating layer is provided between two light-emitting layers is used as the EL layer 786W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using such a configuration, a display device that combines high resolution and high contrast can be realized.

[0374] The EL layer 786W and the conductor 788 are preferably separated by photolithography, which allows the interval between light-emitting elements to be narrowed, thereby realizing a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0375] In the case of a bottom-emission light-emitting element, a colored layer may be provided between the conductor 772 and the substrate 751 .

[0376] FIG. 22D shows an example different from the above. Specifically, FIG. 22D shows a structure in which the insulating layer 755 is not provided between the display element 61_R, the display element 61_G, and the display element 61_B. This structure enables a display device with a high aperture ratio. Furthermore, the protective layer 756 covers the side surfaces of the display element 61_R, the display element 61_G, and the display element 61_B. This structure can suppress impurities (typically, water) that may enter through the side surfaces of the display element 61_R, the display element 61_G, and the display element 61_B. Furthermore, in the structure shown in FIG. 22D , the conductor 772, the EL layer 786R, and the conductor 788 have generally the same top surface shape. This structure can be formed collectively using a resist mask or the like after the conductor 772, the EL layer 786R, and the conductor 788 are formed. Such a process can also be called self-aligned patterning because the EL layer 786R and the conductor 788 are processed using the conductor 788 as a mask. Note that although the display element 61_R has been described here, the display element 61_G and the display element 61_B can also have a similar structure.

[0377] 22D shows a structure in which a protective layer 758 is further provided on the protective layer 756. For example, the protective layer 756 is formed using an apparatus (typically, an ALD apparatus) capable of depositing a film with high coverage, and the protective layer 758 is formed using an apparatus (typically, a sputtering apparatus) capable of depositing a film with lower coverage than the protective layer 756, whereby a gap 759 can be provided between the protective layer 756 and the protective layer 758. In other words, the gap 759 is located between the display element 61_R and the display element 61_G, and between the display element 61_G and the display element 61_B.

[0378] The voids 759 contain, for example, one or more selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, krypton, etc.). The voids 759 may also contain, for example, a gas used when forming the protective layer 758. For example, when the protective layer 758 is formed by sputtering, the voids 759 may contain one or more of the above Group 18 elements. When the voids 759 contain a gas, the gas can be identified by gas chromatography or the like. When the protective layer 758 is formed by sputtering, the gas used during sputtering may also be contained in the protective layer 758. In this case, elements such as argon may be detected when the protective layer 758 is analyzed by energy dispersive X-ray analysis (EDX analysis) or the like.

[0379] Furthermore, when the refractive index of the void 759 is lower than the refractive index of the protective layer 756, light emitted from the display element 61_R, the display element 61_G, or the display element 61_B is reflected at the interface between the protective layer 756 and the void 759. This prevents the light emitted from the display element 61_R, the display element 61_G, or the display element 61_B from entering an adjacent pixel. This prevents light of different colors from mixing, thereby improving the image quality of the display device.

[0380] 22D , the area between the display element 61_R and the display element 61_G or the area between the display element 61_G and the display element 61_B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be set to 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of the display element 61_R and the side surface of the display element 61_G or the distance between the side surface of the display element 61_G and the side surface of the display element 61_B has an area of ​​1 μm or less, preferably an area of ​​0.5 μm (500 nm) or less, and more preferably an area of ​​100 nm or less.

[0381] 22D can be referred to as an air isolation structure, for example, when the void 759 contains air. The air isolation structure can isolate the light emitting elements while suppressing color mixing or crosstalk of light from the light emitting elements.

[0382] FIG. 23A shows an example different from the above. Specifically, the structure shown in FIG. 23A differs from the structure shown in FIG. 22D in the structure of the substrate 751. The substrate 751 has a recess formed by removing a portion of its upper surface during processing of the display elements 61_R, 61_G, and 61_B. A protective layer 756 is formed in the recess. In other words, the substrate 751 has a region where the lower surface of the protective layer 756 is located lower than the lower surface of the conductor 772 in a cross-sectional view. By providing this region, impurities (typically, water, etc.) that may enter the display elements 61_R, 61_G, and 61_B from below can be suitably suppressed. Note that the recess can be formed when impurities (also referred to as residue) that may adhere to the side surfaces of the light-emitting elements during processing of the display elements 61_R, 61_G, and 61_B are removed by wet etching or the like. After removing the residue, the side surfaces of the light-emitting elements are covered with a protective layer 756, whereby a highly reliable display device can be obtained.

[0383] FIG. 23B also shows a different example. Specifically, the configuration shown in FIG. 23B includes an insulating layer 776 and a microlens array 777 in addition to the configuration shown in FIG. 23A . The insulating layer 776 functions as an adhesive layer. Note that if the refractive index of the insulating layer 776 is lower than that of the microlens array 777, the microlens array 777 can focus light emitted from the display elements 61_R, 61_G, and 61_B. This improves the light extraction efficiency of the display device. This is particularly advantageous because it allows a bright image to be viewed when a user views the display surface from directly in front of the display surface. Note that various curing adhesives, such as a photo-curing adhesive (e.g., an ultraviolet curing adhesive), a reactive curing adhesive, a thermosetting adhesive, or an anaerobic adhesive, can be used as the insulating layer 776. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, materials with low moisture permeability, such as epoxy resin, are preferred. Two-component resins may also be used. Adhesive sheets may also be used.

[0384] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes will be given regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0385] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0386] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0387] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0388] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0389] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0390] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0391] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0392] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0393] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0394] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0395] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0396] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0397] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0398] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, transmission of an electrical signal between A and B is possible.

[0399] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0400] In this specification and the like, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification and the like, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (for example, a color filter) to realize a full-color display device.

[0401] Furthermore, light-emitting devices can be broadly divided into single structures and tandem structures. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, two or more light-emitting layers may be selected so that the light emitted from each of the two or more light-emitting layers has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration in which the entire light-emitting device emits white light can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0402] A tandem-structure device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, light from the light-emitting layers of the light-emitting units may be combined to obtain white light emission. The configuration for obtaining white light emission is the same as that of the single-structure device. In a tandem-structure device, it is preferable to provide an intermediate layer such as a charge-generating layer between the light-emitting units.

[0403] Furthermore, when comparing the above-described white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If it is desired to reduce power consumption, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0404] 10_L: display device, 10_R: display device, 30: drive circuit, 40: functional circuit, 51: pixel circuit, 61: display element, 100: electronic device, 101: motion detection unit, 102: line of sight detection unit, 103: calculation unit, 104: communication unit, 105: housing

Claims

1. A device having a housing, a display device, a calculation unit, a gaze detection unit, and a motion detection unit, the display device includes a display unit having a plurality of display elements and a plurality of pixel circuits, a plurality of drive circuits having a function of driving the plurality of pixel circuits for each section, and a functional circuit; the motion detection unit has a function of detecting a motion of the housing, The line-of-sight detection unit has a function of detecting a gaze point according to a line of sight of a user on the display unit, the calculation unit has a function of performing a drawing process in accordance with a movement of the housing, and a function of dividing the display unit into at least a first area and a second area in accordance with the gaze point; The first region has a region overlapping with the gaze point, the second region has a region located around the first region, the functional circuit has a function of controlling a drive frequency of the drive circuit, among the plurality of drive circuits, arranged in a section corresponding to the first region, so as to be higher than a drive frequency of the drive circuit arranged in a section corresponding to the second region. electronic equipment.

2. A device having a housing, a display device, a calculation unit, a gaze detection unit, and a motion detection unit, the display device includes a display unit having a plurality of display elements and a plurality of pixel circuits, a plurality of drive circuits having a function of driving the plurality of pixel circuits for each section, and a functional circuit; the motion detection unit has a function of detecting a motion of the housing, The line-of-sight detection unit has a function of detecting a gaze point according to a line of sight of a user on the display unit, the calculation unit has a function of performing a drawing process in accordance with a movement of the housing, and a function of dividing the display unit into at least a first area and a second area in accordance with the gaze point; The first region has a region overlapping with the gaze point, the second region has a region located around the first region, the functional circuit has a function of controlling a drive frequency of the drive circuit arranged in a section corresponding to the first region among the plurality of drive circuits so as to be higher than a drive frequency of the drive circuit arranged in a section corresponding to the second region; the plurality of driving circuits and the functional circuit are disposed in a first layer of the display device; the plurality of pixel circuits are arranged in a second layer of the display device; The second layer is located above the first layer. electronic equipment.

3. In claim 2, the first layer includes a first transistor having silicon in a channel formation region; the second layer includes a second transistor having a metal oxide in a channel formation region; electronic equipment.

4. In claim 3, The metal oxide comprises In, an element M (wherein M is Al, Ga, Y, or Sn), and Zn; electronic equipment.

5. In any one of claims 1 to 4, Each of the plurality of driving circuits includes a gate driver circuit and a source driver circuit. electronic equipment.