head-mounted display

Abstract

The present invention provides a display device having a novel configuration. The display device includes a display unit in which a first transistor and a display element are provided stacked on one another. The display unit includes a first sub-display unit and a second sub-display unit. The first sub-display unit and the second sub-display unit each include a plurality of pixel circuits that control the display element and a gate line driving circuit that outputs signals for driving the plurality of pixel circuits. The gate line driving circuit and the plurality of pixel circuits each include a first transistor. In the display unit, the number of times image data in the first sub-display unit is rewritten per unit time is less than the number of times image data in the second sub-display unit is rewritten per unit time.

Description

Display device and electronic device having the display device

[0001] This specification describes a display device, an electronic device having the display device, and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] Display devices are applied to a variety of electronic devices, including portable information terminals such as smartphones, television devices, and head-mounted displays (HMDs) suitable for applications such as virtual reality (VR) and augmented reality (AR). Applications such as HMDs require display devices with narrow frame widths and low power consumption, as well as display performance with a high refresh rate of, for example, 120 Hz or higher. For example, Patent Document 1 discloses an HMD with fine pixels achieved by using transistors capable of high-speed operation.

[0004] Japanese Patent Application Laid-Open No. 2000-2856

[0005] In a display device, when displaying at a high refresh rate, it is desirable to use a transistor that can be switched at high speed. However, a transistor that can be switched at high speed has a large current (leakage current) that flows in the off state (also called a non-conducting state), making it difficult to display at a low refresh rate. When displaying at a low refresh rate, it is effective to use a transistor with a small leakage current as the transistor in the pixel circuit. However, when refreshing the entire screen, there is a risk of increasing power consumption in the driver circuit that drives the pixel circuit.

[0006] An object of one embodiment of the present invention is to provide a novel display device and an electronic device or the like including the display device.Another object of one embodiment of the present invention is to provide a display device with a novel structure that can suppress an increase in power consumption in a display device that performs display at a high refresh rate, and an electronic device or the like including the display device.Another object of one embodiment of the present invention is to provide a display device with a novel structure that is excellent in design.Another object of one embodiment of the present invention is to provide a display device with a novel structure that is highly convenient, and an electronic device or the like including the display device.

[0007] The description of multiple problems does not preclude the existence of each other's problems. One embodiment of the present invention does not necessarily solve all of the problems exemplified. Furthermore, problems other than those listed will become apparent from the description in this specification, and such problems may also be problems of one embodiment of the present invention.

[0008] One embodiment of the present invention is a display device having a display portion in which a first transistor and a display element are stacked, the display portion having a first sub-display portion and a second sub-display portion, each of the first sub-display portion and the second sub-display portion having a plurality of pixel circuits that control the display elements and a gate line driver circuit that outputs signals for driving the plurality of pixel circuits, the gate line driver circuit and the plurality of pixel circuits each having the first transistor, and in the display portion, the number of times image data is rewritten per unit time in the first sub-display portion is smaller than the number of times image data is rewritten per unit time in the second sub-display portion.

[0009] In one embodiment of the present invention, the semiconductor layer including the channel formation region of the first transistor preferably contains metal oxide.

[0010] One embodiment of the present invention is a display device that includes a display portion in which a first layer having a first transistor, a second layer having a second transistor, and a display element are stacked, the display portion having a first sub-display portion and a second sub-display portion, each of the first sub-display portion and the second sub-display portion having a plurality of pixel circuits that control the display elements provided in the sub-display portion and a gate line driver circuit that outputs signals for driving the plurality of pixel circuits, the gate line driver circuit having a first transistor and a second transistor, and each of the plurality of pixel circuits having the first transistor and the second transistor, and in the display portion, the number of times image data is rewritten per unit time in the first sub-display portion is smaller than the number of times image data is rewritten per unit time in the second sub-display portion.

[0011] One embodiment of the present invention is a display device that includes a display portion in which a first layer having a first transistor, a second layer having a second transistor, and a display element are stacked, the display portion having a first sub-display portion and a second sub-display portion, each of which has a plurality of pixel circuits that control the display elements provided in the sub-display portion and a gate line driver circuit that outputs signals for driving the plurality of pixel circuits, the gate line driver circuit having a first transistor and a second transistor, the plurality of pixel circuits each having the first transistor and the second transistor, and the second transistor having a metal oxide in a semiconductor layer having a channel formation region, and in which the number of times image data is rewritten per unit time in the first sub-display portion is smaller than the number of times image data is rewritten per unit time in the second sub-display portion.

[0012] In one embodiment of the present invention, the display device preferably includes a semiconductor layer in which the first transistor has a channel formation region and silicon.

[0013] In one embodiment of the present invention, the first transistor preferably includes a metal oxide in a semiconductor layer having a channel formation region.

[0014] In one embodiment of the present invention, a display device is preferably provided with a source line driver circuit in a region outside a display portion.

[0015] One embodiment of the present invention is a display device having a display unit in which a first layer having a first transistor and a display element are stacked, the display unit having a first sub-display unit and a second sub-display unit, the first sub-display unit and the second sub-display unit being provided in different display panels, the display panels each having a pixel circuit unit and a light-transmitting region, and the light-transmitting region in one of the display panels having a region that overlaps with the pixel circuit unit in the other of the display panels.

[0016] One embodiment of the present invention is an electronic device including the above display device and a housing.

[0017] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0018] One embodiment of the present invention can provide a novel display device and an electronic device, etc. including the display device. Alternatively, one embodiment of the present invention can provide a display device with a novel structure that can suppress an increase in power consumption in a display device that performs display at a high refresh rate, and an electronic device, etc. including the display device. Another object of one embodiment of the present invention is to provide a display device with a novel structure that is excellent in design. Alternatively, one embodiment of the present invention can provide a display device with a novel structure that is highly convenient, and an electronic device, etc. including the display device.

[0019] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification.

[0020] FIGS. 1A and 1B are diagrams illustrating an example of the configuration of a display device. FIGS. 2A to 2C are diagrams illustrating an example of the configuration of a display device. FIGS. 3A and 3B are diagrams illustrating an example of the configuration of a display device. FIGS. 4A to 4C are diagrams illustrating an example of the configuration of a display device. FIGS. 5A and 5B are diagrams illustrating an example of the configuration of a display device. FIG. 6 is a diagram illustrating an example of the configuration of a display device. FIGS. 7A to 7D are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 8A to 8D are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 9A to 9D are circuit diagrams and timing charts illustrating an example of the configuration of a display device. FIGS. 10A to 10C are circuit diagrams and timing charts illustrating an example of the configuration of a display device. FIGS. 11A and 11B are circuit diagrams and timing charts illustrating an example of the configuration of a display device. FIG. 12 is a circuit diagram illustrating an example of the configuration of a display device. FIG. 13 is a circuit diagram illustrating an example of the configuration of a display device. FIG. 14 is a circuit diagram illustrating an example of the configuration of a display device. FIG. 15 is a circuit diagram illustrating an example of the configuration of a display device. FIG. 16 is a circuit diagram illustrating an example of the configuration of a display device. FIG. 17 is a circuit diagram showing an example of the configuration of a display device. FIGS. 18A and 18B are diagrams showing an example of the configuration of a display device. FIGS. 19A and 19B are diagrams explaining an example of the configuration of a display device. FIG. 20 is a timing chart showing an example of the configuration of a display device. FIG. 21 is a timing chart showing an example of the configuration of a display device. FIG. 22 is a diagram explaining an example of the configuration of a display device. FIGS. 23A and 23B are diagrams explaining an example of the configuration of a display device. FIG. 24 is a diagram explaining an example of the configuration of a display device. FIGS. 25A to 25C are diagrams explaining an example of the configuration of a display device. FIGS. 26A to 26C are diagrams explaining an example of the configuration of a display device. FIGS. 27A to 27D are diagrams explaining an example of the configuration of a display device. FIG. 28 is a diagram explaining an example of the configuration of a display device. FIGS. 29A and 29B are diagrams explaining an example of the configuration of a display device. FIG. 30 is a diagram showing an example of the configuration of a display device. FIG. 31 is a diagram showing an example of the configuration of a display device. FIGS. 32A to 32F are diagrams explaining an example of the configuration of an electronic device. FIGS. 33A to 33E are diagrams explaining an example of the configuration of an electronic device. 34A to 34G are diagrams illustrating configuration examples of electronic devices.35A to 35D are diagrams illustrating configuration examples of electronic devices.

[0021] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0022] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0023] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0024] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0025] Furthermore, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "[n]", "[m, n]", etc. may be added to the reference numeral. For example, the second gate line GL is referred to as gate line GL[2].

[0026] Embodiment 1 A structural example of a display device which is one embodiment of the present invention will be described with reference to FIGS. 1A to 22. FIG.

[0027] 1A and 1B are schematic perspective views of a display device 200. The structure of a display device according to one embodiment of the present invention will be described with reference to FIGS.

[0028] The display device 200 has a substrate 11 and a substrate 12. The display device 200 has a display unit 13 that is composed of elements provided between the substrate 11 and the substrate 12. The display unit 13 is divided into a plurality of sections, one of which is referred to as a sub-display unit 13A.

[0029] In addition, in the display device 200, a layer 20, a layer 50, and a layer 60 are provided between the substrate 11 and the substrate 12. In addition, various signals and power supply potentials are input to the display device 200 from the outside via the terminal portion 14, and the display device 200 can perform display.

[0030] The layer 20 is provided with a plurality of gate line driving circuits for driving the display device 200. In the driving circuit section 30 provided with a plurality of gate line driving circuits, a gate line driving circuit is provided for each section 39 provided in the layer 20. The section 39 is an area corresponding to the sub-display section 13A. The layer 20 is also provided with a source line driving circuit 40 for driving the display device 200 or a control circuit 41 for controlling the driving circuit section 30 and the source line driving circuit.

[0031] The control circuit 41 may have an LVDS (Low Voltage Differential Signaling) circuit, a MIPI (Mobile Industry Processor Interface) circuit, and / or a D / A (Digital to Analog) conversion circuit, etc., which function as an interface for receiving image data and the like from outside the display device 200. The control circuit 41 may also have a circuit for compressing and decompressing image data and / or a power supply circuit, etc.

[0032] The drive circuit unit 30, in which the gate line drive circuit is provided, is arranged on top of the display unit 13. Therefore, compared to when the drive circuit unit 30 and the display unit 13 are arranged side by side, the width of the non-display area (also called the frame) existing on the periphery of the display unit of the display device 200 can be made extremely narrow, thereby enabling the display device 200 to be made smaller.

[0033] By arranging the section 39 in which the gate line driving circuit is provided, the source line driving circuit 40, and the control circuit 41 in close proximity to each other, it is possible to shorten the wiring that electrically connects each circuit, thereby shortening the charging and discharging time of the control signals for controlling each circuit and reducing power consumption.

[0034] The layer 20 is a layer where transistors included in the gate line driver circuit are provided. The transistors provided in the layer 20 use silicon for the semiconductor layer having a channel formation region. In particular, the transistors provided in the layer 20 use transistors having polycrystalline silicon for the semiconductor layer having the channel formation region (also referred to as "poly-Si transistors"). Low-temperature polysilicon (LTPS) is preferably used as the polycrystalline silicon. Note that a transistor having LTPS in the channel formation region is also referred to as an "LTPS transistor." By using an LTPS transistor for the transistor in the layer 20, the substrate 11 can be a glass substrate, thereby reducing the cost and increasing the area of ​​the display device 200. Note that the substrate 11 may be a flexible substrate such as a resin film.

[0035] As the transistor provided in the layer 20, a transistor including a metal oxide (also referred to as an oxide semiconductor) in a semiconductor layer having a channel formation region (OS transistor) may be used.

[0036] The source line driving circuit 40 or the control circuit 41 may be configured to have a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) attached thereto, or may be configured to have an IC (Integrated Circuit) directly mounted on the substrate 11 using a COG (Chip On Glass) method.

[0037] Layer 50 is provided with a plurality of pixel circuits for independently controlling a plurality of display elements provided in layer 60. In pixel circuit section 57 in which a plurality of pixel circuits are provided, a pixel circuit is provided for each section 59 provided in layer 50. Section 59, like section 39, is an area corresponding to sub-display section 13A.

[0038] The layer 50 is a layer where transistors included in pixel circuits are provided. It is preferable to use OS transistors as the transistors included in the layer 50. When the transistors included in the layer 50 are OS transistors, they can be provided overlapping with a layer including other transistors such as LTPS transistors. Overlapping transistors reduce the area occupied by the pixel circuits. Therefore, the resolution of the display device 200 can be improved. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO.

[0039] An OS transistor has a characteristic of having a very low off-state current, and therefore, it is preferable to use an OS transistor particularly as a transistor provided in a pixel circuit because analog data written to the pixel circuit can be held for a long period of time.

[0040] Examples of metal oxides that can be used in OS transistors include Zn oxide, Zn—Sn oxide, Ga—Sn oxide, In—Ga oxide, In—Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). Metal oxides using Ga as M are particularly preferred for use in OS transistors because they can provide transistors with excellent electrical characteristics, such as field-effect mobility, by adjusting the ratio of elements. The oxide containing indium and zinc may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0041] A plurality of display elements 61 are provided on the layer 60. The substrate 12 on the layer 60 is preferably a substrate using a light-transmitting material. The display elements 61 can be light-emitting devices. Examples of light-emitting devices that can be used include organic electroluminescence elements (also called organic EL elements). However, the light-emitting device is not limited to this, and for example, inorganic EL elements made of inorganic materials may also be used. Note that "organic EL elements" and "inorganic EL elements" are sometimes collectively referred to as "EL elements." The light-emitting device may contain inorganic compounds such as quantum dots. For example, quantum dots can be used in the light-emitting layer to function as a light-emitting material.

[0042] In this specification and the like, the term “element” may be replaced with “device.” For example, a display element and a light-emitting element may be replaced with a display device and a light-emitting device, respectively.

[0043] Although an example in which the transistors included in the pixel circuit are OS transistors has been described in one embodiment of the present invention, other structures may be used. For example, the transistors included in the pixel circuit may include LTPS transistors in addition to OS transistors.

[0044] Metal oxides used in OS transistors are n-type (n-channel) metal oxides, such as In—Ga—Zn oxide. Therefore, by combining an OS transistor with an LTPS transistor to form a pixel circuit, a complementary metal oxide semiconductor (CMOS) circuit can be formed. The pixel circuit having a CMOS circuit can achieve a circuit with high driving capability and low power consumption. Furthermore, since there is no need to separately fabricate n-type (n-channel) and p-type (p-channel) LTPS transistors, the process cost of the display device 200 can be reduced.

[0045] Although the above example illustrates a configuration in which either an OS transistor or an LTPS transistor is used as the transistor in the gate line driver circuit, other configurations may also be used. The gate line driver circuit may include an OS transistor in addition to the LTPS transistor. In this case, the gate line driver circuit can be configured as a CMOS circuit using an n-channel OS transistor and a p-channel LTPS transistor, thereby realizing a CMOS circuit without using an n-channel LTPS transistor. Therefore, compared to a case in which the gate line driver circuit is configured only with n-channel transistors, a circuit having both the advantages of high driving capability due to the use of LTPS transistors and low power consumption due to the low off-state current of the OS transistor can be realized. Furthermore, since it is no longer necessary to separately fabricate n-type (n-channel) and p-type (p-channel) LTPS transistors, the process cost of the display device 200 can be reduced.

[0046] FIG. 2A shows an example of the configuration of a pixel circuit unit 57 included in the display device 200. FIG. 2B shows an example of the configuration of a drive circuit unit 30 included in the display device 200. The partitions 59 and 39 are each arranged in a matrix of m rows and n columns (m and n are each integers equal to or greater than 1). In this specification, the partition 59 in the first row and first column is referred to as partition 59[1,1], and the partition 59 in the mth row and nth column is referred to as partition 59[m,n]. Similarly, the partition 39 in the first row and first column is referred to as partition 39[1,1], and the partition 39 in the mth row and nth column is referred to as partition 39[m,n]. FIGS. 2A and 2B show a case where m is 4 and n is 8. That is, the pixel circuit unit 57 and the drive circuit unit 30 are each divided into 32 sections.

[0047] Each of the plurality of sections 59 has a plurality of source lines SL and a plurality of gate lines GL (not shown) in addition to a plurality of pixel circuits 51. In each of the plurality of sections 59, one of the plurality of pixel circuits 51 is electrically connected to at least one of the plurality of source lines SL and at least one of the plurality of gate lines GL.

[0048] One of the sections 59 and one of the sections 39 are arranged to overlap (see FIG. 2C ). For example, section 59[i,j] (i is an integer between 1 and m, and j is an integer between 1 and n) and section 39[i,j] are arranged to overlap. The source line driving circuit 31 is electrically connected to the source line SL of section 59[i,j]. The gate line driving circuit 33 of section 39[i,j] is electrically connected to the gate line GL of section 59[i,j]. The gate line driving circuit 33 of section 39[i,j] has the function of controlling the multiple pixel circuits 51 of section 59[i,j].

[0049] By overlapping the section 59[i,j] and the section 39[i,j], the connection distance (wiring length) between the pixel circuit 51 in the section 59[i,j] and the gate line driving circuit 33 in the section 39[i,j] can be made extremely short. As a result, the wiring resistance and parasitic capacitance are reduced, which shortens the time required for charging and discharging, enabling high-speed driving. This also reduces power consumption. Furthermore, miniaturization and weight reduction can be achieved.

[0050] Furthermore, the display device 200 is configured to have a gate line drive circuit 33 for each section 39. Therefore, the display unit 13 can be divided into sections 59 corresponding to the sections 39, and the image can be rewritten for each sub-display section 13A. For example, it is possible to rewrite image data only in sections of the display unit 13 where changes have occurred in the image, and to retain image data in sections where no changes have occurred, thereby realizing a reduction in power consumption.

[0051] In the present embodiment and other embodiments, one of the display units 13 divided into sections 59 is referred to as a sub-display unit. The display device 200 described with reference to FIGS. 1A, 1B, 2A, and 2B shows a case in which the display unit 13 is divided into 32 sub-display units 13A (see FIG. 1A). Each sub-display unit 13A includes a plurality of pixels each consisting of a pixel circuit and a display element. Specifically, one sub-display unit 13A includes one of the sections 59 each including a plurality of pixel circuits 51, and a plurality of display elements 61. Furthermore, one section 39 has the function of controlling the potential of the gate lines of the plurality of pixels included in one sub-display unit 13A.

[0052] Furthermore, the display device 200 can arbitrarily set the drive frequency (also referred to as the frame frequency, frame rate, or refresh rate) for image display for each sub-display unit 13A using a timing controller included in the control circuit 41. The control circuit 41 has the function of controlling the operation of each of the multiple sections 39 and the multiple sections 59. In other words, the control circuit 41 has the function of controlling the drive frequency and operation timing of each of the multiple sub-display units 13A arranged in a matrix. The control circuit 41 also has the function of adjusting synchronization between the sub-display units.

[0053] 1A to 2C , the layer 20 and the layer 50 are illustrated as separate layers, but the structure of one embodiment of the present invention is not limited to this. By using OS transistors as the transistors included in the layer 20 and OS transistors as the transistors included in the layer 50, the transistors included in the pixel circuit and the transistors included in the gate line driver circuit can be provided in the same section.

[0054] The display device 200A shown in FIG. 3A is an example of a display device configuration in which the above-described layer 20 and layer 50 are the same layer. Layer 20A is provided with circuit section 30A, in which the above-described drive circuit section 30 and pixel circuit section 57 are integrated. Circuit section 30A is provided with section 39A, which corresponds to section 39 and section 59, as described above. Section 39A is an area corresponding to sub-display section 13A. Layer 20A is also provided with a source line drive circuit 40 for driving display device 200A or a control circuit 41 for controlling drive circuit section 30 and source line drive circuit 40.

[0055] The layer 20A is a layer where transistors included in the pixel circuit and the gate line driver circuit are provided. OS transistors are used as the transistors provided in the layer 20A. Unlike the above-described structure in which an OS transistor and an LTPS transistor are provided in different layers, the layer including the OS transistors is provided without stacking, which reduces manufacturing costs and makes it possible to reduce the thickness of the layer including the transistors. Note that the OS transistors provided in the same layer can also be OS transistors with different characteristics, for example, by varying the thickness of the insulating layer or by using metal oxides with different numbers of atoms of metal elements.

[0056] 3B, pixel circuits 51 configured with OS transistors and gate line driving circuits 33 are provided in section 39A of layer 20A. Although Fig. 3B explicitly illustrates gate line driving circuits 33 within section 39A, it is preferable that the multiple transistors included in gate line driving circuits 33 be dispersed within section 39A in which pixel circuits 51 are provided.

[0057] In a display device according to one embodiment of the present invention, pixel circuits and driver circuits are stacked and the drive frequencies of the sub-display portions 13A are varied to achieve low power consumption. For example, the drive frequencies of the sub-display portions 13A are varied depending on the gaze movement. Note that information about the gaze movement (gazing point G) may be obtained by an eye tracking method such as the Pupil Center Corneal Reflection method or the Bright / Dark Pupil Effect method. Alternatively, the information may be obtained by an eye tracking method using a laser or ultrasound.

[0058] FIG. 4A shows a display unit 13 having four rows and eight columns of sub-display units 13A. FIG. 4A also shows first to third regions S1 to S3, each centered around a gaze point G. The display device 200 assigns each of the sub-display units 13A to either a first section 29A that overlaps with the first region S1 or the second region S2, or a second section 29B that overlaps with the third region S3. That is, the display device 200 assigns each of the sub-display units 13A to either the first section 29A or the second section 29B. In this case, the first section 29A that overlaps with the first region S1 and the second region S2 is a sub-display unit that includes an area overlapping with the gaze point G, and the second section 29B is a sub-display unit located outside the first section 29A and far from the user's gaze point G (see FIG. 4B).

[0059] The operation of the gate line drive circuit of each of the multiple sub-display units 13A is controlled by the control circuit 41. For example, the sub-display unit corresponding to the second section 29B overlaps with the third region S3, which includes the stable fixation field, the guided field, and the auxiliary field, and is therefore a section with low user discrimination. Therefore, even if the number of times image data is rewritten per unit time (hereinafter also referred to as "image rewriting number") for the sub-display unit belonging to the second section 29B is reduced compared to the sub-display unit corresponding to the first section 29A, the degradation of the actual display quality perceived by the user (hereinafter also referred to as "actual display quality") is small. In other words, even if the drive frequency of the sub-display unit corresponding to the second section 29B is reduced compared to the drive frequency of the sub-display unit corresponding to the first section 29A, the degradation of the actual display quality is small.

[0060] Lowering the drive frequency can reduce the power consumption of the display device. On the other hand, lowering the drive frequency also reduces the display quality, particularly when displaying moving images. According to one aspect of the present invention, by setting the drive frequency of the sub-display unit corresponding to the second section 29B lower than the drive frequency of the sub-display unit corresponding to the first section 29A, it is possible to reduce the power consumption of sections with low user visibility while suppressing a substantial decrease in display quality. According to one aspect of the present invention, it is possible to maintain display quality while reducing power consumption.

[0061] The drive frequency of the sub-display unit corresponding to the first section 29A may be 30 Hz to 500 Hz, preferably 60 Hz to 500 Hz. The drive frequency of the sub-display unit corresponding to the second section 29B is preferably equal to or lower than the drive frequency of the first section 29A, more preferably equal to or lower than half the drive frequency of the sub-display unit corresponding to the first section 29A, and even more preferably equal to or lower than one-fifth the drive frequency of the sub-display unit corresponding to the first section 29A.

[0062] Furthermore, the sub-display section corresponding to the third region S3 may be set outside the second section 29B as the third section 29C (see FIG. 4C ), and the drive frequency of the sub-display section corresponding to the third section 29C may be lower than that of the sub-display section corresponding to the second section 29B. The drive frequency of the sub-display section corresponding to the third section 29C is preferably equal to or lower than the drive frequency of the sub-display section corresponding to the second section 29B, more preferably equal to or lower than half the drive frequency of the sub-display section corresponding to the second section 29B, and even more preferably equal to or lower than one-fifth the drive frequency of the sub-display section corresponding to the second section 29B. By significantly reducing the number of times the image is rewritten, power consumption can be further reduced. Furthermore, image data rewriting may be stopped as necessary. Stopping image data rewriting can further reduce power consumption.

[0063] When such a driving method is performed, it is preferable to use a transistor with extremely low off-state current as the transistor constituting the pixel circuit 51. For example, an OS transistor is preferable as the transistor constituting the pixel circuit 51. Since the off-state current of an OS transistor is extremely low, image data supplied to the pixel circuit 51 can be held for a long period of time by stopping the output signal output from the gate line driver circuit.

[0064] Furthermore, when the video scene displayed on the display unit 13 changes, an image with significantly different brightness, contrast, or color tone from the immediately preceding image may be displayed. In such a case, a difference occurs in the timing of image switching between the first section 29A and a section with a lower drive frequency than the first section 29A, resulting in a significant difference in brightness, contrast, or color tone between the two sections, which may result in a loss of substantial display quality. In such a case, for example, the image in sections other than the first section 29A may be rewritten at the same drive frequency as the first section 29A, and then the drive frequency of the sections other than the first section 29A may be lowered.

[0065] Furthermore, if it is determined that the amount of change in the gaze point G has exceeded a certain amount, the sub-display units other than the sub-display unit corresponding to the first section 29A may also rewrite the images at the same drive frequency as the sub-display unit corresponding to the first section 29A, and if it is determined that the amount of change is within the certain amount, the drive frequency of the sub-display units other than the sub-display unit corresponding to the first section 29A may be reduced. Furthermore, if it is determined that the amount of change in the gaze point G is small, the drive frequency of the sub-display units other than the sub-display unit corresponding to the first section 29A may be further reduced.

[0066] The sections corresponding to the sub-display sections that make up the display unit 13 are not limited to the three sections, the first section 29A, the second section 29B, and the third section 29C. Four or more sections may be set in the display unit 13. By setting multiple sections in the display unit 13 and gradually lowering the drive frequency, it is possible to further reduce the actual degradation of display quality.

[0067] Furthermore, high-speed rewriting can be achieved by simultaneously rewriting image data for all sub-display sections 13A instead of for each sub-display section 13A. That is, high-speed rewriting can be achieved by simultaneously rewriting image data for all sections 39 instead of for each section 39.

[0068] In addition, in the display device 200 exemplified in this embodiment, the display unit 13 is divided into eight sections in the column direction, so the length of the gate lines GL that electrically connect the gate line driving circuit and the pixel circuits is reduced to one-eighth, which reduces the resistance and parasitic capacitance of the gate lines GL to one-eighth, improving signal degradation and delay and making it easier to ensure time for rewriting image data.

[0069] According to the display device 200 according to one embodiment of the present invention, the time required for writing image data is short, and thus high-speed rewriting of a display image can be realized. As a result, a display device with high display quality can be realized, and in particular, a display device with excellent moving image display can be realized.

[0070] Furthermore, according to the display device 200 of one aspect of the present invention, the output signals output by the gate line driving circuit for each sub-display unit 13A can be controlled independently, so that the shapes or sizes of the sub-display units 13A can be made different from each other. In other words, the display unit 13 can be made up of sub-display units with different shapes or sizes. Therefore, the display unit 13 is not limited to a rectangular shape, and can be made into a display unit with excellent design, such as a circular shape.

[0071] 5A is a diagram showing an example of a configuration in which the display device 200 described in FIGS. 1A to 4C is applied to a head-mounted display (HMD) type electronic device to detect gaze movement. The example shown in FIG. 5A shows a perspective view of the HMD type electronic device 100.

[0072] FIG. 5A illustrates the electronic device 100 including a pair of display devices 200_L and 200_R in a housing 251. FIG. 5A also illustrates the eye 252 of a user wearing the electronic device 100. FIG. 5A also includes a pair of imaging devices 253_L and 253_R for capturing an image of the user's eye 252. The imaging devices 253_L and 253_R can capture not only the user's eye 252 but also movements around the eyeball, such as the eyelid, the space between the eyebrows, the inner corner of the eye, and the outer corner of the eye. As shown in FIG. 5A , the pair of imaging devices 253_L and 253_R are disposed in positions for capturing an image of the eye 252, for example. The housing 251 may include an acceleration sensor, such as a gyro sensor, to detect the orientation of the user's head and display an image corresponding to that orientation.

[0073] 5A can have a configuration in which the pixel circuit unit 57 and the drive circuit unit 30 are stacked, similar to the display device 200 described above, and therefore can have an extremely high pixel aperture ratio (effective display area ratio). For example, the pixel aperture ratio can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less.

[0074] The display devices 200_L and 200_R can be made extremely high-definition, and are therefore suitable for VR devices such as head-mounted display electronic devices, or for AR glasses-type devices. For example, even in a configuration in which the display unit of the display device 200 is viewed through an optical member such as a lens, the display device 200 has an extremely high-definition display unit, so that pixels are not visible even when the display unit is enlarged with a lens, thereby providing a highly immersive display.

[0075] When the display device 200 is used as a wearable display device for VR or AR, the diagonal size of the display unit can be 0.1 inches or more and 5.0 inches or less, preferably 0.5 inches or more and 2.0 inches or less, and more preferably 1 inch or more and 1.7 inches or less. For example, the diagonal size of the display unit may be 1.5 inches or close to 1.5 inches. By setting the diagonal size of the display unit to 2.0 inches or less, preferably close to 1.5 inches, it becomes possible to process the display unit in a single exposure process using an exposure device (typically a scanner device), thereby improving the productivity of the manufacturing process.

[0076] Fig. 5B shows a state in which a user 130 wearing electronic device 100 shown in Fig. 5A views an image 24 ahead of line of sight 131. Fig. 5B illustrates a first region S1 including point of gaze G, a second region S2 adjacent to first region S1, and a third region S3 outside the second region.

[0077] Generally, human visual fields are broadly classified into the following five categories, although there are individual differences. The discriminative visual field is the area where visual functions such as visual acuity and color discrimination are at their best, and refers to the area including the point of gaze within approximately 5° of the center of the visual field. The effective visual field is the area where specific information can be instantly identified using eye movement alone, and refers to the area adjacent to the discriminative visual field, within approximately 30° horizontally and 20° vertically of the center of the visual field (point of gaze). The stable visual field is the area where specific information can be identified effortlessly with head movement, and refers to the area adjacent to the effective visual field, within approximately 90° horizontally and 70° vertically of the center of the visual field. The induced visual field is the area where the presence of a specific object can be detected but the ability to identify it is low, and refers to the area adjacent to the stable visual field, within approximately 100° horizontally and 85° vertically of the center of the visual field. The auxiliary visual field is an area in which the ability to distinguish specific objects is significantly reduced, but the presence of stimuli can be detected. It is an area within approximately 100° to 200° horizontally and approximately 85° to 130° vertically from the center of the visual field, adjacent to the induced visual field.

[0078] From the above, it can be seen that the image quality from the discriminative field to the effective field is important in the image 24. In particular, the image quality of the discriminative field is crucial.

[0079] When the line of sight 131 of the user 130 moves, the point of gaze G also moves. Therefore, the first area S1 and the second area S2 also move. For example, if the amount of change in the line of sight 131 exceeds a certain amount, it is determined that the line of sight 131 is moving. In other words, if the amount of change in the point of gaze G exceeds a certain amount, it is determined that the point of gaze G is moving. Furthermore, if the amount of change in the line of sight 131 becomes equal to or less than a certain amount, it is determined that the movement of the line of sight 131 has stopped, and the first area S1 to the third area S3 are determined. In other words, if the amount of change in the point of gaze G becomes equal to or less than a certain amount, it is determined that the movement of the point of gaze G has stopped, and the first area S1 to the third area S3 can be determined.

[0080] 6 is a schematic diagram illustrating the configuration of adjacent pixel circuits 51 and gate line driving circuits 33 in a sub-display section in which partitions 39 and 59 are stacked in a display device 200. In FIG. 6, partitions 39[i,j] and 39[i+1,j] and partitions 59[i,j] and 59[i+1,j] are illustrated as adjacent partitions.

[0081] FIG. 6 illustrates the x, y, and z directions. As illustrated in FIG. 6, the x direction is parallel to the gate line GL. The y direction is parallel to the source line (not shown). As illustrated in FIG. 6, the z direction is perpendicular to the plane defined by the x and y directions. That is, FIG. 6 illustrates a state in which the pixel circuit 51 and the gate line driving circuit 33 are provided on the xy plane, and the partitions 39 and 59 are stacked in the z direction. The configuration illustrated in FIG. 6 is an example, and a configuration in which part of the pixel circuit 51 or the gate line driving circuit 33 is provided in a partition in an upper or lower layer may also be used.

[0082] The gate line driving circuits 33 provided in the sections 39[i,j] and 59[i+1,j] each have a plurality of pulse output circuits 34. The pulse output circuits 34 output signals that simultaneously select the pixel circuits 51 provided in the x direction via gate lines GL extending in the z direction. By arranging the gate line driving circuits 33 below the pixel circuits 51, it is possible to increase the degree of freedom in design, such as narrowing the frame.

[0083] Although the gate line driving circuits 33 provided in the sections 39[i,j] and 39[i+1,j] are shown with the same number of pulse output circuits 34, different numbers may be used. By differentiating the number of pulse output circuits 34 provided in the gate line driving circuits 33 between the sections 39[i,j] and 39[i+1,j], the number of pixels in the y direction can be made different. This increases the degree of freedom in the shape of the display unit. Therefore, a display unit 13 having a sub-display unit 13A corresponding to the sections 39[i,j] and 39[i+1,j] can be made into a display unit with excellent design.

[0084] 7 to 9 show configuration examples of pixel circuits applicable to the pixel circuit 51, and a display element 61 connected to the pixel circuit 51. In the following description, the display element 61 will be described as a light-emitting device such as an organic EL element (OLED: Organic Light Emitting Diode).

[0085] Note that the light-emitting device described in one embodiment of the present invention is not limited to an organic EL element, and may be a self-luminous light-emitting device such as an LED (Light Emitting Diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser.

[0086] A pixel circuit 51A shown in Fig. 7A includes a transistor 55A, a transistor 55B, and a capacitor 56. Fig. 7A also shows a display element 61 connected to the pixel circuit 51A. Fig. 7A also shows a source line SL, a gate line GL, a power supply line ANO, and a power supply line VCOM.

[0087] The transistor 55A has a gate electrically connected to the gate line GL, one of its source and drain electrically connected to the source line SL, and the other electrically connected to the gate of the transistor 55B and one electrode of the capacitor 56. The transistor 55B has a source electrically connected to the power supply line ANO and the other electrically connected to the anode of the display element 61. The capacitor C1 has another electrode electrically connected to the anode of the display element 61. The display element 61 has a cathode electrically connected to the power supply line VCOM. The anode and cathode of the display element 61 can be switched as needed by changing the magnitude of the potential supplied to the power supply line ANO and the power supply line VCOM.

[0088] 7B is a configuration in which a transistor 55C is added to the pixel circuit 51A. The transistor 55C has a gate electrically connected to the gate line GL, one of a source and a drain electrically connected to the anode of the display element 61, and the other of the source and drain electrically connected to the wiring V0.

[0089] A pixel circuit 51C shown in FIG. 7C is an example in which transistors having a pair of gates are used as the transistors 55A and 55B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 7D is an example in which the same transistors are used in the pixel circuit 51B. This can increase the current that the transistors can pass. Note that, although transistors having a pair of gates are used for all the transistors here, this is not a limitation. Alternatively, a transistor having a pair of gates electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to the source.

[0090] 8A has a configuration in which a transistor 55D is added to the pixel circuit 51B. In addition, three gate lines (gate line GL1, gate line GL2, and gate line GL3) are electrically connected to the pixel circuit 51E.

[0091] The gate of the transistor 55D is electrically connected to the gate line GL3, one of the source and drain of the transistor 55B is electrically connected to the gate line GL3, and the other is electrically connected to the wiring V0. The gate of the transistor 55A is electrically connected to the gate line GL1, and the gate of the transistor 55C is electrically connected to the gate line GL2.

[0092] By simultaneously turning on transistors 55C and 55D, the source and gate of transistor 55B have the same potential, and when the threshold voltage of transistor 55B is higher than 0 V, transistor 55B can be turned off. This forcibly cuts off the current flowing through display element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0093] 8B is an example in which a capacitor 56A is added to the pixel circuit 51E. The capacitor 56A functions as a storage capacitor.

[0094] 8C and 8D are examples in which transistors each having a pair of gates are applied to the pixel circuit 51E or 51F. Transistors 55A, 55C, and 55D are transistors in which a pair of gates are electrically connected, and transistor 55B is a transistor in which one gate is electrically connected to a source.

[0095] 7A to 8D show examples in which the pixel circuit can be configured using only n-channel OS transistors, but one embodiment of the present invention is not limited to this. For example, as shown in FIGS. 9A to 9C , a pixel circuit may be configured including an OS transistor and an LTPS transistor.

[0096] A pixel circuit 51I shown in FIG. 9A includes a transistor 55A, a transistor 55P, and a capacitor 56. The pixel circuit 51I shown in FIG. 9A is an example in which the transistor 55B in the pixel circuit 51A is replaced with a p-channel LTPS transistor 55P. The pixel circuit 51I shown in FIG. 9A can hold an analog potential by turning off the OS transistor 55A. Furthermore, the pixel circuit 51I uses the LTPS transistor 55P as a driving transistor, thereby increasing the amount of current flowing through the display element 61.

[0097] The pixel circuit 51J shown in FIG. 9B includes transistors 55A, 55B, 55P, and a capacitor 56. The pixel circuit 51J shown in FIG. 9B is an example in which the transistor 55B in the pixel circuit 51B is replaced with a p-channel LTPS transistor 55P. The pixel circuit 51J shown in FIG. 9B can hold an analog potential by turning off the OS transistor 55A. Furthermore, the pixel circuit 51J uses the LTPS transistor 55P as a driving transistor, thereby increasing the amount of current flowing through the display element 61.

[0098] The pixel circuit 51K shown in FIG. 9C includes a transistor 55A, transistors 55P to 55T, and a capacitor 56. The pixel circuit 51K shown in FIG. 9C is an example of a pixel circuit including n-channel LTPS transistors 55P to 55T. The pixel circuit 51K shown in FIG. 9C can hold an analog potential by turning off the transistor 55A, which is an OS transistor. Furthermore, the pixel circuit 51K uses the LTPS transistors 55P to 55T as driving transistors or switching transistors, thereby increasing the amount of current flowing through the display element 61.

[0099] 9D shows an operation timing chart of the pixel circuit 51K shown in FIG. 9C. By applying the signals shown in FIG. 9D to the gate lines GL1 to GL4, it is possible to control light emission according to the image data D(N) of the source line SL. As shown in FIG. 9D, the gate lines GL1 and GL3, and the gate lines GL2 and GL4 are configured to receive a selection signal and its inverted signal, respectively.

[0100] <Configuration Example of Gate Line Driving Circuit> FIGS. 10A to 10C show an example of the gate line driving circuit 33 described in FIGS. 2B and 6, a pulse output circuit 34 applicable to the gate line driving circuit 33, and a timing chart.

[0101] 10A shows an example of a shift register included in the gate line driving circuit 33. Fig. 10A illustrates pulse output circuits 34_1 to 34_n+2, a wiring for supplying a gate clock signal GCK_A, a wiring for supplying a gate clock signal GCK_B, and a wiring for supplying a gate start pulse GSP. The wiring between the pulse output circuits 34_1 and 34_2 is connected to the gate line GL. The output signals of the pulse output circuits 34_n+1 and 34_n+2 are used to reset the pulse output circuit in the preceding stage.

[0102] Fig. 10B shows an example of a circuit configuration of a pulse output circuit applicable to the pulse output circuits 34_1 to 34_n+2 shown in Fig. 10A. The pulse output circuit 34 shown in Fig. 10B includes transistors M11 to M14 and a capacitance element C11. Fig. 10B also shows signals and voltages applied to each transistor, including a gate clock signal GCK_A, a gate clock signal GCK_B, an output signal GP, a gate start pulse GSP (or an output signal Former GP from the previous pulse output circuit 34), an output signal Next GP from the next pulse output circuit 34, and a voltage VSS. Fig. 10B also shows a node connected to the transistors M11, M12, and M13 and the capacitance element C11 as net A.

[0103] 10C is a timing chart for explaining the operation of the pulse output circuit shown in FIG. 10B. At time T1 in FIG. 10C, GCK_A is low and GCK_B is high, and at this time GSP is set to high, increasing the voltage of net A. Next, at time T2, GSP is set to low, causing net A to float. At time T2, GCK_A is high and GCK_B is low, so the voltage of net A, which is floating, increases due to the capacitive coupling of capacitive element C11. As a result, transistor M13 becomes conductive, and GP goes high. At time T3, Next GL goes high, causing net A to go low, and GCK_B goes high, causing GP to go low.

[0104] When driving the pixel circuit 51K shown in FIG. 9C or the like, an inverted signal of the output signal GP shown in FIG. 10C is required. The output signal GP is preferably configured to generate an inverted signal using an inverter circuit configured with a CMOS circuit. That is, as shown in FIG. 11A, the pulse output circuit configuration described in FIG. 10B is preferably configured with a p-channel transistor M15 and an n-channel transistor M16 that configure an inverter circuit that generates an inverted signal of the output signal GP. The transistor M15 can be configured as an LTPS transistor, and the transistor M16 can be configured as an LTPS transistor or an OS transistor.

[0105] Fig. 11B is a timing chart for explaining the operation of the pulse output circuit shown in Fig. 11A. As shown in Fig. 11B, a signal can be generated in which GPB, which is an inverted signal, goes low when GP goes high.

[0106] The pulse output circuit is not limited to the circuit configuration shown in Figures 10B and 11A, and may have other configurations. Figure 12 shows transistors M21 to M33 and capacitive elements C21 to C23. In Figure 12, LIN is the output signal or gate start pulse of the previous stage, CLK1 to CLK3 are gate clock signals, RES is a reset signal, RIN is the output signal of the next stage, and PWCA is a pulse width control signal. The output signal GP is the signal output to the gate line GL, and the output signal 34N is the signal output to the pulse output circuit of the next stage.

[0107] 12, the pulse output circuit can have a circuit configuration that can be configured only with n-channel transistors. In FIG. 12, transistors M21 to M33 are n-channel transistors, and the circuit configuration can be configured with OS transistors or n-channel LTPS transistors, or a circuit configuration in which OS transistors and n-channel LTPS transistors are combined.

[0108] The pulse output circuit is not limited to the circuit configurations shown in Figures 10B, 11A, and 12, and may have other configurations. Figure 13 shows transistors M41 to M63. In Figure 13, LIN is the output signal or gate start pulse of the previous stage, CLK1 and CLK2 are gate clock signals, and PWCA is the pulse width control signal. The output signal GP is the signal output to the gate line GL, and the output signal 34N is the signal output to the pulse output circuit of the next stage.

[0109] 13, the pulse output circuit can have a circuit configuration including a combination of n-channel transistors and p-channel transistors. The n-channel transistors and p-channel transistors can be configured using an n-channel OS transistor and a p-channel LTPS transistor, or a p-channel LTPS transistor and an n-channel LTPS transistor.

[0110] Fig. 14 uses circuit symbols to illustrate an example of a configuration in which the pixel circuit 51A of Fig. 7A and the pulse output circuit of Fig. 10B are stacked. Note that Fig. 14 illustrates the x-direction, y-direction, and z-direction, as in Fig. 6. Fig. 14 illustrates pulse output circuits, pixel circuits, and light-emitting elements that are display elements, corresponding to the layers 20, 50, and 60 described in Fig. 1B.

[0111] If the configuration of FIG. 14 is configured such that the pixel circuit and the gate line driving circuit are provided in the same layer as described with reference to FIGS. 3A and 3B, the resulting configuration will be as shown in FIG. 15. In FIG. 15, a configuration example in which the pixel circuit 51A of FIG. 7A and the pulse output circuit of FIG. 10B are arranged in layer 20A is illustrated using circuit symbols. In FIG. 15, the x-direction, y-direction, and z-direction are illustrated, as in FIG. 14. In FIG. 15, the pulse output circuit, pixel circuit, and light-emitting element, which is a display element, are illustrated corresponding to layer 20A and layer 60 described with reference to FIGS. 3A and 3B.

[0112] 16 also uses circuit symbols to illustrate an example of a configuration in which the pixel circuit 51J of FIG. 9B and the pulse output circuit of FIG. 10B are stacked. Note that, like FIG. 6, the x-, y-, and z-directions are illustrated in FIG. 16. Like FIG. 14 and FIG. 15, FIG. 16 illustrates a pulse output circuit, a pixel circuit, and a light-emitting element that is a display element, corresponding to the layer 20, the layer 50, and the layer 60 described in FIG. 1B.

[0113] 16 differs from FIG. 14 in that a transistor 55P constituting a pixel circuit is provided in the layer 20. In one embodiment of the present invention, a circuit other than the pulse output circuit, for example, a part of the pixel circuit, can also be provided in the layer 20. Since the number of transistors in the layer 50 can be reduced, the area of ​​the pixel circuit can be reduced, and a display device with higher definition can be obtained.

[0114] 17 also uses circuit symbols to illustrate an example of a configuration in which the pixel circuit 51A of FIG. 7A and the pulse output circuit of FIG. 11A are stacked. Note that, like FIGS. 14 to 16, the x-, y-, and z-directions are illustrated in FIG. 17. Like FIGS. 14 to 16, FIG. 17 illustrates pulse output circuits, pixel circuits, and light-emitting elements that are display elements, corresponding to the layers 20, 50, and 60 described in FIG. 1B.

[0115] 14 to 16 in that the diagram shown in Figure 17 includes a transistor M16 that configures the pulse output circuit in the layer 50. In one embodiment of the present invention, a circuit other than the pixel circuit, for example, a part of the pulse output circuit, can also be provided in the layer 50. Since the number of transistors in the layer 20 can be reduced, the area of ​​the pulse output circuit can be reduced.

[0116] As described above, the pixel circuit and the pulse output circuit included in the gate line driver circuit according to one embodiment of the present invention are not limited to a circuit configuration including only OS transistors or only LTPS transistors, and can have a circuit configuration including a combination of OS transistors and LTPS transistors. Therefore, in one embodiment of the present invention, the pixel circuit and the pulse output circuit included in the gate line driver circuit can be arranged with greater freedom, which can increase the freedom in the shape of the display portion, thereby providing a display device with excellent design.

[0117] <Example of Operation of Display Device> Figure 18A is a schematic diagram of a display device in which the partitions of the pixel circuit unit 57 described in Figures 2A and 2B and the partitions 39 of the drive circuit unit 30 are m = 4 and n = 4, i.e., 4 rows and 4 columns, and the display unit 13 in Figure 1A is divided into 16 sub-display units 13A. In Figure 18A, the 16 sub-display units 13A are assigned reference numerals such as (1, 1) to (4, 4). Figure 18A also shows how each sub-display unit 13A is provided with a gate line drive circuit 33 and how a source line drive circuit 31 is provided outside the display unit 13.

[0118] 18B is a schematic diagram illustrating signals output to gate lines by the gate line driving circuit 33 corresponding to the sub-display unit 13A shown in FIG. 18A . Note that (1, x) in FIG. 18B represents any one of the sub-display units 13A (1, 1) to (1, 4) in the first row. That is, the sub-display units 13A (2, 1) to (2, 4) in the second row can be expressed as (2, x). Similarly, the sub-display units 13A (3, 1) to (3, 4) in the third row can be expressed as (3, x), and the sub-display units 13A (4, 1) to (4, 4) in the fourth row can be expressed as (4, x).

[0119] 18B represents a start pulse signal to be supplied to each of the gate line driving circuits 33 of the sub-display units 13A in the first row (1,1) to (1,4). Also, (1,x)_1 to (1,x)_n (n is a natural number) represent output signals sequentially output by the pulse output circuits of the gate line driving circuits 33 of the sub-display units 13A in the first row (1,1) to (1,4).

[0120] In the configuration of FIG. 18A, the screen is scanned in one direction, but partial rewriting is possible by operating the gate driver only for the block to be rewritten.

[0121] Next, the operation method of the gate line driving circuit when rewriting image data will be described using timing charts, showing when image data is rewritten in all sub-display areas 13A of the display area 13 (schematic diagram shown in FIG. 19A ) and when image data is rewritten only in the sub-display area 13A in the third row and third column of the display area 13 (the shaded area indicated by (3, 3) in the diagram) (schematic diagram shown in FIG. 19B ).

[0122] Figure 20 shows start pulse signals (1, x)_SP to (4, x)_SP to be given to the gate line driving circuits of each row when rewriting image data corresponding to the schematic diagram shown in Figure 19A, as well as output signals (1, x)_1 to (1, x)_n, (2, x)_1 to (2, x)_n, (3, x)_1 to (3, x)_n, and (4, x)_1 to (4, x)_n from the gate line driving circuits of each row.

[0123] As shown in Figure 20, when rewriting image data corresponding to the schematic diagram shown in Figure 19A, a start pulse signal (1,x) is input to the gate line drive circuits of the sub-display sections (1,1), (1,2), (1,3), and (1,4), causing the gate line drive circuits to sequentially output output signals. Next, a start pulse signal (2,x) is input to the gate line drive circuits of the sub-display sections (2,1), (2,2), (2,3), and (2,4), causing the gate line drive circuits to sequentially output output signals. Next, a start pulse signal (3,x) is input to the gate line drive circuits of the sub-display sections (3,1), (3,2), (3,3), and (3,4), causing the gate line drive circuits to sequentially output output signals. Next, a start pulse signal (4,x) is input to the gate line drive circuits of the sub-display sections (4,1), (4,2), (4,3), and (4,4), causing the gate line drive circuits to sequentially output output signals.

[0124] By the operation shown in FIG. 20, it is possible to generate an output signal in the gate line driving circuit so that image data output from the source line driving circuit is selected for each row and written to each pixel.

[0125] Figure 21 shows start pulse signals (1, x)_SP to (4, x)_SP to be given to the gate line driving circuits of each row when rewriting image data corresponding to the schematic diagram shown in Figure 19B, as well as output signals (1, x)_1 to (1, x)_n, (2, x)_1 to (2, x)_n, (3, x)_1 to (3, x)_n, and (4, x)_1 to (4, x)_n from the gate line driving circuits of each row.

[0126] 21, in rewriting image data corresponding to the schematic diagram shown in Fig. 19B, a start pulse signal (3,3)_SP is input to the gate line drive circuit of the (3,3) sub-display unit, causing the gate line drive circuit of the (3,3) sub-display unit to output sequential output signals. No start pulse signal is output to the gate line drive circuits of the other sub-display units, causing the corresponding gate line drive circuits not to output sequential output signals.

[0127] The operation shown in FIG. 21 makes it possible to stop the operation of the gate line driving circuit of the sub-display section that is not being rewritten, thereby making it possible to reduce power consumption.

[0128] As shown in FIG. 18A, a gate line driving circuit is provided in each sub-display section, but a gate line driving circuit may be shared by adjacent sub-display sections.

[0129] For example, in a configuration in which the display section is divided into 4 × 4 blocks as shown in Fig. 18A, the sub-display sections in the first and second columns may share a shift register of the gate line driving circuit, and the sub-display sections in the third and fourth columns may share a shift register of the gate driver. A schematic diagram of this case is shown in Fig. 22.

[0130] As shown in FIG. 22, the shift register SR in the gate line drive circuit is shared by multiple sub-display units, but by providing a separate buffer BUF (a unit that supplies selection signals to pixels) for each sub-display unit, for example, when rewriting image data for only the sub-display unit 13A (1,2), it becomes possible to rewrite only the sub-display unit (1,2) by stopping the signal supplied to the buffer BUF of the sub-display unit 13A (1,1).

[0131] <Configuration Example of Source Line Driver Circuit> FIGS. 23A and 23B show modified examples of the source line driver circuit 31 described with reference to FIG. 2B and the like.

[0132] 2B and the like. Fig. 23A illustrates a configuration example in which a plurality of source line driving circuits 31 described in Fig. 2B and the like are provided. Fig. 23A illustrates a configuration in which source line driving circuits 31A and source line driving circuits 31B are provided in regions corresponding to the upper and lower sides of a driving circuit unit 30 having a plurality of sections 39 in which gate line driving circuits 33 are provided. This configuration makes it possible to divide the sections of the pixel circuit unit to which image data is supplied by source line driving circuits 31A and source line driving circuits 31B, and therefore makes it possible to configure the source line driving circuits to suspend operation in accordance with the operation of the gate line driving circuits not to sequentially output output signals.

[0133] 23A illustrates a configuration in which two source line drive circuits are provided, but it is preferable to provide a configuration in which the source line drive circuits are divided according to the number of sub-display sections. For example, as illustrated in FIG. 23B, it is preferable to provide the same number of source line drive circuits 31 as the number of n columns of partitions 39 corresponding to the sub-display sections. With this configuration, it is possible to operate the gate line drive circuits corresponding to the sub-display sections that are to be operated and the source line drive circuits corresponding to a certain column of the sub-display sections that are to be operated, while suspending the operation of the other gate line drive circuits and source line drive circuits, thereby reducing the power consumption of the display device.

[0134] <Configuration Example 2 of Display Device> FIGS. 24 and 25 illustrate a configuration example of a display device in which a plurality of display panels are combined.

[0135] Fig. 24 illustrates an example of a case where the display unit 13 of a display device is configured by combining display panels 400 exemplified below. Fig. 25 shows a schematic top view of the display unit 13 and the display panel 400 as viewed from the display surface side.

[0136] The display panel 400 includes a sub-display section 13A, a pixel circuit section 57, a source line driving circuit 31, a gate line driving circuit 33, a region 401 that transmits visible light, and a terminal section 14. In Fig. 24, an example is shown in which the display panel 400 has two terminal sections 14, and an FPC 21 is connected to each of the terminal sections 14.

[0137] 24, the gate line driving circuit 33 is configured to be provided around the pixel circuit portion 57, but this configuration is not limited thereto. For example, as described with reference to FIGS. 1A to 2B, a configuration may be adopted in which transistors are arranged in multiple layers and the gate line driving circuit and the pixel circuit portion are arranged to overlap. As another configuration, as described with reference to FIGS. 3A and 3B, a configuration may be adopted in which the gate line driving circuit is arranged in a region where the pixel circuit portion is provided in a layer having transistors.

[0138] In the case of the sub-display unit 13A having m rows and n columns, the sub-display unit 13A is configured such that the sub-display unit 13A[1,1] to the sub-display unit 13A[m,n] are provided in the display unit 13. In other words, by combining the display panels 400, a display device having a plurality of sub-display units 13A can be formed.

[0139] The region 401 is a region that transmits visible light. A material that transmits visible light can be used for the member provided in the region 401. Alternatively, a light-blocking material that is processed to be thin enough to be invisible (for example, a width of 5 μm or less) can be used.

[0140] 25A and 25B show an example of the configuration of a display device 200X having four display panels (display panel 400a, display panel 400b, display panel 400c, and display panel 400d). Fig. 25A is a schematic top view of the display device 200X as viewed from the display surface side, and Fig. 25B is a schematic top view of the display device as viewed from the side opposite the display surface (also referred to as the back side).

[0141] In the following description, unless otherwise specified, when describing each display panel or each component of the display panel, the symbols a to d are used. When describing matters common to each display panel or each component of the display panel, these symbols may not be used.

[0142] 25A and 25B, display panels 400a, 400b, 400c, and 400d are stacked in this order from the rear surface side. Display panel 400a is located on the rear surface side, and display panel 400d is located closest to the display surface side.

[0143] A part of a region 401b of the display panel 400b is provided so as to overlap a part of the pixel circuit portion 57a ​​in a region overlapping with the display element. In the part of the pixel circuit portion 57a ​​that overlaps with the region 401b, light from the display element passes through the region 401b and is emitted to the display surface side.

[0144] Similarly, a portion of a region 401c of the display panel 400c is provided overlapping with a portion of the pixel circuit portion 57a. A portion of a region 401d of the display panel 400d is provided overlapping with a portion of the pixel circuit portion 57a, another portion is provided overlapping with a portion of the pixel circuit portion 57b, and another portion is provided overlapping with a portion of the pixel circuit portion 57c.

[0145] That is, the display unit 13 of the display device 200X is composed of the pixel circuit unit 57a, the pixel circuit unit 57b, the pixel circuit unit 57c, and the pixel circuit unit 57d. This makes it possible to realize a display device in which the pixel circuit unit 57a, the pixel circuit unit 57b, the pixel circuit unit 57c, and the pixel circuit unit 57d of each of the display panels 400a to 400d serve as sub-display units.

[0146] As shown in FIG. 25B, the FPC 21a connected to the display panel 400a and the FPC 21b connected to the display panel 400b are provided so as to overlap with the display panel 400c and the display panel 400d, respectively.

[0147] Here, because each display panel 400 is provided with a source line driver circuit 31 and a gate line driver circuit 33, the number of signals supplied to each display panel 400 can be reduced. This allows for a reduction in the number of FPCs 21 required to connect to one display panel 400, thereby reducing the number of components. Furthermore, as shown in FIG. 25B , by varying the lengths of the FPCs 21 connected to each display panel 400 and gathering the ends of each FPC 21 on one side of the display device 200X, the driver circuits for supplying signals and the like to the display device 200X can be concentrated in one location. This simplifies the configuration on the back side of the display device 200X.

[0148] FIG. 25C shows a schematic cross-sectional view of the display device 200X taken along the dashed dotted line XY in FIG. 25B.

[0149] The portion of the display panel 400a that overlaps with the display panel 400c is curved toward the rear surface, and the FPC 21a is connected to the terminal portion 14a at this portion. At this time, the source line driving circuit 31A and the terminal portion 14A of the display panel 400a are arranged so as to overlap with the pixel circuit portion 57c of the display panel 400c. This allows the display unit 13 of the display device 200X to display high-quality images without any seams.

[0150] 26A to 26C illustrate another example of the configuration of a display device in which a plurality of display panels are combined. A display panel 450 shown in FIG. 26A includes a pixel circuit portion 57, a region 401, and a region 22. The region 22 blocks visible light. The region 401 and the region 22 are each provided adjacent to the pixel circuit portion 57. FIG. 26A illustrates an example in which an FPC 21 is provided on the display panel 450. Note that a gate line driver circuit and a source line driver circuit are not provided on the display panel, and image data and other signals are input from the outside via the FPC.

[0151] 26A to 26C, the gate line driver circuit and the source line driver circuit are described as being provided outside the display panel, but this configuration is not limited thereto. For example, the source line driver circuit may be provided outside the display panel, and the gate line driver circuit may be provided in a region overlapping with the pixel circuit. In this case, as described in FIGS. 1A to 2B, transistors may be arranged in multiple layers, and the gate line driver circuit may be arranged to overlap with the pixel circuit portion. As another configuration, as described in FIGS. 3A and 3B, the gate line driver circuit may be arranged in a region where the pixel circuit portion is provided in the layer having the transistors.

[0152] The pixel circuit portion 57 includes a plurality of pixel circuits. The region 401 includes a pair of substrates constituting the display panel 450, a sealant for sealing a display element sandwiched between the pair of substrates, and the like. At this time, a material that is transparent to visible light is used for the members provided in the region 401. The region 22 includes wirings and the like electrically connected to pixels included in the pixel circuit portion 57. The region 22 may also include a terminal connected to the FPC 21, a wiring connected to the terminal, and the like.

[0153] 26B and 26C show examples in which the display panel 450 shown in Fig. 26A is arranged in a matrix (two in the vertical direction and two in the horizontal direction) to form a 2 x 2 sub-display section. Fig. 26B is a perspective view of the display surface side of the display panel 450, and Fig. 26C is a perspective view of the side opposite to the display surface of the display panel 450.

[0154] The four display panels 450 (display panels 450a, 450b, 450c, and 450d) are arranged so that they overlap with one another. Specifically, the display panels 450a, 450b, 450c, and 450d are arranged so that the region 401 of one display panel 450 overlaps (on the display surface side of) the pixel circuit unit 57 of the other display panels 450. The display panels 450a, 450b, 450c, and 450d are also arranged so that the region 22 that blocks visible light of one display panel 450 does not overlap the pixel circuit unit 57 of the other display panels 450. In the overlapping portions of the four display panels 450, the display panel 450b overlaps the display panel 450a, the display panel 450c overlaps the display panel 450b, and the display panel 450d overlaps the display panel 450c.

[0155] The short sides of the display panels 450a and 450b overlap each other, and a part of the pixel circuit unit 57a overlaps with a part of the region 401b. The long sides of the display panels 450a and 450c overlap each other, and a part of the pixel circuit unit 57a overlaps with a part of the region 401c.

[0156] A part of the pixel circuit section 57b overlaps a part of the region 401d, and a part of the pixel circuit section 57c overlaps a part of the region 401d.

[0157] Therefore, the area in which the pixel circuit sections 57a to 57d are arranged almost seamlessly can be used as the sub-display section, which serves as the display section 13 of the display device.

[0158] Here, the display panel 450 preferably has flexibility. For example, a pair of substrates constituting the display panel 450 preferably have flexibility.

[0159] As a result, for example, as shown in Figures 26B and 26C, the vicinity of the FPC 21a of the display panel 450a can be curved, and a portion of the display panel 450a and a portion of the FPC 21a can be arranged below the pixel circuit unit 57b of the display panel 450b adjacent to the FPC 21a. As a result, the FPC 21a can be arranged without physically interfering with the rear surface of the display panel 450b. Furthermore, when the display panels 450a and 450b are stacked and fixed, the thickness of the FPC 21a does not need to be taken into consideration, so the height difference between the top surface of the visible light-transmitting region 401b and the top surface of the display panel 450a can be reduced. As a result, the edge of the display panel 450b located above the pixel circuit unit 57a can be made less noticeable.

[0160] Furthermore, by providing flexibility to each display panel 450, the display panel 450b can be gently curved so that the height of the upper surface of the pixel circuit unit 57b of the display panel 450b matches the height of the upper surface of the pixel circuit unit 57a of the display panel 450a. Therefore, except for the vicinity of the area where the display panels 450a and 450b overlap, the heights of the display areas can be made uniform, thereby improving the display quality of the image displayed in the display area 79.

[0161] Although the relationship between the display panel 450a and the display panel 450b has been described above as an example, the same applies to any other two adjacent display panels 450.

[0162] It is preferable that the thickness of the display panel 450 is thin in order to reduce the step between two adjacent display panels 450. For example, the thickness of the display panel 450 is preferably 1 mm or less, more preferably 300 μm or less, and even more preferably 100 μm or less.

[0163] In the above configuration example, the FPC 21 is provided on the terminal portion 14 provided on the side (front side) from which the display portion 13 is viewed, and a display device combining a plurality of display panels is shown, but this is not limiting. For example, the terminal portion 14 electrically connected to the FPC 21 may be exposed on the back side (rear side) of the side from which the display portion 13 is viewed.

[0164] 27A to 27C are diagrams illustrating a configuration in which the terminal portion 14 is exposed on the back surface side and is connected to the FPC 21 via an electrode (through electrode) that penetrates the substrate 11. For ease of explanation, Figures 27A to 27C illustrate, as components of the display panel 450, the transistor MT provided in the pixel circuit portion 57 and the terminal portion 14 having conductive layers 15A and 15B.

[0165] 27A is a schematic cross-sectional view of a display panel before conductive layers 15A and 15B are exposed in terminal portion 14. Transistor MT and terminal portion 14 are provided between substrate 11A and substrate 12. A release layer 11B is provided between substrate 11A and transistor MT and terminal portion 14.

[0166] The substrate 11A may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, a semiconductor substrate, or the like. Alternatively, a plastic substrate having heat resistance sufficient to withstand the processing temperatures of this embodiment may be used. The release layer 11B may be formed using an element selected from tungsten, molybdenum, titanium, tantalum, niobium, nickel, cobalt, zirconium, ruthenium, rhodium, palladium, osmium, iridium, and silicon, an alloy material containing such an element, or a compound material containing such an element. These materials may be used as a single layer or a laminate.

[0167] 27B is a cross-sectional view of the display panel when substrate 11A is peeled off at peeling layer 11B to expose conductive layer 15A and conductive layer 15B in terminal portion 14. Methods for peeling substrate 11A at peeling layer 11B include applying a mechanical force (a process of peeling off by hand or with a jig, a process of separating while rotating a roller, ultrasonic waves, etc.).

[0168] 27C is a cross-sectional schematic diagram of a display panel in which a substrate 11 is bonded together with an adhesive layer 11C to conductive layers 15A and 15B exposed in terminal portion 14, and through electrodes DE and FPC 21 are provided. Note that the opening in substrate 11 in which through electrodes DE are provided is preferably provided by processing substrate 11 before bonding substrate 11.

[0169] The adhesive layer 11C may be a photo-curable adhesive, a reaction-curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Alternatively, an adhesive sheet or the like may be used. The substrate 11 to be bonded to the display panel may be made of an organic resin material, a glass material having a thickness sufficient to provide flexibility, or a metal material (including an alloy material) having a thickness sufficient to provide flexibility.

[0170] The through electrode DE can be formed using various anisotropic conductive films (ACF), anisotropic conductive pastes (ACP), etc. The through electrode DE is a cured paste or sheet-like material made by mixing conductive particles with a thermosetting or thermosetting and photosetting resin. The through electrode DE becomes a material that exhibits anisotropic conductivity when irradiated with light or thermocompression bonding. Examples of conductive particles used in the through electrode DE include particles made of spherical organic resin coated with a thin film of metal such as Au, Ni, or Co.

[0171] 27A to 27C , the plurality of display panels can be configured so that the terminals are exposed on the rear surface side. This configuration allows a configuration in which a driver IC (integrated circuit) for driving the display panel, such as a source line driver circuit 31, is attached to the rear surface side of each of the plurality of display panels and connected via through electrodes. In other words, the driver IC can be provided on the rear surface side of each of the display panels, on the side (front surface side) from which the display unit 13 is viewed.

[0172] 27D is a cross-sectional schematic diagram illustrating display panels 450A and 450B as adjacent display panels. In FIG. 27D, on the side (front side) from which display unit 13 is viewed, arrows indicate the direction in which light emitted by the displayed image is emitted.

[0173] The display panel 450A shown in Figure 27D includes a visible light transmitting region 401A, a pixel circuit unit 57A, a terminal unit 14A, a driver IC 35A, and an FPC 21A. The display panel 450B shown in Figure 27D includes a visible light transmitting region 401B, a pixel circuit unit 57B, a terminal unit 14B, a driver IC 35B, and an FPC 21B. In Figure 27D, a through-electrode is provided for each display panel, and the driver IC and the pixel circuit unit are connected via the through-electrode. This configuration allows driver ICs 35A and 35B, in which the gate line driver circuit 33 plays the role of the source line driver circuit 31, to be arranged for each display panel, which is a divided region, and each display panel can be driven at a different drive frequency (frame frequency, frame rate, refresh rate, etc.).

[0174] A display device according to one embodiment of the present invention can have a gate line driver circuit and / or a source line driver circuit for each sub-display portion divided in the display unit. This allows an image to be rewritten for each sub-display portion. For example, image data can be rewritten only in a section of the display unit where an image has changed, and image data can be retained in a section where no change has occurred, thereby reducing power consumption.

[0175] Furthermore, in the display device of one embodiment of the present invention, the drive frequency (frame frequency, frame rate, refresh rate, or the like) during image display can be set arbitrarily for each sub-display unit. Therefore, by combining with eye tracking or the like, it becomes possible to apply foveated rendering, which is a type of rendering that varies the frame rate for each region depending on the user's line of sight. Therefore, a configuration can be achieved in which images with excellent display quality can be output with low load.

[0176] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0177] Embodiment 2 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 28, 29A, and 29B.

[0178] The display device of the present embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of the present embodiment can be used in electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0179] [Display Device] FIG. 28 shows a perspective view of a display device 300A, and FIG. 29A shows a cross-sectional view of the display device 300A.

[0180] The display device 300A has a configuration in which the substrate 12 and the substrate 11 are bonded together. In Fig. 28, the substrate 12 is clearly indicated by a dashed line.

[0181] The display device 300A has a display unit 13, a connection unit 340, wiring 365, etc. The display unit 13 has a plurality of sub-display units 13A. Fig. 28 shows an example in which an IC 373 and an FPC 372 are mounted on the display device 300A. Therefore, the configuration shown in Fig. 28 can also be said to be a display module having the display device 300A, an IC (integrated circuit), and an FPC.

[0182] The connection portion 340 is provided on the outside of the display portion 13. The connection portion 340 can be provided along one side or multiple sides of the display portion 13. The connection portion 340 may be single or multiple. FIG. 28 shows an example in which the connection portion 340 is provided so as to surround the display portion. The connection portion 340 electrically connects the common electrode of the light-emitting device and the conductive layer, and can supply a potential to the common electrode.

[0183] The wiring 365 has a function of supplying signals and power to the display portion 13. The signals and power are input to the wiring 365 from the outside via the FPC 372 or input to the wiring 365 from the IC 373.

[0184] 28 shows an example in which an IC 373 is provided on the substrate 11 by a COG method, a COF (chip on film) method, or the like. The IC 373 may be, for example, an IC having a source line driver circuit. The display device 300A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method or the like.

[0185] FIG. 29A shows an example of a cross section of the display device 300A when a part of the area including the FPC 372, a part of the display unit 13, a part of the 340 connection unit 340, and a part of the area including the end portion are cut away.

[0186] The display device 300A shown in Figure 29A has, between the substrate 11 and the substrate 12, a transistor 201, a transistor 205, a light-emitting device 330a that emits red light, a light-emitting device 330b that emits green light, and a light-emitting device 330c that emits blue light, etc.

[0187] The light-emitting device 330a includes a conductive layer 311a, a conductive layer 312a on the conductive layer 311a, and a conductive layer 326a on the conductive layer 312a. All or some of the conductive layers 311a, 312a, and 326a may be called pixel electrodes.

[0188] The conductive layer 311a is connected to the conductive layer 222b of the transistor 205 through an opening provided in the insulating layer 324. The end of the conductive layer 312a is located outside the end of the conductive layer 311a. The end of the conductive layer 312a and the end of the conductive layer 326a are aligned or approximately aligned. For example, a conductive layer functioning as a reflective electrode can be used for the conductive layer 311a and the conductive layer 312a, and a conductive layer functioning as a transparent electrode can be used for the conductive layer 326a.

[0189] The light-emitting device 330b includes a conductive layer 311b, a conductive layer 312b on the conductive layer 311b, and a conductive layer 326b on the conductive layer 312b.

[0190] The light-emitting device 330c includes a conductive layer 311c, a conductive layer 312c on the conductive layer 311c, and a conductive layer 326c on the conductive layer 312c.

[0191] The conductive layer 311b, the conductive layer 312b, and the conductive layer 326b in the light-emitting device 330b, and the conductive layer 311c, the conductive layer 312c, and the conductive layer 326c in the light-emitting device 330c are similar to the conductive layer 311a, the conductive layer 312a, and the conductive layer 326a in the light-emitting device 330a, and therefore detailed description thereof will be omitted.

[0192] The conductive layers 311a, 311b, and 311c have recesses formed therein so as to cover openings formed in the insulating layer 324. A layer 328 is buried in the recesses.

[0193] The layer 328 has a function of planarizing recesses of the conductive layer 311a, the conductive layer 311b, and the conductive layer 311c. The conductive layers 312a, 312b, and 312c, which are electrically connected to the conductive layer 311a, the conductive layer 311b, and the conductive layer 311c, are provided over the conductive layers 311a, 311b, 311c, and the layer 328. Therefore, regions overlapping with the recesses of the conductive layers 311a, 311b, and 311c can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased.

[0194] The layer 328 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 328. In particular, the layer 328 is preferably formed using an insulating material.

[0195] An insulating layer containing an organic material can be suitably used for the layer 328. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, precursors of these resins, or the like can be used for the layer 328. Alternatively, a photosensitive resin can be used for the layer 328. The photosensitive resin can be a positive material or a negative material.

[0196] By using a photosensitive resin, the layer 328 can be formed only through exposure and development steps, and the influence of dry etching, wet etching, etc. on the surfaces of the conductive layers 311 a, 311 b, and 311 c can be reduced. Furthermore, by forming the layer 328 using a negative photosensitive resin, the layer 328 can be formed using the same photomask (exposure mask) as that used to form the openings in the insulating layer 324 in some cases.

[0197] The top and side surfaces of the conductive layer 312a and the conductive layer 326a are covered with the first layer 313a. The top and side surfaces of the conductive layer 312b and the conductive layer 326b are covered with the second layer 313b. The top and side surfaces of the conductive layer 312c and the conductive layer 326c are covered with the third layer 313c. Therefore, the entire region where the conductive layer 312a, the conductive layer 312b, or the conductive layer 312c is provided can be used as the light-emitting region of the light-emitting device 330a, the light-emitting device 330b, or the light-emitting device 330c, thereby increasing the aperture ratio of the pixel.

[0198] The side surfaces of the first layer 313a, the second layer 313b, and the third layer 313c are covered with an insulating layer 325 and an insulating layer 327, respectively. A sacrificial layer 318a is located between the first layer 313a and the insulating layer 325, a sacrificial layer 318b is located between the second layer 313b and the insulating layer 325, and a sacrificial layer 318c is located between the third layer 313c and the insulating layer 325. A fourth layer 314 is provided on the first layer 313a, the second layer 313b, the third layer 313c, the insulating layer 325, and the insulating layer 327, and a common electrode 315 is provided on the fourth layer 314. The fourth layer 314 and the common electrode 315 are continuous films provided in common to the light-receiving device and the light-emitting device, respectively. In addition, a protective layer 331 is provided on the light emitting device 330a, the light emitting device 330b, and the light emitting device 330c.

[0199] The protective layer 331 and the substrate 12 are bonded via an adhesive layer 342. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting device. In FIG. 29A , the space between the substrate 12 and the substrate 11 is filled with the adhesive layer 342, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 342 may be provided so as not to overlap with the light-emitting device. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 342.

[0200] In the connection portion 340, a conductive layer 323 is provided over the insulating layer 324. The conductive layer 323 has an example of a stacked structure including a conductive film obtained by processing the same conductive film as the conductive layers 311a, 311b, and 311c, a conductive film obtained by processing the same conductive film as the conductive layers 312a, 312b, and 312c, and a conductive film obtained by processing the same conductive film as the conductive layers 326a, 326b, and 326c. Ends of the conductive layer 323 are covered with a sacrificial layer, an insulating layer 325, and an insulating layer 327. A fourth layer 314 is provided over the conductive layer 323, and a common electrode 315 is provided over the fourth layer 314. The conductive layer 323 and the common electrode 315 are electrically connected via the fourth layer 314. The fourth layer 314 does not necessarily have to be formed in the connection portion 340. In this case, the conductive layer 323 and the common electrode 315 are in direct contact with each other and electrically connected.

[0201] The display device 300A is a top-emission type. Light emitted by the light-emitting device is emitted toward the substrate 12. The substrate 12 is preferably made of a material that is highly transparent to visible light. The pixel electrodes contain a material that reflects visible light, and the counter electrode (common electrode 315) contains a material that transmits visible light.

[0202] The insulating layer 215 is provided to cover the transistor. The insulating layer 324 is provided to cover the transistor and functions as a planarization layer. Note that the number of insulating layers covering the transistor is not limited, and each insulating layer may be a single layer or two or more layers.

[0203] At least one insulating layer covering the transistor is preferably made of a material that is resistant to the diffusion of impurities such as water and hydrogen. This allows the insulating layer to function as a barrier layer. With this structure, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device.

[0204] The insulating layer 215 is preferably an inorganic insulating film. Examples of inorganic insulating films that can be used include a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, and an aluminum nitride film. Alternatively, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film may be used. Two or more of the above insulating films may be stacked.

[0205] The insulating layer 324, which functions as a planarization layer, can be preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 324 may also have a stacked structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 324 preferably functions as an etching protection film. This can prevent recesses from being formed in the insulating layer 324 during processing of the conductive layer 311b, the conductive layer 312b, the conductive layer 326b, or the like. Alternatively, recesses may be formed in the insulating layer 324 during processing of the conductive layer 311b, the conductive layer 312b, the conductive layer 326b, or the like.

[0206] A connection portion 204 is provided in a region of the substrate 11 where the substrate 12 does not overlap. In the connection portion 204, a wiring 365 is electrically connected to the FPC 372 via a conductive layer 366 and a connection layer 203. The conductive layer 366 has an example of a stacked structure including a conductive film obtained by processing the same conductive film as the conductive layers 311a, 311b, and 311c, a conductive film obtained by processing the same conductive film as the conductive layers 312a, 312b, and 312c, and a conductive film obtained by processing the same conductive film as the conductive layers 326a, 326b, and 326c. The conductive layer 366 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 372 to be electrically connected via the connection layer 203.

[0207] A light-shielding layer 317 is preferably provided on the surface of the substrate 12 facing the substrate 11. The light-shielding layer 317 can be provided between adjacent light-emitting devices, at the connection portion 340, or the like. Various optical members can be disposed on the outer surface of the substrate 12. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. The outer surface of the substrate 12 may also be provided with an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, an impact absorbing layer, or the like.

[0208] By providing the protective layer 331 that covers the light emitting device and the light receiving device, it is possible to prevent impurities such as water from entering the light emitting device and the light receiving device, thereby improving the reliability of the light emitting device and the light receiving device.

[0209] The substrates 11 and 12 may each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. The substrate on the side from which light from the light-emitting device is extracted is made of a material that transmits the light. Using a flexible material for the substrates 11 and 12 can increase the flexibility of the display device. Alternatively, a polarizing plate may be used as the substrate 11 or 12.

[0210] Substrate 11 and substrate 12 can each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. One or both of substrates 11 and 12 may be made of glass having a thickness sufficient to provide flexibility.

[0211] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (or a small amount of birefringence).

[0212] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0213] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0214] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display panel. Therefore, it is preferable to use a film with low water absorption as the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0215] The adhesive layer 342 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. Adhesive sheets or the like may also be used.

[0216] The connection layer 203 may be made of ACF, ACP, or the like.

[0217] Materials that can be used for conductive layers such as the gate, source, and drain of a transistor, as well as various wirings and electrodes that constitute a display device include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys containing these metals as main components, etc. Films containing these materials can be used as a single layer or a stacked layer structure.

[0218] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloy materials containing such metal materials, can be used. Alternatively, nitrides of such metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), it is preferable to thin them sufficiently to ensure light-transmitting properties. A stacked film of the above materials can also be used as the conductive layer. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because it can enhance conductivity. These materials can also be used for conductive layers such as various wirings and electrodes constituting display devices, and conductive layers (conductive layers functioning as pixel electrodes or common electrodes) in light-emitting devices.

[0219] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0220] <Transistor>

[0221] FIG. 29B is an enlarged view of a cross section including transistor 201 and transistor 205.

[0222] The transistor 205 includes a semiconductor layer 108, an insulating layer 117, an insulating layer 110, and a conductive layer 112 stacked in this order. Parts of the insulating layer 117 and the insulating layer 110 function as gate insulating layers of the transistor 201. The conductive layer 112 functions as a gate electrode of the transistor 201. The transistor 201 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 108.

[0223] The transistor 201 includes a semiconductor layer 208, an insulating layer 110, and a conductive layer 212 stacked in this order. Part of the insulating layer 110 functions as a gate insulating layer of the transistor 205. The conductive layer 212 functions as a gate electrode of the transistor 205. The transistor 205 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 208. The transistor 205 differs from the transistor 201 in the surface where the semiconductor layer is formed. Furthermore, the transistor 205 differs from the transistor 201 in the configuration of the gate insulating layer.

[0224] The components of the transistor 201 and the transistor 205 other than the semiconductor layers can be formed in the same process, which can prevent an increase in the number of processes even when two types of transistors are mixed.

[0225] 29B includes a conductive layer 106 that functions as a back gate. The transistor 201 in FIG. 29B includes a conductive layer 206 that functions as a back gate.

[0226] 29B , a conductive layer 106 is provided on and in contact with the substrate 11. An insulating layer 103 is provided on and in contact with the conductive layer 106 and the substrate 11. A semiconductor layer 108 is provided on and in contact with the insulating layer 103. An insulating layer 117 is provided on and in contact with the upper surface of the insulating layer 103, the substrate 11, and the upper surface and side surfaces of the semiconductor layer 108. A semiconductor layer 208 is provided on and in contact with the insulating layer 117. That is, the semiconductor layer 208 is provided on a surface different from that of the semiconductor layer 108. The insulating layer 117 functions as a base film in the transistor 201. An insulating layer 110 is provided on and in contact with the upper surface of the insulating layer 117 and the upper surface and side surfaces of the semiconductor layer 208. A conductive layer 112 and a conductive layer 212 are provided on and in contact with the insulating layer 110. The conductive layer 112 has a region overlapping with the semiconductor layer 108 with the insulating layer 117 and the insulating layer 110 interposed therebetween. The conductive layer 212 has a region overlapping with the semiconductor layer 208 with the insulating layer 110 interposed therebetween.

[0227] 29B , the transistor 201 and the transistor 205 preferably further include an insulating layer 118. The insulating layer 118 is provided to cover the insulating layer 110, the conductive layer 112, and the conductive layer 212 and functions as a protective layer to protect the transistor 201 and the transistor 205.

[0228] The transistor 205 may include a conductive layer 222a and a conductive layer 222b over the insulating layer 118. The conductive layer 222a functions as one of a source electrode and a drain electrode of the transistor 205, and the conductive layer 222b functions as the other of the source electrode and the drain electrode of the transistor 205. The conductive layer 222a and the conductive layer 222b are electrically connected to the low-resistance region 108N of the semiconductor layer 108 through openings provided in the insulating layer 118, the insulating layer 110, and the insulating layer 117, respectively.

[0229] The transistor 201 may include a conductive layer 365a and a conductive layer 365b over the insulating layer 118. The conductive layer 365a functions as one of a source electrode and a drain electrode of the transistor 201, and the conductive layer 365b functions as the other of the source electrode and the drain electrode of the transistor 201. The conductive layer 365a and the conductive layer 365b are electrically connected to the low-resistance region 208N of the semiconductor layer 208 through openings provided in the insulating layer 118 and the insulating layer 110, respectively.

[0230] Here, the semiconductor layer 108 and the semiconductor layer 208 preferably contain metal oxides having different compositions. The semiconductor layer 108 and the semiconductor layer 208 can be formed by processing metal oxide films having different compositions. A display device which is one embodiment of the present invention includes a plurality of transistors having semiconductor layers with different compositions over the same substrate, and components other than the semiconductor layers can be formed in the same process.

[0231] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a display device that has both excellent electrical characteristics and high reliability can be obtained.

[0232] The following describes an example in which the transistor 201 is used as a transistor that requires a large on-state current. For example, when In—Ga—Zn oxide is used for both the semiconductor layer 108 and the semiconductor layer 208, the semiconductor layer 208 can be made of a metal oxide in which the ratio of the number of indium atoms to the number of atoms of the metal elements contained therein is higher than that of the semiconductor layer 108. Alternatively, the semiconductor layer 108 can be made of a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the metal elements contained therein is higher than that of the semiconductor layer 208.

[0233] Similarly, when an In—Ga—Zn oxide is used for the semiconductor layer 108 and a metal oxide containing indium other than an In—Ga—Zn oxide is used for the semiconductor layer 208, a metal oxide having a higher ratio of the number of indium atoms to the number of atoms of the metal element compared to the semiconductor layer 108 can be used for the semiconductor layer 208.

[0234] A metal oxide containing indium other than In—Ga—Zn oxide can also be used for the semiconductor layer 108. In this case, similarly, the semiconductor layer 208 can be made of a metal oxide in which the ratio of the number of indium atoms to the number of atoms of the metal element is higher than that of the semiconductor layer 108.

[0235] Alternatively, the semiconductor layer 108 may be formed using a metal oxide in which the ratio of the number of indium atoms to the number of atoms of the metal element contained therein is higher than that of the semiconductor layer 208 .

[0236] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions 108N sandwiching the region. The region of the semiconductor layer 108 overlapping with the conductive layer 112 functions as a channel formation region of the transistor 205. The pair of low-resistance regions 108N function as a source region and a drain region of the transistor 205. Similarly, the semiconductor layer 208 has a channel formation region overlapping with the conductive layer 212 and a pair of low-resistance regions 208N sandwiching the channel formation region.

[0237] In the transistor 205, the low-resistance region 108N can also be referred to as a region having lower resistance, a region having a higher carrier concentration, a region having a higher oxygen vacancy density, a region having a higher impurity concentration, or an n-type region than the channel formation region of the transistor 205. Similarly, in the transistor 201, the low-resistance region 208N can also be referred to as a region having lower resistance, a region having a higher carrier concentration, a region having a higher oxygen vacancy density, a region having a higher impurity concentration, or an n-type region than the channel formation region of the transistor 201.

[0238] The low-resistance region 108N and the low-resistance region 208N are regions containing impurity elements. Examples of such impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. The low-resistance region 108N and the low-resistance region 208N preferably contain boron or phosphorus. The low-resistance region 108N and the low-resistance region 208N may contain two or more of the above elements. The low-resistance region 108N and the low-resistance region 208N may contain different impurity elements.

[0239] The low resistance region 108N and the low resistance region 208N can be formed by adding impurities through the insulating layer 110 using the conductive layer 112 or the conductive layer 212 as a mask, for example.

[0240] 30 illustrates an example in which the transistor 201 and the transistor 205 are used as transistors included in the display portion 13. The pixel circuit of the display portion 13 includes the transistor 201 and the transistor 205, thereby realizing a display device with high display quality and excellent reliability. Furthermore, the manufacturing process of the display device can be simplified compared to that of FIG. 31 described later.

[0241] 31 illustrates an example in which the transistors 201, 205, and 202 are used as transistors constituting the display unit 13. When the pixel circuit of the display unit 13 includes the transistors 201, 202, and 205, a display device with high display quality and excellent reliability can be realized.

[0242] The transistor 202 includes a semiconductor layer 411, an insulating layer 412, a conductive layer 413, and the like. The semiconductor layer 411 includes a channel formation region 411i and a low-resistance region 411n. The semiconductor layer 411 includes silicon. The semiconductor layer 411 preferably includes polycrystalline silicon. For example, LTPS can be used as the polycrystalline silicon. A part of the insulating layer 412 functions as a gate insulating layer. A part of the conductive layer 413 functions as a gate electrode.

[0243] The low-resistance region 311n is a region containing an impurity element. For example, when the transistor 202 is an n-channel transistor, phosphorus, arsenic, or the like may be added to the low-resistance region 311n. On the other hand, when the transistor 202 is a p-channel transistor, boron, aluminum, or the like may be added to the low-resistance region 311n. Furthermore, in order to control the threshold voltage of the transistor 202, the above-mentioned impurities may be added to the channel formation region 311i.

[0244] The transistor 202 may include a conductive layer 421a and a conductive layer 421b over the insulating layer 118. The conductive layer 421a functions as one of a source electrode and a drain electrode of the transistor 202, and the conductive layer 421b functions as the other of the source electrode and the drain electrode of the transistor 202. The conductive layer 421a and the conductive layer 421b are electrically connected to the low-resistance region 411n through openings provided in the insulating layer 118, the insulating layer 110, the insulating layer 117, and the insulating layer 412, respectively.

[0245] Here, the conductive layers 421a and 421b electrically connected to the transistor 202 are preferably formed by processing the same conductive film as the conductive layers 222a, 222b, 365a, and 365b, which can simplify the manufacturing process.

[0246] The conductive layer 413 functioning as the gate electrode of the transistor 202, the conductive layer 206 functioning as the second gate electrode of the transistor 201, and the conductive layer 106 functioning as the second gate of the transistor 205 are preferably formed by processing the same conductive film, which is preferable because the manufacturing process can be simplified.

[0247] Note that the transistor 202 may have a second gate electrode. In the case where the transistor 202 has the second gate electrode, for example, a conductive layer functioning as the second gate electrode may be provided over the substrate 11, an insulating layer may be provided so as to be in contact with the conductive layer and top surfaces of the substrate 11, and the semiconductor layer 411 may be provided over the insulating layer. Furthermore, the conductive layer 413 and the conductive layer functioning as the second gate electrode preferably have regions overlapping each other.

[0248] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0249] Embodiment 3 In this embodiment, a light-emitting device that can be used for a display device according to one embodiment of the present invention will be described.

[0250] As shown in FIG. 32A , the light-emitting device has an EL layer 786 between a pair of electrodes (a lower electrode 772 and an upper electrode 788). The EL layer 786 can be composed of multiple layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can have, for example, a layer containing a substance with high electron-injecting properties (electron-injecting layer) and a layer containing a substance with high electron-transporting properties (electron-transporting layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with high hole-injecting properties (hole-injecting layer) and a layer containing a substance with high hole-transporting properties (hole-transporting layer).

[0251] A structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 32A is referred to as a single structure in this specification.

[0252] Fig. 32B shows a modified example of the EL layer 786 included in the light-emitting device shown in Fig. 32A. Specifically, the light-emitting device shown in Fig. 32B includes a layer 4431 on a lower electrode 772, a layer 4432 on the layer 4431, a light-emitting layer 4411 on the layer 4432, a layer 4421 on the light-emitting layer 4411, a layer 4422 on the layer 4421, and an upper electrode 788 on the layer 4422. For example, when the lower electrode 772 is an anode and the upper electrode 788 is a cathode, the layer 4431 functions as a hole injection layer, the layer 4432 functions as a hole transport layer, the layer 4421 functions as an electron transport layer, and the layer 4422 functions as an electron injection layer. Alternatively, when the lower electrode 772 is a cathode and the upper electrode 788 is an anode, the layer 4431 functions as an electron injection layer, the layer 4432 functions as an electron transport layer, the layer 4421 functions as a hole transport layer, and the layer 4422 functions as a hole injection layer. With such a layer structure, carriers can be efficiently injected into the light-emitting layer 4411, and the efficiency of carrier recombination in the light-emitting layer 4411 can be increased.

[0253] As shown in Figures 32C and 32D, a configuration in which multiple light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between the layer 4420 and the layer 4430 is also a variation of the single structure.

[0254] 32E and 32F, a configuration in which a plurality of light-emitting units (EL layer 786a, EL layer 786b) are connected in series via charge generation layer 4440 is referred to as a tandem structure in this specification. The tandem structure may also be referred to as a stack structure. The tandem structure makes it possible to provide a light-emitting device capable of emitting light with high brightness.

[0255] 32C and 32D , the light-emitting layers 4411, 4412, and 4413 may be made of light-emitting materials that emit light of the same color, or even the same light-emitting material. For example, the light-emitting layers 4411, 4412, and 4413 may be made of a light-emitting material that emits blue light. A color conversion layer may be provided as the layer 785 shown in Fig. 32D . Note that by using quantum dots as the color conversion layer, a light-emitting device with excellent color purity and good external quantum efficiency can be obtained.

[0256] The light-emitting layers 4411, 4412, and 4413 may each be made of a light-emitting material that emits light of a different color. When the light emitted from the light-emitting layers 4411, 4412, and 4413 has a complementary color relationship, white light can be obtained. A color filter (also referred to as a coloring layer) may be provided as the layer 785 shown in FIG. 32D. When white light passes through the color filter, light of a desired color can be obtained.

[0257] 32E and 32F , the light-emitting layer 4411 and the light-emitting layer 4412 may be made of light-emitting materials that emit light of the same color, or even the same light-emitting material. Alternatively, the light-emitting layer 4411 and the light-emitting layer 4412 may be made of light-emitting materials that emit different colors. When the light emitted by the light-emitting layer 4411 and the light emitted by the light-emitting layer 4412 are complementary colors, white light is obtained. FIG. 32F shows an example in which a layer 785 is further provided. The layer 785 can be one or both of a color conversion layer and a color filter (coloring layer).

[0258] 32C, 32D, 32E, and 32F, the layer 4420 and the layer 4430 may have a laminated structure consisting of two or more layers, as shown in FIG. 32B.

[0259] A structure that produces different luminescent colors (for example, blue (B), green (G), and red (R)) for each light-emitting device is sometimes called an SBS (Side By Side) structure.

[0260] The light-emitting device can emit light of red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 786. Furthermore, the color purity can be further improved by providing the light-emitting device with a microcavity structure.

[0261] A light-emitting device that emits white light preferably has a configuration in which two or more types of light-emitting materials are contained in the light-emitting layer. To obtain white light emission, light-emitting materials can be selected so that the light emitted from each of the two or more light-emitting materials has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a light-emitting device that emits white light as a whole can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0262] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0263] This embodiment mode can be combined with other embodiment modes as appropriate.

[0264] Embodiment 4 In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described.

[0265] The electronic devices exemplified below each include a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices can achieve high resolution. Furthermore, the electronic devices can also have both high resolution and a large screen.

[0266] The display portion of the electronic device according to one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0267] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0268] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a house or building, or the interior or exterior of an automobile or the like.

[0269] FIG. 33A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0270] The camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, etc. The camera 8000 is also provided with a detachable lens 8006 attached thereto.

[0271] Note that the camera 8000 may have the lens 8006 and the housing integrated together.

[0272] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display portion 8002 that functions as a touch panel.

[0273] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as a strobe device and the like.

[0274] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0275] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display portion 8102.

[0276] The button 8103 has a function as a power button or the like.

[0277] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the camera 8000 may have a built-in finder.

[0278] FIG. 33B is a diagram showing the appearance of the head-mounted display 8200.

[0279] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0280] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like and can display received video information on a display portion 8204. The main body 8203 also includes a camera and can use information on the movement of the user's eyeballs or eyelids as an input means.

[0281] The wearing unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user, capable of detecting a current that flows in association with the movement of the user's eyeballs, and may have a function of recognizing the line of sight. The wearing unit 8201 may also have a function of monitoring the user's pulse based on the current that flows through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying biometric information of the user on the display unit 8204 or a function of changing an image displayed on the display unit 8204 in accordance with the movement of the user's head.

[0282] The display device of one embodiment of the present invention can be applied to the display portion 8204 .

[0283] 33C, 33D, and 33E are diagrams showing the appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0284] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to curve the display portion 8302 because the user can feel a high sense of presence. In addition, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, three-dimensional display using parallax can be performed. Note that the present invention is not limited to a configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided, with one display portion provided for each eye of the user.

[0285] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. The display device including the semiconductor device of one embodiment of the present invention has extremely high definition, and therefore, even when an image is enlarged using the lens 8305 as in FIG. 33E , pixels are not visible to a user, and a more realistic image can be displayed.

[0286] The electronic device shown in Figures 34A to 34G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0287] The electronic devices shown in Figures 34A to 34G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on a display unit, etc.

[0288] Details of the electronic device shown in Figures 34A to 34G will be described below.

[0289] 34A is a perspective view showing a television device 9100. The television device 9100 can incorporate a display unit 9001 with a large screen, for example, 50 inches or more, or 100 inches or more.

[0290] FIG. 34B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text or image information on multiple surfaces. FIG. 34B shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and the strength of antenna reception. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0291] 34C is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0292] 34D is a perspective view showing a wristwatch-type portable information terminal 9200. The display surface of the display unit 9001 is curved, and a display can be displayed along the curved display surface. The portable information terminal 9200 can also perform hands-free conversations by communicating with, for example, a wireless headset. The portable information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0293] 34E, 34F, and 34G are perspective views showing a foldable mobile information terminal 9201. Also, FIG. 34E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 34G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 34F is a perspective view of a state in the process of changing from one of FIG. 34E and FIG. 34G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent visibility of the display. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0294] 35A shows an example of a television set. A television set 7100 includes a display portion 7500 built in a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0295] 35A can be operated not only by operation switches provided on the housing 7101 but also by a separate remote control 7111. Alternatively, a touch panel may be applied to the display portion 7500, and the television set 7100 may be operated by touching the touch panel. The remote control 7111 may have a display portion in addition to operation buttons.

[0296] The television device 7100 may include not only a television broadcast receiver but also a communication device for network connection.

[0297] 35B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7500 is incorporated in the housing 7211.

[0298] FIG. 35C shows an example of digital signage.

[0299] 35C includes a housing 7301, a display portion 7500, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0300] The larger the display unit 7500, the more information can be provided at one time, and the larger the display unit 7500 is, the more easily it will catch people's attention, which will have the effect of increasing the advertising effectiveness of advertisements, for example.

[0301] It is preferable that a touch panel be applied to the display unit 7500 so that the user can operate it, which allows the display unit 7500 to be used not only for advertising purposes but also for providing information desired by the user, such as route information, traffic information, and commercial facility guidance information.

[0302] 35C , the digital signage 7300 is preferably capable of wirelessly communicating with an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, and the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0303] Furthermore, a game can be executed on the digital signage 7300 using the information terminal 7311 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0304] 35D shows a digital signage 7400 attached to an inner wall 7401 of a cylindrical space. The digital signage 7400 includes a display unit 7500 provided along the curved surface of the inner wall 7401, as well as multiple imaging devices 7402 and multiple audio devices 7403. The digital signage 7400 can detect a user's line of sight (eye tracking) or gestures using the multiple imaging devices 7402, and can coordinate the operation of the display unit 7500 and the audio device 7403. For example, when the user directs their gaze toward advertising information displayed on the display unit 7500, the display on the display unit 7500 can be switched and the audio on the audio device 7403 can be switched. This allows the user to enjoy highly realistic displays and audio.

[0305] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS. 35A to 35D.

[0306] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0307] (Additional Notes Regarding the Description of the Present Specification, etc.) The following additional notes will be given regarding the above-described embodiments and the explanation of each configuration in the embodiments.

[0308] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0309] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0310] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0311] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0312] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0313] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0314] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0315] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0316] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0317] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0318] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0319] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0320] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0321] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, transmission of an electrical signal between A and B is possible.

[0322] 11: substrate, 12: substrate, 13A: sub-display section, 13: display section, 14: terminal section, 20: layer, 30: drive circuit section, 31: source line drive circuit, 33: gate line drive circuit, 34: pulse output circuit, 39: section, 40: source line drive circuit, 41: control circuit, 50: layer, 51: pixel circuit, 55A: transistor, 55B: transistor, 55C: transistor, 55D: transistor, 57: pixel circuit section, 56A: capacitor, 56: capacitor, 59: section, 60: layer, 61: display element

Claims

1. A head mounted display having a display unit including a first layer in which a first gate line drive circuit and a second gate line drive circuit are provided, a second layer located on the first layer and in which a first pixel circuit and a second pixel circuit are provided, and a first display element and a second display element located on the second layer, the display unit has a first sub-display unit and a second sub-display unit, the first sub-display unit corresponds to a user's gaze point, the second sub-display unit is located around the first sub-display unit, the first sub-display unit includes the first pixel circuit that controls the first display element, and the first gate line drive circuit that outputs a signal for driving the first pixel circuit; the second sub-display unit includes the second pixel circuit that controls the second display element, and the second gate line drive circuit that outputs a signal for driving the second pixel circuit; the first gate line driving circuit has a first transistor; the second gate line driving circuit has a second transistor; the first pixel circuit includes a third transistor; the second pixel circuit includes a fourth transistor; A head-mounted display, wherein in the display unit, the number of times image data is rewritten per unit time in the second sub-display unit is less than the number of times image data is rewritten per unit time in the first sub-display unit.

2. A head mounted display having a display unit including a first layer in which a first gate line drive circuit and a second gate line drive circuit are provided, a second layer located on the first layer and in which a first pixel circuit and a second pixel circuit are provided, and a first display element and a second display element located on the second layer, the display unit has a first sub-display unit and a second sub-display unit, the first sub-display unit corresponds to a user's gaze point, the second sub-display unit is located around the first sub-display unit, the first sub-display unit includes the first pixel circuit that controls the first display element, and the first gate line drive circuit that outputs a signal for driving the first pixel circuit; the second sub-display unit includes the second pixel circuit that controls the second display element, and the second gate line drive circuit that outputs a signal for driving the second pixel circuit; the first gate line driving circuit has a first transistor; the second gate line driving circuit has a second transistor; the first pixel circuit includes a third transistor; the second pixel circuit includes a fourth transistor; In the display unit, the number of times that image data is rewritten per unit time in the second sub-display unit is less than the number of times that image data is rewritten per unit time in the first sub-display unit, A head-mounted display, wherein the number of times image data is rewritten per unit time in the second sub-display section located on the outer side of the second sub-display section is less than the number of times image data is rewritten per unit time in the second sub-display section located on the inner side of the second sub-display section.

3. In claim 1 or 2, A head mounted display in which a start pulse signal is input to only one of the first gate line driving circuit and the second gate line driving circuit.