Display apparatus and electronic equipment

Abstract

Provided is a display apparatus having high display quality. The display apparatus has a picture element and a circuit. The picture element has a light-emitting device, a drive transistor, first to fourth switches, and a first capacitor. The circuit has a fifth switch, a sixth switch, and a second capacitor. A gate of the drive transistor is electrically connected to a first terminal of the first switch, a first terminal of the second switch, and a first terminal of the first capacitor, one of the source or drain of the drive transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the fourth switch, and an anode of the light-emitting device, and the other of the source or drain of the drive transistor is electrically connected to a second terminal of the second switch and a first terminal of the third switch. A second terminal of the first switch is electrically connected to a first terminal of the second capacitor, and a first terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and a second terminal of the second capacitor.

Description

Display device and electronic device

[0001] One embodiment of the present invention relates to a display device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof.

[0003] In recent years, improvements have been made in various aspects in display devices for electronic devices for XR (Extended reality or Cross reality) such as VR (Virtual Reality) and AR (Augmented Reality), mobile phones such as smartphones, tablet information terminals, notebook PCs (Personal Computers), etc. For example, display devices with high screen resolution, high color reproducibility (NTSC ratio), small drive circuits, or low power consumption are being developed.

[0004] In particular, by increasing the pixel density (resolution) and color reproducibility of the display device, the displayed image becomes clearer and the sense of reality can be enhanced. Furthermore, Patent Document 1 discloses a display device with a high number of pixels and high resolution, which is equipped with a light-emitting device containing an organic EL (Electroluminescence) material.

[0005] International Publication No. 2019 / 220278

[0006] In particular, by increasing the resolution of a display device having a light-emitting device containing an organic EL material, the area of ​​the region (light-emitting surface) on which the light-emitting device is formed becomes smaller. When the area of ​​the region (light-emitting surface) of the light-emitting device becomes smaller, the amount of current required for the light-emitting device to emit light becomes smaller, but the amount of allowable current also becomes smaller. In other words, by increasing the resolution of a display device having a light-emitting device, the range of the amount of current that can be passed through the light-emitting device becomes narrower, so that precise control of the amount of current is required to adjust the brightness of the light-emitting device.

[0007] An object of one embodiment of the present invention is to provide a display device in which the amount of current flowing in a light-emitting device can be precisely controlled.An object of one embodiment of the present invention is to provide a display device with high definition.An object of one embodiment of the present invention is to provide a display device with high display quality.An object of one embodiment of the present invention is to provide a novel display device.An object of one embodiment of the present invention is to provide an electronic device including the above-described display device.

[0008] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems.

[0009] (1) One aspect of the present invention is a display device including a pixel and a circuit. The pixel includes a light-emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, and a first capacitor. The circuit also includes a fifth switch, a sixth switch, and a second capacitor. The gate of the driving transistor is electrically connected to a first terminal of the first switch, a first terminal of the second switch, and a first terminal of the first capacitor. One of the source or drain of the driving transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the fourth switch, and an anode of the light-emitting device. The other of the source or drain of the driving transistor is electrically connected to a second terminal of the second switch and a first terminal of the third switch. The second terminal of the first switch is electrically connected to a first terminal of the second capacitor. The first terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and a second terminal of the second capacitor.

[0010] (2) Alternatively, according to one aspect of the present invention, in the above-described (1), the first switch may include a first n-channel transistor, the second switch may include a second n-channel transistor, the third switch may include a third n-channel transistor, and the fourth switch may include a fourth n-channel transistor. In particular, it is preferable that one of the source or the drain of the first transistor is electrically connected to a first terminal of the first switch, and the other of the source or the drain of the first transistor is electrically connected to a second terminal of the first switch. It is also preferable that one of the source or the drain of the second transistor is electrically connected to a first terminal of the second switch, and the other of the source or the drain of the second transistor is electrically connected to a second terminal of the second switch. It is also preferable that one of the source or the drain of the third transistor is electrically connected to a first terminal of the third switch, and the other of the source or the drain of the third transistor is electrically connected to a second terminal of the third switch. It is also preferable that one of the source or drain of the fourth transistor is electrically connected to a first terminal of the fourth switch, and the other of the source or drain of the fourth transistor is electrically connected to a second terminal of the fourth switch.

[0011] (3) Another embodiment of the present invention is a display device including a pixel and a circuit, the display device having a configuration different from that of the display device described in (1). The pixel includes a light-emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a third capacitor. The circuit includes a sixth switch, a seventh switch, an eighth switch, and a second capacitor. The driving transistor includes a first gate and a second gate. The first gate of the driving transistor is electrically connected to a first terminal of the first switch, a first terminal of the second switch, and a first terminal of the first capacitor. One of the source and the drain of the driving transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the third capacitor, a second terminal of the second switch, a first terminal of the third switch, and a first terminal of the fourth switch. The second gate of the driving transistor is electrically connected to a second terminal of the third capacitor and a first terminal of the fifth switch. The second terminal of the third switch is electrically connected to the anode of the light-emitting device, the second terminal of the first switch is electrically connected to the first terminal of the second capacitor and the first terminal of the eighth switch, and the first terminal of the sixth switch is electrically connected to the first terminal of the seventh switch and the second terminal of the second capacitor.

[0012] (4) Alternatively, according to one embodiment of the present invention, in the above (3), the first switch may include a first n-channel transistor, the second switch may include a second n-channel transistor, the third switch may include a third n-channel transistor, the fourth switch may include a fourth n-channel transistor, and the fifth switch may include a fifth n-channel transistor. In particular, it is preferable that one of the source or the drain of the first transistor is electrically connected to a first terminal of the first switch, and the other of the source or the drain of the first transistor is electrically connected to a second terminal of the first switch. It is also preferable that one of the source or the drain of the second transistor is electrically connected to a first terminal of the second switch, and the other of the source or the drain of the second transistor is electrically connected to a second terminal of the second switch. It is also preferable that one of the source or the drain of the third transistor is electrically connected to a first terminal of the third switch, and the other of the source or the drain of the third transistor is electrically connected to a second terminal of the third switch. Preferably, one of the source or drain of the fourth transistor is electrically connected to a first terminal of the fourth switch, and the other of the source or drain of the fourth transistor is electrically connected to a second terminal of the fourth switch. Preferably, one of the source or drain of the fifth transistor is electrically connected to a first terminal of the fifth switch, and the other of the source or drain of the fifth transistor is electrically connected to a second terminal of the fifth switch.

[0013] (5) Another aspect of the present invention is a display device including a pixel and a circuit, and having a configuration different from that of the display devices described above in (1) and (3). The pixel includes a light-emitting device, a driving transistor, a first switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a third capacitor. The circuit includes a sixth switch, a seventh switch, an eighth switch, and a second capacitor. The driving transistor includes a first gate and a second gate. The first gate of the driving transistor is electrically connected to a first terminal of the first switch and a first terminal of the first capacitor. One of the source and the drain of the driving transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the third capacitor, a first terminal of the third switch, and a first terminal of the fourth switch. The second gate of the driving transistor is electrically connected to a second terminal of the third capacitor and a first terminal of the fifth switch. The second terminal of the third switch is electrically connected to an anode of the light-emitting device. The second terminal of the first switch is electrically connected to the first terminal of the second capacitor and the first terminal of the eighth switch, and the first terminal of the sixth switch is electrically connected to the first terminal of the seventh switch and the second terminal of the second capacitor.

[0014] (6) Alternatively, according to one aspect of the present invention, in the above (5), the first switch may include a first n-channel transistor, the third switch may include a third n-channel transistor, the fourth switch may include a fourth n-channel transistor, and the fifth switch may include a fifth n-channel transistor. In particular, it is preferable that one of the source or the drain of the first transistor is electrically connected to a first terminal of the first switch, and the other of the source or the drain of the first transistor is electrically connected to a second terminal of the first switch. It is also preferable that one of the source or the drain of the third transistor is electrically connected to a first terminal of the third switch, and the other of the source or the drain of the third transistor is electrically connected to a second terminal of the third switch. It is also preferable that one of the source or the drain of the fourth transistor is electrically connected to a first terminal of the fourth switch, and the other of the source or the drain of the fourth transistor is electrically connected to a second terminal of the fourth switch. It is also preferable that one of the source or drain of the fifth transistor is electrically connected to a first terminal of the fifth switch, and the other of the source or drain of the fifth transistor is electrically connected to a second terminal of the fifth switch.

[0015] (7) One aspect of the present invention is a display device including a pixel and a circuit. The pixel includes a light-emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor. The circuit also includes a fifth switch and a sixth switch. The gate of the driving transistor is electrically connected to a first terminal of the first switch, a first terminal of the second switch, and a first terminal of the first capacitor. One of the source or the drain of the driving transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the fourth switch, and an anode of the light-emitting device. The other of the source or the drain of the driving transistor is electrically connected to a second terminal of the second switch and a first terminal of the third switch. The second terminal of the first switch is electrically connected to a first terminal of the second capacitor. The first terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and a second terminal of the second capacitor.

[0016] (8) Another embodiment of the present invention is a display device including a pixel and a circuit, and having a configuration different from that of the display device described in (7). The pixel includes a light-emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor. The circuit also includes a fifth switch and a sixth switch. The gate of the driving transistor is electrically connected to a first terminal of the second switch, a first terminal of the first capacitor, and a first terminal of the second capacitor. One of the source or drain of the driving transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the fourth switch, and an anode of the light-emitting device. The other of the source or drain of the driving transistor is electrically connected to a second terminal of the second switch and a first terminal of the third switch. The second terminal of the second capacitor is electrically connected to a first terminal of the first switch. The first terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and a second terminal of the first switch.

[0017] (9) Another aspect of the present invention is a display device including a pixel and a circuit, and having a configuration different from that of the display devices of (7) and (8). The pixel includes a light-emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a second capacitor. The circuit also includes a sixth switch. The gate of the driving transistor is electrically connected to a first terminal of the second switch, a first terminal of the first capacitor, and a first terminal of the second capacitor. One of the source or drain of the driving transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the fourth switch, and an anode of the light-emitting device. The other of the source or drain of the driving transistor is electrically connected to a second terminal of the second switch and a first terminal of the third switch. The second terminal of the second capacitor is electrically connected to a first terminal of the first switch and a first terminal of the fifth switch. The first terminal of the sixth switch is electrically connected to a second terminal of the first switch.

[0018] (10) Another embodiment of the present invention is a display device including a pixel and a driver circuit. The pixel includes a light-emitting device, a driver transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a second capacitor. A gate of the driver transistor is electrically connected to a first terminal of the second switch, a first terminal of the first capacitor, and a first terminal of the second capacitor. One of a source or a drain of the driver transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the fourth switch, and an anode of the light-emitting device. The other of the source or the drain of the driver transistor is electrically connected to a second terminal of the second switch and a first terminal of the third switch. The second terminal of the second capacitor is electrically connected to a first terminal of the first switch and a first terminal of the fifth switch. The driver circuit is electrically connected to a second terminal of the first switch. The driver circuit has a function of transmitting an image signal to the second terminal of the first switch.

[0019] (11) Alternatively, according to one embodiment of the present invention, in any one of the above (7) to (10), the first switch may include an n-channel first transistor, the second switch may include an n-channel second transistor, the third switch may include an n-channel third transistor, and the fourth switch may include an n-channel fourth transistor. In particular, it is preferable that one of the source or the drain of the first transistor is electrically connected to a first terminal of the first switch, and the other of the source or the drain of the first transistor is electrically connected to a second terminal of the first switch. It is also preferable that one of the source or the drain of the second transistor is electrically connected to a first terminal of the second switch, and the other of the source or the drain of the second transistor is electrically connected to a second terminal of the second switch. It is also preferable that one of the source or the drain of the third transistor is electrically connected to a first terminal of the third switch, and the other of the source or the drain of the third transistor is electrically connected to a second terminal of the third switch. It is also preferable that one of the source or drain of the fourth transistor is electrically connected to a first terminal of the fourth switch, and the other of the source or drain of the fourth transistor is electrically connected to a second terminal of the fourth switch.

[0020] (12) Another embodiment of the present invention is a display device including a pixel and a circuit, and having a configuration different from that of any of the above-described (7) to (9). The pixel includes a light-emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an eighth switch, a first capacitor, a second capacitor, and a third capacitor. The circuit includes a sixth switch and a seventh switch. The driving transistor includes a first gate and a second gate. A first gate of the driving transistor is electrically connected to a first terminal of the first switch, a first terminal of the second switch, a first terminal of the eighth switch, and a first terminal of the first capacitor, one of a source or a drain of the driving transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the third capacitor, a second terminal of the second switch, a first terminal of the third switch, and a first terminal of the fourth switch, and a second gate of the driving transistor is electrically connected to a second terminal of the third capacitor and a first terminal of the fifth switch. The second terminal of the third switch is electrically connected to an anode of the light-emitting device. The second terminal of the first switch is electrically connected to a first terminal of the second capacitor. The second terminal of the second capacitor is electrically connected to a first terminal of the sixth switch and a first terminal of the seventh switch.

[0021] (13) Another embodiment of the present invention is a display device including a pixel and a circuit, and having a configuration different from those of the above-described (7) to (9) and (12). The pixel includes a light-emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an eighth switch, a first capacitor, a second capacitor, and a third capacitor. The circuit includes a sixth switch and a seventh switch. The driving transistor includes a first gate and a second gate. A first gate of the driving transistor is electrically connected to a first terminal of the second switch, a first terminal of the eighth switch, a first terminal of the first capacitor, and a first terminal of the second capacitor terminal, one of a source or a drain of the driving transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the third capacitor, a second terminal of the second switch, a first terminal of the third switch, and a first terminal of the fourth switch, and a second gate of the driving transistor is electrically connected to a second terminal of the third capacitor and a first terminal of the fifth switch. The second terminal of the third switch is electrically connected to an anode of the light-emitting device. The second terminal of the second capacitor is electrically connected to a first terminal of the first switch. The second terminal of the first switch is electrically connected to a first terminal of the sixth switch and a first terminal of the seventh switch.

[0022] (14) Another embodiment of the present invention is a display device including a pixel and a circuit, and having a configuration different from the above-described (7) to (9), (12), and (13). The pixel includes a light-emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, an eighth switch, a first capacitor, a second capacitor, and a third capacitor. The circuit includes a seventh switch. The driving transistor includes a first gate and a second gate. A first gate of the driving transistor is electrically connected to a first terminal of the second switch, a first terminal of the eighth switch, a first terminal of the first capacitor, and a first terminal of the second capacitor terminal, one of a source or a drain of the driving transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the third capacitor, a second terminal of the second switch, a first terminal of the third switch, and a first terminal of the fourth switch, and a second gate of the driving transistor is electrically connected to a second terminal of the third capacitor and a first terminal of the fifth switch. The second terminal of the third switch is electrically connected to an anode of the light-emitting device. The second terminal of the second capacitor is electrically connected to a first terminal of the first switch and a first terminal of the sixth switch. The second terminal of the first switch is electrically connected to a first terminal of the seventh switch.

[0023] (15) Another embodiment of the present invention is a display device including a pixel and a drive circuit, and having a configuration different from that of the display device of (10). The pixel includes a light-emitting device, a drive transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, an eighth switch, a first capacitor, a second capacitor, and a third capacitor. The drive transistor also has a first gate and a second gate. The first gate of the drive transistor is electrically connected to a first terminal of the second switch, a first terminal of the eighth switch, a first terminal of the first capacitor, and a first terminal of the second capacitor terminal. One of the source and the drain of the drive transistor is electrically connected to a second terminal of the first capacitor, a first terminal of the third capacitor, a second terminal of the second switch, a first terminal of the third switch, and a first terminal of the fourth switch. The second gate of the drive transistor is electrically connected to a second terminal of the third capacitor and a first terminal of the fifth switch. The second terminal of the third switch is electrically connected to the anode of the light-emitting device. The second terminal of the second capacitor is electrically connected to the first terminal of the first switch and the first terminal of the sixth switch. The drive circuit is electrically connected to the second terminal of the first switch. The drive circuit has a function of transmitting an image signal to the second terminal of the first switch.

[0024] (16) Alternatively, according to one embodiment of the present invention, in any one of the above (12) to (15), the first switch may include an n-channel first transistor, the second switch may include an n-channel second transistor, the third switch may include an n-channel third transistor, the fourth switch may include an n-channel fourth transistor, and the fifth switch may include an n-channel fifth transistor. In particular, it is preferable that one of the source or the drain of the first transistor is electrically connected to a first terminal of the first switch, and the other of the source or the drain of the first transistor is electrically connected to a second terminal of the first switch. It is also preferable that one of the source or the drain of the second transistor is electrically connected to a first terminal of the second switch, and the other of the source or the drain of the second transistor is electrically connected to a second terminal of the second switch. It is also preferable that one of the source or the drain of the third transistor is electrically connected to a first terminal of the third switch, and the other of the source or the drain of the third transistor is electrically connected to a second terminal of the third switch. Preferably, one of the source or drain of the fourth transistor is electrically connected to a first terminal of the fourth switch, and the other of the source or drain of the fourth transistor is electrically connected to a second terminal of the fourth switch. Preferably, one of the source or drain of the fifth transistor is electrically connected to a first terminal of the fifth switch, and the other of the source or drain of the fifth transistor is electrically connected to a second terminal of the fifth switch.

[0025] (17) Alternatively, in one embodiment of the present invention, in any of the above (1) to (16), the light-emitting device may include an organic EL device.

[0026] (18) Another embodiment of the present invention is an electronic device including the display device described in (17) above and a housing.

[0027] According to one embodiment of the present invention, a display device in which the amount of current flowing through a light-emitting device can be precisely controlled can be provided. Alternatively, according to one embodiment of the present invention, a display device with high resolution can be provided. Alternatively, according to one embodiment of the present invention, a display device with high display quality can be provided. Alternatively, according to one embodiment of the present invention, a novel display device can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the above-described display device can be provided.

[0028] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0029] FIG. 1 is a block diagram showing an example of the configuration of a display device. FIG. 2 is a circuit diagram showing an example of the configuration of a display device. FIGS. 3A and 3B are timing charts showing an example of the operation of the display device. FIGS. 4A to 4C are diagrams showing the relationship between the potential of an image data signal input to a circuit and the potential of an image data signal output from the circuit. FIG. 5 is a timing chart showing an example of the operation of the display device. FIGS. 6A and 6B are plan views showing an example of a circuit layout. FIG. 7 is a plan view showing an example of a circuit layout. FIGS. 8A to 8C are circuit diagrams showing an example of the configuration of a pixel included in the display device. FIG. 9 is a circuit diagram showing an example of the configuration of a display device. FIG. 10 is a circuit diagram showing an example of the configuration of a display device. FIG. 11 is a circuit diagram showing an example of the configuration of a display device. FIG. 12 is a circuit diagram showing an example of the configuration of a display device. FIG. 13 is a circuit diagram showing an example of the configuration of a display device. FIG. 14 is a circuit diagram showing an example of the configuration of a display device. FIG. 15 is a circuit diagram showing an example of the configuration of a display device. FIG. 16 is a timing chart showing an example of the operation of the display device. FIG. 17 is a circuit diagram showing an example of the configuration of a display device. 18A to 18C are timing charts showing an example of the operation of a display device. FIGS. 19A to 19C are diagrams showing the relationship between the potential of an image data signal input to a circuit and the potential of an image data signal output from the circuit. FIG. 20 is a plan view showing an example of a circuit layout. FIG. 21 is a circuit diagram showing an example of the configuration of a display device. FIG. 22 is a circuit diagram showing an example of the configuration of a display device. FIGS. 23A to 23D are circuit diagrams showing an example of the configuration of a circuit included in a display device. FIG. 24 is a circuit diagram showing an example of the configuration of a display device. FIG. 25 is a circuit diagram showing an example of the configuration of a display device. FIG. 26 is a circuit diagram showing an example of the configuration of a display device. FIG. 27 is a circuit diagram showing an example of the configuration of a display device. FIG. 28 is a circuit diagram showing an example of the configuration of a display device. FIG. 29 is a circuit diagram showing an example of the configuration of a display device. FIG. 30 is a circuit diagram showing an example of the configuration of a display device. FIG. 31 is a timing chart showing an example of the operation of a display device. FIGS. 32A to 32C are schematic cross-sectional views showing an example of the configuration of a display device. FIG. 33A is a plan view schematically illustrating an example of a display section of a display device, and FIG. 33B is a plan view schematically illustrating an example of a drive circuit region of the display device.34A and 34B are plan schematic views showing an example of the configuration of a display device. FIGS. 35A and 35B are block diagrams showing an example of the configuration of a display device. FIG. 36 is a cross-sectional schematic view showing an example of the configuration of a display device. FIGS. 37A to 37C are cross-sectional schematic views showing partial regions of an example of the configuration of a display device. FIG. 38 is a cross-sectional schematic view showing an example of the configuration of a display device. FIG. 39 is a cross-sectional schematic view showing an example of the configuration of a display device. FIG. 40 is a cross-sectional schematic view showing an example of the configuration of a display device. FIG. 41 is a cross-sectional schematic view showing an example of the configuration of a display device. FIG. 42 is a cross-sectional schematic view showing an example of the configuration of a display device. FIG. 43A is a cross-sectional schematic view showing an example of the configuration of a display device, and FIGS. 43B and 43C are cross-sectional schematic views showing examples of the configuration of a transistor. FIG. 44 is a cross-sectional schematic view showing an example of the configuration of a display device. FIG. 45 is a cross-sectional schematic view showing an example of the configuration of a display device. FIG. 46 is a cross-sectional schematic view showing an example of the configuration of a display device. FIG. 47A is a cross-sectional view showing an example of the configuration of a display device, and FIG. 47B is a cross-sectional view showing an example of the configuration of a light-emitting device. FIG. 48 is a cross-sectional view showing an example of the configuration of a display device. FIGS. 49A to 49D are cross-sectional views showing an example of the configuration of an LED package. FIGS. 50A and 50B are plan views showing an example of the configuration of an LED package. FIG. 51A is a cross-sectional view showing an example of the configuration of a display device, and FIG. 51B is a cross-sectional view showing an example of the configuration of a substrate provided in the display device and light-emitting diodes on the substrate. FIGS. 52A to 52F are views showing an example of the configuration of a light-emitting device. FIGS. 53A to 53C are views showing an example of the configuration of a light-emitting device. FIG. 54A is a circuit diagram showing an example of the configuration of a pixel circuit included in the display device, and FIG. 54B is a perspective view showing an example of the configuration of a pixel circuit included in the display device. FIGS. 55A to 55G are plan views showing an example of a pixel. FIGS. 56A to 56F are plan views showing an example of a pixel. Figures 57A to 57H are plan views showing an example of a pixel. Figures 58A to 58D are plan views showing an example of a pixel. Figures 59A to 59G are plan views showing an example of a pixel. Figure 60A is a schematic plan view showing an example of the configuration of a transistor, and Figures 60B and 60C are schematic cross-sectional views showing an example of the configuration of a transistor.Fig. 61A and Fig. 61B are diagrams showing configuration examples of a display module. Fig. 62A to Fig. 62F are diagrams showing configuration examples of an electronic device. Fig. 63A to Fig. 63D are diagrams showing configuration examples of an electronic device. Fig. 64A to Fig. 64C are diagrams showing configuration examples of an electronic device. Fig. 65A to Fig. 65H are diagrams showing configuration examples of an electronic device.

[0030] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (e.g., a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are all examples of semiconductor devices. Furthermore, for example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device or may include a semiconductor device.

[0031] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and connection relationships other than those shown in a figure or text are also understood to be disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, or a layer).

[0032] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, and a load) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows.

[0033] Note that when both an element and a power supply line (for example, VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or a wiring that provides a desired potential) are arranged between X and Y, it is not specified that X and Y are electrically connected. Note that when only a power supply line is arranged between X and Y, there is no other element between X and Y, so X and Y are directly connected. Therefore, when only a power supply line is arranged between X and Y, it can also be said that "X and Y are electrically connected." However, when both an element and a power supply line are arranged between X and Y, it can be said that X and the power supply line are electrically connected (via the element) and Y and the power supply line are electrically connected, but it is not specified that X and Y are electrically connected. Note that when the gate and source of a transistor are connected between X and Y, it is not specified that X and Y are electrically connected. Note that when the gate and drain of a transistor are connected between X and Y, it is not specified that X and Y are electrically connected. That is, in the case of a transistor, if there is a connection between X and Y via the drain and source of the transistor, it is defined that X and Y are electrically connected. Note that if a capacitive element is disposed between X and Y, it may or may not be defined that X and Y are electrically connected. For example, in the configuration of a digital circuit or logic circuit, if a capacitive element is disposed between X and Y, it may not be defined that X and Y are electrically connected. On the other hand, for example, in the configuration of an analog circuit, if a capacitive element is disposed between X and Y, it may be defined that X and Y are electrically connected.

[0034] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (for example, inverters, NAND circuits, and NOR circuits), signal conversion circuits (for example, digital-analog conversion circuits, analog-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (for example, power supply circuits such as step-up circuits or step-down circuits, and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (for example, circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0035] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0036] For example, it can be expressed as follows: "X, Y, the source (sometimes referred to as either the first terminal or the second terminal) and the drain (sometimes referred to as the other of the first terminal or the second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y." Or, it can be expressed as follows: "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in the circuit configuration, it is possible to distinguish between the source and drain of the transistor and determine the technical scope. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

[0037] Note that even when independent components are shown electrically connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0038] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0039] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," or "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," or "gate capacitance." A "capacitance" (including a "capacitance" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0040] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification.

[0041] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0042] Furthermore, in this specification, circuit elements such as a "light-emitting device" and a "light-receiving device" may have polarities referred to as an "anode" and a "cathode." In the case of a "light-emitting device," applying a forward bias (applying a positive potential relative to the "cathode" to the "anode") may cause the "light-emitting device" to emit light. In the case of a "light-receiving device," applying a zero bias or a reverse bias (applying a negative potential relative to the "cathode" to the "anode") and irradiating the "light-receiving device" with light may generate a current between the "anode" and the "cathode." As described above, the "anode" and the "cathode" may be treated as input / output terminals in circuit elements such as a "light-emitting device" and a "light-receiving device." In this specification, the "anode" and the "cathode" in circuit elements such as a "light-emitting device" and a "light-receiving device" may be referred to as terminals (first terminal, second terminal, etc.). For example, one of the "anode" or the "cathode" may be referred to as a first terminal, and the other of the "anode" or the "cathode" may be referred to as a second terminal.

[0043] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a single resistor is shown on a circuit diagram, this includes two or more resistors electrically connected in series. For example, when a single capacitor is shown on a circuit diagram, this includes two or more capacitors electrically connected in parallel. For example, when a single transistor is shown on a circuit diagram, this includes two or more transistors electrically connected in series, with the gates of the respective transistors electrically connected to each other. Similarly, when a single switch is shown on a circuit diagram, this includes two or more transistors, with the switch including two or more transistors electrically connected in series or parallel, and the gates of the respective transistors electrically connected to each other.

[0044] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0045] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0046] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0047] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0048] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0049] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0050] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0051] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0052] Furthermore, in this specification, wiring electrically connecting components arranged in a matrix can extend in the row direction or the column direction. For example, when this specification describes that "wiring A extends in the row direction," wiring A may also extend in the column direction. Conversely, when this specification describes that "wiring A extends in the column direction," wiring A may also extend in the row direction. In other words, the direction in which wiring electrically connecting components arranged in a matrix extends is not limited to the directions described in this specification, and may be the row direction or the column direction.

[0053] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" or "insulating film" may be changed to the term "insulator".

[0054] Furthermore, the terms "electrode," "wiring," and "terminal" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0055] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0056] In addition, timing charts may be used in this specification and the like to explain an operation method of a semiconductor device. The timing charts used in this specification and the like illustrate ideal operation examples, and the periods, magnitudes of signals (e.g., potentials or currents), and timings described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification and the like can be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as being long and the other period is shown as being short, the lengths of the two periods may be equal, or one period may be short and the other period may be long.

[0057] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0058] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0059] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause, for example, one or both of the following: an increase in defect level density in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0060] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0061] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0062] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls conduction and non-conduction.

[0063] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0064] In this specification and the like, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification and the like, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (e.g., a color filter) to form a full-color display device.

[0065] Light-emitting devices can be broadly divided into single structures and tandem structures. A single-structure device preferably has one light-emitting unit between a pair of electrodes, and the light-emitting unit includes one or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers may be selected such that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration in which the entire light-emitting device emits white light may be obtained. When three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers may be combined to produce a configuration in which the entire light-emitting device emits white light.

[0066] A tandem-structure device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, light from the light-emitting layers of the multiple light-emitting units may be combined to obtain white light emission. The configuration for obtaining white light emission is the same as that of the single-structure device. In a tandem-structure device, it is preferable to provide an intermediate layer such as a charge-generating layer between the multiple light-emitting units.

[0067] Furthermore, when comparing the above-described white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If it is desired to reduce power consumption, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0068] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0069] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0070] In addition, the content (or even a part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even a part of the content) described in that embodiment and one or more other content (or even a part of the content) described in another embodiment.

[0071] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0072] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0073] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0074] In addition, in the drawings of this specification, plan views may be used to explain the configuration of each embodiment. A plan view, for example, is a diagram showing the appearance of a surface (cut surface) obtained by cutting a configuration horizontally. Furthermore, hidden lines (e.g., dashed lines) may be included in the plan view to show the positional relationship of multiple elements included in the configuration or the overlapping relationship of the multiple elements. Note that, in this specification, the term "plan view" may be replaced with the terms "projection view," "top view," or "bottom view." Depending on the situation, a plan view may refer to a surface (cut surface) obtained by cutting a configuration in a direction other than the horizontal direction, rather than a surface (cut surface) obtained by cutting the configuration horizontally.

[0075] In addition, in the drawings of this specification, cross-sectional views may be used to explain the configuration of each embodiment. A cross-sectional view is, for example, a view showing a surface (cut surface) of a configuration cut in a vertical direction. In this specification, the term "cross-sectional view" may be replaced with the terms "front view" or "side view." Depending on the situation, a cross-sectional view may refer to a surface (cut surface) of a configuration cut in a direction other than the vertical direction, rather than a surface (cut surface) cut in a vertical direction.

[0076] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0077] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0078] Embodiment 1 In this embodiment, a display device according to one embodiment of the present invention will be described.

[0079] 1 shows a display device according to one embodiment of the present invention. The display device DSP0 includes, for example, a pixel array ALP, a row driver circuit RWD, and a column driver circuit CLM.

[0080] As an example, the pixel array ALP has m×n pixels PX (m is an integer equal to or greater than 1, and n is an integer equal to or greater than 1). In particular, the pixels PX are arranged in a matrix of m rows and n columns within the pixel array ALP. Note that FIG. 1 excerpts the multiple pixels PX, including pixel PX[1,1], pixel PX[m,1], pixel PX[1,n], pixel PX[m,n], and pixel PX[i,j] (i is an integer equal to or greater than 1 and m, and j is an integer equal to or greater than 1 and n).

[0081] The pixel PX functions as a display pixel. As an example, the display pixel may be a pixel to which one or both of a liquid crystal display device and a light-emitting device are applied. Examples of the light-emitting device include a light-emitting device including an organic EL element (OLED (Organic Light Emitting Diode)), an inorganic EL element, an LED (including a micro LED), a QLED (Quantum-dot Light Emitting Diode), and a semiconductor laser. In this embodiment, a light-emitting device including an organic EL material is applied to the pixel PX. The brightness of light emitted from a light-emitting device capable of emitting light with particularly high brightness is, for example, 500 cd / m ２ or more, preferably 1000 cd / m ２ More than 10000cd / m ２ More preferably, 2000 cd / m or less ２ More than 5000cd / m ２ It can be as follows:

[0082] In addition, in the pixel array ALP, for example, wirings GL[1] to GL[m] are provided extending in the row direction, and in the pixel array ALP, for example, wirings SL[1] to SL[n] are provided extending in the column direction.

[0083] For example, the pixel PX[i,j] is electrically connected to a wiring GL[i] and a wiring SL[j].

[0084] For example, the line SL[j] functions as a line that transmits an image data signal to the pixel PX[i,j].

[0085] 1 illustrates one line SL extending per column in the pixel array, the number of lines SL extending per column is not limited to 1. In other words, the number of lines SL extending per column of the pixel array ALP may be two or more.

[0086] For example, the wiring GL[i] functions as a wiring for transmitting a selection signal for selecting the pixel PX[i,j] to which the image data signal is to be supplied. Furthermore, for example, the wiring GL[i] may also function as a wiring for transmitting a selection signal for selecting the pixel PX[i,j] in order to correct the threshold voltage of the drive transistor included in the pixel PX[i,j]. Furthermore, the wiring GL[i] may also function as a wiring for transmitting a control signal (digital potential) for switching the switch included in the pixel PX[i,j] between the on state and the off state.

[0087] 1 illustrates one wiring GL extending per row in the pixel array, but the number of wirings GL extending per row is not limited to one. That is, the number of wirings GL extending per row in the pixel array ALP may be two or more. For example, the number of wirings GL extending per row can be determined according to the circuit configuration of the pixel PX, and depending on the circuit configuration of the pixel PX, the number of wirings GL may be two or more.

[0088] The row driver circuit RWD includes, for example, a driver circuit GD.

[0089] For example, the driver circuit GD is electrically connected to each of the wirings GL[1] to GL[m].

[0090] For example, the driver circuit GD has a function of selecting one or more pixels PX selected from the first to mth rows of the pixel array ALP to which the image data signal is to be supplied and transmitting a selection signal to the plurality of pixels PX arranged in the selected row. For this purpose, the driver circuit GD may be equipped with a demultiplexer. The selection signal may be, for example, an analog potential, a digital potential (high-level potential or low-level potential), or a pulse potential. Furthermore, the driver circuit GD may have a function of not only selecting the pixel PX to which the image data signal is to be supplied, but also selecting the pixel PX for the purpose of correcting the threshold voltage of the transistor included in the pixel PX. In other words, the driver circuit GD may have a function of transmitting a selection signal for correcting the threshold voltage of the transistor included in the pixel PX.

[0091] The column driver circuit CLM includes, for example, a driver circuit SD and circuits CD[1] to CD[n].

[0092] Each of the circuits CD[1] to CD[j] ​​is electrically connected to the driver circuit SD. The circuit CD[j] ​​is electrically connected to a wiring SL[j], for example.

[0093] For example, the drive circuit SD has a function of transmitting image data signals to the pixels PX included in the pixel array ALP. Depending on the method of transmitting the image data signals, the drive circuit SD may also be provided with a demultiplexer. The image data signals may be, for example, analog potentials, digital potentials (high-level potentials or low-level potentials), or pulse potentials.

[0094] For example, the circuit CD[j] ​​has a function of level-shifting an image data signal input from the driver circuit SD and transmitting the level-shifted image data signal to the wiring SL[j].

[0095] Next, an example of the configuration of the pixel PX and the circuit CD will be described. The display device DSP1A shown in Fig. 2 is an example of the display device DSP0 in Fig. 1, and Fig. 2 shows an excerpt of one of the multiple pixels PX included in the pixel array ALP, the drive circuit GD of the row driver circuit RWD, and the circuit CD and drive circuit SD of the column driver circuit CLM, which are electrically connected to the pixel PX.

[0096] 2, pixel PX includes, for example, transistor M2, switches SW1, SW3, SW5, SW6, a capacitor C1, and a light-emitting device LD. Circuit CD includes switches SW11, SW12, and a capacitor C2. In particular, transistor M2 functions as a drive transistor for pixel PX.

[0097] For example, an OS transistor is preferably used as the transistor M2. Examples of metal oxides included in the channel formation region of an OS transistor include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes one or more elements selected from the group consisting of indium, the element M, and zinc. The element M is preferably one or more elements selected from the group consisting of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. The element M is preferably one or more elements selected from the group consisting of aluminum, gallium, yttrium, and tin.

[0098] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) is preferably used. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) is preferably used. Note that an OS transistor will be described in detail in Embodiment 5.

[0099] The transistor M2 may be a transistor other than an OS transistor. For example, a transistor having silicon in a channel formation region (hereinafter referred to as a Si transistor) may be used as the transistor M2. As the silicon, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon (including low-temperature polycrystalline silicon) may be used.

[0100] In addition to OS transistors and Si transistors, the transistor M2 can be, for example, a transistor including germanium or the like in a channel formation region, a transistor including a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor including a carbon nanotube in a channel formation region, or a transistor including an organic semiconductor in a channel formation region.

[0101] Note that while the transistor M2 shown in FIG. 2 is an n-channel transistor, it may be a p-channel transistor depending on the situation or circumstances. Furthermore, if an n-channel transistor is replaced with a p-channel transistor, the potential input to the pixel PX must be appropriately changed so that the pixel PX operates normally. This also applies to transistors described elsewhere in the specification or shown in other drawings, not just FIG. 2. In this embodiment, the configuration and operation of the pixel PX will be described assuming that the transistor M2 is an n-channel transistor.

[0102] Furthermore, it is preferable that the transistor M2 operates to pass a current between the source and drain according to the gate-source voltage, not the source-drain voltage. That is, it is preferable that the transistor M2 operates in the saturation region when in the on state. By operating the transistor M2 in the saturation region, the amount of current flowing through the transistor M2 can be determined by the gate-source voltage. Furthermore, by operating the transistor M2 in the saturation region, the drain current does not change significantly even when the source-drain voltage of the transistor M2 changes. That is, by determining the amount of current flowing through the transistor M2 according to the gate-source voltage, the transistor M2 can pass a stable current between the anode and cathode of the light-emitting device LD. Furthermore, depending on the situation, the transistor M2 may operate in the linear region when in the on state. Alternatively, the transistor M2 may operate in the subthreshold region.

[0103] The above description of the transistors is applicable not only to the transistor M2 but also to other transistors described in the specification and in the drawings.

[0104] For example, electrical switches such as analog switches and transistors can be used for each of the switches SW1, SW3, SW5, SW6, SW11, and SW12. In particular, the above-described transistors are preferably used as the electrical switches for the switches SW1, SW3, SW5, SW6, SW11, and SW12, and OS transistors are more preferably used. Note that when electrical switches are used for the switches SW1, SW3, SW5, SW6, SW11, and SW12, transistors applicable to the transistor M2, other than OS transistors, can be used for the electrical switches. Specifically, Si transistors can be used as the electrical switches. Furthermore, for example, mechanical switches may be applied to the switches SW1, SW3, SW5, SW6, SW11, and SW12.

[0105] In this specification, each of the switches SW1, SW3, SW5, SW6, SW11, and SW12 shown in FIG. 2 is assumed to be in an on state when a high-level potential is applied to its control terminal, and to be in an off state when a low-level potential is applied to its control terminal.

[0106] 2, the light emitting device LD is, for example, a self-luminous light emitting device having an organic EL element (OLED). The configuration of the light emitting device LD applicable to the pixel PX will be described in detail in the fourth embodiment.

[0107] In pixel PX, a first terminal of switch SW1 is electrically connected to the gate of transistor M2, a first terminal of switch SW3, and a first terminal of capacitor C1; a second terminal of switch SW1 is electrically connected to wiring SL; and a control terminal of switch SW1 is electrically connected to wiring GL1. A first terminal of transistor M2 is electrically connected to the second terminal of capacitor C1, a first terminal of switch SW6, and an anode of light-emitting device LD; a second terminal of transistor M2 is electrically connected to the second terminal of switch SW3 and a first terminal of switch SW5. A control terminal of switch SW3 is electrically connected to wiring GL3. A second terminal of switch SW5 is electrically connected to wiring VE2, and a control terminal of switch SW5 is electrically connected to wiring GL5. A second terminal of switch SW6 is electrically connected to wiring VE1, and a control terminal of switch SW6 is electrically connected to wiring GL6. The cathode of the light emitting device LD is electrically connected to the wiring VE0.

[0108] In this embodiment, the electrical connection point between the first terminal of the switch SW1, the first terminal of the switch SW3, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as node N1, and the electrical connection point between the first terminal of the transistor M2, the second terminal of the capacitor C1, the first terminal of the switch SW6, and the anode of the light-emitting device LD is referred to as node N2.

[0109] In the circuit CD, a first terminal of the capacitor C2 is electrically connected to the line SL, and a second terminal of the capacitor C2 is electrically connected to a first terminal of the switch SW11 and a first terminal of the switch SW12. The second terminal of the switch SW11 is electrically connected to the line VE3, and a control terminal of the switch SW11 is electrically connected to the line SWL11. The second terminal of the switch SW12 is electrically connected to the drive circuit SD, and a control terminal of the switch SW12 is electrically connected to the line SWL12.

[0110] In this embodiment, the electrical connection point between the first terminal of the switch SW11, the first terminal of the switch SW12, and the second terminal of the capacitor C2 is called a node N3.

[0111] For example, each of the wirings VE0 to VE3 functions as a wiring that applies a constant potential. The constant potentials applied by the wirings VE0 to VE3 may be equal to each other or different from each other. Alternatively, some of the potentials applied by the wirings VE0 to VE3 may be equal to each other, and the remaining potentials may be different from each other. Furthermore, one or more selected from the wirings VE0 to VE3 may function as a wiring that applies a pulse potential instead of a constant potential.

[0112] 2, the wiring VE0 preferably functions as a wiring that applies a potential to the cathode of the light-emitting device LD, and the wiring VE2 preferably functions as a wiring that applies a potential to the anode of the light-emitting device LD.

[0113] 2, the cathode of the light-emitting device LD is electrically connected to the wiring VE0, and the anode of the light-emitting device LD is electrically connected to the wiring VE2 via the transistor M2 and the switch SW5. However, the anode of the light-emitting device LD may be electrically connected to the wiring VE0, and the cathode of the light-emitting device LD may be electrically connected to the wiring VE2. That is, when the former light-emitting device LD is configured in a forward stacking configuration, the light-emitting device of the pixel according to the display device of one embodiment of the present invention may be configured in a reverse stacking configuration. In this case, the wiring VE0 functions as a wiring that applies a potential to the anode of the light-emitting device LD, and the wiring VE2 functions as a wiring that applies a potential to the cathode of the light-emitting device LD.

[0114] The wirings GL1, GL3, GL5, and GL6 correspond to one of the wirings GL[1] to GL[m] in Fig. 1. That is, in the circuit configuration of the pixel PX shown in Fig. 2, the number of wirings GL extending in one row of the pixel array ALP is four.

[0115] The wiring SWL11 functions as a wiring for transmitting a control signal (digital potential) for switching the switch SW11 between an on state and an off state. Similarly, the wiring SWL12 functions as a wiring for transmitting a control signal (digital potential) for switching the switch SW12 between an on state and an off state.

[0116] <<Example 1 of Operation Method of Display Device>> Next, an example of an operation method of the display device DSP1A of FIG. 2 will be described.

[0117] 3A and 3B are timing charts illustrating an example of an operation method of the display device DSP1A. Specifically, the timing chart in FIG. 3A shows changes in the potentials of the wirings GL1, GL3, GL5, GL6, SWL11, SWL12, and node N3 during each of the periods T11 to T17. FIG. 3B also shows changes in the potentials of the nodes N1 and N2 during each of the periods T11 to T17. In FIG. 3B, the potential change of the node N1 is indicated by a solid line, and the potential change of the node N2 is indicated by a dashed-dotted line. The timing chart in FIG. 3B illustrates a case where the threshold voltage of the transistor M2 is higher than 0 V.

[0118] In FIG. 3A, "High" indicates a high level potential, and "Low" indicates a low level potential.

[0119] The wiring VE1 is connected to a constant potential V Ｎ Furthermore, a constant potential V is applied to the wiring VE3. ｒｅｆ It is assumed that V is given. Ｎ and V ｒｅｆ and may be at the same potential.

[0120] Furthermore, the wiring VE2 is connected to a constant potential V ＡＮ In addition, a constant potential V ＣＴ is given. Also, V ＡＮ is V ＣＴ The potential is set to be higher than

[0121] In addition, V ＡＮ is VＮ The potential is set to be higher than V Ｎ -V ＣＴ The voltage V is a voltage at which the light emitting device LD does not emit light (no current flows between the anode and cathode of the light emitting device LD). Ｎ is V ＣＴ or V ＣＴ It is preferable that the potential is lower than

[0122] Furthermore, the threshold voltage of the transistor M2 is V ｔｈ In addition, V ｔｈ is V ＡＮ -V Ｎ The voltage shall be lower than

[0123] Before the period T11, a low-level potential is applied to the wirings GL1, GL3, GL5, GL6, SWL11, and SWL12. As a result, a low-level potential is applied to the control terminals of the switches SW1, SW3, SW5, SW6, SW11, and SW12, and the switches are turned off.

[0124] Before the period T11, the potentials of the nodes N1 and N2 are not particularly limited. For example, in FIG. 3B , the potential of the node N1 is increased during a period T11 (to be described later), but the potential of the node N1 before the period T11 may be decreased during the period T11. For example, in FIG. 3B , the potential of the node N2 is decreased during a period T11 (to be described later), but the potential of the node N2 before the period T11 may be increased during the period T11.

[0125] The potential of the node N3 is undefined before the period T11, and therefore the potential of the node N3 before the period T11 in the timing chart of FIG.

[0126] [Period T11] In the period T11, a high-level potential is applied to the wirings GL1, GL3, GL5, GL6, and SWL11. As a result, a high-level potential is applied to the control terminals of the switches SW1, SW3, SW5, SW6, and SW11, and these switches are turned on.

[0127] Since the switches SW1, SW3, and SW5 are turned on, the gate of the transistor M2, the first terminal of the capacitor C1, and the first terminal of the capacitor C2 are electrically connected to the wiring VE2. Therefore, the potential V ＡＮ is given (see FIG. 3B).

[0128] Furthermore, since the switch SW6 is in an on state, the first terminal of the transistor M2, the second terminal of the capacitor C1, and the anode of the light-emitting device LD are electrically connected to the wiring VE1, and therefore the first terminal of the transistor M2, the second terminal of the capacitor C1, and the anode (node ​​N2) of the light-emitting device LD are electrically connected to the wiring VE1. Ｎ is given (see FIG. 3B).

[0129] At this time, the voltage between the anode and cathode of the light emitting device LD is V Ｎ -V ＣＴ As described above, when the voltage between the anode and cathode of the light-emitting device LD is V Ｎ -V ＣＴ When the voltage Vcc is 0, the light emitting device LD does not emit light (no current flows between the anode and cathode of the light emitting device LD).

[0130] The potential of the gate and second terminal of the transistor M2 is V ＡＮ The potential of the first terminal of the transistor M2 is V Ｎ Therefore, the gate-source voltage of the transistor M2 is V ＡＮ -V Ｎ The gate-source voltage V ＡＮ -V Ｎ is Vｔｈ Since the voltage at the line VE1 is higher than the voltage at the line VE2, the transistor M2 is turned on. If no current flows between the anode and cathode of the light-emitting device LD, a current flows between the line VE1 and the line VE2 via the switch SW5, the transistor M2, and the switch SW6.

[0131] Furthermore, since the switch SW11 is in an on state, the second terminal of the capacitor C2 and the first terminal of the switch SW12 are electrically connected to the wiring VE3, and therefore the second terminal of the capacitor C2 and the first terminal of the switch SW12 (node ​​N3) are electrically connected to the wiring VE3. ｒｅｆ is given (see FIG. 3A).

[0132] In the period T11 of the timing chart in FIG. 3A, a high-level potential is input to each of the wirings GL1, GL3, GL5, GL6, and SWL11 at the same timing. However, within the period T11, the timing at which a high-level potential is input to each of the wirings GL1, GL3, GL5, GL6, and SWL11 may be different from each other.

[0133] [Period T12] During the period T12, a low-level potential is applied to the wiring GL5. As a result, a low-level potential is applied to the control terminal of the switch SW5, turning the switch SW5 off. As a result, electrical continuity is broken between the second terminal of the transistor M2 and the wiring VE2.

[0134] Immediately before the switch SW5 is turned off, the gate-source voltage V ＡＮ -V Ｎ is the threshold voltage V of the transistor M2 ｔｈ When the switch SW5 is turned off, the potential V ＡＮ Since the application of the voltage Vcc is stopped, the positive charge supplied to the node N1 is discharged to the wiring VE1 through the first terminal and the second terminal of the transistor M2 and the switch SW6. As a result, the potential of the node N1 drops.

[0135] As the potential of the node N1 decreases, the gate-source voltage of the transistor M2 also decreases. ｔｈ When the potential of the node N1 drops to V, the transistor M2 is turned off, and the discharge of the positive charge from the node N1 stops. ＡＮ From V Ｎ +V ｔｈ When the potential of the node N1 reaches V, the transistor M2 is turned off. Since the transistor M2 is turned off, the potential of the node N1 is V Ｎ +V ｔｈ (See FIG. 3B.) When the transistor M2 is turned off, the node N1 and the wiring SL are brought into a floating state.

[0136] [Period T13] In the period T13, a low-level potential is applied to the wiring GL3 and the wiring SWL11. As a result, a low-level potential is applied to the control terminals of the switches SW3 and SW11, and the switches SW3 and SW11 are turned off.

[0137] Since the switch SW3 is in the off state, there is no conduction between the first terminal of the capacitor C2, the gate of the transistor M2, the first terminal of the capacitor C1 and the second terminal of the transistor M2.

[0138] Furthermore, since the switch SW11 is in the off state, there is no conduction between the second terminal of the capacitor C2 and the first terminal of the switch SW12 and the line VE3, and the node N3 is in a floating state.

[0139] [Period T14] In the period T14, a high-level potential is applied to the wiring SWL12, so that a high-level potential is applied to the control terminal of the switch SW12, turning the switch SW12 on.

[0140] In particular, when the switch SW12 is turned on, the drive circuit SD transmits an image data signal corresponding to the image to be displayed on the pixel PX to the second terminal (node ​​N3) of the capacitor C2 via the switch SW12. ｄａｔａ Let's say.

[0141] Therefore, the potential of the node N3 is V ｒｅｆ From V ｄａｔａ The potentials of the wiring SL and the node N1 change due to the capacitance coupling of the capacitor C2, as the potential of the node N3 changes. The amount of change in the potential of the wiring SL and the node N1 is determined by, for example, the capacitance of the capacitor C1, the capacitance of the capacitor C2, the gate capacitance of the transistor M2, the parasitic capacitance of the switch SW1, the parasitic capacitance of the switch SW3, and the parasitic capacitance of the wiring SL. In this operation example, for the sake of simplicity, the amount of change in the potential of the wiring SL and the node N1 is described as being determined by the capacitance of the capacitor C1 and the capacitance of the capacitor C2.

[0142] The capacitance of the capacitor C1 is C １ , the capacitance of the capacitor C2 is C ２ As a result, the potential of the node N3 becomes V ｒｅｆ From V ｄａｔａ , the potentials of the wiring SL and the node N1 change by an amount of ΔV ｄａｔａ = (V ｄａｔａ -V ｒｅｆ ) × C ２ / (C １ +C ２ ) is given. Therefore, the potentials of the wiring SL and the node N1 are V Ｎ +V ｔｈ +ΔV ｄａｔａ (See FIG. 3B).

[0143] On the other hand, the second terminal (node ​​N2) of the capacitor C1 has been supplied with the potential V Ｎ is given, the potential of the node N3 is V ｒｅｆ From V ｄａｔａ Even during the period when the potential of the second terminal (node ​​N2) of the capacitor C1 changes to V ＮIt remains unchanged.

[0144] From the above, the gate-source voltage of the transistor M2 during the period T14 is V ｄｒｖ Then, V ｄｒｖ = (potential of node N1) - (potential of node N2) = V ｔｈ +ΔV ｄａｔａ That is, during the period T14, the voltage V held between the first terminal and the second terminal of the capacitor C1 is ｄｒｖ is a potential ΔV corresponding to the image displayed on the pixel PX. ｄａｔａ and the threshold voltage V of the transistor M2. ｔｈ It is set to the sum of

[0145] Also, the gate-source voltage V of the transistor M2 ｄｒｖ is the threshold voltage V of the transistor M2 ｔｈ , the transistor M2 is turned on. However, because the switches SW3 and SW5 are both off, there is no conduction between the second terminal of the transistor M2 and the node N1, and between the second terminal of the transistor M2 and the wiring VE2. Therefore, no current flows between the first terminal and the second terminal of the transistor M2.

[0146] [Period T15] In the period T15, a low-level potential is applied to the wiring GL1, so that the control terminal of the switch SW1 is supplied with a low-level potential, turning the switch SW1 off.

[0147] When the switch SW1 is turned off, there is no conduction between the gate of the transistor M2, the first terminal of the capacitor C1, and the wiring SL. In addition, since the switch SW3 has been turned off since the period T13, the first terminal of the capacitor C1 (node ​​N1) is supplied with the potential V Ｎ +V ｔｈ +ΔV ｄａｔａ is maintained.

[0148] [Period T16] During the period T16, a high-level potential is applied to the wiring GL5, and a low-level potential is applied to the wiring GL6. As a result, a high-level potential is applied to the control terminal of the switch SW5, turning the switch SW5 on. Also, a low-level potential is applied to the control terminal of the switch SW6, turning the switch SW6 off.

[0149] Because the switch SW5 is in the on state, conduction is established between the second terminal of the transistor M2 and the wiring VE2. Moreover, because the switch SW6 is in the off state, conduction is established between the first terminal of the transistor M2 and the second terminal of the capacitor C1 and the wiring VE1. Moreover, because the switch SW3 has been in the off state since period T13, conduction is established between the second terminal of the transistor M2 and the gate (node ​​N1) of the transistor M2.

[0150] The gate-source voltage of the transistor M2 is V ｄｒｖ =V ｔｈ +ΔV ｄａｔａ and the threshold voltage V of the transistor M2 ｔｈ Since the voltage Vcc is greater than 1 V, the transistor M2 is in an on state.

[0151] Therefore, a current flows between the wiring VE0 and the wiring VE2 via the switch SW5, the transistor M2, and the light-emitting device LD.

[0152] At this time, the voltage V between the wiring VE0 and the wiring VE2 ＡＮ -V ＣＴ is divided by the transistor M2, the light emitting device LD, and the switch SW5. In this operation example, the potential of the first terminal of the transistor M2 (the second terminal of the capacitor C1 and the node N2) is V Ｎ From V Ｓ (See FIG. 3B).

[0153] Furthermore, the potential of the first terminal of the transistor M2 (the second terminal of the capacitor C1 and the node N2) is V Ｎ From V Ｓ, the potential of the gate of the transistor M2 (the first terminal of the capacitor C1 and the node N1) also changes due to the capacitive coupling of the capacitor C1. In this operation example, the operation in the period T16 causes the potential of the gate of the transistor M2 (the first terminal of the capacitor C1 and the node N1) to change to V Ｎ +V ｔｈ +ΔV ｄａｔａ From V Ｇ (See FIG. 3B).

[0154] The amount of change in the potential of the node N1 due to the capacitive coupling of the capacitor C1 described above is determined by the capacitance of the capacitor C1, the gate capacitance of the transistor M2, the parasitic capacitance of the switch SW1, and the parasitic capacitance of the switch SW3. In this operation example, for the sake of simplicity, the amount of change in the potential of the node N1 is assumed to be equal to the amount of change in the potential of the node N2. In other words, the amount of change in the potential of the node N2 is assumed to be ΔV Ｃ (=V Ｓ -V Ｎ ), the change in the potential of the node N1 is also ΔV Ｃ This corresponds to the case where the capacitive coupling coefficient in the vicinity of the node N1 is 1.

[0155] Also, at node N1, ΔV Ｃ =V Ｇ −(V Ｎ +V ｔｈ +ΔV ｄａｔａ ) and therefore the change in the potential of the node N2, ΔV Ｃ =V Ｓ -V Ｎ Substituting V Ｇ -V Ｓ =V ｔｈ +ΔV ｄａｔａ =V ｄｒｖ That is, the gate-source voltage of the transistor M2 during the period T16 has not changed since the image data signal was input to the circuit CD during the period T14.

[0156] Now, consider the case where the transistor M2 operates in the saturation region. The amount of current flowing between the first terminal and the second terminal of the transistor M2 is determined by the gate-source voltage V ｄｒｖSpecifically, the amount of current I flowing between the source and drain of a transistor operating in the saturation region is determined by the gate-source voltage V of the transistor. ＧＳ and the threshold voltage V of the transistor ｔｈ Since it is proportional to the square of the difference between ＧＳ -V ｔｈ ) ２ where k is a proportionality constant that depends on the structure of the transistor. ＧＳ , the gate-source voltage V of the transistor M2 ｄｒｖ By substituting I = k (ΔV ｄａｔａ ) ２ The amount of current I flowing through the transistor M2 is determined by the threshold voltage V ｔｈ does not depend on ΔV ｄａｔａ It is determined by:

[0157] As described above, by performing the operations from the period T11 to the period T16, the threshold voltage V ｔｈ It is possible to generate a current that is independent of

[0158] In addition, the potential of the anode of the light-emitting device LD is V Ｓ Therefore, the potential between the anode and cathode of the light emitting device LD is V Ｓ -V ＣＴ In addition, a current (I=k(ΔV ｄａｔａ ) ２ ) flows through the light emitting device LD, causing the light emitting device LD to emit light. When the light emitting device LD is an organic EL element, the light emitting luminance of the light emitting device LD is determined by the amount of current flowing between the anode and cathode of the light emitting device LD. In other words, the light emitting luminance of the light emitting device LD is determined by the amount of current flowing between the anode and cathode of the light emitting device LD. ｄａｔａ It is determined by:

[0159] By the way, the image data signal V output from the drive circuit SD ｄａｔａ is connected to the circuit CD. ＡＮ + K × (V ｄａｔａ -V ｒｅｆ ) changes to VＡＮ + K × (V ｄａｔａ -V ｒｅｆ ) is input to pixel PX. Note that K=C ２ / (C １ +C ２ ) where the minimum value of the pixel gradation level is V ｄａｔａ＿ｍｉｎ The maximum value of the pixel gradation level is V ｄａｔａ＿ｍａｘ , the image data signal V ｄａｔａ V ｄａｔａ＿ｍｉｎ ~V ｄａｔａ＿ｍａｘ Consider the case where one of the multiple potentials is taken. ｄａｔａ＿ｍｉｎ ~V ｄａｔａ＿ｍａｘ Each of the potentials V ＡＮ + K × (V ｄａｔａ＿ｍｉｎ -V ｒｅｆ ) to V ＡＮ + K × (V ｄａｔａ＿ｍａｘ -V ｒｅｆ ) changes to

[0160] V ｒｅｆ V ＡＮ If the image data signal V ｄａｔａ＿ｍｉｎ ~V ｄａｔａ＿ｍａｘ and V input to the pixel PX via the circuit CD. ＡＮ + K × (V ｄａｔａ＿ｍｉｎ -V ｒｅｆ ) to V ＡＮ + K × (V ｄａｔａ＿ｍａｘ -V ｒｅｆ ) is as shown in Figure 4A. In other words, when the image data signal output from the drive circuit SD is input to the pixel PX via the circuit CD, the potential range of the image data signal becomes narrower and the potential increment of the image data signal becomes smaller. This allows the potential of the image data signal input to the pixel PX to be changed more finely, and therefore the amount of current flowing between the source and drain of the transistor M2 to be changed more finely.

[0161] Also, V ｒｅｆ V ＡＮ When the image data signal V ｄａｔａ＿ｍｉｎ ~V ｄａｔａ＿ｍａｘ and V input to the pixel PX via the circuit CD.ＡＮ + K × (V ｄａｔａ＿ｍｉｎ -V ｒｅｆ ) to V ＡＮ + K × (V ｄａｔａ＿ｍａｘ -V ｒｅｆ 4B. As in FIG. 4A, the amount of current flowing between the source and drain of the transistor M2 can be finely changed by reducing the potential increment of the image data signal.

[0162] Also, V ｒｅｆ and V ＡＮ When these are equal to each other, the image data signal V output from the drive circuit SD ｄａｔａ＿ｍｉｎ ~V ｄａｔａ＿ｍａｘ and V input to the pixel PX via the circuit CD. ＡＮ + K × (V ｄａｔａ＿ｍｉｎ -V ｒｅｆ ) to V ＡＮ + K × (V ｄａｔａ＿ｍａｘ -V ｒｅｆ 4C. Similarly to FIGS. 4A and 4B, the amount of current flowing between the source and drain of the transistor M2 can be finely changed by reducing the potential step size of the image data signal.

[0163] In the period T16 in the timing chart of FIG. 3A, a high-level potential is input to the wiring GL5 and a low-level potential is input to the wiring GL6 at the same timing. However, within the period T16, the timing at which the potentials are input to the wiring GL5 and the wiring GL6 may be different from each other.

[0164] [Period T17] During the period T17, a low-level potential is applied to the wiring GL5 and the wiring SWL12, and a high-level potential is applied to the wiring GL6. Therefore, a low-level potential is applied to the control terminals of the switches SW5 and SW12, so that the switches SW5 and SW12 are turned off. Furthermore, a high-level potential is applied to the control terminal of the switch SW6, so that the switch SW6 is turned on.

[0165] Since the switch SW5 is in the OFF state, there is no conduction between the second terminal of the transistor M2 and the wiring VE2. Also, since the switch SW6 is in the ON state, there is conduction between the first terminal of the transistor M2, the second terminal of the capacitor C1, and the anode of the light-emitting device LD and the wiring VE1. Therefore, the first terminal of the transistor M2, the second terminal of the capacitor C1, and the anode (node ​​N2) of the light-emitting device LD receive the potential V Ｎ is given (see FIG. 3B).

[0166] At this time, the voltage between the anode and cathode of the light emitting device LD is V Ｎ -V ＣＴ As described above, when the voltage between the anode and cathode of the light-emitting device LD is V Ｎ -V ＣＴ When the voltage Vcc is 0, the light emitting device LD does not emit light (no current flows between the anode and cathode of the light emitting device LD).

[0167] That is, by performing the operation in the period T17, it is possible to stop the light emission of the light emitting device LD.

[0168] By performing the above-described operations in the periods T11 to T17, the transistor M2 of the pixel PX is turned on at the threshold voltage V ｔｈ A current independent of the voltage Vcc can be generated and supplied to the light emitting device LD.

[0169] The threshold voltages of the driving transistors of the pixels included in the pixel array of a display device may vary depending on the manufacturing process and manufacturing environment of the display device. In other words, even if the same image data signal is supplied to different pixels, if the threshold voltages of the transistors of each pixel are different, the amount of current flowing through each transistor may also be different, and the light-emitting device of each pixel may emit light with different brightness. As a result, unevenness occurs in the light-emitting device's emission brightness, which reduces the display quality of the image on the display device.

[0170] On the other hand, by using the display device DSP1A according to one embodiment of the present invention, the transistor M2 of the pixel PX can be prevented from being turned off by a threshold voltage V ｔｈ Since it is possible to generate a current that is independent of the pixel PX of the pixel array ALP, it is possible to prevent unevenness in the light emission luminance of the light emitting devices included in each pixel PX of the pixel array ALP. Therefore, by using the display device DSP1A, it is possible to improve the display quality of the display device DSP1A.

[0171] Furthermore, by performing the operations in the periods T11 to T17 described above, the amount of current flowing through the light emitting device LD of the pixel PX of the display device DSP1A can be controlled more precisely.

[0172] As the resolution of a display device increases, the area (light-emitting surface) where the light-emitting devices of multiple pixels included in a pixel array are formed decreases. When the area (light-emitting surface) of the light-emitting device decreases, the amount of current required for the light-emitting device to emit light decreases, but the amount of allowable current also decreases. Therefore, in order to accurately adjust the brightness of the light-emitting device, it is necessary to control the current very precisely.

[0173] In one embodiment of the present invention, the use of the display device DSP1A allows for precise control of the amount of current flowing through the light-emitting device LD, thereby enabling precise adjustment of the luminance of light emitted from the light-emitting device LD of the pixel PX. Therefore, the use of the display device DSP1A allows for precise setting of the gradation of an image, thereby improving the display quality of the display device DSP1A. Furthermore, the use of the display device DSP1A allows for a reduction in the amount of current flowing through the light-emitting device LD, thereby preventing the light-emitting device LD from being damaged by an overcurrent.

[0174] 3A and 3B, the operation of one pixel PX included in the pixel array ALP of the display device DSP1A has been described. Here, the operation of the entire pixel array ALP in the display device DSP0 to which the display device DSP1A is applied will be described.

[0175] Note that, since the display device DSP1A is applied to the display device DSP0, the circuit CD in Fig. 2 is applied to the circuits CD[1] to CD[n] of the display device DSP0. Also, the pixel PX in Fig. 2 is applied to each of the pixels PX[1,1] to PX[m,n].

[0176] FIG. 5 is a timing chart showing an example of a method for writing image data to a plurality of pixels PX included in the pixel array ALP of the display device DSP0.

[0177] The timing chart in Figure 5 shows changes in the potentials of node N3[1], node N3[2], node N3[n], wiring GL1[1], wiring GL6[1], wiring GL1[2], wiring GL6[2], wiring GL1[m], and wiring GL6[m], and changes in image data held between the first terminal and the second terminal of each of capacitance C1[1,1], capacitance C1[1,2], capacitance C1[1,n], capacitance C1[2,1], capacitance C1[2,2], capacitance C1[2,n], capacitance C1[m,1], capacitance C1[m,2], and capacitance C1[m,n], during and around the periods U1 to U7.

[0178] Note that the node N3[1] corresponds to the node N3 included in the circuit CD[1] in the display device DSP0. Similarly, the node N3[2] corresponds to the node N3 included in the circuit CD[2] (not shown in FIG. 1) in the display device DSP0, and the node N3[n] corresponds to the node N3 included in the circuit CD[n] in the display device DSP0.

[0179] 2 that is extended to the first row in the pixel array ALP of the display device DSP0. Similarly, the wiring GL1[2] corresponds to the wiring GL1 in FIG. 2 that is extended to the second row in the pixel array ALP of the display device DSP0, and the wiring GL1[m] corresponds to the wiring GL1 in FIG. 2 that is extended to the mth row in the pixel array ALP of the display device DSP0.

[0180] 2 that is possessed by pixel PX[1,1] included in the pixel array ALP of the display device DSP0. Similarly, capacitance C1[1,2] corresponds to capacitance C1 in FIG. 2 that is possessed by pixel PX[1,2] (not shown in FIG. 1) included in the pixel array ALP of the display device DSP0, and capacitance C1[1,n] corresponds to capacitance C1 in FIG. 2 that is possessed by pixel PX[1,n] included in the pixel array ALP of the display device DSP0. Hereinafter, the notation capacitance C1[i,j] will be treated as equivalent to capacitance C1 in FIG. 2 that is possessed by pixel PX[i,j] included in the pixel array ALP of the display device DSP0.

[0181] In addition, during periods U1, U3, and U6 in the timing chart of Fig. 5, the operations of periods T11 to T13 in the timing chart of Fig. 3 are performed on a plurality of pixels PX located on a predetermined row. In addition, during periods U2, U4, and U7 in the timing chart of Fig. 5, the operations of periods T14 to T17 in the timing chart of Fig. 3A are performed on a plurality of pixels PX located on a predetermined row.

[0182] Before the period U1, the capacitance C1[1,1] is charged with a voltage V ｄｒｖ [1,1]_0 is held, and the voltage V ｄｒｖ [1, 2]_0 is held, and the voltage V ｄｒｖ [1, n]_0 is held, and the voltage V ｄｒｖ [2,1]_0 is held, and the voltage V ｄｒｖ [2, 2]_0 is held, and the capacitor C1[2, n] is charged with a voltage V ｄｒｖ [2, n]_0 is held, and the capacitor C1[m, 1] is charged with a voltage V ｄｒｖ [m, 1]_0 is held, and the voltage V ｄｒｖ [m, 2]_0 is held, and the capacitance C1[m, n] is charged with a voltage V ｄｒｖ [m, n]_0 is held. ｄｒｖ [i, j] is V in the timing chart of FIG. 3B at pixel PX[i, j] ｄｒｖ is equivalent to

[0183] Before the period U1, a low-level potential is input to each of the wirings GL1[1] to GL1[m]. As a result, a low-level potential is applied to each of the control terminals of the switches SW1 of all the pixels PX in the pixel array ALP, and the switches SW1 of all the pixels PX are turned off. This operation also causes current to flow between the anode and cathode of the light-emitting device LD of all the pixels PX in the pixel array ALP, causing the light-emitting device LD to emit light.

[0184] In the period U1, the pixels PX[1,1] to PX[1,n] located in the first row of the pixel array ALP perform the operations of the periods T11 to T13 in the timing chart of FIG. 3A. As a result, the potentials of the nodes N3[1] to N3[n] are V ｒｅｆ This becomes:

[0185] During the period U1, a high-level potential is input to the wiring GL1[1]. As a result, a high-level potential is applied to each of the control terminals of the switches SW1 of the pixels PX[1,1] to PX[1,n] arranged in the first row of the pixel array ALP, and the switches SW1 of the pixels PX[1,1] to PX[1,n] are turned on.

[0186] During period U1, a high-level potential is input to the wiring GL6[1]. As a result, a high-level potential is applied to each of the control terminals of the switches SW6 of the pixels PX[1,1] to PX[1,n] arranged in the first row of the pixel array ALP, and therefore the switches SW6 of the pixels PX[1,1] to PX[1,n] are turned on. This operation also prevents current from flowing between the anode and cathode of the light-emitting devices LD of the pixels PX[1,1] to PX[1,n], and therefore these light-emitting devices LD do not emit light.

[0187] Furthermore, due to the operations in the periods T11 to T13 in the timing chart of FIG. 3A, the voltages V held in the capacitors C1[1,1] to C1[1,n] included in the pixels PX[1,1] to PX[1,n], respectively, before the period U1 are ｄｒｖ[1,1]_0 to V ｄｒｖ [1,n]_0 is initialized, and a voltage for correcting the threshold voltage of the transistor M2 is written to each of the capacitors C1[1,1] to C1[1,n]. Note that no correction voltage is written to the capacitors C1[1,1], C1[1,2], and C1[1,n] during the period U1 in FIG.

[0188] In the period U2, the pixels PX[1,1] to PX[1,n] located in the first row of the pixel array ALP perform the operations of the periods T14 to T17 in the timing chart of FIG. 3A. At this time, as an example, the nodes N3[1] to N3[n] are supplied with a potential V ｄ [1,1]_1 to V ｄ [1, n]_1 is input. ｄ [1,1]_1 to V ｄ [1, n]_1 is V in the description of FIG. 3A and FIG. 3B. ｄａｔａ is equivalent to

[0189] Furthermore, due to the operation of the periods T14 to T17 in the timing chart of FIG. 3A, the first terminals of the capacitors C1[1,1] to C1[1,n] included in the pixels PX[1,1] to PX[1,n], respectively, are supplied with V ｄ [1,1]_1 to V ｄ As a result, the capacitors C1[1,1] to C1[1,n] are supplied with a potential V according to the image data. ｄｒｖ [1,1]_1 to V ｄｒｖ [1,n]_1 is retained.

[0190] After that, a low-level potential is input to the wiring GL1[1], which causes a low-level potential to be applied to each of the control terminals of the switches SW1 of the pixels PX[1,1] to PX[1,n] arranged in the first row of the pixel array ALP, turning off the switches SW1 of the pixels PX[1,1] to PX[1,n].

[0191] Furthermore, during period U2, after a low-level potential is applied to the wiring GL1[1], a low-level potential is input to the wiring GL6[1]. As a result, a low-level potential is applied to each of the control terminals of the switches SW6 of the pixels PX[1,1] to PX[1,n] arranged in the first row of the pixel array ALP, and therefore the switches SW6 of the pixels PX[1,1] to PX[1,n] are turned off. This operation also causes current to flow between the anode and cathode of the light-emitting device LD of each of the pixels PX[1,1] to PX[1,n], causing these light-emitting devices LD to emit light with a brightness corresponding to the amount of current. Note that the amount of current is determined by the gate-source voltage of the transistor M2, i.e., the voltage held in the capacitor C1, as described in FIGS. 3A and 3B . In other words, the light-emitting device LD of the pixel PX[1,1] is turned off when the voltage V ｄｒｖ The light emitting device LD of the pixel PX[1,2] emits light with a brightness corresponding to the voltage V ｄｒｖ The light emitting device LD of the pixel PX[1, n] emits light with a brightness corresponding to the voltage V ｄｒｖ [1, n]_1 emits light of a brightness according to the wavelength.

[0192] In the period U3, the operations of the periods T11 to T13 in the timing chart of FIG. 3A are performed in the pixels PX[2,1] to PX[2,n] (not shown in FIG. 1) located in the second row of the pixel array ALP. As a result, the potentials of the nodes N3[1] to N3[n] are V ｒｅｆ This becomes:

[0193] During the period U3, a high-level potential is input to the wiring GL1[2]. As a result, a high-level potential is applied to each of the control terminals of the switches SW1 of the pixels PX[2,1] to PX[2,n] arranged in the second row of the pixel array ALP, and the switches SW1 of the pixels PX[2,1] to PX[2,n] are turned on.

[0194] During period U3, a high-level potential is input to line GL6[2]. As a result, a high-level potential is applied to each of the control terminals of switches SW6 of pixels PX[2,1] to PX[2,n] arranged in the second row of pixel array ALP, and therefore, switches SW6 of pixels PX[2,1] to PX[2,n] are turned on. This operation also prevents current from flowing between the anode and cathode of each light-emitting device LD of pixels PX[2,1] to PX[2,n], and therefore these light-emitting devices LD do not emit light.

[0195] Furthermore, due to the operations in the periods T11 to T13 in the timing chart of FIG. 3A, the voltages V held in the capacitors C1[2,1] to C1[2,n] included in the pixels PX[2,1] to PX[2,n], respectively, before the period U3 are ｄｒｖ [2,1]_0 to V ｄｒｖ [2,n]_0 is initialized, and a voltage for correcting the threshold voltage of the transistor M2 is written to each of the capacitors C1[2,1] to C1[2,n]. Note that no correction voltage is written to the capacitors C1[2,1], C1[2,2], and C1[2,n] during the period U3 in FIG.

[0196] In the period U4, the pixels PX[2,1] to PX[2,n] located in the second row of the pixel array ALP perform the operations of the periods T14 to T17 in the timing chart of FIG. 3A. At this time, as an example, the nodes N3[1] to N3[n] are supplied with a potential V ｄ [2,1]_1 to V ｄ [2, n]_1 is input. ｄ [2,1]_1 to V ｄ [2, n]_1 is V in the description of FIG. 3A and FIG. 3B. ｄａｔａ is equivalent to

[0197] Furthermore, due to the operation of the periods T14 to T17 in the timing chart of FIG. 3A, the first terminals of the capacitors C1[2,1] to C1[2,n] included in the pixels PX[2,1] to PX[2,n], respectively, are supplied with V ｄ [2,1]_1 to V ｄ As a result, a potential V1[2,1] to V1[2,n] is input to each of the capacitors C1[2,1] to C1[2,n] as a potential according to the image data. ｄｒｖ [2,1]_1 to V ｄｒｖ [2,n]_1 is retained.

[0198] After that, a low-level potential is input to the wiring GL1[2], which causes a low-level potential to be applied to each of the control terminals of the switches SW1 of the pixels PX[2,1] to PX[2,n] arranged in the second row of the pixel array ALP, turning off the switches SW1 of the pixels PX[2,1] to PX[2,n].

[0199] Furthermore, during period U4, after a low-level potential is applied to the wiring GL1[2], a low-level potential is input to the wiring GL6[2]. As a result, a low-level potential is applied to each of the control terminals of the switches SW6 of the pixels PX[2,1] to PX[2,n] arranged in the second row of the pixel array ALP, and therefore the switches SW6 of the pixels PX[2,1] to PX[2,n] are turned off. This operation also causes current to flow between the anode and cathode of the light-emitting device LD of each of the pixels PX[2,1] to PX[2,n], causing these light-emitting devices LD to emit light with a brightness corresponding to the amount of current. Note that the amount of current is determined by the gate-source voltage of the transistor M2, i.e., the voltage held in the capacitor C1, as described in FIGS. 3A and 3B . In other words, the light-emitting device LD of the pixel PX[2,1] is turned off when the voltage V ｄｒｖ The light emitting device LD of the pixel PX[2,2] emits light with a brightness corresponding to the voltage V ｄｒｖ The light emitting device LD of the pixel PX[2, n] emits light with a brightness corresponding to the voltage V ｄｒｖ [2, n]_1 emits light of a brightness according to the

[0200] In the period U5, similarly to the periods U1 and U2 (periods U3 and U4), image data is written to the pixels PX in each of the third to (m-1)th rows. Note that the writing of image data to the pixels PX in the period U5 is performed sequentially for each row.

[0201] In the period U6, the operations of the periods T11 to T13 in the timing chart of FIG. 3A are performed in the pixels PX[m,1] to PX[m,n] located on the m-th row of the pixel array ALP. As a result, the potentials of the nodes N3[1] to N3[n] are V ｒｅｆ This becomes:

[0202] In addition, during the period U6, a high-level potential is input to the wiring GL1[m]. As a result, a high-level potential is applied to each of the control terminals of the switches SW1 of the pixels PX[m,1] to PX[m,n] arranged in the m-th row of the pixel array ALP, and therefore the switches SW1 of the pixels PX[m,1] to PX[m,n] are turned on.

[0203] During period U6, a high-level potential is input to the wiring GL6[m]. As a result, a high-level potential is applied to each of the control terminals of the switches SW6 of the pixels PX[m,1] to PX[m,n] arranged in the m-th row of the pixel array ALP, and the switches SW6 of the pixels PX[m,1] to PX[m,n] are turned on. This operation also prevents current from flowing between the anode and cathode of the light-emitting devices LD of the pixels PX[m,1] to PX[m,n], and therefore these light-emitting devices LD do not emit light.

[0204] Furthermore, due to the operations in the periods T11 to T13 in the timing chart of FIG. 3A, the voltages V held in the capacitors C1[m,1] to C1[m,n] included in the pixels PX[m,1] to PX[m,n], respectively, before the period U6 are ｄｒｖ [m, 1]_0 to V ｄｒｖ[m,n]_0 is initialized, and a voltage for correcting the threshold voltage of the transistor M2 is written to each of the capacitors C1[1,1] to C1[1,n]. Note that no correction voltage is written to the capacitors C1[m,1], C1[m,2], and C1[m,n] during the period U6 in FIG.

[0205] In the period U7, the operations of the periods T14 to T17 in the timing chart of FIG. 3A are performed in the pixels PX[m,1] to PX[m,n] located on the m-th row of the pixel array ALP. At this time, as an example, the potential V ｄ [m, 1]_1 to V ｄ [m, n]_1 is input. ｄ [m, 1]_1 to V ｄ [m, n]_1 is V in the description of FIG. 3A and FIG. 3B. ｄａｔａ is equivalent to

[0206] Furthermore, due to the operation of the periods T14 to T17 in the timing chart of FIG. 3A, the first terminals of the capacitors C1[m,1] to C1[m,n] included in the pixels PX[m,1] to PX[m,n], respectively, are supplied with V ｄ [m, 1]_1 to V ｄ As a result, a potential V[m, n]_1 is input to each of the capacitors C1[m, 1] to C1[m, n] as a potential according to the image data. ｄｒｖ [m, 1]_1 to V ｄｒｖ [m, n]_1 is retained.

[0207] After that, a low-level potential is input to the wiring GL1[m], which causes a low-level potential to be applied to each of the control terminals of the switches SW1 of the pixels PX[m,1] to PX[m,n] arranged in the m-th row of the pixel array ALP, turning off the switches SW1 of the pixels PX[m,1] to PX[m,n].

[0208] Furthermore, during period U7, after a low-level potential is applied to the wiring GL1[3], a low-level potential is input to the wiring GL6[m]. As a result, a low-level potential is applied to each of the control terminals of the switches SW6 of the pixels PX[m,1] to PX[m,n] arranged in the m-th row of the pixel array ALP, and therefore the switches SW6 of the pixels PX[m,1] to PX[m,n] are turned off. This operation also causes current to flow between the anode and cathode of the light-emitting device LD of each of the pixels PX[m,1] to PX[m,n], and these light-emitting devices LD emit light with a brightness corresponding to the amount of current. Note that the amount of current is determined by the gate-source voltage of the transistor M2, i.e., the voltage held in the capacitor C1, as described in FIGS. 3A and 3B . In other words, the light-emitting device LD of the pixel PX[m,1] is turned off when the voltage V ｄｒｖ The light emitting device LD of the pixel PX[m,2] (not shown in FIG. 1) emits light with a brightness corresponding to the voltage V ｄｒｖ The light emitting device LD of the pixel PX[m, n] emits light with a brightness corresponding to the voltage V ｄｒｖ It emits light with a brightness according to [m, n]_1.

[0209] As described above, by performing the operations in the periods U1 to U7, the display device DSP0 to which the display device DSP1A is applied can display an image. Furthermore, each time the operations in the periods U1 to U7 are repeated, the image displayed on the display device DSP0 can be updated.

[0210] Furthermore, the above-described operation method of the display device DSP0 is not limited to the operation method of the display device according to one embodiment of the present invention. For example, the operation method of the display device according to one embodiment of the present invention may be a method in which the display device DSP0 of FIG. 1 causes the light-emitting device of the pixel PX to emit light in a pulsed manner during one frame period by controlling the on / off state of a switch included in the pixel PX and / or controlling the voltage applied to the pixel PX, thereby displaying an image. Conversely, the display device DSP0 of FIG. 1 can prevent the light-emitting device of the pixel PX from emitting light during periods other than when the light-emitting device of the pixel PX is emitting light during one frame period. In other words, the display device DSP0 can perform an operation (called duty driving) of displaying an image and displaying black during one frame period.

[0211] 1, when a moving image is displayed on the display device DSP0, the frame frequency of the display device DSP0 may be 30 Hz or more, 60 Hz or more, 120 Hz or more, 165 Hz or more, or 240 Hz or more. When a still image is displayed on the display device DSP0, the frame frequency of the display device DSP0 may be 10 Hz or less, 5 Hz or less, 1 Hz or less, 0.5 Hz or less, or 0.1 Hz or less.

[0212] <<Layout Example of Display Device>> Figures 6A and 6B are layout diagrams (plan views) showing an example of a circuit configuration of a part of the display device DSP1A of Figure 2. Figure 6A shows a layout diagram of the circuit CD, and Figure 6B shows a layout diagram of the pixel PX.

[0213] In the layout diagram of Fig. 6A, a transistor M11 is applied to the switch SW11 included in the circuit CD of Fig. 1, and a transistor M12 is applied to the switch SW12 included in the circuit CD of Fig. 1. In addition, in the layout diagram of Fig. 6B, a transistor M1 is applied to the switch SW1 included in the pixel PX of Fig. 1, a transistor M3 is applied to the switch SW3 included in the pixel PX of Fig. 1, a transistor M5 is applied to the switch SW5 included in the pixel PX of Fig. 1, and a transistor M6 is applied to the switch SW6 included in the pixel PX of Fig. 1.

[0214] 6A and 6B, the display device DSP1A includes a conductor GEM, a conductor SDMB, a conductor SDMT, a semiconductor SMC, and a conductor PLG. Note that insulators included in the display device DSP1A are not shown in either of FIGS.

[0215] As an example, the semiconductor SMC is located below the conductor GEM. Also, as an example, the conductor GEM is located below the conductor SDMB. Also, as an example, the conductor SDMB is located below the conductor SDMT. That is, in Figures 6A and 6B, the circuit CD and the pixel PX are formed in the order of the semiconductor SMC, the conductor GEM, the conductor SDMB, and the conductor SDMT.

[0216] As an example, a portion of the conductor GEM functions as the gates (sometimes referred to as first gates) of the transistors M1, M2, M3, M5, M6, M11, and M12.

[0217] The semiconductor SMC, conductor GEM, conductor SDMB, and conductor SDMT can each be formed using, for example, a photolithography method. Specifically, for example, when forming the conductor GEM, a conductive material to be the conductor GEM can be formed using one or more methods selected from a sputtering method, a chemical vapor deposition (CVD) method, a pulsed laser deposition (PLD) method, and an atomic layer deposition (ALD) method, and then a desired pattern can be formed using a photolithography method. The semiconductor SMC, conductor SDMB, and conductor SDMT can also be formed using the same method as above.

[0218] Furthermore, an insulator may be provided between the semiconductor SMC and the conductor GEM, between the conductor GEM and the conductor SDMB, and between the conductor SDMB and the conductor SDMT. In particular, the insulator provided between the semiconductor SMC and the conductor GEM may function as a gate insulating film (which may be referred to as a first gate insulating film or a front gate insulating film).

[0219] Furthermore, conductors PLG functioning as wiring or plugs are provided between the semiconductor SMC and the conductor SDMB, between the semiconductor SMC and the conductor SDMT, and between the conductor GEM and the conductor SDMT. The conductors PLG are formed, for example, by forming openings in the insulator and filling the openings with a conductive material that will become the conductors PLG. After the conductors PLG are formed, they may be planarized by a planarization process using a chemical mechanical polishing method or the like to align the film surfaces of the conductors PLG and the surrounding insulators.

[0220] As an example, each of the transistors M1, M2, M3, M5, M6, M11, and M12 shown in Figures 6A and 6B includes a portion of a semiconductor SMC, a conductor GEM, an insulator, and a conductor PLG.

[0221] 6A and 6B, the capacitances C1 and C2 each include a portion of the conductor SDMB and a portion of the conductor SDMT. Specifically, the capacitances C1 and C2 each include a region where the conductor SDMB and the conductor SDMT overlap. That is, in the capacitances C1 and C2, a portion of the conductor SDMB functions as one of a pair of electrodes, and a portion of the conductor SDMT functions as the other of the pair of electrodes. It is preferable that an insulator with a high dielectric constant be provided between the conductor SDMB and the conductor SDMT included in the capacitances C1 and C2.

[0222] 6B is formed on the conductor SDMT, and functions as a wiring or a plug for electrically connecting to the anode of the light-emitting device LD (not shown in FIG. 6B) located above the conductor SDMT.

[0223] Note that the layout diagram of the display device of one embodiment of the present invention is not limited to Fig. 6A and Fig. 6B The layout diagram of the display device of one embodiment of the present invention may be modified as appropriate to Fig. 6A or Fig. 6B .

[0224] A modification of Fig. 6B is shown in Fig. 7. The layout diagram of the pixel PX shown in Fig. 7 differs from the layout diagram of the pixel PX in Fig. 6B in that the semiconductor SMC included in the transistor M3 and the semiconductor SMC included in the transistor M5 are not separated from each other but are formed as a continuous semiconductor film.

[0225] Also, in Figure 7, the semiconductor SMC included in transistor M3 and the semiconductor SMC included in transistor M5 are formed as a continuous semiconductor film, so one conductor PLG is formed on the area including one of the source or drain of transistor M3, which corresponds to the second terminal of switch SW3, and one of the source or drain of transistor M5, which corresponds to the first terminal of switch SW5.

[0226] 7, by forming a continuous semiconductor film without separating the semiconductor film, the distance over which a current flows between the source or drain of the transistor M3 and the source or drain of the transistor M5 can be shortened, which reduces the resistance between the source or drain of the transistor M3 and the source or drain of the transistor M5, leading to a reduction in power consumption.

[0227] Furthermore, not only for semiconductor films but also for conductor and insulator films, the finer the processing pattern, the more likely processing defects of the film occur. As shown in Figure 7, by not separating the semiconductor SMC between one of the source or drain of transistor M3 and one of the source or drain of transistor M5, processing defects can be prevented in some cases when separating the semiconductor SMC between one of the source or drain of transistor M3 and one of the source or drain of transistor M5.

[0228] <<Modification 1 of Display Device>> Note that the pixel of the display device according to one embodiment of the present invention described above is not limited to the pixel PX shown in Fig. 2. The display device according to one embodiment of the present invention may have an appropriately modified configuration of the pixel PX shown in Fig. 2.

[0229] Figure 8A shows a modification of the pixel PX of Figure 2. The pixel PX shown in Figure 8A differs from the pixel PX of Figure 2 in that the transistor M2 has a back gate.

[0230] Specifically, the transistor M2 shown in FIG. 8A is, for example, a transistor having a structure with gates above and below the channel, and the transistor M2 has a first gate and a second gate. For convenience, the first gate is described as a gate (sometimes referred to as a front gate) and the second gate is described as a back gate, but the first gate and the second gate can be interchanged. Therefore, in this specification, the term "gate" can be interchanged with the term "back gate." Similarly, the term "back gate" can be interchanged with the term "gate." As a specific example, a connection configuration in which "the gate is electrically connected to the first wiring, and the back gate is electrically connected to the second wiring" can be replaced with a connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring."

[0231] Furthermore, the pixel PX of the display device according to one embodiment of the present invention does not depend on the connection configuration of the back gate of the transistor. The transistor M2 in FIG. 8A is illustrated with a back gate, but the connection configuration of the back gate is not illustrated. However, the electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-state current of the transistor. That is, the gate and the back gate of the transistor M2 may be electrically connected. Furthermore, in a transistor having a back gate, for example, in order to change the threshold voltage or reduce the off-state current of the transistor, a wiring electrically connected to an external circuit or the like may be provided, and a fixed or variable potential may be applied to the back gate of the transistor by the external circuit or the like. Note that this applies not only to FIG. 8A but also to transistors described elsewhere in the specification and transistors illustrated in other drawings.

[0232] Furthermore, in the pixel PX of FIG. 8A, the gate of the transistor M2 is electrically connected to the first terminal of the switch SW3, the first terminal of the switch SW1, and the first terminal of the capacitor C1. However, as shown in FIG. 8B, the pixel PX may be configured such that the back gate of the transistor M2, rather than the gate of the transistor M2, is electrically connected to the first terminal of the switch SW3, the first terminal of the switch SW1, and the first terminal of the capacitor C1.

[0233] As described above, electrical switches such as transistors can be used for the switches SW1, SW3, SW5, and SW6 included in the pixel PX shown in Fig. 2. Specifically, as shown in Fig. 8C, the pixel PX can be configured such that the switch SW1 includes a transistor M1, the switch SW3 includes a transistor M3, the switch SW5 includes a transistor M5, and the switch SW6 includes a transistor M6. Note that the transistors applicable to the transistor M2 can be used for the transistors M1, M3, M5, and M6, respectively.

[0234] 2 performs potential conversion of image data signals using the capacitance C1 inside the pixel PX and the capacitance C2 outside the pixel PX. For example, when a voltage for correcting the threshold voltage of the transistor M2 is written to the capacitance C1, the potential of the node N1 changes due to a change in the potential of the node N2. １ / (C １ +C ２ ) is added, the voltage written to the capacitor C1 to correct the threshold voltage of the transistor M2 may be shifted (if the change in the potential of the node N2 is the same as the change in the potential of the node N1, the voltage written to the capacitor C1 to correct the threshold voltage of the transistor M2 will not be shifted). However, in the display device DSP1A of FIG. 2, as shown in the timing charts of FIGS. 3A and 3B, the potential of the node N2 does not change except during periods T11, T16, and T17, and in periods T16 and T17, there is no conduction between the node N1 and the first terminal of the capacitor C2. Therefore, the change in the potential of the node N1 due to the change in the potential of the node N2 is not affected by the capacitor C2. In other words, when the potential of the node N2 changes, the amount of change in the potential of the node N1 is approximately the same as the amount of change in the potential of the node N2.

[0235] <<Modification Example 2 of Display Device>> Next, an example of the display device DSP0 of Fig. 1, which is different from the display device DSP1A, is shown in Fig. 9. The display device DSP1B shown in Fig. 9 is a modification of the display device DSP1A of Fig. 2, and differs from the display device DSP1A in that a capacitance C2I is provided in the pixel PX and that a capacitance C2 is not provided in the circuit CD.

[0236] Therefore, in the description of the display device DSP1B, for parts that are common to the contents of the display device DSP1A, reference will be made to the description of the display device DSP1A.

[0237] In the display device DSP1B, a first terminal of the capacitor C2I is electrically connected to a second terminal of the switch SW1, and a second terminal of the capacitor C2I is electrically connected to the line SL.

[0238] A first terminal of the switch SW11 is electrically connected to the line SL and a first terminal of the switch SW12.

[0239] In the display device DSP1B, the electrical connection point between the first terminal of the switch SW11, the first terminal of the switch SW12, and the capacitance C2I is referred to as a node N3. In the case of the display device DSP1B of this configuration example, the node N3 may be replaced with the line SL in some cases.

[0240] In the display device DSP1B, the capacitance C2I corresponds to the capacitance C2 of the display device DSP1A. That is, the display device DSP1B is configured such that the capacitance C2 included in the circuit CD in the display device DSP1A is provided in the pixel PX as capacitance C2I. Therefore, the operation method of the display device DSP1B can sometimes be explained by replacing the capacitance C2 with the capacitance C2I in the operation method of the display device DSP1A.

[0241] The display device DSP1B can correct the threshold voltage of the transistor M2 of the pixel PX and display an image on the pixel PX by performing the same operation method as the display device DSP1A.

[0242] Note that the display device according to one embodiment of the present invention is not limited to the configuration of the display device DSP1B, and may have an appropriately modified configuration of the display device DSP1B.

[0243] Fig. 10 shows a modification of the display device DSP1B of Fig. 9. The display device DSP1C shown in Fig. 10 differs from the display device DSP1B of Fig. 9 in that the second terminal of the switch SW1 is electrically connected to the line SL instead of the first terminal of the capacitor C2I, the first terminal of the switch SW1 is electrically connected to the second terminal of the capacitor C2I instead of the gate of the transistor M2, the first terminal of the switch SW3, and the first terminal of the capacitor C1, and the first terminal of the capacitor C2I is electrically connected to the gate of the transistor M2, the first terminal of the switch SW3, and the first terminal of the capacitor C1.

[0244] In other words, the display device DSP1B is configured such that the electrical path from the wiring SL to the wiring VE0 is provided with a capacitance C2I, a switch SW1, a capacitance C1, and a light-emitting device LD, in that order, and the display device DSP1C is configured such that the electrical path from the wiring SL to the wiring VE0 is provided with a switch SW1, a capacitance C2I, a capacitance C1, and a light-emitting device LD, in that order.

[0245] In this specification and the like, the electrical connection point between the first terminal of the switch SW1 and the second terminal of the capacitor C2I is referred to as a node N4.

[0246] Furthermore, in the display device DSP1C, the capacitance C2I corresponds to the capacitance C2 of the display device DSP1A. Furthermore, in the display device DSP1C, the node N4 corresponds to the node N3 of the display device DSP1A. That is, the display device DSP1C is configured such that the capacitance C2 included in the circuit CD in the display device DSP1A is provided in the pixel PX as capacitance C2I. Therefore, the operation method of the display device DSP1C can sometimes be explained by replacing the capacitance C2 with the capacitance C2I and the node N3 with the node N4 in the operation method of the display device DSP1A.

[0247] The display device DSP1C also performs the same operation method as the display device DSP1A, thereby correcting the threshold voltage of the transistor M2 of the pixel PX and displaying an image on the pixel PX.

[0248] 11 shows another modified example of the display device DSP1A, which is different from the display device DSP1C of Fig. 10. The display device DSP1D shown in Fig. 11 is a further modified example of the display device DSP1C of Fig. 10, and differs from the display device DSP1C in that a switch SW11I is provided in the pixel PX and that a switch SW11 is not provided in the circuit CD. In other words, the display device DSP1D shown in Fig. 11 differs from the display device DSP1A in that a switch SW11I and a capacitor C2I are provided in the pixel PX and that a switch SW11 and a capacitor C2 are not provided in the circuit CD.

[0249] In the display device DSP1D, a first terminal of a switch SW11I is electrically connected to a first terminal of a switch SW1 and a second terminal of a capacitor C2I. The second terminal of the switch SW11I is electrically connected to a wiring VE3. The control terminal of the switch SW11I is electrically connected to a wiring GL11.

[0250] A first terminal of the capacitor C2I is electrically connected to a first terminal of the switch SW3, a first terminal of the capacitor C1, and the gate of the transistor M2, and a second terminal of the switch SW1 is electrically connected to the line SL.

[0251] A first terminal of the switch SW12 is electrically connected to the line SL.

[0252] The wiring GL11, together with the wiring GL1, the wiring GL3, the wiring GL5, and the wiring GL6, corresponds to one of the wirings GL[1] to GL[m] in Fig. 1. That is, in the circuit configuration of the pixel PX shown in Fig. 11, the number of wirings GL extending in one row of the pixel array ALP is five.

[0253] In the display device DSP1D, the capacitance C2I corresponds to the capacitance C2 of the display device DSP1A. The switch SW11I corresponds to the switch SW11 of the display device DSP1A. The wiring GL11 corresponds to the wiring SWL11 of the display device DSP1A. The node N4 corresponds to the node N3 of the display device DSP1A. That is, the display device DSP1D is configured such that the switch SW11 and the capacitance C2 included in the circuit CD of the display device DSP1A are provided in the pixel PX as the switch SW11I and the capacitance C2I, respectively. Therefore, the operation method of the display device DSP1D can sometimes be explained by replacing the switch SW11 with the switch SW11I, the capacitance C2 with the capacitance C2I, the node N3 with the node N4, and the wiring SWL11 with the wiring GL11 in the operation method of the display device DSP1A.

[0254] The display device DSP1D can correct the threshold voltage of the transistor M2 of the pixel PX and display an image on the pixel PX by performing the same operation method as the display device DSP1A.

[0255] As described in the operation method of the display device DSP1A, the potentials applied to the wiring VE2 and the wiring VE3 can be made equal to each other. In this case, the wiring VE2 and the wiring VE3 may be combined into a single wiring. As an example, FIG. 12 shows a display device DSP1DA having a configuration in which the wirings VE2 and VE3 in the display device DSP1D are combined into a single wiring VE3.

[0256] As described in the operation method of the display device DSP1A, the potentials applied to the wiring VE1 and the wiring VE3 can be made equal to each other. In this case, the wiring VE1 and the wiring VE3 may be combined into a single wiring. As an example, FIG. 13 shows a display device DSP1DB having a configuration in which the wirings VE1 and VE3 in the display device DSP1D are combined into a single wiring VE1.

[0257] 14 shows another modified example of the display device DSP1A, which is different from the display device DSP1B of FIG. 9, the display device DSP1C of FIG. 10, the display device DSP1D of FIG. 11, the display device DSP1DA of FIG. 12, and the display device DSP1DB of FIG. 13. The display device DSP1E shown in FIG. 14 is a further modified example of the display device DSP1D of FIG. 11, and differs from the display device DSP1D in that the circuit CD does not include a switch SW12. In other words, the display device DSP1E shown in FIG. 14 differs from the display device DSP1A in that the pixel PX is provided with a switch SW11I, a switch SW12I, and a capacitor C2I, and in that the circuit CD is not included.

[0258] For convenience, in the display device DSP1E, the switch SW1 of the display device DSP1D is written as a switch SW12I, and the line GL1 of the display device DSP1D is written as a line GL12.

[0259] In the display device DSP1E, the driver circuit SD is electrically connected to a wiring SL, and the wiring SL is electrically connected to a second terminal of the switch SW12I.

[0260] The switch SW12I provided in the display device DSP1E can also serve as the switch SW1 provided in the pixel PX in the display device DSP1D. Therefore, the display device DSP1D can be modified to have a configuration in which the switch SW12 is not provided in the circuit CD, as in the display device DSP1E in FIG.

[0261] The operation method of the display device DSP1E can be explained by replacing the switch SW11 with the switch SW11I, the capacitance C2 with the capacitance C2I, the node N3 with the node N4, the wiring SWL11 with the wiring GL11, and the wiring SWL12 with the wiring GL12 in the operation method of the display device DSP1A. Note that the signal supplied by the wiring GL1 of the display device DSP1A does not need to be considered in the display device DSP1E.

[0262] <<Modification Example 3 of Display Device>> Next, an example of the display device DSP0 of Fig. 1, which is different from the display devices DSP1A to DSP1E, is shown in Fig. 15. The display device DSP1F shown in Fig. 15 is a modification of the display device DSP1A of Fig. 2, and differs from the display device DSP1A in that a switch SW4 is provided so as to be electrically connected in series between the second terminal of the capacitor C1, the first terminal of the transistor M2, and the first terminal of the switch SW6 and the light-emitting device LD, and in that a switch SW9 is provided so as to be electrically connected in parallel to the light-emitting device LD.

[0263] Each of the switches SW4 and SW9 can be, for example, a switch that can be applied to the switches SW1, SW3, SW5, SW6, SW11, or SW12. Each of the switches SW4 and SW9 is turned on when a high-level potential is applied to its control terminal, and turned off when a low-level potential is applied to its control terminal.

[0264] A first terminal of the switch SW4 is electrically connected to the second terminal of the capacitor C1, the first terminal of the transistor M2, and the first terminal of the switch SW6. A second terminal of the switch SW4 is electrically connected to the anode of the light-emitting device LD and the first terminal of the switch SW9. A control terminal of the switch SW4 is electrically connected to the wiring GL4.

[0265] A second terminal of the switch SW9 is electrically connected to the cathode of the light emitting device LD and the wiring VE0, and a control terminal of the switch SW9 is electrically connected to the wiring GL9.

[0266] 15, the wiring GL4 and the wiring GL9, together with the wiring GL1, the wiring GL3, the wiring GL5, and the wiring GL6, correspond to one of the wirings GL[1] to GL[m] in Fig. 1. That is, in the circuit configuration of the pixel PX shown in Fig. 15, the number of wirings GL extending in one row of the pixel array ALP is six.

[0267] Next, an example of the operation method of the display device DSP1F of FIG. 15 will be described.

[0268] 16 is a timing chart illustrating an example of an operation method of the display device DSP1F. Specifically, the timing chart of FIG. 16 is a modified example of the timing chart of FIG. 3A, and shows changes in the potentials of the wirings GL4 and GL9 in addition to the timing chart of FIG. 3A. Therefore, for operations of the display device DSP1F other than the changes in the potentials of the wirings GL4 and GL9, refer to the description of the timing chart of FIG. 3A.

[0269] In the period T16, a high-level potential is applied to the wiring GL4, and a low-level potential is applied to the wiring GL9. As a result, a high-level potential is applied to the control terminal of the switch SW4, so that the switch SW4 is in an on state. Also, a low-level potential is applied to the control terminal of the switch SW9, so that the switch SW9 is in an off state.

[0270] That is, in the period T16, the wiring VE0, the cathode of the light emitting device LD, and the anode of the light emitting device LD are not electrically connected to each other, and therefore the anode of the light emitting device LD is supplied with the potential V ＣＴ On the other hand, in a period T16, the switches SW5 and SW4 are both in the on state, so that a current flows from the wiring VE2 to the anode of the light-emitting device LD, causing the light-emitting device LD to emit light.

[0271] In the periods T11 to T15 and T17, a low-level potential is applied to the wiring GL4, and a high-level potential is applied to the wiring GL9. As a result, a low-level potential is applied to the control terminal of the switch SW4, turning the switch SW4 off. Also, a high-level potential is applied to the control terminal of the switch SW9, turning the switch SW9 on.

[0272] That is, during periods T11 to T15 and period T17, conduction occurs between the wiring VE0, the cathode of the light-emitting device LD, and the anode of the light-emitting device LD, and therefore the anode-cathode voltage of the light-emitting device LD is 0 V. Furthermore, because the switch SW4 is in the off state, no current flows between the node N2 and the anode of the light-emitting device LD via the switch SW4.

[0273] In particular, periods T11 to T15 and period T17 are periods during which the light-emitting device LD does not emit light, but by turning on the switch SW9 during these periods, the charge accumulated in the anode of the light-emitting device LD can be discharged to the wiring VE0 via the switch SW9. In other words, during the periods during which the light-emitting device LD does not emit light, the display device DSP1F can discharge the charge accumulated in the anode of the light-emitting device LD faster than display devices that do not have the switch SW9 (e.g., display devices DSP1A to DSP1E). This allows the light-emitting state of the light-emitting device LD to transition to the extinction state more quickly.

[0274] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0275] Embodiment 2 In this embodiment, a display device according to one embodiment of the present invention, which is different from the display device DSP1A described above, will be described.

[0276] <Configuration Example 1 of Display Device> Figure 17 shows configuration examples of the pixels PX and the circuits CD that can be applied to the display device DSP0 of Figure 1 described in embodiment 1. Similar to Figure 2, the display device DSP2A shown in Figure 17 shows an excerpt of one of the multiple pixels PX included in the pixel array ALP, and the drive circuit GD of the row driver circuit RWD, and the circuit CD and drive circuit SD of the column driver circuit CLM that are electrically connected to the pixel PX.

[0277] 17, the pixel PX includes, for example, a transistor M2, switches SW1, SW4, SW6, SW7, SW8, capacitors C1 and C3, and a light-emitting device LD. The circuit CD includes switches SW11, SW12, SW13, and a capacitor C2.

[0278] Note that the transistor M2 shown in Fig. 17 can be a transistor that can be applied to the transistor M2 shown in Fig. 2. However, the transistor M2 in Fig. 17 differs from the transistor M2 in Fig. 2 in that it has a back gate.

[0279] Furthermore, for switches SW1, SW4, SW6, SW7, SW8, SW11, SW12, and SW13 shown in FIG. 17, switches that can be applied to switches SW1, SW3, SW5, SW6, SW11, and SW12 shown in FIG. 2 can be used.

[0280] In addition, in this specification, each of the switches SW1, SW4, SW6, SW7, SW8, SW11, SW12, and SW13 shown in FIG. 17 is assumed to be in an on state when a high-level potential is applied to its control terminal, and to be in an off state when a low-level potential is applied to its control terminal.

[0281] For the light emitting device LD, the description of the light emitting device LD in the first embodiment is referred to.

[0282] In pixel PX, a first terminal of switch SW1 is electrically connected to the gate of transistor M2, a first terminal of switch SW8, and a first terminal of capacitor C1, a second terminal of switch SW1 is electrically connected to wiring SL, and a control terminal of switch SW1 is electrically connected to wiring GL1. A first terminal of transistor M2 is electrically connected to a first terminal of switch SW4, a first terminal of switch SW6, a second terminal of switch SW8, a second terminal of capacitor C1, and a first terminal of capacitor C3, a second terminal of transistor M2 is electrically connected to wiring VE2, and a back gate of transistor M2 is electrically connected to a second terminal of capacitor C3 and a first terminal of switch SW7. A second terminal of switch SW4 is electrically connected to the anode of light-emitting device LD, and a control terminal of switch SW4 is electrically connected to wiring GL4. The second terminal of the switch SW6 is electrically connected to the wiring VE1, and the control terminal of the switch SW6 is electrically connected to the wiring GL6. The second terminal of the switch SW7 is electrically connected to the wiring VE5, and the control terminal of the switch SW7 is electrically connected to the wiring GL7. The cathode of the light-emitting device LD is electrically connected to the wiring VE0.

[0283] In this embodiment, the electrical connection point between the first terminal of switch SW1, the first terminal of switch SW8, the gate of transistor M2, and the first terminal of capacitor C1 is referred to as node N1. Also, the electrical connection point between the first terminal of transistor M2, the second terminal of capacitor C1, the first terminal of capacitor C3, the first terminal of switch SW4, the first terminal of switch SW6, and the second terminal of switch SW8 is referred to as node N2. Also, the electrical connection point between the back gate of transistor M2, the second terminal of capacitor C3, and the first terminal of switch SW7 is referred to as node NB.

[0284] In the circuit CD, a first terminal of the capacitor C2 is electrically connected to the line SL and a first terminal of the switch SW13, and a second terminal of the capacitor C2 is electrically connected to a first terminal of the switch SW11 and a first terminal of the switch SW12. The second terminal of the switch SW11 is electrically connected to the line VE3, and the control terminal of the switch SW11 is electrically connected to the line SWL11. The second terminal of the switch SW12 is electrically connected to the drive circuit SD, and the control terminal of the switch SW12 is electrically connected to the line SWL12. The second terminal of the switch SW13 is electrically connected to the line VE4, and the control terminal of the switch SW13 is electrically connected to the line SWL13.

[0285] In this embodiment, the electrical connection point between the first terminal of the switch SW11, the first terminal of the switch SW12, and the second terminal of the capacitor C2 is called a node N3.

[0286] For example, each of the wirings VE0 to VE5 functions as a wiring that applies a constant potential. The constant potentials applied by the wirings VE0 to VE5 may be equal to each other or different from each other. Alternatively, some of the potentials applied by the wirings VE0 to VE5 may be equal to each other, and the remaining potentials may be different from each other. Furthermore, one or more selected from the wirings VE0 to VE5 may function as a wiring that applies a pulse potential instead of a constant potential.

[0287] 17, the wiring VE0 preferably functions as a wiring that applies a potential to the cathode of the light-emitting device LD, and the wiring VE2 preferably functions as a wiring that applies a potential to the anode of the light-emitting device LD.

[0288] In addition, when the light emitting device LD provided in the pixel PX in Fig. 17 is configured in a forward stacking configuration, the light emitting device LD in Fig. 17 may be configured in a reverse stacking configuration. In this case, the wiring VE0 functions as a wiring that applies a potential to the anode of the light emitting device LD, and the wiring VE2 functions as a wiring that applies a potential to the cathode of the light emitting device LD.

[0289] The wirings GL1, GL4, GL6, and GL7 correspond to one of the wirings GL[1] to GL[m] in Fig. 1. That is, in the circuit configuration of the pixel PX shown in Fig. 17, the number of wirings GL extending in one row of the pixel array ALP is four.

[0290] For the wirings SWL11 and SWL12, refer to the description of the wirings SWL11 and SWL12 in Fig. 2. The wiring SWL13 functions as a wiring for transmitting a control signal (digital potential) for switching the switch SW13 between an on state and an off state.

[0291] <<Example 1 of Operation Method of Display Device>> Next, an example of an operation method of the display device DSP2A of FIG. 17 will be described.

[0292] 18A to 18C are timing charts illustrating an example of an operation method of the display device DSP1A. Specifically, the timing chart in FIG. 18A shows changes in the potentials of the wirings GL1, GL4, GL6, GL7, SWL11, SWL12, and SWL13, and the node N3 during each of the periods T21 to T30. FIG. 18B shows changes in the potentials of the nodes N1 and N2 during each of the periods T21 to T30, and FIG. 18C shows changes in the potentials of the nodes N2 and NB during each of the periods T21 to T30. In FIGS. 18B and 18C, the potential change of the node N1 is indicated by a solid line, the potential change of the node N2 is indicated by a dashed line, and the potential change of the node NB is indicated by a dashed line.

[0293] In FIG. 18A, "High" indicates a high level potential, and "Low" indicates a low level potential.

[0294] The wiring VE1 is connected to a constant potential V Ｎ１ Furthermore, a constant potential V is applied to the wiring VE3. ｒｅｆ Furthermore, a constant potential V is applied to the wiring VE5. Ｎ５ In FIG. 18C, V Ｎ１ is V Ｎ５ Although the potential is lower thanＮ１ is V Ｎ５ or V Ｎ５ In some cases, a potential lower than this may be acceptable.

[0295] Also, V Ｎ５ is the back gate-source voltage of the transistor M2 is V Ｎ５ -V Ｎ１ When this is the case, it is preferable to set the potential so that the threshold voltage of the transistor M2 is lower than 0V.

[0296] Furthermore, the wiring VE2 is connected to a constant potential V ＡＮ In addition, a constant potential V ＣＴ is given. Also, V ＡＮ is V ＣＴ The potential is set to be higher than

[0297] In addition, V ＡＮ is V Ｎ１ The potential is set to be higher than V Ｎ１ -V ＣＴ The voltage V is a voltage at which the light emitting device LD does not emit light (no current flows between the anode and cathode of the light emitting device LD). Ｎ１ is V ＣＴ or V ＣＴ It is preferable that the potential is lower than

[0298] Before the period T21, a low-level potential is applied to the wirings GL1, GL6, GL7, SWL11, SWL12, and SWL13. Therefore, a low-level potential is applied to the control terminals of the switches SW1, SW6, SW7, SW8, SW11, SW12, and SW13, and the switches are turned off.

[0299] Before the period T21, a high-level potential is applied to the wiring GL4, and therefore a high-level potential is applied to the control terminal of the switch SW4, turning the switch SW4 on.

[0300] The potential of the node N3 is undefined before the period T21, and therefore the potential of the node N3 before the period T21 in the timing chart of FIG.

[0301] Furthermore, because the switch SW4 is in an on state, when the gate-source voltage of the transistor M2 is higher than the threshold voltage of the transistor M2, a current flows between the wiring VE2 and the wiring VE0 via the transistor M2, the switch SW4, and the light-emitting device LD. Therefore, the light-emitting device LD may emit light before the period T21.

[0302] [Period T21] In the period T21, a high-level potential is applied to the wirings GL6, GL7, and SWL11. As a result, a high-level potential is applied to the control terminals of the switches SW6, SW7, SW8, and SW11, and these switches are turned on.

[0303] Since the switches SW6 and SW8 are on, the gate of the transistor M2, the first terminal of the transistor M2, the first terminal of the capacitor C1, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 are electrically connected to the wiring VE1. Therefore, the potential V from the wiring VE1 is applied to the gate of the transistor M2, the first terminal of the capacitor C1 (node ​​N1), the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 (node ​​N2). Ｎ１ is given (see Figures 18B and 18C).

[0304] Furthermore, since the switch SW7 is in an on state, conduction is established between the back gate of the transistor M2 and the second terminal of the capacitor C3 and the wiring VE5. Therefore, the back gate of the transistor M2 and the second terminal of the capacitor C3 (node ​​NB) are supplied with the potential V Ｎ５ is given (see FIG. 18C).

[0305] At this time, the switch SW4 is in the on state, so the anode of the light emitting device is supplied with the potential VＮ１ Therefore, the voltage between the anode and cathode of the light emitting device LD is V Ｎ１ -V ＣＴ As described above, when the voltage between the anode and cathode of the light-emitting device LD is V Ｎ１ -V ＣＴ When the transistor M2 is in the ON state, the light emitting device LD does not emit light (no current flows between the anode and cathode of the light emitting device LD). When the transistor M2 is in the ON state, a current flows from the wiring VE2 to the wiring VE1 via the transistor M2 and the switch SW6.

[0306] Furthermore, since the switch SW11 is in an on state, the second terminal of the capacitor C2 and the first terminal of the switch SW12 are electrically connected to the wiring VE3, and therefore the second terminal of the capacitor C2 and the first terminal of the switch SW12 (node ​​N3) are electrically connected to the wiring VE3. ｒｅｆ is given (see FIG. 18A).

[0307] In the period T21 of the timing chart in Figure 18A, a high-level potential is input to each of the wirings GL6, GL7, and SWL11 at the same timing, but within the period T21, the timing at which a high-level potential is input to each of the wirings GL6, GL7, and SWL11 may be different from each other.

[0308] [Period T22] During period T22, a low-level potential is applied to the wiring GL4. As a result, a low-level potential is applied to the control terminal of the switch SW4, turning the switch SW4 off. As a result, electrical continuity is not established between the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 and the anode of the light-emitting device LD.

[0309] [Period T23] In the period T23, a low-level potential is applied to the wiring GL6, so that the control terminal of the switch SW6 is supplied with a low-level potential, turning the switch SW6 off.

[0310] The potentials of the gate of the transistor M2 and the first terminal of the transistor M2 are VＮ１ Therefore, the gate-source voltage of the transistor M2 is 0 V. When the threshold voltage of the transistor M2 is 0 V or less, the transistor M2 is in an on state.

[0311] Also, just before the switch SW6 is turned off, the back gate-source voltage of the transistor M2 is V Ｎ５ -V Ｎ１ When the switch SW6 is turned off, the potential V Ｎ１ Since the application of the voltage Vcc is stopped, the nodes N1 and N2 are charged with positive charges from the line VE2 via the first terminal and the second terminal of the transistor M2 and the switch SW8, thereby increasing the potentials of the nodes N1 and N2.

[0312] As the potentials of the nodes N1 and N2 increase, the back gate-source voltage of the transistor M2 decreases. ｔｈ When the voltage between the gate and source of the transistor M2 reaches 0 V, the transistor M2 is turned off, and the charging of positive charges from the wiring VE2 stops. The back gate-source voltage at this time is defined as ΔV Ｂ In addition, the switch SW7 is in an on state, and the potential of the node NB is V Ｎ５ Therefore, the potentials of the nodes N1 and N2 at this time are V Ｎ５ −ΔV Ｂ When the transistor M2 is turned off, the charging of positive charges from the wiring VE2 stops, and the potentials of the nodes N1 and N2 become V Ｎ５ −ΔV Ｂ (See FIGS. 18B and 18C.) Furthermore, when the transistor M2 is turned off, the nodes N1 and N2 are brought into a floating state.

[0313] [Period T24] During the period T24, a low-level potential is applied to the wiring GL7. As a result, a low-level potential is applied to the control terminals of the switches SW7 and SW8, and the switches SW7 and SW8 are turned off.

[0314] Since the switch SW7 is in the off state, the second terminal of the capacitor C3 and the back gate of the transistor M2 are not electrically connected to the wiring VE5. At this time, the node NB is in a floating state. As a result, the voltage ΔV between the first terminal and the second terminal of the capacitor C3 Ｂ can be maintained.

[0315] Furthermore, because the switch SW8 is in the off state, there is no conduction between the first terminal of the capacitor C1 and the gate of the transistor M2 and the second terminal of the capacitor C1, the first terminal of the transistor M2, and the first terminal of the capacitor C3, respectively, and the nodes N1 and N2 are in a floating state.

[0316] [Period T25] In the period T25, a high-level potential is applied to each of the wirings GL1, GL6, and SWL13. As a result, a high-level potential is applied to the control terminals of the switches SW1, SW6, and SW13, and the switches SW1, SW6, and SW12 are turned on.

[0317] Since the switches SW1 and SW13 are on, the gate of the transistor M2, the first terminal of the capacitor C1, and the wiring SL are electrically connected to the wiring VE4. Therefore, the gate of the transistor M2, the first terminal of the capacitor C1 (node ​​N1), and the wiring SL are electrically connected to the potential V ｉｎｉｔ is given (see FIG. 18B).

[0318] Furthermore, since the switch SW6 is in an on state, the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 are electrically connected to the wiring VE1, and therefore the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 (node ​​N2) are supplied with the potential V Ｎ１ is given (see Figures 18B and 18C).

[0319] At this time, the potentials of the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 (node ​​N2) are V Ｎ５ −ΔV Ｂ From V Ｎ１ In this operation example, the potential of the back gate (the second terminal of the capacitor C3 and the node NB) of the transistor M2 changes to V Ｎ５ From V Ｎ１ +ΔV Ｂ (See FIG. 18C.) This corresponds to the case where the capacitive coupling coefficient around the node NB is 1.

[0320] [Period T26] In the period T26, a low-level potential is applied to the wiring SWL13, and therefore, a low-level potential is applied to the control terminal of the switch SW13, turning the switch SW13 off.

[0321] Because the switch SW13 is off, the gate of the transistor M2, the first terminal of the capacitor C1 (node ​​N1), and the wiring SL are not electrically connected to the wiring VE4, and the gate of the transistor M2, the first terminal of the capacitor C1 (node ​​N1), and the wiring SL are in a floating state.

[0322] [Period T27] During period T27, a low-level potential is applied to the wiring SWL11, and a high-level potential is applied to the wiring SWL12. As a result, a low-level potential is applied to the control terminal of the switch SW11, turning the switch SW11 off. Also, a high-level potential is applied to the control terminal of the switch SW12, turning the switch SW12 on.

[0323] In particular, when the switch SW12 is turned on, the drive circuit SD transmits an image data signal corresponding to the image to be displayed on the pixel PX to the second terminal (node ​​N3) of the capacitor C2 via the switch SW12. ｄａｔａ Let's say.

[0324] Therefore, the potential of the node N3 is V ｒｅｆ From V ｄａｔａ The potentials of the wiring SL and the node N1 change due to the capacitance coupling of the capacitor C2, as the potential of the node N3 changes. The amount of change in the potential of the wiring SL and the node N1 is determined by, for example, the capacitance of the capacitor C1, the capacitance of the capacitor C2, the gate capacitance of the transistor M2, the parasitic capacitance of the switch SW1, the parasitic capacitance of the switch SW8, and the parasitic capacitance of the wiring SL. In this operation example, for the sake of simplicity, the amount of change in the potential of the wiring SL and the node N1 is described as being determined by the capacitance of the capacitor C1 and the capacitance of the capacitor C2.

[0325] The capacitance of the capacitor C1 is C １ , the capacitance of the capacitor C2 is C ２ As a result, the potential of the node N3 becomes V ｒｅｆ From V ｄａｔａ , the potentials of the wiring SL and the node N1 change by an amount of ΔV ｄａｔａ = (V ｄａｔａ -V ｒｅｆ ) × C ２ / (C １ +C ２ ) is given. Therefore, the potentials of the wiring SL and the node N1 are V ｉｎｉｔ +ΔV ｄａｔａ (See FIG. 18B).

[0326] On the other hand, the second terminal (node ​​N2) of the capacitor C1 has been supplied with the potential V Ｎ１ is given, the potential of the node N3 is V ｒｅｆ From V ｄａｔａ Even during the period when the potential of the second terminal (node ​​N2) of the capacitor C1 changes to V Ｎ１ It remains unchanged.

[0327] From the above, the gate-source voltage of the transistor M2 during the period T27 is V ｄｒｖ Then, V ｄｒｖ = (potential of node N1) - (potential of node N2) = V ｉｎｉｔ +ΔV ｄａｔａ -V Ｎ１ Therefore, during the period T27, the voltage held between the first terminal and the second terminal of the capacitor C1 is V ｄｒｖ =V ｉｎｉｔ +ΔV ｄａｔａ -V Ｎ１ This becomes:

[0328] Also, the gate-source voltage V of the transistor M2 ｄｒｖ becomes larger than the threshold voltage (0 V) of the transistor M2, so the transistor M2 is turned on. However, since the switches SW4 and SW8 are off and the switch SW6 is on, a current flows between the wiring VE2 and the wiring VE1 via the transistor M2 and the switch SW6.

[0329] [Period T28] In the period T28, a low-level potential is applied to the wiring GL1, so that the control terminal of the switch SW1 is supplied with a low-level potential, turning the switch SW1 off.

[0330] When the switch SW1 is turned off, there is no conduction between the gate of the transistor M2, the first terminal of the capacitor C1, and the wiring SL. In addition, since the switch SW8 has been turned off since the period T24, the first terminal of the capacitor C1 (node ​​N1) is supplied with the potential V ｉｎｉｔ +ΔV ｄａｔａ is maintained.

[0331] [Period T29] During the period T29, a high-level potential is applied to the wiring GL4, and a low-level potential is applied to the wiring GL6. As a result, a high-level potential is applied to the control terminal of the switch SW4, turning the switch SW4 on. Also, a low-level potential is applied to the control terminal of the switch SW6, turning the switch SW6 off.

[0332] Because the switch SW4 is in the on state, conduction is established between the first terminal of the transistor M2 and the anode of the light-emitting device LD. Also, because the switch SW6 is in the off state, conduction is established between the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 and the wiring VE1. Also, because the switch SW8 has been in the off state since period T24, conduction is established between the first terminal of the transistor M2 (node ​​N2) and the gate of the transistor M2 (node ​​N1).

[0333] The gate-source voltage of the transistor M2 is V ｄｒｖ =V ｉｎｉｔ +ΔV ｄａｔａ Also, V ｄｒｖ is greater than the threshold voltage (0 V) of the transistor M2, so the transistor M2 is in an on state.

[0334] Therefore, a current flows between the wiring VE0 and the wiring VE2 via the transistor M2, the switch SW4, and the light-emitting device LD.

[0335] At this time, the voltage V between the wiring VE0 and the wiring VE2 ＡＮ -V ＣＴ is divided by the transistor M2, the light emitting device LD, and the switch SW4. In this operation example, the operation in the period T29 causes the potential of the first terminal of the transistor M2 (the second terminal of the capacitor C1, the first terminal of the capacitor C3, and the node N2) to be V Ｎ１ From V Ｓ (See FIGS. 18B and 18C).

[0336] The potential of the first terminal of the transistor M2 (the second terminal of the capacitor C1 and the node N2) is V Ｎ１ From VＳ , the potential of the gate of the transistor M2 (the first terminal of the capacitor C1 and the node N1) also changes due to the capacitive coupling of the capacitor C1. In this operation example, the operation in the period T29 causes the potential of the gate of the transistor M2 (the first terminal of the capacitor C1 and the node N1) to change to V ｉｎｉｔ +ΔV ｄａｔａ From V Ｇ (See FIG. 18B).

[0337] The amount of change in the potential of the node N1 due to the capacitive coupling of the capacitor C1 described above is determined by the electrostatic capacitance of the capacitor C1, the gate capacitance of the transistor M2, and the parasitic capacitance of the switch SW1. In this operation example, for the sake of simplicity, the amount of change in the potential of the node N1 is assumed to be equal to the amount of change in the potential of the node N2. In other words, the amount of change in the potential of the node N2 is assumed to be ΔV Ｃ１ (=V Ｓ -V Ｎ１ ), the change in the potential of the node N1 is also ΔV Ｃ１ This corresponds to the case where the capacitive coupling coefficient in the vicinity of the node N1 is 1.

[0338] Also, at node N1, ΔV Ｃ１ =V Ｇ −(V ｉｎｉｔ +ΔV ｄａｔａ ) and therefore the change in the potential of the node N2, ΔV Ｃ１ =V Ｓ -V Ｎ１ Substituting V Ｇ -V Ｓ =V ｉｎｉｔ +ΔV ｄａｔａ -V Ｎ１ =V ｄｒｖ That is, the gate-source voltage of the transistor M2 during the period T29 has not changed since the image data signal was input to the circuit CD during the period T27.

[0339] Furthermore, the potential of the first terminal of the transistor M2 (the second terminal of the capacitor C1 and the node N2) is V Ｎ１ From V Ｓ, the potential of the back gate of the transistor M2 (the second terminal of the capacitor C3 and the node NB) also changes due to the capacitive coupling of the capacitor C3. In this operation example, the operation in the period T29 causes the potential of the back gate of the transistor M2 (the second terminal of the capacitor C3 and the node NB) to change to V Ｎ１ +ΔV Ｂ From V Ｎ１ +ΔV Ｂ +ΔV Ｃ１ (See FIG. 18C. In FIG. 18C, V ＢＧ =V Ｎ１ +ΔV Ｂ +ΔV Ｃ１ At this time, the back gate-source voltage of the transistor M2 is ΔV Ｂ Since the voltage remains unchanged, the threshold voltage of the transistor M2 remains at 0V.

[0340] Now, consider the case where the transistor M2 operates in the saturation region. The amount of current flowing between the first terminal and the second terminal of the transistor M2 is determined by the gate-source voltage V ｄｒｖ Specifically, the amount of current I flowing between the source and drain of a transistor operating in the saturation region is determined by the gate-source voltage V of the transistor. ＧＳ and the threshold voltage V of the transistor ｔｈ Since it is proportional to the square of the difference between ＧＳ -V ｔｈ ) ２ where k is a proportionality constant that depends on the structure of the transistor. ＧＳ , the gate-source voltage V of the transistor M2 ｄｒｖ Substituting and V ｔｈ By substituting ≠0, I = k(V ｉｎｉｔ +ΔV ｄａｔａ ) ２ The amount of current I flowing through the transistor M2 is determined by the threshold voltage V ｔｈ Independent of V ｉｎｉｔ +ΔV ｄａｔａ It is determined by:

[0341] As described above, by performing the operations from the period T21 to the period T30, the threshold voltage V ｔｈ It is possible to generate a current that is independent of

[0342] In addition, the potential of the anode of the light-emitting device LD is V Ｓ Therefore, the potential between the anode and cathode of the light emitting device LD is V Ｓ -V ＣＴ In addition, a current (I=k(V ｉｎｉｔ +ΔV ｄａｔａ ) ２ When the light emitting device LD is an organic EL element, the luminance of the light emitting device LD is determined by the amount of current flowing between the anode and cathode of the light emitting device LD. ｉｎｉｔ is a constant potential, the light emission luminance of the light emitting device LD is controlled by the image data signal V ｄａｔａ It is determined by:

[0343] 4A to 4C, the minimum value of the pixel gradation level is V ｄａｔａ＿ｍｉｎ The maximum value of the pixel gradation level is V ｄａｔａ＿ｍａｘ When the image data signal V output from the drive circuit SD is ｄａｔａ However, through the circuit CD, the pixel PX receives V ｉｎｉｔ + K × (V ｄａｔａ＿ｍｉｎ -V ｒｅｆ ) to V ｉｎｉｔ + K × (V ｄａｔａ＿ｍａｘ -V ｒｅｆ ) will be input. ２ / (C １ +C ２ )

[0344] V ｒｅｆ V ｉｎｉｔ If the image data signal V ｄａｔａ＿ｍｉｎ ~V ｄａｔａ＿ｍａｘ and V input to the pixel PX via the circuit CD. ｉｎｉｔ + K × (Vｄａｔａ＿ｍｉｎ -V ｒｅｆ ) to V ｉｎｉｔ + K × (V ｄａｔａ＿ｍａｘ -V ｒｅｆ ) is as shown in Figure 19A. ｒｅｆ V ｉｎｉｔ When the image data signal V ｄａｔａ＿ｍｉｎ ~V ｄａｔａ＿ｍａｘ and V input to the pixel PX via the circuit CD. ｉｎｉｔ + K × (V ｄａｔａ＿ｍｉｎ -V ｒｅｆ ) to V ｉｎｉｔ + K × (V ｄａｔａ＿ｍａｘ -V ｒｅｆ ) is as shown in Figure 19B. ｒｅｆ V ｉｎｉｔ When this is the case, the image data signal V output from the drive circuit SD ｄａｔａ＿ｍｉｎ ~V ｄａｔａ＿ｍａｘ and V input to the pixel PX via the circuit CD. ｉｎｉｔ + K × (V ｄａｔａ＿ｍｉｎ -V ｒｅｆ ) to V ｉｎｉｔ + K × (V ｄａｔａ＿ｍａｘ -V ｒｅｆ ) is as shown in FIG. 19C.

[0345] 4A to 4C , the image data signal output from the drive circuit SD is input to the pixel PX via the circuit CD, thereby narrowing the potential range of the image data signal and reducing the potential increment of the image data signal, thereby enabling the potential of the image data signal input to the pixel PX to be changed finely, and therefore enabling the amount of current flowing between the source and drain of the transistor M2 to be changed finely.

[0346] In the period T29 of the timing chart in Figure 18A, a high-level potential is input to the wiring GL4 and a low-level potential is input to the wiring GL6 at the same timing, but within the period T29, the timing at which the potentials are input to the wiring GL4 and the wiring GL6 may be different from each other.

[0347] [Period T30] During the period T30, a low-level potential is applied to the wiring GL4 and the wiring SWL12, and a high-level potential is applied to the wiring GL6. Therefore, a low-level potential is applied to the control terminals of the switches SW4 and SW12, so that the switches SW4 and SW12 are turned off. Furthermore, a high-level potential is applied to the control terminal of the switch SW6, so that the switch SW6 is turned on.

[0348] Since the switch SW4 is in the OFF state, there is no conduction between the second terminal of the transistor M2 and the light emitting device LD. Also, since the switch SW6 is in the ON state, there is conduction between the first terminal of the transistor M2, the second terminal of the capacitor C1, the first terminal of the capacitor C3, and the anode of the light emitting device LD and the wiring VE1. Therefore, the first terminal of the transistor M2, the second terminal of the capacitor C1, and the anode (node ​​N2) of the light emitting device LD are supplied with the potential V from the wiring VE1. Ｎ１ is given (see Figures 18B and 18C).

[0349] At this time, the voltage between the anode and cathode of the light emitting device LD is V Ｎ１ -V ＣＴ As described above, when the voltage between the anode and cathode of the light-emitting device LD is V Ｎ１ -V ＣＴ When the voltage Vcc is 0, the light emitting device LD does not emit light (no current flows between the anode and cathode of the light emitting device LD).

[0350] That is, by performing the operation in the period T30, it is possible to stop the light emission of the light emitting device LD.

[0351] By performing the operations in the periods T21 to T30 described above, the transistor M2 of the pixel PX is turned on at a threshold voltage V ｔｈ A current independent of the voltage Vcc can be generated and supplied to the light emitting device LD.

[0352] Furthermore, by performing the operations from the period T21 to the period T30 described above, the amount of current flowing through the light emitting device LD of the pixel PX of the display device DSP2A can be controlled more precisely, as in the display device DSP1A of the first embodiment.

[0353] 18A to 18C, the operation of one pixel PX included in the pixel array ALP of the display device DSP2A has been described. Here, the operation of the entire pixel array ALP in the display device DSP0 to which the display device DSP2A is applied will be described.

[0354] The overall operation of the pixel array ALP in the display device DSP0 to which the display device DSP2A is applied can be the same as the overall operation of the pixel array ALP in the display device DSP0 to which the display device DSP1A is applied, as described in embodiment 1. That is, the timing chart of Fig. 5 can be applied as an example of the overall operation of the pixel array ALP in the display device DSP0 to which the display device DSP2A is applied. Hereinafter, with regard to this operation, only the parts that differ from the overall operation of the pixel array ALP in the display device DSP0 to which the display device DSP1A, as described in embodiment 1, will be described, and for the other parts, refer to the description of embodiment 1.

[0355] The node N3[1] corresponds to the node N3 included in the circuit CD[1] in the display device DSP0. Similarly, the node N3[2] corresponds to the node N3 included in the circuit CD[2] (not shown in FIG. 1) in the display device DSP0, and the node N3[n] corresponds to the node N3 included in the circuit CD[n] in the display device DSP0.

[0356] 17, which is extended to the first row in the pixel array ALP of the display device DSP0. Similarly, the wiring GL1[2] corresponds to the wiring GL1 in FIG. 17, which is extended to the second row in the pixel array ALP of the display device DSP0, and the wiring GL1[m] corresponds to the wiring GL1 in FIG. 17, which is extended to the mth row in the pixel array ALP of the display device DSP0.

[0357] 17, which is extended to the first row in the pixel array ALP of the display device DSP0. Similarly, the wiring GL6[2] corresponds to the wiring GL6 in FIG. 17, which is extended to the second row in the pixel array ALP of the display device DSP0, and the wiring GL1[m] corresponds to the wiring GL6 in FIG. 17, which is extended to the mth row in the pixel array ALP of the display device DSP0.

[0358] 17 that is possessed by pixel PX[1,1] included in the pixel array ALP of the display device DSP0. Similarly, capacitance C1[1,2] corresponds to capacitance C1 in FIG. 17 that is possessed by pixel PX[1,2] (not shown in FIG. 1) included in the pixel array ALP of the display device DSP0, and capacitance C1[1,n] corresponds to capacitance C1 in FIG. 17 that is possessed by pixel PX[1,n] included in the pixel array ALP of the display device DSP0. Hereinafter, the notation capacitance C1[i,j] will be treated as equivalent to capacitance C1 in FIG. 17 that is possessed by pixel PX[i,j] included in the pixel array ALP of the display device DSP0.

[0359] It should be noted that, during periods U1, U3, and U6 in the timing chart of Fig. 5, the operations of periods T21 to T26 in the timing chart of Fig. 18A are performed on a plurality of pixels PX located on a predetermined row, respectively. Also, during periods U2, U4, and U7 in the timing chart of Fig. 5, the operations of periods T27 to T30 in the timing chart of Fig. 18A are performed on a plurality of pixels PX located on a predetermined row, respectively.

[0360] As described above, by performing the operations in the periods U1 to U7, the display device DSP0 to which the display device DSP2A is applied can display an image. Furthermore, each time the operations in the periods U1 to U7 are repeated, the image displayed on the display device DSP0 can be updated.

[0361] <<Layout Example of Display Device>> Fig. 20 is a layout diagram (plan view) showing an example of the circuit configuration of a part of the display device DSP2A of Fig. 17. Specifically, Fig. 20 shows a layout diagram of a pixel PX. Note that the layout diagram of Fig. 6A is used as an example for the layout diagram of the circuit CD of the display device DSP2A.

[0362] In the layout diagram of FIG. 20, a transistor M1 is applied to the switch SW1 included in the pixel PX of FIG. 17, a transistor M4 is applied to the switch SW4 included in the pixel PX of FIG. 17, a transistor M6 is applied to the switch SW6 included in the pixel PX of FIG. 17, a transistor M7 is applied to the switch SW7 included in the pixel PX of FIG. 17, and a transistor M8 is applied to the switch SW8.

[0363] 20, the pixel PX has a conductor BGM, a conductor GEM, a conductor SDMB, a conductor SDMT, a semiconductor SMC, and a conductor PLG. Note that insulators included in the display device DSP2A are not shown in FIG.

[0364] As an example, the conductor BGM is located below the semiconductor SMC. Also, as an example, the semiconductor SMC is located below the conductor GEM. Also, as an example, the conductor GEM is located below the conductor SDMB. Also, as an example, the conductor SDMB is located below the conductor SDMT. In other words, in FIG. 20 , the circuit CD and the pixel PX are formed in the order of the conductor BGM, semiconductor SMC, conductor GEM, conductor SDMB, and conductor SDMT.

[0365] For example, a portion of the conductor GEM functions as the gates (sometimes referred to as first gates) of the transistors M1, M2, M4, M6, M7, and M8. Also, for example, a portion of the conductor BGM functions as the back gate (sometimes referred to as second gate) of the transistor M2.

[0366] The conductor BGM, semiconductor SMC, conductor GEM, conductor SDMB, and conductor SDMT can each be formed using, for example, a photolithography method. Specifically, for example, when forming the conductor GEM, a conductive material to become the conductor GEM can be formed using one or more methods selected from a sputtering method, a CVD method, a PLD method, and an ALD method, and then a desired pattern can be formed using a photolithography method. The conductor BGM, semiconductor SMC, conductor SDMB, and conductor SDMT can also be formed using the same method as above.

[0367] Insulators may be provided between the conductor BGM and the semiconductor SMC, between the semiconductor SMC and the conductor GEM, between the conductor GEM and the conductor SDMB, and between the conductor SDMB and the conductor SDMT. In particular, the insulator provided between the semiconductor SMC and the conductor GEM may function as a first gate insulating film (sometimes referred to as a front gate insulating film). In addition, the insulator provided between the conductor BGM and the semiconductor SMC may function as a second gate insulating film (sometimes referred to as a back gate insulating film).

[0368] Furthermore, conductors PLG functioning as wiring or plugs are provided between the conductor BGM and the conductor SDMT, between the semiconductor SMC and the conductor SDMB, between the semiconductor SMC and the conductor SDMT, and between the conductor GEM and the conductor SDMT. The conductor PLG is formed, for example, by forming openings in the insulator and filling the openings with a conductive material that will become the conductor PLG. After the conductor PLG is formed, it may be planarized by a planarization process using a chemical mechanical polishing method or the like to align the film surfaces of the conductor PLG and the surrounding insulator.

[0369] 20, the transistors M1, M2, M4, M6, M7, and M8 each include, for example, a portion of the semiconductor SMC, a portion of the conductor GEM, an insulator, and a portion of the conductor PLG. Furthermore, the transistor M2 includes, for example, a portion of the conductor BGM.

[0370] 20, the capacitors C1 and C3 each include a portion of the conductor SDMB and a portion of the conductor SDMT. Specifically, the capacitors C1 and C3 each include a region where the conductor SDMB and the conductor SDMT overlap. That is, in each of the capacitors C1 and C3, a portion of the conductor SDMB functions as one of a pair of electrodes, and a portion of the conductor SDMT functions as the other of the pair of electrodes. It is preferable that an insulator with a high dielectric constant be provided between the conductor SDMB and the conductor SDMT included in the capacitors C1 and C3.

[0371] 20 is formed on the conductor SDMT, as an example, and functions as a wiring or a plug for electrically connecting to the anode of the light-emitting device LD (not shown in FIG. 20) located above the conductor SDMT.

[0372] <<Modification 1 of Display Device>> Note that the pixel of the display device according to one embodiment of the present invention described above is not limited to the pixel PX shown in Fig. 17. The pixel of the display device according to one embodiment of the present invention may have the configuration of the pixel PX shown in Fig. 17 that has been appropriately modified.

[0373] Fig. 21 shows a modified example of the pixel PX in Fig. 17. The pixel PX of the display device DSP2AA shown in Fig. 21 differs from the pixel PX of the display device DSP2A in Fig. 17 in that the anode of the light-emitting device LD is electrically connected to a first terminal of a switch SW6, a second terminal of a switch SW8, a first terminal of a transistor M2, a second terminal of a capacitor C1, and a first terminal of a capacitor C3, the cathode of the light-emitting device LD is electrically connected to a first terminal of a switch SW4, and the second terminal of the switch SW4 is electrically connected to a wiring VE0. In other words, the pixel PX of the display device DSP2AA shown in Fig. 21 has a configuration in which the positions of the switch SW4 and the light-emitting device LD of the pixel PX in Fig. 17 are swapped.

[0374] For the operation method of the display device DSP2AA in Fig. 21, refer to the same operation method as that of the display device DSP2A in Fig. 17 described above. The display device DSP2AA can obtain the same effect as that of the display device DSP2A by performing the same operation method as that of the display device DSP2A in Fig. 17.

[0375] 22 shows a modified example of the pixel PX of Fig. 17 which is different from the pixel PX of Fig. 21. The pixel PX of the display device DSP2B shown in Fig. 22 differs from the pixel PX of the display device DSP2A of Fig. 17 in that the pixel PX is not provided with the switch SW8.

[0376] 22 is partially different from the operation method of the display device DSP2A. The differences in operation method from the display device DSP2A will be described below.

[0377] The switch SW1 of the display device DSP2B is turned on during period T21 in Fig. 18A and turned off during period T23. The switch SW13 of the display device DSP2B is turned on during period T21 in Fig. 18A and turned off during period T24. The switch SW13 of the display device DSP2B may be kept on until period T25.

[0378] When the display device DSP2B is operated, the potential V ｉｎｉｔ is the potential V given by the wiring VE1 Ｎ１ The potential is equal to

[0379] The operation after the period T25 may be substantially the same as that of the display device DSP2A in FIG. 18A.

[0380] As described above, by operating the display device DSP2B, the display device DSP2B ｉｎｉｔ and V Ｎ１ The same effect as that of the display device DSP2A when the values ​​are equal can be obtained.

[0381] <<Modification Example 2 of Display Device>> The circuit CD of the display device according to one embodiment of the present invention described above is not limited to the circuit CD shown in Fig. 17. The circuit CD of the display device according to one embodiment of the present invention may have the configuration of the circuit CD shown in Fig. 17, which is modified as appropriate.

[0382] For example, in the display device DSP2A of FIG. 17, the potential V ｒｅｆ and the potential V applied to the wiring VE4 ｉｎｉｔ When and are equal, the circuit CD of the display device DSP2A of FIG. 17 may be changed to the configuration of the circuit CD shown in FIG. 23A.

[0383] 23A differs from the display device DSP2A shown in Fig. 17 in that the second terminal of the switch SW11 is electrically connected to the wiring VE4 instead of the wiring VE3. Although not shown, the display device DSP2A may be configured such that the second terminal of the switch SW11 and the second terminal of the switch SW13 are electrically connected to the wiring VE3.

[0384] Furthermore, the display device DSP2A to which the circuit CD of FIG. 23A is applied can operate in the same manner as the operation of the timing chart of FIG. 18A.

[0385] 23A may be changed to a circuit CD shown in Fig. 23B, which differs from the circuit CD shown in Fig. 23A in that the second terminal of the switch SW11 is electrically connected to the first terminal of the switch SW13, the first terminal of the capacitor C2, and the line SL, rather than to the line VE4.

[0386] Note that, as for the operation of the circuit CD in FIG. 23B, for example, during the period in which the threshold voltage of the transistor M2 is corrected (the period from T21 to T26 in the timing chart in FIG. 18A), the switches SW11 and SW13 are turned on, and the potentials of the node N3 and the wiring SL are set to V ｉｎｉｔ (=V ｒｅｆ ), and then, before the image data signal is input from the driver circuit SD to the circuit CD (after the period T27 in the timing chart of FIG. 18A), the switches SW11 and SW13 are turned off.

[0387] 23A , a new capacitor may be added. Specifically, as shown in the circuit CD of FIG. 23C , the circuit CD may include a capacitor C4, and a first terminal of the capacitor C4 may be electrically connected to a first terminal of the switch SW13, a first terminal of the capacitor C2, and a wiring SL. A second terminal of the capacitor C4 is electrically connected to a wiring VE6.

[0388] For example, the wiring VE6 functions as a wiring that applies a constant potential. Note that the constant potential applied by the wiring VE6 may be equal to or different from the constant potential applied by any of the wirings VE0 to VE5.

[0389] 23C, by adding the capacitor C4 to the circuit CD, the amount of change in the potential of the wiring SL and the node due to the change in the potential of the node N3 in the period T27 of the timing chart in FIG. ４ When the potential change of the node N3 is set as follows, the amount of change in the potential of the wiring SL and the node due to the potential change of the node N3 is ２ / (C １ +C ２ +C ４ ) is the value multiplied by

[0390] 23C, the capacitor C4 is provided inside the circuit CD, but the capacitor C4 may be provided outside the circuit CD. Specifically, for example, as in a display device DSP2C shown in FIG. 24, the wiring SL and the first terminal of the capacitor C4 may be electrically connected, and the wiring VE6 and the second terminal of the capacitor C4 may be electrically connected.

[0391] 24, in all circuits CD described in this specification, the drawings, etc., some of the capacitors and the switches included in the circuit CD may be provided outside the circuit CD. In other words, one embodiment of the present invention is not limited to the configuration of the circuit CD shown in this specification, the drawings, etc. For example, some of the circuit elements included in the circuit CD shown in this specification, the drawings, etc. may be provided outside the circuit CD.

[0392] Furthermore, for example, the circuit CD of the display device DSP2A in Fig. 17 may be changed to the circuit CD in Fig. 23D. The circuit CD in Fig. 23D differs from the circuit CD in Fig. 23A in that it includes an inverter circuit INV and that the control terminal of the switch SW12 is electrically connected to the wiring SWL11 instead of the wiring SWL12.

[0393] By applying the circuit CD shown in FIG. 23D to the display device DSP2A in FIG. 17, it becomes unnecessary to provide the wiring SWL12, and therefore the circuit area of ​​the display device DSP2A can be reduced.

[0394] Furthermore, although not shown, when a switch SW12 is applied that is turned off when a high-level potential is input to the control terminal and turned on when a low-level potential is input to the control terminal, the control terminal of the switch SW12 may be electrically connected to the wiring SWL11 without going through the inverter circuit INV.

[0395] <<Modification Example 3 of Display Device>> Next, an example of the display device DSP0 of Fig. 1, which is different from the display devices DSP2A to DSP2C, is shown in Fig. 25. The display device DSP2D shown in Fig. 25 is a modification of the display device DSP2A of Fig. 17, and differs from the display device DSP2A in that a capacitance C2I and a switch SW13I are provided in the pixel PX, and that a capacitance C2 and a switch SW13 are not provided in the circuit CD.

[0396] Therefore, in the description of the display device DSP2D, for parts that are common to the contents of the display device DSP2A, reference will be made to the description of the display device DSP2A.

[0397] The switch SW13I can be, for example, a switch that can be applied to the switch SW13. The switch SW13I is turned on when a high-level potential is applied to its control terminal, and is turned off when a low-level potential is applied to its control terminal.

[0398] In the display device DSP2D, a first terminal of the capacitor C2I is electrically connected to a second terminal of the switch SW1. A second terminal of the capacitor C2I is electrically connected to a wiring SL. A first terminal of the switch SW13I is electrically connected to a first terminal of the switch SW1, a first terminal of the switch SW8, a first terminal of the capacitor C1, and a gate of the transistor M2. A second terminal of the switch SW13I is electrically connected to a wiring VE4, and a control terminal of the switch SW13I is electrically connected to a wiring GL13.

[0399] A first terminal of the switch SW11 is electrically connected to the line SL and a first terminal of the switch SW12.

[0400] In the display device DSP2D, the electrical connection point between the first terminal of the switch SW11, the first terminal of the switch SW12, and the capacitance C2I is referred to as a node N3. In the case of the display device DSP2D of this configuration example, the node N3 may be replaced with the line SL in some cases.

[0401] The wiring GL13, together with the wiring GL1, the wiring GL4, the wiring GL6, and the wiring GL7, corresponds to one of the wirings GL[1] to GL[m] in Fig. 1. That is, in the circuit configuration of the pixel PX shown in Fig. 25, the number of wirings GL extending in one row of the pixel array ALP is five.

[0402] In the display device DSP2D, the capacitance C2I corresponds to the capacitance C2 of the display device DSP2A. Furthermore, in the display device DSP2D, the switch SW13I corresponds to the switch SW13 of the display device DSP2A. Furthermore, in the display device DSP2D, the wiring GL13 corresponds to the wiring SWL13 of the display device DSP2A. That is, the display device DSP2D is configured such that the switch SW13 and the capacitance C2 included in the circuit CD of the display device DSP2A are provided in the pixel PX as the switch SW13I and the capacitance C2I, respectively. Therefore, the operation method of the display device DSP2D can sometimes be explained by replacing the capacitance C2 with the capacitance C2I, the switch SW13 with the switch SW13I, and the wiring SWL13 with the wiring GL13 in the operation method of the display device DSP2A.

[0403] The display device DSP2D can correct the threshold voltage of the transistor M2 of the pixel PX and display an image on the pixel PX by performing the same operation method as the display device DSP1A.

[0404] Note that the display device according to one embodiment of the present invention is not limited to the configuration of the display device DSP2D, and may have the configuration of the display device DSP2D that has been appropriately modified.

[0405] Fig. 26 shows a modification of the display device DSP2D of Fig. 25. The display device DSP2DA shown in Fig. 26 differs from the display device DSP2D of Fig. 25 in that the first terminal of the switch SW13I is electrically connected to the second terminal of the switch SW1 and the first terminal of the capacitor C2I, rather than to the first terminal of the switch SW1, the first terminal of the switch SW8, the first terminal of the capacitor C1, and the gate of the transistor M2.

[0406] As shown in the display device DSP2DA of Figure 26, even if the configuration of the display device DSP2D is changed, the display device DSP2DA can correct the threshold voltage of the transistor M2 of the pixel PX and display an image in the pixel PX by performing the same operating method as the display device DSP1A.

[0407] Fig. 27 shows a modified example of the display device DSP2D of Fig. 25, which differs from the display device DSP2DA of Fig. 26. The display device DSP2E shown in Fig. 27 differs from the display device DSP2D of Fig. 25 in that the second terminal of the switch SW1 is electrically connected to the line SL rather than the first terminal of the capacitor C2I, the first terminal of the switch SW1 is electrically connected to the second terminal of the capacitor C2I rather than to the gate of the transistor M2, the first terminal of the switch SW13I, the first terminal of the switch SW8, and the first terminal of the capacitor C1, and the first terminal of the capacitor C2I is electrically connected to the gate of the transistor M2, the first terminal of the switch SW13I, the first terminal of the switch SW8, and the first terminal of the capacitor C1.

[0408] In other words, the display device DSP2D is configured such that the electrical path from the wiring SL to the wiring VE0 is provided in order with a capacitance C2I, a switch SW1, a capacitance C1 (or a switch SW8), a switch SW4, and a light-emitting device LD, and the display device DSP2E is configured such that the electrical path from the wiring SL to the wiring VE0 is provided in order with a switch SW1, a capacitance C2I, a capacitance C1 (or a switch SW8), a switch SW4, and a light-emitting device LD.

[0409] In this specification and the like, the electrical connection point between the first terminal of the switch SW1 and the second terminal of the capacitor C2I is referred to as a node N4.

[0410] Furthermore, in the display device DSP2E, the capacitance C2I corresponds to the capacitance C2 of the display device DSP2A. Furthermore, in the display device DSP2E, the switch SW13I corresponds to the switch SW13 of the display device DSP2A. Furthermore, in the display device DSP2E, the wiring GL13 corresponds to the wiring SWL13. Furthermore, in the display device DSP2E, the node N4 corresponds to the node N3 of the display device DSP2A. That is, the display device DSP2E is configured such that the switch SW13 and the capacitance C2 included in the circuit CD of the display device DSP2A are provided in the pixel PX as the switch SW13I and the capacitance C2I, respectively. Therefore, the operation method of the display device DSP2E can sometimes be explained by replacing the capacitance C2 with the capacitance C2I, the switch SW13 with the switch SW13I, the wiring SWL13 with the wiring GL13, and the node N3 with the node N4 in the operation method of the display device DSP2A.

[0411] The display device DSP2E also performs the same operation method as the display device DSP1A, thereby correcting the threshold voltage of the transistor M2 of the pixel PX and displaying an image on the pixel PX.

[0412] 28 shows another modified example of the display device DSP2D, which is different from the display device DSP2DA of FIG. 26 and the display device DSP2E of FIG. 27. The display device DSP2F shown in FIG. 28 is a further modified example of the display device DSP2E of FIG. 27, and differs from the display device DSP2E in that a switch SW11I is provided in the pixel PX and that a switch SW11 is not provided in the circuit CD. In other words, the display device DSP2F shown in FIG. 28 differs from the display device DSP2A in that a switch SW11I, a switch SW13I, and a capacitor C2I are provided in the pixel PX and that a switch SW11, a switch SW13, and a capacitor C2 are not provided in the circuit CD.

[0413] In the display device DSP2F, a first terminal of a switch SW11I is electrically connected to a first terminal of a switch SW1 and a second terminal of a capacitor C2I. A second terminal of the switch SW11I is electrically connected to a wiring VE3. A control terminal of the switch SW11I is electrically connected to a wiring GL11.

[0414] A first terminal of the capacitor C2I is electrically connected to a first terminal of the switch SW8, a first terminal of the switch SW13I, a first terminal of the capacitor C1, and the gate of the transistor M2. A second terminal of the switch SW1 is electrically connected to the wiring SL.

[0415] A first terminal of the switch SW12 is electrically connected to the line SL.

[0416] The wiring GL11, together with the wiring GL1, the wiring GL4, the wiring GL6, the wiring GL7, and the wiring GL13, corresponds to one of the wirings GL[1] to GL[m] in Fig. 1. That is, in the circuit configuration of the pixel PX shown in Fig. 28, the number of wirings GL extending in one row of the pixel array ALP is six.

[0417] In the display device DSP2F, the capacitance C2I corresponds to the capacitance C2 of the display device DSP2A. The switch SW11I corresponds to the switch SW11 of the display device DSP2A. The wiring GL11 corresponds to the wiring SWL11 of the display device DSP2A. The switch SW13I corresponds to the switch SW13 of the display device DSP2A. The wiring GL13 corresponds to the wiring SWL13 of the display device DSP2A. The node N4 corresponds to the node N3 of the display device DSP2A. In other words, the display device DSP2F is configured such that the switch SW11, the switch SW13, and the capacitance C2, which are included in the circuit CD in the display device DSP2A, are provided in the pixel PX as the switch SW11I, the switch SW13I, and the capacitance C2I, respectively. Therefore, the operating method of the display device DSP2F can sometimes be explained by replacing switch SW11 with switch SW11I, switch SW13 with switch SW13I, capacitance C2 with capacitance C2I, node N3 with node N4, wiring SWL11 with wiring GL11, and wiring SWL13 with wiring GL13 in the operating method of the display device DSP2A.

[0418] The display device DSP2F can correct the threshold voltage of the transistor M2 of the pixel PX and display an image on the pixel PX by performing the same operation method as the display device DSP2A.

[0419] As described in the operation method of the display device DSP2A, the potentials applied to two or more wirings selected from the wirings VE1 to VE5 can be made equal to each other. In this case, the selected wirings may be combined into one wiring.

[0420] 29 shows another modified example of the display device DSP2A, which is different from the display device DSP2B of FIG. 22, the display device DSP2C of FIG. 24, the display device DSP2D of FIG. 25, the display device DSP2DA of FIG. 26, the display device DSP2E of FIG. 27, and the display device DSP2F of FIG. 28. The display device DSP2G shown in FIG. 29 is a further modified example of the display device DSP2F of FIG. 28, and differs from the display device DSP2F in that the circuit CD does not include a switch SW12. In other words, the display device DSP2G shown in FIG. 29 differs from the display device DSP2A in that the pixel PX includes a switch SW11I, a switch SW12I, a switch SW13I, and a capacitor C2I, and in that the circuit CD is not included.

[0421] For convenience, in the display device DSP2G, the switch SW1 of the display device DSP1F is written as a switch SW12I, and the line GL1 of the display device DSP1F is written as a line GL12.

[0422] In the display device DSP2G, the driver circuit SD is electrically connected to the wiring SL, and the wiring SL is electrically connected to the second terminal of the switch SW12I.

[0423] The switch SW12I provided in the display device DSP2G can also serve as the switch SW1 provided in the pixel PX in the display device DSP2D. Therefore, the display device DSP2D can be modified to have a configuration in which the switch SW12 is not provided in the circuit CD, as in the display device DSP2G in FIG.

[0424] The operation method of the display device DSP2G can sometimes be explained by replacing the switch SW11 with a switch SW11I, the switch SW13 with a switch SW13I, the capacitance C2 with a capacitance C2I, the node N3 with a node N4, the wiring SWL11 with a wiring GL11, the wiring SWL12 with a wiring GL12, and the wiring SWL13 with a wiring GL13 in the operation method of the display device DSP2A. Note that the signal provided by the wiring GL1 of the display device DSP2A does not need to be considered in the display device DSP2G.

[0425] <<Modification Example 4 of Display Device>> Next, an example of the display device DSP0 in Fig. 1, which is different from the display devices DSP2A to DSP2G, is shown in Fig. 30. The display device DSP2H shown in Fig. 30 is a modification of the display device DSP2A in Fig. 17, and differs from the display device DSP2A in that a switch SW9 is provided so as to be electrically connected in parallel to the light-emitting device LD.

[0426] The switch SW9 may be, for example, a switch that can be applied to the switches SW1, SW4, SW6, SW7, and SW8. The switch SW9 is turned on when a high-level potential is applied to its control terminal, and turned off when a low-level potential is applied to its control terminal.

[0427] A first terminal of the switch SW9 is electrically connected to the second terminal of the switch SW4 and the anode of the light emitting device LD. A second terminal of the switch SW9 is electrically connected to the cathode of the light emitting device LD and the wiring VE0. A control terminal of the switch SW9 is electrically connected to the wiring GL9.

[0428] In the display device DSP2H in Fig. 30, the wiring GL9, together with the wiring GL1, the wiring GL4, the wiring GL6, and the wiring GL7, corresponds to one of the wirings GL[1] to GL[m] in Fig. 1. That is, in the circuit configuration of the pixel PX shown in Fig. 30, the number of wirings GL extending in one row of the pixel array ALP is five.

[0429] Next, an example of the operation method of the display device DSP2H of FIG. 30 will be described.

[0430] 31 is a timing chart illustrating an example of an operation method of the display device DSP2H. Specifically, the timing chart of FIG. 31 is a modified example of the timing chart of FIG. 18A , and shows changes in the potential of the wiring GL9 in addition to the timing chart of FIG. 18A . Furthermore, changes in the potential of the wiring GL4 in the timing chart of FIG. 31 are different from changes in the potential of the wiring GL4 in the timing chart of FIG. 18A . Therefore, for operations of the display device DSP2H other than the changes in the potential of the wiring GL4 and the wiring GL9, refer to the description of the timing chart of FIG. 18A .

[0431] During the period T29, a high-level potential is applied to the wiring GL4, and a low-level potential is applied to the wiring GL9. As a result, a high-level potential is applied to the control terminal of the switch SW4, turning the switch SW4 on. Also, a low-level potential is applied to the control terminal of the switch SW9, turning the switch SW9 off.

[0432] That is, in the period T29, the wiring VE0 and the cathode of the light emitting device LD are not electrically connected to the anode of the light emitting device LD, and therefore the potential V ＣＴ On the other hand, in a period T29, the switch SW4 is in the on state, so that a current flows from the wiring VE2 to the anode of the light-emitting device LD, causing the light-emitting device LD to emit light.

[0433] In the periods T21 to T28 and T30, a low-level potential is applied to the wiring GL4, and a high-level potential is applied to the wiring GL9. As a result, a low-level potential is applied to the control terminal of the switch SW4, turning the switch SW4 off. Also, a high-level potential is applied to the control terminal of the switch SW9, turning the switch SW9 on.

[0434] That is, during periods T21 to T28 and period T30, conduction occurs between the wiring VE0, the cathode of the light-emitting device LD, and the anode of the light-emitting device LD, and therefore the anode-cathode voltage of the light-emitting device LD is 0 V. Furthermore, because the switch SW4 is in the off state, no current flows between the node N2 and the anode of the light-emitting device LD via the switch SW4.

[0435] In particular, periods T21 to T28 and period T30 are periods during which the light-emitting device LD does not emit light, but by turning on the switch SW9 during these periods, the charge accumulated in the anode of the light-emitting device LD can be discharged to the wiring VE0 via the switch SW9. In other words, during the periods during which the light-emitting device LD does not emit light, the display device DSP1F can discharge the charge accumulated in the anode of the light-emitting device LD faster than display devices that do not have the switch SW9 (e.g., display devices DSP2A to DSP2G). This allows the light-emitting state of the light-emitting device LD to transition to the extinction state more quickly.

[0436] Note that a high-level potential is applied to the wiring GL4 in period T21 of the timing chart of Fig. 18A, but a low-level potential is applied to the wiring GL4 in period T21 of the timing chart of Fig. 31. These timing charts differ in operation in that a potential from the wiring VE1 is applied to the anode of the light-emitting device LD to prevent the light-emitting device LD from emitting light in period T21 of the timing chart of Fig. 18A, and a potential from the wiring VE0 is applied to the anode of the light-emitting device LD to prevent the light-emitting device LD from emitting light in period T21 of the timing chart of Fig. 31.

[0437] As described above, the display device DSP2A in Fig. 17 and the display device DSP2B in Fig. 22 convert the potential of the image data signal using the capacitance C1 in the pixel PX and the capacitance C2 outside the pixel PX. For example, when a voltage for correcting the threshold voltage of the transistor M2 is written to the capacitance C1, the potential of the node N1 changes due to the potential change of the node N2. １ / (C１ +C ２ ) is added, which may result in a deviation in the voltage written to the capacitor C1 for correcting the threshold voltage of the transistor M2 (if the change in potential of the node N2 is the same as the change in potential of the node N1, the voltage written to the capacitor C1 for correcting the threshold voltage of the transistor M2 will not deviate). On the other hand, as shown in the display device DSP2A of FIG. 17 and the display device DSP2B of FIG. 22, by using a configuration in which a voltage for correcting the threshold voltage of the transistor M2 is written to the capacitor C3, the amount of change in the potential of the node N1 due to a change in the potential of the node N2 can be made approximately equal to the amount of change in the potential of the node N2, thereby suppressing deviation in the voltage written to the capacitor C3 for correcting the threshold voltage of the transistor M2.

[0438] This embodiment describes a configuration example of a display device DSP2A that has different configurations from the pixel PX and the circuit CD described in Embodiment 1. As described above, in the display device of one embodiment of the present invention, the configurations of the pixel PX and the circuit CD may be changed as appropriate.

[0439] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0440] (Embodiment 3) In this embodiment, an example of the configuration of the display device described in the above embodiment will be described. Fig. 32A is a schematic cross-sectional view of an example of the display device described in the above embodiment. The display device DSP has, as an example, a pixel layer PXAL, a wiring layer LINL, and a circuit layer SICL.

[0441] The wiring layer LINL is provided on the circuit layer SICL, and the pixel layer PXAL is provided on the wiring layer LINL. The pixel layer PXAL overlaps a region including a drive circuit region DRV, which will be described later.

[0442] The circuit layer SICL has a substrate BS and a drive circuit region DRV.

[0443] The substrate BS can be, for example, a single-crystal substrate (e.g., a semiconductor substrate made of silicon or germanium). In addition to single-crystal substrates, the substrate BS can be, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) are examples. Alternatively, synthetic resins such as acrylic resins are also examples. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device DSP includes a heat treatment, it is preferable to select a substrate with high heat resistance for the substrate BS.

[0444] In this embodiment, the substrate BS is described as a semiconductor substrate made of silicon, and therefore, the transistors included in the driver circuit region DRV can be transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors).

[0445] The drive circuit region DRV is provided on the substrate BS.

[0446] The drive circuit region DRV has, as an example, a drive circuit for driving pixels included in a pixel layer PXAL, which will be described later. Note that a specific configuration example of the drive circuit region DRV will be described later.

[0447] The wiring layer LINL is provided on the circuit layer SICL.

[0448] The wiring layer LINL is provided with wiring, for example. The wiring included in the wiring layer LINL functions as wiring that electrically connects, for example, a drive circuit included in a drive circuit region DRV provided below and a circuit included in a pixel layer PXAL provided above.

[0449] The pixel layer PXAL has, for example, a plurality of pixels (for example, pixels PX[1,1] to PX[m,n] in FIG. 1).

[0450] 33A is an example of a plan view of the display device DSP, showing only the display unit DIS. Note that the display unit DIS can be a plan view of the pixel layer PXAL.

[0451] 33A, the display unit DIS is divided into areas of p rows and q columns (p is an integer greater than or equal to 1, and q is an integer greater than or equal to 1), for example. Therefore, the display unit DIS has display areas ARA[1,1] to ARA[p,q]. In addition, in Figure 33A, as an example, display area ARA[1,1], display area ARA[2,1], display area ARA[p-1,1], display area ARA[p,1], display area ARA[1,2], display area ARA[2,2], display area ARA[p-1,2], display area ARA[p,2], display area ARA[1,q-1], display area ARA[2,q-1], display area ARA[p-1,q-1], display area ARA[p,q-1], display area ARA[1,q], display area ARA[2,q], display area ARA[p-1,q], and display area ARA[p,q] are each shown in excerpt form.

[0452] For example, if it is desired to divide the display unit DIS into 32 regions, p = 4 and q = 8, and the configuration shown in FIG. 33A can be applied. Incidentally, if the resolution of the display device DSP is 8K4K, the number of display pixels is 7680 x 4320 pixels. Furthermore, if the sub-pixels of the display unit DIS are of three colors, red (R), green (G), and blue (B), the total number of sub-pixels is 7680 x 4320 x 3. Here, if the pixel array of the display unit DIS with an 8K4K resolution is divided into 32 regions, the number of display pixels per region is 960 x 1080 pixels. Furthermore, if the sub-pixels of the display device DSP are of three colors, red (R), green (G), and blue (B), the number of sub-pixels per region is 960 x 1080 x 3.

[0453] Here, in the display device DSP of FIG. 33A, a drive circuit region DRV included in the circuit layer SICL in the case where the display unit DIS is divided into regions of p rows and q columns will be considered.

[0454] FIG. 33B is an example of a plan view of the display device DSP, showing only the drive circuit region DRV included in the circuit layer SICL.

[0455] 33A, the display unit DIS is divided into p rows and q columns, and therefore a corresponding drive circuit is required for each of the divided display areas ARA[1,1] to ARA[p,q]. Specifically, the drive circuit area DRV may also be divided into p rows and q columns, and a drive circuit may be provided in each divided area.

[0456] 33B shows a configuration in which the drive circuit region DRV is divided into regions with p rows and q columns, and therefore the drive circuit region DRV has circuit regions ARD[1,1] to ARD[p,q]. In addition, in Figure 33B, as an example, circuit area ARD[1,1], circuit area ARD[2,1], circuit area ARD[p-1,1], circuit area ARD[p,1], circuit area ARD[1,2], circuit area ARD[2,2], circuit area ARD[p-1,2], circuit area ARD[p,2], circuit area ARD[1,q-1], circuit area ARD[2,q-1], circuit area ARD[p-1,q-1], circuit area ARD[p,q-1], circuit area ARD[1,q], circuit area ARD[2,q], circuit area ARD[p-1,q], and circuit area ARD[p,q] are each shown in excerpt form.

[0457] Each of the circuit areas ARD[1,1] to ARD[p,q] has a column driver circuit CLM and a row driver circuit RWD. For example, the column driver circuit CLM and the row driver circuit RWD included in the circuit area ARD[h,k] (not shown in FIG. 33B ) located in the hth row and the kth column (h is an integer of 1 to p, and k is an integer of 1 to q) can drive a plurality of pixels included in the display area ARA[h,k] (not shown in FIG. 33A ) located in the hth row and the kth column of the display unit DIS.

[0458] The column driver circuit CLM includes, for example, a source driver circuit that transmits image signals to a plurality of pixels included in the corresponding display area ARA. Therefore, the display device DSP of FIG. 32A or FIG. 33A preferably has a configuration in which the column driver circuit CLM is electrically connected to the wirings SL[1] to SL[n], similar to the display device DSP0 of FIG. 1. The column driver circuit CLM may also include a digital-to-analog conversion circuit that converts digital image signals into analog data.

[0459] The row driver circuit RWD includes, for example, a gate driver circuit for selecting a plurality of display pixels to which an image signal is to be sent in the corresponding display area ARA. Therefore, the display device DSP in FIG. 32A or 33A is preferably configured such that the row driver circuit RWD is electrically connected to the wirings GL[1] to GL[m], similar to the display device DSP0 in FIG. 1.

[0460] 32A , 33A , and 33B have a configuration in which the display region ARA[h, k] and the circuit region ARD[h, k] of the display unit DIS overlap each other, but the display device of one embodiment of the present invention is not limited to this. In the configuration of the display device of one embodiment of the present invention, the display region ARA[h, k] and the circuit region ARD[h, k] do not necessarily overlap each other.

[0461] For example, as shown in FIG. 32B, the display device DSP may have a configuration in which not only the drive circuit region DRV but also the region LIA is provided on the substrate BS.

[0462] As an example, wiring is provided in the region LIA. The wiring included in the region LIA may be electrically connected to wiring included in the wiring layer LINL. In this case, the display device DSP may be configured so that the circuit included in the drive circuit region DRV and the circuit included in the pixel layer PXAL are electrically connected by the wiring included in the region LIA and the wiring included in the wiring layer LINL. The display device DSP may be configured so that the circuit included in the drive circuit region DRV and the wiring included in the region LIA or the circuit are electrically connected via the wiring included in the wiring layer LINL.

[0463] Furthermore, the region LIA may include, for example, a GPU (Graphics Processing Unit). Furthermore, if the display device DSP includes a touch panel, the region LIA may include a sensor controller that controls a touch sensor included in the touch panel. Furthermore, if a liquid crystal element is used as the display element of the display device DSP, the region LIA may include a gamma correction circuit. Furthermore, the region LIA may include a controller having the function of processing input signals from outside the display device DSP. Furthermore, the region LIA may include the above-mentioned circuits and a voltage generation circuit for generating voltages to be supplied to the drive circuits included in the circuit region ARD.

[0464] Furthermore, when a light-emitting device using an organic EL material is used as a display element of the display device DSP, the region LIA may include an EL correction circuit. The EL correction circuit, for example, has the function of appropriately adjusting the amount of current input to the light-emitting device containing the organic EL material. Since the luminance of a light-emitting device containing an organic EL material when emitting light is proportional to the amount of current, if the characteristics of the drive transistor electrically connected to the light-emitting device are poor, the luminance of the light emitted by the light-emitting device may be lower than the desired luminance. The EL correction circuit, for example, monitors the amount of current flowing through the light-emitting device, and when the amount of current is smaller than the desired amount, increases the amount of current flowing through the light-emitting device to increase the luminance of light emitted by the light-emitting device. Conversely, when the amount of current is larger than the desired amount, the EL correction circuit may decrease the amount of current flowing through the light-emitting device.

[0465] Fig. 34A is an example of a plan view of the display device DSP shown in Fig. 32B, showing the drive circuit region DRV indicated by a solid line and the display unit DIS indicated by a dotted line. The display device DSP in Fig. 34A also shows, as an example, a configuration in which the drive circuit region DRV is surrounded by a region LIA (an example of a plan view of the display device DSP showing only the circuit layer SICL is shown in Fig. 34B). Therefore, as shown in Fig. 34A, the drive circuit region DRV is arranged so as to overlap the inside of the display unit DIS in a plan view.

[0466] Furthermore, in the display device DSP shown in Figure 34A, similar to Figure 33A, the display unit DIS is divided into display areas ARA[1,1] to ARA[p,q], and the drive circuit area DRV is also divided into circuit areas ARD[1,1] to ARD[p,q].

[0467] 34A, as an example, the correspondence between the display area ARA and the circuit area ARD including the drive circuits that drive the pixels included in the display area ARA is illustrated by thick arrows. Specifically, the drive circuit included in the circuit area ARD[1,1] drives the pixels included in the display area ARA[1,1], and the drive circuit included in the circuit area ARD[2,1] drives the pixels included in the display area ARA[2,1]. Furthermore, the drive circuit included in the circuit area ARD[p-1,1] drives the pixels included in the display area ARA[p-1,1], and the drive circuit included in the circuit area ARD[p,1] drives the pixels included in the display area ARA[p,1]. Furthermore, the drive circuit included in the circuit area ARD[1,q] drives the pixels included in the display area ARA[1,q], and the drive circuit included in the circuit area ARD[2,q] drives the pixels included in the display area ARA[2,q]. Furthermore, the drive circuit included in the circuit area ARD[p-1,q] drives the pixels included in the display area ARA[p-1,q], and the drive circuit included in the circuit area ARD[p,q] drives the pixels included in the display area ARA[p,q]. In other words, although not shown in Figure 34A, the drive circuit included in the circuit area ARD[h,k] located in row h and column k drives the pixels included in the display area ARA[h,k].

[0468] 32B , the drive circuit included in the circuit region ARD in the circuit layer SICL and the pixels included in the display region ARA in the pixel layer PXAL are electrically connected by wiring included in the wiring layer LINL, so that the display region ARA[h, k] and the circuit region ARD[h, k] do not necessarily overlap each other in the configuration of the display device DSP. Therefore, the positional relationship between the drive circuit region DRV and the display unit DIS is not limited to the plan view of the display device DSP shown in FIG. 34A , and the arrangement of the drive circuit region DRV can be freely determined.

[0469] 32A and 32B has a configuration in which the wiring layer LINL is provided, but one embodiment of the present invention is not limited thereto. For example, the display device of one embodiment of the present invention may have a configuration in which the pixel layer PXAL is provided over the circuit layer SICL, as shown in FIG.

[0470] 33B and 34A , the arrangement of the column driver circuits CLM and the row driver circuits RWD in each of the circuit regions ARD[1,1] to ARD[p,q] is not limited to the configuration of the display device of one embodiment of the present invention. Although the column driver circuits CLM and the row driver circuits RWD are arranged to intersect with each other (to form a cross) in each of the circuit regions ARD, the column driver circuits CLM and the row driver circuits RWD may be arranged in various shapes within one circuit region ARD.

[0471] 33A to 34B, by dividing the display unit DIS into multiple display areas ARA and providing a corresponding driving circuit for each display area ARA, the circuits included in the multiple display areas ARA can be driven independently. For example, for a display area ARA where image data is frequently rewritten, the column driver circuit CLM and row driver circuit RWD provided in the corresponding circuit area ARD can be driven at a high frame frequency, and for a display area ARA where image data is not frequently rewritten, the column driver circuit CLM and row driver circuit RWD provided in the corresponding circuit area ARD can be driven at a low frame frequency. Specifically, the column driver circuit CLM and row driver circuit RWD corresponding to a display area ARA where image data, such as moving images, is frequently rewritten can be operated at a high frame frequency of 60 Hz or more, 120 Hz or more, 165 Hz or more, or 240 Hz or more. Furthermore, the column driver circuit CLM and row driver circuit RWD corresponding to the display area ARA where image data, such as still images, is not frequently rewritten may operate at a low frame frequency of 5 Hz or less, 1 Hz or less, 0.5 Hz or less, or 0.1 Hz or less. By dividing the display unit DIS of the display device DSP into display areas ARA[1,1] to ARA[p,q] in this way, the rewriting frequency (frame frequency) can be changed according to the image displayed in the display area ARA. In other words, the display device DSP can display images at different frame frequencies in at least two of the display areas ARA[1,1] to ARA[p,q] in the display unit DIS.

[0472] Next, an example of each component included in the display device DSP will be described. Fig. 35A is a block diagram showing an example of the display device DSP of Fig. 32A or Fig. 32B. The display device DSP shown in Fig. 35A has a display unit DIS and a peripheral circuit PRPH.

[0473] The peripheral circuit PRPH includes a circuit GDS including a plurality of row driver circuits RWD, a circuit SDS including a plurality of column driver circuits CLM, a distribution circuit DMG, a distribution circuit DMS, a control unit CTR, a memory device MD, a voltage generation circuit PG, a timing controller TMC, a clock signal generation circuit CKS, an image processing unit GPS, and an interface INT. Note that the peripheral circuit PRPH can be, for example, a circuit included in the circuit layer SICL in Figures 32A and 32B.

[0474] In the display device DSP, the drive circuit region DRV including each of the plurality of row driver circuits RWD overlaps with the pixel layer PXAL including the plurality of display regions ARA as shown in Figures 32A to 34A, but for convenience in Figure 35A, the plurality of row driver circuits RWD are illustrated as being lined up in a row outside the display unit DIS. Similarly, the drive circuit region DRV including each of the plurality of column driver circuits CLM overlaps with the pixel layer PXAL including the plurality of display regions ARA, but for convenience in Figure 35A, the plurality of column driver circuits CLM are illustrated as being lined up in a row outside the display unit DIS.

[0475] The peripheral circuit PRPH is included in, for example, the circuit layer SICL shown in Figures 32A and 32B. The circuit GDS and the circuit SDS included in the peripheral circuit PRPH are included in, for example, the drive circuit region DRV shown in Figures 32A and 32B.

[0476] 32B , one or more selected from the distribution circuit DMG, distribution circuit DMS, control unit CTR, memory device MD, voltage generation circuit PG, timing controller TMC, clock signal generation circuit CKS, image processing unit GPS, and interface INT may be included in the area LIA. Furthermore, among the above-mentioned circuits, circuits not included in the area LIA may be electrically connected as external circuits to one or both of the circuits included in the area LIA and the circuits included in the drive circuit area DRV.

[0477] The distribution circuit DMG, distribution circuit DMS, control unit CTR, memory device MD, voltage generation circuit PG, timing controller TMC, clock signal generation circuit CKS, image processing unit GPS, and interface INT each transmit and receive various signals to and from each other via bus wiring BW.

[0478] The interface INT functions as a circuit for inputting image information for displaying an image on the display device DSP, which is output from an external device, into the circuitry within the peripheral circuit PRPH. Examples of the external device include a recording media player, a hard disk drive (HDD), and a non-volatile storage device such as a solid state drive (SSD). The interface INT may also function as a circuit for outputting a signal from the circuitry within the peripheral circuit PRPH to a device outside the display device DSP.

[0479] Furthermore, when image information is input to the interface INT from an external device via wireless communication, the interface INT can be configured to have, as an example, one or more components selected from an antenna for receiving the image information, a mixer, an amplifier circuit, and an analog-to-digital conversion circuit.

[0480] The control unit CTR has the function of processing various control signals sent from an external device via the interface INT and controlling various circuits included in the peripheral circuit PRPH.

[0481] The memory device MD has the function of temporarily storing information and image signals. In this case, the memory device MD functions, for example, as a frame memory (sometimes called a frame buffer). The memory device MD may also have the function of temporarily storing either or both of information sent from an external device via the interface INT and information processed by the control unit CTR. Note that, for example, one or both of SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) can be used as the memory device MD.

[0482] The voltage generation circuit PG has a function of generating power supply voltages to be supplied to the pixel circuits included in the display unit DIS and the circuits included in the peripheral circuit PRPH. The voltage generation circuit PG may also have a function of selecting the circuits to which the voltage is supplied. For example, during a period in which a still image is displayed on the display unit DIS, the voltage generation circuit PG can reduce the power consumption of the entire display device DSP by stopping the supply of voltage to one or more selected from the circuit GDS, the circuit SDS, the image processing unit GPS, the timing controller TMC, and the clock signal generation circuit CKS.

[0483] The timing controller TMC has a function of generating timing signals used by the row driver circuits RWD included in the circuit GDS and the column driver circuits CLM included in the circuit SDS. The timing signals can be generated using clock signals generated by a clock signal generation circuit CKS.

[0484] The image processing unit GPS has a function of performing processing to draw an image on the display unit DIS. For example, the image processing unit GPS may have a GPU. In particular, the image processing unit GPS is configured to perform parallel pipeline processing, thereby enabling high-speed processing of image data to be displayed on the display unit DIS. The image processing unit GPS can also function as a decoder to restore encoded images.

[0485] The image processing unit GPS may also have a function of correcting the color tone of the image displayed on the display unit DIS. In this case, it is preferable that the image processing unit GPS is provided with one or both of a light adjustment circuit and a color adjustment circuit. Furthermore, if the display pixel circuit included in the display unit DIS includes an organic EL element, the image processing unit GPS may be provided with an EL correction circuit.

[0486] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through a display device (or the voltage applied to the display device) provided in the pixel may be monitored and acquired, the image displayed on the display unit DIS may be acquired by an image sensor, the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (for example, an artificial neural network), and the output result may be used to determine whether or not to correct the image.

[0487] Furthermore, the calculations of the artificial intelligence can be applied not only to image correction but also to image data up-conversion processing, which allows high-quality images to be displayed on the display unit DIS by up-converting low-resolution image data to match the resolution of the display unit DIS.

[0488] The above-mentioned artificial intelligence calculations can be performed using, for example, a GPU included in the image processing unit GPS. That is, various correction calculations (for example, color unevenness correction or up-conversion) can be performed using the GPU.

[0489] In this specification, a GPU that performs computations for artificial intelligence is referred to as an AI accelerator. That is, in this specification, a GPU may be substituted for an AI accelerator in the following description.

[0490] The clock signal generating circuit CKS has a function of generating a clock signal. Furthermore, for example, the clock signal generating circuit CKS may be configured to be able to change the frame frequency of the clock signal in accordance with the image to be displayed on the display unit DIS.

[0491] The distribution circuit DMG has a function of transmitting a signal received from the bus line BW to a row driver circuit RWD that drives a pixel included in one of the plurality of display areas ARA according to the content of the signal.

[0492] The distribution circuit DMS has a function of transmitting a signal received from the bus line BW to a column driver circuit CLM that drives a pixel included in one of the plurality of display areas ARA, depending on the content of the signal.

[0493] 35A, the display device DSP may use LVDS (Low Voltage Differential Signaling) as a digital signal transmission technology, or may use eDP (embedded DisplayPort) or iDP (internal DisplayPort).

[0494] 35A, the peripheral circuit PRPH may include a level shifter. The level shifter has a function of converting signals input to each circuit to an appropriate level, for example.

[0495] 35A is an example, and the circuit configuration included in the peripheral circuit PRPH may be changed depending on the situation. For example, if the display device DSP is configured to receive drive voltages for each circuit from an external source, there is no need to generate the drive voltages within the display device DSP, and in this case, the display device DSP may be configured not to include a voltage generation circuit PG.

[0496] 35A, the distribution circuit DMG, the distribution circuit DMS, the control unit CTR, the memory device MD, the voltage generation circuit PG, the timing controller TMC, the clock signal generation circuit CKS, the image processing unit GPS, and the interface INT may not be included in the display device DSP. Specifically, as shown in FIG. 35B, the peripheral circuit PRPH may be provided outside the display device DSP as a configuration including the distribution circuit DMG, the distribution circuit DMS, the control unit CTR, the memory device MD, the voltage generation circuit PG, the timing controller TMC, the clock signal generation circuit CKS, the image processing unit GPS, and the interface INT. 35B shows signal transmission and reception between the circuit GDS and the distribution circuit DMG and between the circuit SDS and the distribution circuit DMS, but signal transmission and reception between the circuit GDS and the distribution circuit DMG and between the circuit SDS and the distribution circuit DMS may be performed via an interface INT. The configuration of the display device DSP shown in FIG. 35B can be applied to, for example, the display device DSP of FIG. 32C. Also, Figure 35B shows an example in which a configuration including a distribution circuit DMG, a distribution circuit DMS, a control unit CTR, a memory device MD, a voltage generation circuit PG, a timing controller TMC, a clock signal generation circuit CKS, an image processing unit GPS, and an interface INT is provided outside the display device DSP, but one or more selected from the distribution circuit DMG, distribution circuit DMS, control unit CTR, a memory device MD, a voltage generation circuit PG, a timing controller TMC, a clock signal generation circuit CKS, an image processing unit GPS, and an interface INT may be electrically connected as external circuits to the remaining circuits included in the drive circuit region DRV.

[0497] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0498] Embodiment 4 In this embodiment, a structural example of a display device according to one embodiment of the present invention will be described.

[0499] <Structure Example 1 of Display Device> Figure 36 is a cross-sectional view illustrating an example of a display device of one embodiment of the present invention. As an example, a display device 1000 illustrated in Figure 36 has a structure in which a pixel circuit, a driver circuit, and the like are provided over a substrate 310. Note that the structure of the display device DSP0 or the like illustrated in Figure 1 of the above-described embodiment can be the structure of the display device 1000 illustrated in Figure 36. Note that the pixel circuit described in this embodiment can be the display pixel circuit described in the above embodiment.

[0500] Furthermore, for example, each of the circuit layer SICL, the wiring layer LINL, and the pixel layer PXAL shown in the display device DSP of Figures 32A and 32B can be configured as in the display device 1000 of Figure 36. As an example, the circuit layer SICL has a substrate 310, and a transistor 300 is formed on the substrate 310. Furthermore, a wiring layer LINL is provided above the transistor 300, and the wiring layer LINL is provided with wiring that electrically connects the transistor 300, a transistor 500 described later, and a light-emitting device 130R, a light-emitting device 130G, and a light-emitting device 130B described later. Furthermore, a pixel layer PXAL is provided above the wiring layer LINL, and the pixel layer PXAL has, as an example, the transistor 500 and a light-emitting device 130 (in Figure 36, the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B).

[0501] Therefore, the transistor 500 can be a transistor included in the pixel PX described in Embodiment 1 and Embodiment 2. Specifically, for example, the transistor 500 can be a transistor M2 included in the pixel PX shown in FIG. 2 or 17. Furthermore, for example, the transistor 500 can be a transistor included in a switch included in the display device DSP1A of FIG. 2 or a transistor included in a switch included in the display device DSP1B of FIG. 17.

[0502] The light emitting device 130 may be the light emitting device LD included in the pixel PX described in the first and second embodiments.

[0503] 2 or 17 may be included in, for example, the pixel layer PXAL. That is, the transistor included in the circuit CD may have the structure of the transistor 500. Also, the circuit CD shown in FIG. 2 or 17 may be included in, for example, the circuit layer SICL. That is, the transistor included in the circuit CD may have the structure of the transistor 300.

[0504] The substrate 310 can be, for example, a substrate that can be used for the substrate BS described in Embodiment 3. When heat treatment is included in the manufacturing process of the display device 1000, a substrate with high heat resistance is preferably selected as the substrate 310.

[0505] The diagonal size of the display device can be determined, for example, by the type and size of the substrate 310. For example, when manufacturing a display device with a diagonal size of 30 inches or more, 50 inches or more, 70 inches or more, or 100 inches or more for a television device or an electronic device for digital signage, a glass substrate may be used as the substrate 310. Furthermore, when manufacturing a display device with a diagonal size of 10 inches or less, 5 inches or less, 1.5 inches or less, or 1 inch or less for an XR device or a wearable information terminal, a semiconductor substrate may be used as the substrate 310.

[0506] Furthermore, there are no particular limitations on the screen ratio (aspect ratio) of the display device 1000. For example, the display device 1000 can support various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, or 32:9.

[0507] In this embodiment, the substrate 310 is described as a semiconductor substrate made of silicon.

[0508] The transistor 300 is provided over a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. Therefore, the transistor 300 is a Si transistor. Note that although FIG. 36 illustrates a structure in which one of the source and drain of the transistor 300 is electrically connected to a conductor 330 and a conductor 356 (described later) via a conductor 328 (described later), the electrical connection structure of the display device of one embodiment of the present invention is not limited thereto. For example, the display device of one embodiment of the present invention may have a structure in which the gate of the transistor 300 is electrically connected to the conductor 330 and the conductor 356 via the conductor 328.

[0509] The transistor 300 can be a Fin type transistor by, for example, covering the top surface and the side surfaces in the channel width direction of the semiconductor region 313 with a conductor 316 via an insulator 315 that functions as a gate insulating film. By configuring the transistor 300 as a Fin type transistor, the effective channel width can be increased, and the on-state characteristics of the transistor 300 can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and the off-state characteristics of the transistor 300 can be improved.

[0510] Note that the transistor 300 may be either a p-channel transistor or an n-channel transistor. Alternatively, a plurality of transistors 300 may be provided, and both p-channel and n-channel transistors may be used.

[0511] The region where the channel of the semiconductor region 313 is formed, the region nearby, and the low-resistance region 314a and low-resistance region 314b that serve as the source region or drain region preferably contain a silicon-based semiconductor, specifically, single-crystal silicon. Alternatively, each of the above-mentioned regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. Alternatively, the transistor 300 may be configured using silicon whose effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be, for example, a high electron mobility transistor (HEMT) using gallium arsenide and aluminum gallium arsenide.

[0512] The conductor 316, which functions as a gate electrode, can be a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron or aluminum, or can be a conductive material such as a metal material, an alloy material, or a metal oxide material.

[0513] Note that the work function is determined by the material of the conductor, and therefore the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0514] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0515] 36 is just an example, and the structure of the transistor 300 is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 may have a planar structure instead of a fin structure.

[0516] In the transistor 300 shown in FIG. 36, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0517] The insulators 320, 322, and 326 may be formed using, for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride.

[0518] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0519] The insulator 322 may function as a planarizing film that planarizes steps caused by the insulator 320 and the transistor 300 covered with the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method to improve the planarity.

[0520] Furthermore, it is preferable to use an insulating film (referred to as a barrier insulating film) for the insulator 324 that has barrier properties to prevent impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to a region above the insulator 324 (for example, a region where the transistor 500, the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B are provided). Therefore, it is preferable to use an insulating material for the insulator 324 that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (these impurities are less likely to permeate). Depending on the situation, the insulator 324 may be made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (these impurities are less likely to permeate). Furthermore, depending on the situation, the insulator 324 may be made of a material that has barrier properties to prevent the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and nitrogen oxide molecules (for example, N ２ O, NO, and NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., that is difficult for the oxygen to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0521] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used.

[0522] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, in the TDS analysis, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. and the amount of desorption converted into hydrogen atoms is 10×10 １５ atoms / cm ２ Below 5 × 10, preferably １５ atoms / cm ２ The following is fine.

[0523] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0524] Furthermore, conductors 328, 330, etc., which connect to a light-emitting device or the like provided above the insulator 326, are embedded in the insulators 320, 322, 324, and 326. The conductors 328, 330, etc., function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification, the wiring and the plug connecting to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0525] The materials for each plug and wiring (e.g., conductor 328 and conductor 330) can be one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials, and can be used in a single layer or a laminated layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the plug and wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0526] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 36 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductors 328 and 330.

[0527] Note that, for example, the insulator 350 is preferably an insulator having barrier properties against one or more selected from hydrogen, oxygen, and water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulators 352 and 354 also function as interlayer insulating films and planarizing films. The conductor 356 preferably includes a conductor having barrier properties against one or more selected from hydrogen, oxygen, and water.

[0528] Note that, for example, tantalum nitride is preferably used as the conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0529] In addition, an insulator 512 is provided above the insulator 354 and the conductor 356 .

[0530] 36 , the transistor 500 is provided over an insulator 512. The insulator 512 is preferably formed using a substance having a barrier property against one or more of oxygen and hydrogen. Specifically, for example, the insulator 512 can be formed using one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride.

[0531] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0532] For example, the insulator 512 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulator 512 can be made of a silicon oxide film or a silicon oxynitride film.

[0533] An insulator 514 is provided over the insulator 512, and the transistor 500 is provided over the insulator 514. An insulator 574 is formed over the transistor 500, and an insulator 581 is formed over the insulator 574.

[0534] The insulators 574 and 581 will be described in detail in Embodiment 5.

[0535] For the insulator 514, a film (a film having a barrier property) that suppresses diffusion of impurities such as water and hydrogen from a region where circuit elements are provided below the substrate 310 or the insulator 512 to a region where the transistor 500 is provided is preferably used. Therefore, for example, silicon nitride formed by a CVD method can be used for the insulator 514.

[0536] 36 is an OS transistor including a metal oxide in a channel formation region, as described above. Note that the OS transistor will be described in detail in Embodiment 5.

[0537] An insulator 592 and an insulator 594 are formed in this order over the insulator 581. A conductor 596 is embedded in the insulator 592 and the insulator 594. The conductor 596 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 596 can be formed using a material similar to that of the conductors 328 and 330.

[0538] Note that, for example, the insulator 592 is preferably an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulator 324. Similarly to the insulator 326, the insulator 594 is preferably an insulator having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulator 594 also functions as an interlayer insulating film and a planarizing film. The conductor 596 preferably includes a conductor having a barrier property against one or more selected from hydrogen, oxygen, and water.

[0539] An insulator 598 and an insulator 599 are formed over the insulator 594 and the conductor 596 .

[0540] For example, the insulator 598 is preferably an insulator having barrier properties against one or more selected from hydrogen, oxygen, and water, similar to the insulator 324. As the insulator 599, it is preferably an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings, similar to the insulator 326. The insulator 599 also functions as an interlayer insulating film and a planarizing film.

[0541] On the insulator 599, the light emitting device 130R, the light emitting device 130G, the light emitting device 130B, and the connection portion 140 are formed.

[0542] The connection portion 140 may be referred to as a cathode contact portion, and is electrically connected to the cathode electrodes of the light-emitting devices 130R, 130G, and 130B. In Fig. 36, the connection portion 140 has one or more conductors selected from conductors 112a to 112c described below, at least one conductor from conductors 126a to 126c described below, one or more conductors selected from conductors 129a to 129c described below, a common layer 114 described below, and a common electrode 115 described below.

[0543] The connection section 140 may be provided so as to surround the four sides of the display section, or may be provided within the display section (for example, between adjacent light-emitting devices 130).

[0544] The light-emitting device 130R has a conductor 112a, a conductor 126a on the conductor 112a, and a conductor 129a on the conductor 126a. The conductors 112a, 126a, and 129a may all be called pixel electrodes, or some of them may be called pixel electrodes.

[0545] The light-emitting device 130G has a conductor 112b, a conductor 126b on the conductor 112b, and a conductor 129b on the conductor 126b. As with the light-emitting device 130R, all of the conductors 112b, 126b, and 129b may be referred to as pixel electrodes, or only some of them may be referred to as pixel electrodes.

[0546] The light-emitting device 130B has a conductor 112c, a conductor 126c on the conductor 112c, and a conductor 129c on the conductor 126c. As with the light-emitting devices 130R and 130G, the conductors 112c, 126c, and 129c may all be referred to as pixel electrodes, or some of them may be referred to as pixel electrodes.

[0547] The conductors 112a to 112c and the conductors 126a to 126c can be, for example, conductive layers functioning as reflective electrodes. For the conductive layers functioning as reflective electrodes, conductors with high reflectivity to visible light, such as silver, aluminum, or an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film), can be used. Furthermore, the conductors 112a to 112c and the conductors 126a to 126c can be, for example, a stacked film of aluminum sandwiched between a pair of titanium films (a stacked film of Ti, Al, and Ti in this order) or a stacked film of silver sandwiched between a pair of indium tin oxide films (a stacked film of ITO, Ag, and ITO in this order).

[0548] Alternatively, for example, a conductive layer functioning as a reflective electrode may be used for the conductors 112a to 112c, and a conductor having high light-transmitting properties may be used for the conductors 126a to 126c. Examples of a conductor having high light-transmitting properties include an alloy of silver and magnesium and indium tin oxide (sometimes referred to as ITO).

[0549] The conductors 129a to 129c can be, for example, a conductive layer functioning as a transparent electrode. The conductive layer functioning as a transparent electrode can be, for example, the above-described conductor having high light-transmitting properties.

[0550] Furthermore, a microcavity structure (a microresonator structure) may be provided in the light-emitting device 130, which will be described in detail later. The microcavity structure refers to a structure in which the distance between the bottom surface of a light-emitting layer and the top surface of a lower electrode is set to a thickness that corresponds to the wavelength of the color of light emitted by the light-emitting layer. In this case, it is preferable to use a light-transmitting and light-reflective conductive material for the conductors 129a to 129c, which are upper electrodes (common electrodes), and a light-reflective conductive material for the conductors 112a to 112c and 126a to 126c, which are lower electrodes (pixel electrodes).

[0551] A microcavity structure refers to a structure in which the optical distance between the lower electrode and the light-emitting layer is adjusted to (2n-1)λ / 4 (where n is a natural number greater than or equal to 1, and λ is the wavelength of the light emission to be amplified). As a result, light reflected by the lower electrode and returned (reflected light) causes significant interference with light that is directly incident on the upper electrode from the light-emitting layer (incident light). This allows the phases of the reflected light and incident light, each of which has a wavelength λ, to be matched, thereby further amplifying the light emission from the light-emitting layer. On the other hand, if the reflected light and incident light have a wavelength other than λ, the phases will no longer match, resulting in attenuation without resonance.

[0552] The conductor 112a is connected to the conductor 596 embedded in the insulator 594 through an opening provided in the insulator 599. The end of the conductor 126a is located outside the end of the conductor 112a. The end of the conductor 126a and the end of the conductor 129a are aligned or approximately aligned.

[0553] Conductors 112b, 126b, and 129b in light-emitting device 130G, and conductors 112c, 126c, and 129c in light-emitting device 130B are similar to conductors 112a, 126a, and 129a in light-emitting device 130R, and therefore detailed explanations are omitted.

[0554] The conductors 112a, 112b, and 112c have recesses formed therein so as to cover the openings formed in the insulator 599. The layer 128 is embedded in the recesses.

[0555] The layer 128 has a function of planarizing the recessed portions of the conductor 112a, the conductor 112b, and the conductor 112c. Conductors 126a, 126b, and 126c, which are electrically connected to the conductors 112a, 112b, and 112c, are provided over the conductors 112a, 112b, and 112c and the layer 128. Therefore, regions overlapping with the recessed portions of the conductors 112a, 112b, and 112c can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased.

[0556] The layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. In particular, the layer 128 is preferably formed using an insulating material.

[0557] An insulating layer containing an organic material can be suitably used for the layer 128. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins can be used for the layer 128. Alternatively, a photosensitive resin can be used for the layer 128. Examples of the photosensitive resin include positive-type materials and negative-type materials.

[0558] By using a photosensitive resin, the layer 128 can be formed only through exposure and development steps, and the influence of dry etching or wet etching on the surfaces of the conductors 112 a, 112 b, and 112 c can be reduced. Furthermore, by forming the layer 128 using a negative photosensitive resin, the layer 128 can be formed using the same photomask (exposure mask) as that used to form the opening in the insulator 599 in some cases.

[0559] 36 shows an example in which the top surface of the layer 128 has a flat portion, but there is no particular limitation on the shape of the layer 128. Figures 37A to 37C show modified examples of the layer 128.

[0560] As shown in FIGS. 37A and 37C, the upper surface of layer 128 can be configured to have a recessed shape in the center and its vicinity in cross section, that is, a shape having a concave curved surface.

[0561] Furthermore, as shown in FIG. 37B, the upper surface of layer 128 can be configured to have a shape in which the center and its vicinity bulge in cross section, that is, a shape having a convex curve.

[0562] The upper surface of layer 128 may have one or both of a convex curved surface and a concave curved surface. The number of convex curved surfaces and the number of concave curved surfaces that the upper surface of layer 128 has are not limited, and may be one or more.

[0563] Furthermore, the height of the upper surface of the layer 128 and the height of the upper surface of the conductor 112a may be the same or approximately the same, or may be different from each other. For example, the height of the upper surface of the layer 128 may be lower or higher than the height of the upper surface of the conductor 112a.

[0564] 37A can also be considered an example in which layer 128 is contained within a recess formed in conductor 112a. On the other hand, as shown in FIG. 37C, layer 128 may be present outside the recess formed in conductor 112a, that is, the width of the top surface of layer 128 may be wider than the recess.

[0565] Light-emitting device 130R has a first layer 113a, a common layer 114 on the first layer 113a, and a common electrode 115 on the common layer 114. Light-emitting device 130G has a second layer 113b, a common layer 114 on the second layer 113b, and a common electrode 115 on the common layer 114. Light-emitting device 130B has a third layer 113c, a common layer 114 on the third layer 113c, and a common electrode 115 on the common layer 114.

[0566] The first layer 113a is formed so as to cover the top and side surfaces of the conductor 126a and the conductor 129a. Similarly, the second layer 113b is formed so as to cover the top and side surfaces of the conductor 126b and the conductor 129b. Similarly, the third layer 113c is formed so as to cover the top and side surfaces of the conductor 126c and the conductor 129c. Therefore, the entire regions where the conductors 126a, 126b, and 126c are provided can be used as light-emitting regions for the light-emitting devices 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

[0567] In the light-emitting device 130R, the first layer 113a and the common layer 114 can be collectively referred to as an EL layer. Similarly, in the light-emitting device 130G, the second layer 113b and the common layer 114 can be collectively referred to as an EL layer. Similarly, in the light-emitting device 130B, the third layer 113c and the common layer 114 can be collectively referred to as an EL layer.

[0568] The structure of the light emitting device of this embodiment is not particularly limited, and may be a single structure or a tandem structure.

[0569] The first layer 113a, the second layer 113b, and the third layer 113c are processed into island shapes by photolithography. Therefore, the angles between the top surface and the side surface of each of the first layer 113a, the second layer 113b, and the third layer 113c are close to 90 degrees at their edges. On the other hand, for example, an organic film formed using FMM (Fine Metal Mask) tends to become gradually thinner toward the edge, and the top surface is formed in a sloped shape over a range of, for example, 1 μm to 10 μm, making it difficult to distinguish between the top surface and the side surface.

[0570] The first layer 113a, the second layer 113b, and the third layer 113c have a clear distinction between the top surface and the side surface. As a result, in adjacent first and second layers 113a and 113b, one side surface of the first layer 113a and one side surface of the second layer 113b are arranged opposite each other. This is true for any combination of the first layer 113a, the second layer 113b, and the third layer 113c.

[0571] The first layer 113a, the second layer 113b, and the third layer 113c each include at least a light-emitting layer. For example, it is preferable that the first layer 113a includes a light-emitting layer that emits red light, the second layer 113b includes a light-emitting layer that emits green light, and the third layer 113c includes a light-emitting layer that emits blue light. Furthermore, the respective light-emitting layers may be of a color other than the above, such as cyan, magenta, yellow, or white.

[0572] Furthermore, the first layer 113a, the second layer 113b, and the third layer 113c may each have one or more of a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

[0573] For example, the first layer 113a, the second layer 113b, and the third layer 113c may each include a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer. Alternatively, an electron blocking layer may be provided between the hole transport layer and the light-emitting layer. Alternatively, an electron injection layer may be provided on the electron transport layer.

[0574] For example, the first layer 113 a, the second layer 113 b, and the third layer 113 c may each include an electron injection layer, an electron transport layer, a light-emitting layer, and a hole transport layer stacked in this order. Alternatively, a hole blocking layer may be provided between the electron transport layer and the light-emitting layer. Alternatively, a hole injection layer may be provided on the hole transport layer.

[0575] The first layer 113a, the second layer 113b, and the third layer 113c preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. The surfaces of the first layer 113a, the second layer 113b, and the third layer 113c may be exposed during the manufacturing process of the display device. Therefore, by providing the carrier transport layer on the light-emitting layer, the light-emitting layer can be prevented from being exposed to the outermost surface, and damage to the light-emitting layer can be reduced. This can improve the reliability of the light-emitting device and the light-receiving device.

[0576] The first layer 113a, the second layer 113b, and the third layer 113c may each have, for example, a first light-emitting unit, a charge generation layer, and a second light-emitting unit. For example, it is preferable that the first layer 113a has two or more light-emitting units that emit red light, the second layer 113b has two or more light-emitting units that emit green light, and the third layer 113c has two or more light-emitting units that emit blue light.

[0577] The second light-emitting unit preferably has a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Since the surface of the second light-emitting unit is exposed during the manufacturing process of the display device, providing the carrier transport layer on the light-emitting layer can prevent the light-emitting layer from being exposed on the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting device.

[0578] The common layer 114 may include, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 114 is shared by the light-emitting devices 130R, 130G, and 130B.

[0579] The common electrode 115 is shared by the light-emitting devices 130R, 130G, and 130B. As shown in Fig. 36 , the common electrode 115 shared by the plurality of light-emitting devices is electrically connected to a conductor included in the connection portion 140.

[0580] The side surfaces of the first layer 113a, the second layer 113b, and the third layer 113c are covered with an insulator 125 and an insulator 127, respectively. A mask layer 118a is located between the first layer 113a and the insulator 125. Furthermore, a mask layer 118a is located between the second layer 113b and the insulator 125, and a mask layer 118a is located between the third layer 113c and the insulator 125. A common layer 114 is provided on the first layer 113a, the second layer 113b, the third layer 113c, the insulator 125, and the insulator 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to a plurality of light-emitting devices.

[0581] The insulator 125 can be an insulating layer containing an inorganic material. The insulator 125 can be, for example, one or more inorganic insulating films selected from an insulating oxide film, an insulating nitride film, an insulating oxynitride film, and an insulating nitride oxide film. The insulator 125 can have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, an aluminum oxide film is preferable because it has a high selectivity with respect to the EL layer in an etching process and has a function of protecting the EL layer in the formation of the insulator 127 described later. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method as the insulator 125, it is possible to form an insulator 125 with few pinholes and excellent protection of the EL layer. The insulator 125 may also have a stacked structure of a film formed by an ALD method and a film formed by a sputtering method. For example, the insulator 125 may have a stacked structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method.

[0582] The insulator 125 preferably functions as a barrier insulating layer against water and / or oxygen. The insulator 125 preferably has a function of suppressing diffusion of water and / or oxygen. The insulator 125 preferably has a function of capturing or fixing (also referred to as gettering) water and / or oxygen.

[0583] The insulator 125 has a function as a barrier insulating layer or a gettering function, which can suppress the intrusion of impurities (typically, one or both of water and oxygen) that can diffuse into each light-emitting device from the outside. With this structure, a highly reliable light-emitting device and further a highly reliable display panel can be provided.

[0584] The insulator 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulator 125 and causing deterioration of the EL layer. Furthermore, a low impurity concentration in the insulator 125 can improve the barrier properties against water and / or oxygen. For example, it is desirable that the insulator 125 has a sufficiently low hydrogen concentration and / or carbon concentration.

[0585] An insulating layer containing an organic material can be suitably used as the insulator 127. A photosensitive organic resin is preferably used as the organic material, and for example, a photosensitive resin composition containing an acrylic resin can be used. The viscosity of the material of the insulator 127 may be 1 cP or more and 1500 cP or less, and preferably 1 cP or more and 12 cP or less. By setting the viscosity of the material of the insulator 127 within the above range, the insulator 127 having a tapered shape, as described below, can be formed relatively easily. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0586] As described below, the insulator 127 may have a tapered side surface, and the organic material that can be used for the insulator 127 is not limited to the above. For example, the insulator 127 may be made of an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene resin, a phenolic resin, or a precursor of these resins. The insulator 127 may also be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. The insulator 127 may be made of a photosensitive resin such as a photoresist. Examples of photosensitive resins include positive-type materials and negative-type materials.

[0587] The insulator 127 may be made of a material that absorbs visible light. The insulator 127 absorbs light emitted from the light-emitting device, thereby suppressing light leakage (stray light) from the light-emitting device to an adjacent light-emitting device through the insulator 127. This improves the display quality of the display panel. Furthermore, since the display quality can be improved without using a polarizing plate in the display panel, the display panel can be made lighter and thinner.

[0588] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed is preferable because it can enhance the visible light blocking effect. In particular, mixing three or more color filter materials makes it possible to obtain a black or nearly black resin layer.

[0589] The insulator 127 can be formed by a wet film formation method such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating. In particular, it is preferable to form the organic insulating film that becomes the insulator 127 by spin coating.

[0590] The insulator 127 is formed at a temperature lower than the heat resistance temperature of the EL layer. The substrate temperature when forming the insulator 127 is typically 200° C. or lower, preferably 180° C. or lower, more preferably 160° C. or lower, more preferably 150° C. or lower, and more preferably 140° C. or lower.

[0591] Below, the structure of the insulator 127 and the like will be described using the structure of the insulator 127 between the light-emitting device 130R and the light-emitting device 130G as an example. The same can be said for the insulator 127 between the light-emitting device 130G and the light-emitting device 130B, and the insulator 127 between the light-emitting device 130B and the light-emitting device 130R. Furthermore, below, the end of the insulator 127 on the second layer 113b may be used as an example for description, but the same can be said for the end of the insulator 127 on the first layer 113a and the end of the insulator 127 on the third layer 113c.

[0592] The insulator 127 preferably has a tapered shape with a taper angle θ1 on the side surface in a cross-sectional view of the display device. The taper angle θ1 is the angle between the side surface of the insulator 127 and the substrate surface. However, the taper angle θ1 is not limited to the substrate surface, and may be the angle between the side surface of the insulator 127 and the upper surface of the flat portion of the insulator 125 or the upper surface of the flat portion of the second layer 113b. Furthermore, by tapering the side surface of the insulator 127, the side surface of the insulator 125 and the side surface of the mask layer 118a may also be tapered.

[0593] The taper angle θ1 of the insulator 127 is less than 90°, preferably 60° or less, and more preferably 45° or less. By forming the side end of the insulator 127 in such a forward tapered shape, the common layer 114 and the common electrode 115 provided on the side end of the insulator 127 can be formed with good coverage without causing discontinuities or local thinning of the film. This improves the in-plane uniformity of the common layer 114 and the common electrode 115, thereby improving the display quality of the display device.

[0594] In addition, in a cross-sectional view of the display device, the upper surface of the insulator 127 preferably has a convex curved shape. The convex curved shape of the upper surface of the insulator 127 preferably has a shape that bulges gently toward the center. Furthermore, it is preferable that the convex curved portion at the center of the upper surface of the insulator 127 smoothly connects to the tapered portion at the side edge. By forming the insulator 127 in such a shape, the common layer 114 and the common electrode 115 can be formed with good coverage over the entire insulator 127.

[0595] The insulator 127 is formed in a region between two EL layers (for example, a region between the first layer 113a and the second layer 113b), with a portion of the insulator 127 sandwiched between a side edge of one EL layer (for example, the first layer 113a) and a side edge of the other EL layer (for example, the second layer 113b).

[0596] It is also preferable that one end of the insulator 127 overlaps with the conductor 126a that functions as a pixel electrode, and the other end of the insulator 127 overlaps with the conductor 126b that functions as a pixel electrode. This structure allows the end of the insulator 127 to be formed on a substantially flat region of the first layer 113a (second layer 113b). Therefore, it is relatively easy to process the insulator 127 into a tapered shape as described above.

[0597] As described above, by providing the insulator 127 or the like, it is possible to prevent discontinuities and locally thin portions from being formed in the common layer 114 and the common electrode 115 from the substantially flat region of the first layer 113 a to the substantially flat region of the second layer 113 b. This makes it possible to prevent po...

Claims

1. a pixel and a circuit, the pixel includes a light-emitting device, a drive transistor, a first switch, a second switch, a third switch, a fourth switch, and a first capacitor; the circuit includes a fifth switch, a sixth switch, and a second capacitor; a gate of the driving transistor is electrically connected to a first terminal of the first switch, a first terminal of the second switch, and a first terminal of the first capacitor; one of the source and the drain of the driving transistor is always electrically connected to the second terminal of the first capacitor, the first terminal of the fourth switch, and the anode of the light-emitting device; the other of the source and the drain of the driving transistor is electrically connected to a second terminal of the second switch and a first terminal of the third switch; a second terminal of the first switch electrically connected to a first terminal of the second capacitor; a first terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and a second terminal of the second capacitor; Display device.

2. In claim 1, the first switch has a first transistor of an n-channel type; the second switch includes a second n-channel transistor; the third switch includes a third transistor of an n-channel type; the fourth switch includes a fourth n-channel transistor, one of the source and the drain of the first transistor is electrically connected to a first terminal of the first switch; the other of the source and the drain of the first transistor is electrically connected to a second terminal of the first switch; one of the source and the drain of the second transistor is electrically connected to a first terminal of the second switch; the other of the source and the drain of the second transistor is electrically connected to a second terminal of the second switch; one of the source and the drain of the third transistor is electrically connected to a first terminal of the third switch; the other of the source and the drain of the third transistor is electrically connected to a second terminal of the third switch; one of the source and the drain of the fourth transistor is electrically connected to a first terminal of the fourth switch; the other of the source and the drain of the fourth transistor is electrically connected to a second terminal of the fourth switch. Display device.

3. a pixel and a circuit, the pixel includes a light-emitting device, a drive transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitance, and a second capacitance; the circuit includes a fifth switch and a sixth switch; a gate of the driving transistor is always electrically connected to a first terminal of the first switch, a first terminal of the second switch, and a first terminal of the first capacitor; one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the fourth switch, and the anode of the light-emitting device; the other of the source and the drain of the drive transistor is always electrically connected to the second terminal of the second switch and the first terminal of the third switch; a second terminal of the first switch electrically connected to a first terminal of the second capacitor; a first terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and a second terminal of the second capacitor; Display device.

4. In claim 3, the first switch has a first transistor of an n-channel type; the second switch includes a second n-channel transistor; the third switch includes a third transistor of an n-channel type; the fourth switch includes a fourth n-channel transistor, one of the source and the drain of the first transistor is electrically connected to a first terminal of the first switch; the other of the source and the drain of the first transistor is electrically connected to a second terminal of the first switch; one of the source and the drain of the second transistor is electrically connected to a first terminal of the second switch; the other of the source and the drain of the second transistor is electrically connected to a second terminal of the second switch; one of the source and the drain of the third transistor is electrically connected to a first terminal of the third switch; the other of the source and the drain of the third transistor is electrically connected to a second terminal of the third switch; one of the source and the drain of the fourth transistor is electrically connected to a first terminal of the fourth switch; the other of the source and the drain of the fourth transistor is electrically connected to a second terminal of the fourth switch. Display device.

5. a pixel and a circuit, the pixel includes a light-emitting device, a drive transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitance, and a second capacitance; the circuit includes a fifth switch and a sixth switch; a gate of the driving transistor is always electrically connected to a first terminal of the second switch, a first terminal of the first capacitor, and a first terminal of the second capacitor; one of the source and the drain of the driving transistor is always electrically connected to the second terminal of the first capacitor, the first terminal of the fourth switch, and the anode of the light-emitting device; the other of the source and the drain of the drive transistor is always electrically connected to the second terminal of the second switch and the first terminal of the third switch; a second terminal of the second capacitor is always electrically connected to a first terminal of the first switch; a first terminal of the fifth switch is always electrically connected to a first terminal of the sixth switch and a second terminal of the first switch; Display device.

6. In claim 5, the first switch has a first transistor of an n-channel type; the second switch includes a second n-channel transistor; the third switch includes a third transistor of an n-channel type; the fourth switch includes a fourth n-channel transistor, one of the source and the drain of the first transistor is electrically connected to a first terminal of the first switch; the other of the source and the drain of the first transistor is electrically connected to a second terminal of the first switch; one of the source and the drain of the second transistor is electrically connected to a first terminal of the second switch; the other of the source and the drain of the second transistor is electrically connected to a second terminal of the second switch; one of the source and the drain of the third transistor is electrically connected to a first terminal of the third switch; the other of the source and the drain of the third transistor is electrically connected to a second terminal of the third switch; one of the source and the drain of the fourth transistor is electrically connected to a first terminal of the fourth switch; the other of the source and the drain of the fourth transistor is electrically connected to a second terminal of the fourth switch. Display device.

7. a pixel and a circuit, the pixel includes a light emitting device, a drive transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an eighth switch, a first capacitance, a second capacitance, and a third capacitance; the circuit includes a sixth switch and a seventh switch; the drive transistor has a first gate and a second gate; a first gate of the driving transistor is always electrically connected to a first terminal of the first switch, a first terminal of the second switch, a first terminal of the eighth switch, and a first terminal of the first capacitor; one of the source and the drain of the drive transistor is always electrically connected to the second terminal of the first capacitor, the first terminal of the third capacitor, the second terminal of the second switch, the first terminal of the third switch, and the first terminal of the fourth switch; a second gate of the driving transistor is always electrically connected to a second terminal of the third capacitor and a first terminal of the fifth switch; a second terminal of the third switch always conducting with an anode of the light emitting device; a second terminal of the first switch is always electrically connected to a first terminal of the second capacitor; a second terminal of the second capacitor is always electrically connected to a first terminal of the sixth switch and a first terminal of the seventh switch; Display device.

8. In claim 7, the first switch has a first transistor of an n-channel type; the second switch includes a second n-channel transistor; the third switch includes a third transistor of an n-channel type; the fourth switch includes a fourth n-channel transistor, the fifth switch includes a fifth transistor of an n-channel type, one of the source and the drain of the first transistor is electrically connected to a first terminal of the first switch; the other of the source and the drain of the first transistor is electrically connected to a second terminal of the first switch; one of the source and the drain of the second transistor is electrically connected to a first terminal of the second switch; the other of the source and the drain of the second transistor is electrically connected to a second terminal of the second switch; one of the source and the drain of the third transistor is electrically connected to a first terminal of the third switch; the other of the source and the drain of the third transistor is electrically connected to a second terminal of the third switch; one of the source and the drain of the fourth transistor is electrically connected to a first terminal of the fourth switch; the other of the source and the drain of the fourth transistor is electrically connected to a second terminal of the fourth switch. one of the source and the drain of the fifth transistor is electrically connected to a first terminal of the fifth switch; the other of the source and the drain of the fifth transistor is electrically connected to a second terminal of the fifth switch. Display device.

9. a pixel and a circuit, the pixel includes a light emitting device, a drive transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an eighth switch, a first capacitance, a second capacitance, and a third capacitance; the circuit includes a sixth switch and a seventh switch; the drive transistor has a first gate and a second gate; a first gate of the driving transistor is electrically connected to a first terminal of the second switch, a first terminal of the eighth switch, a first terminal of the first capacitor, and a first terminal of the second capacitor; one of the source and the drain of the drive transistor is always electrically connected to the second terminal of the first capacitor, the first terminal of the third capacitor, the second terminal of the second switch, the first terminal of the third switch, and the first terminal of the fourth switch; a second gate of the driving transistor is electrically connected to a second terminal of the third capacitor and a first terminal of the fifth switch; a second terminal of the third switch electrically connected to an anode of the light emitting device; a second terminal of the second capacitor is always electrically connected to a first terminal of the first switch; a second terminal of the first switch electrically connected to a first terminal of the sixth switch and a first terminal of the seventh switch; Display device.

10. In claim 9, the first switch has a first transistor of an n-channel type; the second switch includes a second n-channel transistor; the third switch includes a third transistor of an n-channel type; the fourth switch includes a fourth n-channel transistor, the fifth switch includes a fifth transistor of an n-channel type, one of the source and the drain of the first transistor is electrically connected to a first terminal of the first switch; the other of the source and the drain of the first transistor is electrically connected to a second terminal of the first switch; one of the source and the drain of the second transistor is electrically connected to a first terminal of the second switch; the other of the source and the drain of the second transistor is electrically connected to a second terminal of the second switch; one of the source and the drain of the third transistor is electrically connected to a first terminal of the third switch; the other of the source and the drain of the third transistor is electrically connected to a second terminal of the third switch; one of the source and the drain of the fourth transistor is electrically connected to a first terminal of the fourth switch; the other of the source and the drain of the fourth transistor is electrically connected to a second terminal of the fourth switch. one of the source and the drain of the fifth transistor is electrically connected to a first terminal of the fifth switch; the other of the source and the drain of the fifth transistor is electrically connected to a second terminal of the fifth switch. Display device.

11. In any one of claims 1 to 10, The light-emitting device includes an organic electroluminescent device. Display device.

12. A display device comprising: the display device according to claim 11; and a housing. electronic equipment.