Plasma processing apparatus, control method, power supply system, program, and storage medium

Abstract

In the disclosed plasma processing apparatus, a bias electric power supply supplies electric bias energy having a bias frequency to a substrate support at a timing that is designated by a first clock signal. While the electric bias energy is being supplied to the substrate support, a high-frequency electric power supply outputs source high-frequency electric power having a source frequency adjusted at a timing that is designated by a second clock signal. The second clock signal has a higher frequency than the bias frequency and is synchronized with the first clock signal.

Description

Plasma processing apparatus, control method, power supply system, program, and storage medium

[0001] SUMMARY OF THE INVENTION An exemplary embodiment of the present disclosure relates to a plasma processing apparatus, a control method, a power supply system, a program, and a storage medium.

[0002] A plasma processing apparatus is used in plasma processing of a substrate. In the plasma processing apparatus, bias high frequency power is used to attract ions from a plasma generated in a chamber to the substrate. Patent Document 1 listed below discloses a plasma processing apparatus in which the power level and frequency of the bias high frequency power are modulated.

[0003] Japanese Patent Application Laid-Open No. 2009-246091

[0004] The present disclosure provides techniques for precisely synchronizing the timing of adjustments to the frequency of source radio frequency power with the phase within a cycle of electrical bias energy.

[0005] In one exemplary embodiment, a plasma processing apparatus is provided. The plasma processing apparatus includes a chamber, a substrate support, a bias power supply, and a radio frequency power supply. The substrate support is disposed within the chamber. The bias power supply is electrically coupled to the substrate support. The bias power supply is configured to generate electrical bias energy having a bias frequency at a timing specified by a first clock signal. The radio frequency power supply is configured to generate source radio frequency power at a source frequency to generate a plasma from a gas within the chamber. The radio frequency power supply is configured to output source radio frequency power having a source frequency adjusted at a timing specified by a second clock signal when the electrical bias energy is supplied to the substrate support. The second clock signal has a frequency higher than the bias frequency and is synchronized to the first clock signal.

[0006] According to one exemplary embodiment, it is possible to precisely synchronize the timing of the adjustment of the frequency of the source RF power with the phase within the period of the electrical bias energy.

[0007] FIG. 4 is a diagram for explaining an example of the configuration of a plasma processing system. FIG. 4 is a diagram for explaining an example of the configuration of a capacitively coupled plasma processing apparatus. FIG. 4 is a diagram for showing a power supply system according to an exemplary embodiment. FIGS. 4A and 4B each show a bias power supply according to an exemplary embodiment. FIG. 4 is a timing chart related to a plasma processing apparatus according to an exemplary embodiment. FIG. 4 is a diagram showing an example frequency divider that can be employed in a plasma processing apparatus according to an exemplary embodiment. FIG. 4 is a flowchart of a control method according to an exemplary embodiment. FIG. 4 is a timing chart related to a first example of adjusting a source frequency. FIG. 4 is a timing chart related to a second example of adjusting a source frequency. FIG. 4 is a flowchart of a third example of adjusting a source frequency. FIG. 4 is a flowchart of a fourth example of adjusting a source frequency. FIG. 11 is a diagram for explaining the fourth example shown in FIG. 11. FIG. 12 is a flowchart of a fifth example of adjusting a source frequency. FIG. 13 is a diagram for explaining the fifth example. FIG. 14 is a diagram for explaining the fifth example. FIG. 15 is a diagram for explaining the fifth example. FIG. 16 is a diagram for explaining the fifth example. FIG. 17 is a diagram for explaining the fifth example. FIG. 18 is a diagram for explaining the sixth example. FIGS. 20A and 20B each show timing charts of example source high frequency power and electrical bias energy. 21(a) and 21(b) are timing charts of an example of source RF power and electrical bias energy, respectively. 21(a) and 21(b) are timing charts relating to a seventh example of adjusting the source frequency.

[0008] Various exemplary embodiments will be described in detail below with reference to the drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0009] FIG. 1 is a diagram illustrating an exemplary configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a main controller 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0010] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma generated in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), surface wave plasma (SWP), or the like.

[0011] The main controller 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various steps described in this disclosure. The main controller 2 may be configured to control each element of the plasma processing apparatus 1 to perform various steps described herein. In one embodiment, part or all of the main controller 2 may be included in the plasma processing apparatus 1. The main controller 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The main controller 2 is implemented, for example, by a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. The program includes computer-executable instructions that cause the plasma processing apparatus 1 to perform various steps of a control method according to an exemplary embodiment described below. The program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The program may be transmitted to the main controller 2 from a higher-level management system. The acquired program is stored in the storage unit 2a2 and is read from the storage unit 2a2 and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a, or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a central processing unit (CPU). The storage unit 2a2 may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0012] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0013] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply system 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The substrate support 11 is electrically insulated from the housing of the plasma processing chamber 10.

[0014] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0017] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0018] The showerhead 13 is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The process gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas inlet may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0020] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0021] The power supply system 30 includes a high frequency power supply 31 and a bias power supply 32. The high frequency power supply 31 constitutes the plasma generating unit 12 of one embodiment. The high frequency power supply 31 is configured to generate a source high frequency power RF. The source high frequency power RF has a source frequency f ＲＦ That is, the source radio frequency power RF has a frequency equal to the source frequency f ＲＦ The source frequency fＲＦ The frequency of the RF power source 31 may be in the range of 10 MHz to 150 MHz. The RF power source 31 is electrically connected to the RF electrode via a matching box 31m and is configured to supply source RF power RF to the RF electrode. The RF electrode may be a conductive member of the base 1110, at least one electrode provided in the ceramic member 1111a, or an upper electrode. When the source RF power RF is supplied to the RF electrode, plasma is generated from the gas in the chamber 10. The matching box 31m has a variable impedance. The variable impedance of the matching box 31m is controlled by the main controller 2 to reduce reflection of the source RF power RF from the load.

[0022] The bias power supply 32 is configured to generate electrical bias energy BE. The bias power supply 32 is electrically coupled to the substrate support 11. The bias power supply 32 is electrically connected to a bias electrode in the substrate support 11 and is configured to supply electrical bias energy BE to the bias electrode. The bias electrode may be at least one electrode provided in the conductive member or ceramic member 1111 a of the base 1110. When the electrical bias energy BE is supplied to the bias electrode, ions from the plasma are attracted to the substrate W.

[0023] The electrical bias energy BE has a bias frequency that is lower than the source frequency. The bias frequency may be in the range of 100 kHz to 60 MHz, for example, 400 kHz. The electrical bias energy BE is periodically supplied to the bias electrode with a bias period (time interval), or period CY, whose time length is the inverse of the bias frequency.

[0024] The electrical bias energy BE may be bias high-frequency power LF having a bias frequency (see FIG. 5). That is, the electrical bias energy BE may have a sinusoidal waveform whose frequency is the bias frequency. In this case, the bias power supply 32 is electrically connected to the bias electrode via a matching device 32m. The variable impedance circuit (i.e., matching circuit) of the matching device 32m is controlled by the main controller 2 to reduce reflection of the bias high-frequency power LF from the load.

[0025] Alternatively, the electric bias energy BE may include a voltage pulse PV. The waveform of the pulse PV of the electric bias energy BE may have a square wave, a triangular wave, or any other waveform. The polarity of the voltage of the pulse PV of the electric bias energy BE is set so as to generate a potential difference between the substrate W and the plasma and attract ions from the plasma to the substrate W. In one example, the pulse PV of the electric bias energy BE may be a negative voltage pulse. The pulse PV of the electric bias energy BE may be generated by waveform shaping a DC voltage from a DC power supply using a pulse unit.

[0026] The power supply system 30 will be described in detail below with reference to FIGS. 3 to 5. FIG. 3 is a diagram showing a power supply system according to an exemplary embodiment. FIGS. 4(a) and 4(b) each show a bias power supply according to an exemplary embodiment. FIG. 5 is a timing chart related to a plasma processing apparatus according to an exemplary embodiment. In FIG. 5, "RF" represents the power level of the traveling wave of the source radio frequency power RF.

[0027] The bias power supply 32 is configured to generate electrical bias energy BE at a timing specified by a first clock signal CK1. The power supply system 30 may further include a reference clock signal generator 33. The reference clock signal generator 33 is configured to generate a reference clock signal RCK. The frequency of the reference clock signal RCK is, for example, 1 GHz. The first clock signal CK1 may be generated by dividing the reference clock signal RCK by a frequency divider 341. The division ratio of the frequency divider 341 and the duty ratio of the clock pulses in the first clock signal CK1 are specified to the frequency divider 341 by the control unit 35.

[0028] In one embodiment, the frequency of the first clock signal CK1 may be the same as the bias frequency. In this case, the first clock signal CK1 includes clock pulses that are periodically generated at the same time interval as the period CY. When the electrical bias energy BE is bias high-frequency power LF, the bias power supply 32 generates the bias high-frequency power LF in synchronization with the first clock signal CK1 so that the period CY starts. For example, the bias power supply 32 generates the bias high-frequency power LF so that the period CY starts at one of the rising and falling edges of the first clock signal CK1. Note that, in this specification, the rising and falling edges of a clock signal refer to the rising and falling edges of a clock pulse in the clock signal.

[0029] When the electrical bias energy BE includes a pulse PV, the bias power supply 32 starts generating the pulse PV at one of the rising and falling edges of the first clock signal CK1. The bias power supply 32 stops generating the pulse PV at the other of the rising and falling edges of the first clock signal CK1. In this case, the frequency divider 341, in response to an instruction from the control unit 35, sets the duty ratio of the clock pulse of the first clock signal CK1 in accordance with the duty ratio of the pulse PV.

[0030] When the electrical bias energy BE includes pulses PV, the bias power supply 32 may have the configuration shown in FIG. 4A. In the example shown in FIG. 4A, the bias power supply 32 includes a DC power supply 32p, switches 32s and 32t, damping circuits 32g and 32h, an output 32o, and a switching control unit 32c. The switches 32s and 32t and the switching control unit 32c constitute a pulse unit. The positive electrode of the DC power supply 32p is connected to ground. The negative electrode of the DC power supply 32p is connected to the switch 32s. The switch 32s is connected to the output 32o via the damping circuit 32g. The switch 32t is connected between ground and the damping circuit 32h. The damping circuit 32h is connected to the output 32o. The output 32o is connected to a bias electrode. The damping circuits 32g and 32h are circuits for reducing ringing during switching. If necessary, the damping circuits 32g and 32h may be incorporated into the bias power supply 32. Furthermore, each of the damping circuits 32g and 32h may be provided at a connection point different from the connection point shown in FIG.

[0031] The switching control unit 32c controls the switches 32s and 32t to close the switch 32s and open the switch 32t at one of the rising and falling edges of the first clock signal CK1. Therefore, the DC power supply 32p is connected to the output 32o at one of the rising and falling edges of the first clock signal CK1. The switching control unit 32c controls the switches 32s and 32t to open the switch 32s and close the switch 32t at the other of the rising and falling edges of the first clock signal CK1. Therefore, the output 32o is connected to ground at the other of the rising and falling edges of the first clock signal CK1. Alternatively, the switching control unit 32c may control the switches 32s and 32t to open the switch 32s and close the switch 32t when a specified time has elapsed since the output 32o was connected to the DC power supply 32p.

[0032] In another embodiment, the frequency of the first clock signal CK1 may be higher than the bias frequency. The power supply system 30 may not include the frequency divider 341, and the first clock signal CK1 may be the reference clock signal RCK. Alternatively, the first clock signal CK1 may be generated by dividing the frequency of the reference clock signal RCK using the frequency divider 341. In this embodiment, the electrical bias energy BE may be a bias high-frequency power LF or a voltage (e.g., pulse PV) that is periodically generated at a time interval that is the reciprocal of the bias frequency. In this embodiment, the bias power supply 32 may include a D / A converter 32da (digital-to-analog converter), a filter 32f, and an amplifier 32a, as shown in FIG. 4B.

[0033] The D / A converter 32da receives waveform data of the electric bias energy BE stored in the memory 36 from the control unit 35. The D / A converter 32da performs digital-to-analog conversion (D / A conversion) of the waveform data at a timing specified by the first clock signal CK1 to generate an analog signal, and outputs the generated analog signal from its output. The output of the D / A converter 32da is connected to the input of the amplifier 32a via a filter 32f. The filter 32f removes unnecessary high-frequency components from the input analog signal. The amplifier 32a generates the electric bias energy BE by amplifying the analog signal from the filter 32f. Note that the output of the D / A converter 32da may be directly connected to the input of the amplifier 32a.

[0034] The high frequency power supply 31 has a source frequency f ＲＦ The device is configured to output a source radio frequency power RF having a source frequency f ＲＦ is adjusted at a timing designated by the second clock signal CK2 when the electrical bias energy BE is supplied to the bias electrode. Each period CY of the electrical bias energy BE is divided into a plurality of phase periods SP, the start timing of which is synchronized with either the rising or falling edge of the second clock signal CK2. The time lengths of the plurality of phase periods SP are equal to each other. The source frequency fＲＦ is set at the start timing of each of the multiple phase periods SP in each cycle CY and maintained at that timing. ＲＦ The details of the adjustment will be described later.

[0035] The second clock signal CK2 has a frequency higher than the bias frequency and is synchronized with the first clock signal CK1. The frequency of the second clock signal CK2 is equal to the source frequency f ＲＦ The frequency of the second clock signal CK2 is N times the bias frequency, where N is the number of phase periods SP in each cycle CY, e.g., 50. The second clock signal CK2 is generated by dividing the reference clock signal RCK by a frequency divider 342. The division ratio of the frequency divider 342 is specified to the frequency divider 342 by the control unit 35.

[0036] In one embodiment, the high frequency power supply 31 may include a D / A converter 31da (digital-to-analog converter), a filter 31f, and an amplifier 31a. The D / A converter 31da receives waveform data of the source high frequency power RF stored in a memory 36 from the control unit 35. The D / A converter 31da performs digital-to-analog conversion (D / A conversion) of the waveform data at a timing specified by a fourth clock signal CK4 to generate an analog signal, and outputs the generated analog signal from its output. The output of the D / A converter 31da is connected to the input of the amplifier 31a via a filter 31f. The filter 31f removes unnecessary high frequency components from the input analog signal. The amplifier 31a generates the source high frequency power RF by amplifying the analog signal from the filter 31f. Note that the output of the D / A converter 31da may be directly connected to the input of the amplifier 31a.

[0037] The frequency of the fourth clock signal CK4 is higher than the frequency of the second clock signal CK2. The fourth clock signal CK4 may be the reference clock signal RCK. Alternatively, the fourth clock signal CK4 may be generated by dividing the reference clock signal RCK using a frequency divider 344. The division ratio of the frequency divider 344 is specified by the control unit 35.

[0038] As shown in FIG. 2 , the plasma processing apparatus 1 further includes a sensor 31s. The sensor 31s is configured to output an electrical signal SS (see FIG. 3 ) reflecting the degree of reflection of the source radio frequency power RF from the load. The sensor 31s is provided, for example, between the radio frequency power supply 31 and the matching device 31m. The sensor 31s may be a directional coupler, and the electrical signal SS may be a signal representing the power level Pr of the source radio frequency power RF reflected from the load. The sensor 31s may be configured to detect a voltage and a current in a power supply path connecting the radio frequency power supply 31 and the radio frequency electrode, and the electrical signal SS may be a signal representing the voltage and the current.

[0039] The power supply system 30 further includes an A / D converter 38 (analog-to-digital converter). The output of the sensor 31s is connected to the input of the A / D converter 38. The output of the sensor 31s may be connected to the input of the A / D converter 38 via a filter 37. The filter 37 filters out the source frequency f ＲＦ The A / D converter 38 is configured to generate a filtered signal by removing harmonic components, intermodulation distortion components, and bias components other than the component of the signal SS, and output the filtered signal. The A / D converter 38 is configured to perform analog-to-digital conversion (A / D conversion) on the electrical signal SS or the filtered signal at a timing specified by a third clock signal CK3, to generate a digital signal DS. The third clock signal CK3 may be the reference clock signal RCK. Alternatively, the third clock signal CK3 may be generated by dividing the reference clock signal RCK by a frequency divider 343. The frequency division ratio of the frequency divider 343 is specified by the control unit 35.

[0040] The control unit 35 is configured to generate a representative value RV from the digital signal DS for each of the multiple phase periods SP. Therefore, the control unit 35 determines a measurement value from the digital signal DS. The measurement value may be the power level Pr of the reflected wave. The measurement value may also be the ratio of the power level Pr of the reflected wave to the output power level of the source high frequency power RF. The measurement value may be each value, average value, or effective value of the voltage and current for each of the multiple phase periods SP, or the phase difference between the voltage and current. The representative value RV may be the average value or maximum value of the measurement values ​​for each of the multiple phase periods SP. The control unit 35 determines a source frequency f that suppresses reflection of the source high frequency power RF, can efficiently transmit the source high frequency power RF to the plasma, or brings the impedance at the sensor position closer to an ideal value (i.e., 50Ω) based on the representative value RV. ＲＦ The control unit 35 determines the determined source frequency f ＲＦ is the source frequency f of the source radio frequency power RF in the same phase period in the subsequent cycle CY. ＲＦ The control unit 35 uses the determined source frequency f ＲＦ The waveform data having the above formula is supplied to the D / A converter 31da of the high frequency power supply 31.

[0041] In the plasma processing apparatus 1 described above, the source frequency f of the source high frequency power RF is applied at a plurality of phases within the period CY of the electric bias energy BE. ＲＦ is adjusted. The source frequency f ＲＦ The timing at which the number is adjusted is specified by a second clock signal CK2. The second clock signal CK2 is synchronized with the first clock signal CK1, which specifies the timing at which the electrical bias energy BE is generated. Therefore, the phase within the period CY of the electrical bias energy BE and the source frequency f ＲＦ This makes it possible to accurately synchronize the timing of the adjustment.

[0042] In one embodiment, at least one of the frequency dividers 341, 342, 343, and 344 may be the frequency divider 340 shown in FIG. 6 . FIG. 6 is a diagram illustrating an example of a frequency divider that can be employed in a plasma processing apparatus according to an exemplary embodiment. The frequency divider 340 includes a frequency divider 340a and a PLL circuit 340b (Phase Locked Loop circuit). The PLL circuit 340b includes a phase comparator 340c, a low-pass filter 340d, a voltage-controlled oscillator 340e, and a frequency divider 340f. The input of the frequency divider 340a is connected to the output of the reference clock signal generator 33. The output of the frequency divider 340a is connected to the reference input of the phase comparator 340c. The output of the phase comparator 340c is connected to the input of the low-pass filter 340d. The output of the low-pass filter 340d is connected to the input of the voltage-controlled oscillator 340e. The output of the voltage-controlled oscillator 340e, i.e., the output of the frequency divider 340, outputs a clock signal generated by dividing the reference clock signal RCK. The output of the voltage-controlled oscillator 340e is connected to the feedback input of the phase comparator 340c via the frequency divider 340f. The frequency division ratio X of the frequency divider 340a and the frequency division ratio Y of the frequency divider 340f are specified by the control unit 35. Here, Y<X, and the frequency division ratio of the frequency divider 340 is Y / X. Note that in order to adjust the duty ratio of the clock pulse output from the frequency divider 340, the control unit 35 may specify the duty ratio of the clock pulse to the frequency divider 340a and the voltage-controlled oscillator 340e.

[0043] A control method according to one exemplary embodiment will be described below with reference to Fig. 7. The control method MT includes steps ST1 to ST3. In step ST1, electric bias energy BE is supplied to the substrate support 11 from the bias power supply 32. In step ST1, the electric bias energy BE is generated at a timing designated by the first clock signal CK1, as described above.

[0044] In step ST2, a source high frequency power RF is supplied from the high frequency power supply 31 to generate plasma from the gas in the chamber 10. When or simultaneously with the supply of the electrical bias energy BE to the substrate support 11, in step ST2, the high frequency power supply 31 generates a source frequency f adjusted at a timing designated by the second clock signal CK2 as described above. ＲＦ The second clock signal CK2 has a frequency lower than the source frequency and higher than the bias frequency, and is synchronized with the first clock signal CK1. As described above, the source frequency f ＲＦ is set to suppress reflection of the source radio frequency power RF in accordance with a representative value RV of the electrical signal SS acquired in each of the plurality of phase periods SP. The source frequency set in each of the plurality of phase periods SP is used as the source frequency of the source radio frequency power RF in the same phase period of the subsequent cycle CY.

[0045] Hereinafter, the source frequency f of each of the multiple phase periods SP ＲＦ Some examples of adjustments are given below.

[0046] [Source frequency f ＲＦ First Example of Adjustment

[0047] 8 is a timing diagram relating to a first example of adjusting the source frequency. In all of the examples described below, the source frequency f ＲＦis adjusted during the period when both the electrical bias energy BE and the source radio frequency power RF are supplied, i.e., the overlap period. As shown in FIG. 8 , the overlap period includes a plurality of cycles CY, i.e., M cycles CY(1) to CY(M). Each of the plurality of cycles CY includes a plurality of phase periods SP, i.e., N phase periods SP(1) to SP(N). In the following description, phase period SP(n) represents the nth phase period among phase periods SP(1) to SP(N). Phase period SP(m,n) represents the nth phase period SP(n) in the mth cycle CY(m). Representative value RV(n) represents the representative value RV acquired during the nth phase period SP(n) among phase periods SP(1) to SP(N). Representative value RV(m,n) represents the representative value RV acquired during the nth phase period within the mth cycle CY.

[0048] In the first example, the control unit 35 controls the source frequency f of the source radio frequency power RF used in the same phase period SP(n) of a plurality of cycles CY. ＲＦ are set to a plurality of different frequencies. The control unit 35 compares the representative values ​​RV(n) acquired in the same phase period SP(n) of a plurality of cycles CY to select a frequency from the plurality of frequencies that best suppresses the reflection of the source high frequency power RF. For example, the control unit 35 selects a frequency that minimizes the power level Pr of the reflected wave of the source high frequency power RF. The control unit 35 sets the selected frequency as the source frequency f for the phase period SP(n) in the subsequent cycle CY. ＲＦ Used as.

[0049] [Source frequency f ＲＦ Second example of adjustment of

[0050] 9 is a timing chart relating to a second example of adjusting the source frequency. As shown in FIG. 9, in the second example, the control unit 35 adjusts the source frequency f of the source radio frequency power RF in the phase period SP(n) within the cycle CY(m), i.e., the phase period SP(m, n). ＲＦis configured to adjust in response to a change in the representative value RV(n). The change in the representative value RV(n) is determined by using different frequencies of the source radio frequency power RF in the corresponding phase periods SP(n) in each of two or more cycles CY prior to the cycle CY(m).

[0051] The two or more periods CY before period CY(m) include a first period and a second period. In the example of Figure 9, the first period is period CY(m-Q(2)), and the second period is the period after the first period, period CY(m-Q(1)). Q(1) is an integer greater than or equal to 1, Q(2) is an integer greater than or equal to 2, and Q(1) < Q(2) is satisfied.

[0052] The control unit 35 imparts one frequency shift from the frequency of the source radio frequency power RF in the phase period SP(m-Q(1),n) to the frequency f(m-Q(1),n) of the source radio frequency power RF in the phase period SP(m-Q(2),n). Here, f(m,n) represents the frequency of the source radio frequency power RF used in the phase period SP(m,n). f(m,n) is expressed as f(m,n) = f(m-Q(1),n) + Δ(m,n). Δ(m,n) represents the amount of the frequency shift. One frequency shift is either a frequency decrease or a frequency increase. If one frequency shift is a frequency decrease, Δ(m,n) has a negative value. If one frequency shift is a frequency increase, Δ(m,n) has a positive value.

[0053] In FIG. 9, the frequency of the source radio frequency power RF in each of the multiple phase periods SP in the cycle CY(m-Q(2)) is the same as each other, and ０ 9, the frequencies of the source radio frequency power RF in each of the phase periods SP in the cycle CY(m-Q(1)) are the same, and the frequency f ０ is set to a frequency reduced from ０ may be increased from

[0054] The control unit 35 determines whether the degree of reflection of the source high frequency power RF (e.g., the power level Pr of the reflected wave) due to the frequency shift has increased or decreased from the change between the representative value RV(m-Q(2),n) and the representative value RV(m-Q(1),n). If the degree of reflection of the source high frequency power RF has decreased due to one of the frequency shifts, the control unit 35 sets the frequency f(m,n) to a frequency that has one of the frequency shifts relative to the frequency f(m-Q(1),n).

[0055] One amount of frequency shift Δ(m, n) in phase period SP(m, n) may be the same as one amount of frequency shift Δ(m−Q(1), n) in phase period SP(m−Q(1), n). That is, the absolute value of the amount of frequency shift Δ(m, n) may be the same as the amount of frequency shift Δ(m−Q(1), n). Alternatively, the absolute value of the amount of frequency shift Δ(m, n) may be greater than the amount of frequency shift Δ(m−Q(1), n). Alternatively, the absolute value of the amount of frequency shift Δ(m, n) may be set to increase as the degree of reflection in phase period SP(m−Q(1), n) increases. For example, the absolute value of the amount of frequency shift Δ(m, n) may be determined by a function of the degree of reflection.

[0056] There may be cases where one frequency shift increases the degree of reflection of the source radio frequency power RF. In this case, the control unit 35 may set the frequency f(m, n) to a frequency having the other frequency shift relative to the frequency f(m-Q(1), n). Note that the frequency of the source radio frequency power RF in each phase period SP(n) of two or more cycles prior to the cycle CY(m) may be updated to have one frequency shift relative to the frequency of the source radio frequency power RF in the phase period SP(n) of the previous cycle. In this case, if the degree of reflection of the source radio frequency power RF in each phase period SP(n) of the two or more cycles is on the rise, the other frequency shift may be imparted to the frequency of the source radio frequency power RF in the phase period SP(n) of the cycle CY(m). For example, the frequency of the source radio frequency power RF in the phase period SP(n) of the cycle CY(m) may be set to a frequency having the other frequency shift relative to the frequency of the source radio frequency power in the earliest cycle of the two or more cycles.

[0057] If the degree of reflection of the source radio frequency power RF in phase period SP(m,n) increases from the degree of reflection of the source radio frequency power RF in phase period SP(m-Q(1),n) due to one of the frequency shifts, the control unit 35 may set the frequency of the source radio frequency power RF in phase period SP(n) within period CY(m+Q(1)) to an intermediate frequency. Period CY(m+Q(1)) is the third period after period CY(m). The intermediate frequency that can be set in phase period SP(m+Q(1),n) is a frequency between f(m-Q(1),n) and f(m,n), and may be the average value of f(m-Q(1),n) and f(m,n).

[0058] A case may occur in which the degree of reflection of the source radio frequency power RF (e.g., the power level Pr of the reflected wave) when an intermediate frequency is used in the phase period SP(m+Q(1),n) exceeds a predetermined threshold. In this case, the control unit 35 may set the frequency of the source radio frequency power RF in the phase period SP(n) within the cycle CY(m+Q(2)) to a frequency having the other frequency shift with respect to the intermediate frequency. The cycle CY(m+Q(2)) is the fourth cycle after the cycle CY(m+Q(2)). The threshold is predetermined. The absolute value of the other frequency shift amount Δ(m+Q(2),n) is greater than the absolute value of the one frequency shift amount Δ(m,n). In this case, it is possible to avoid a situation in which the reflection amount of the source radio frequency power RF cannot be reduced from a local minimum value. Note that the thresholds for the multiple phase periods SP in each of the multiple cycles CY may be the same or different from each other.

[0059] In a second example, the frequency of the source radio frequency power RF set for each of the phase periods SP(1) to SP(N) of the cycle CY(M) is set to be equal to or greater than the source frequency f ＲＦ It is used as.

[0060] [Source frequency f ＲＦ Third example of adjustment of

[0061] 10 is a flow chart of a third example of the adjustment of the source frequency. In FIG. 3, the third example of the adjustment of the source frequency is shown as an example of the step ST3.

[0062] 10 includes steps STa to STc. In step STa, a basic time series TS, which is a time series of a predetermined frequency, is generated. Ｂ is the source frequency f of the source radio frequency power RF for a plurality of phase periods SP within the cycle CY. ＲＦ That is, the time series of frequencies includes a plurality of frequencies, and the plurality of frequencies are the source frequency f of the source radio frequency power RF in each of the plurality of phase periods SP within the cycle CY. ＲＦThe time series of frequencies can be specified by the control unit 35. Ｂ is the source frequency f ＲＦ This can be prepared by carrying out the first example or the second example of the adjustment in advance.

[0063] 10, the process STb is performed next. In the process STb, the changed time series TS Ｍ That is, the time series TS Ｍ are used as the frequencies of the source radio frequency power RF in each of the phase periods SP within the cycle CY. Ｍ can be specified by the control unit 35. In the step STc, the step STb is repeated so as to reduce the degree of reflection of the source high frequency power RF from the load in accordance with the evaluation value.

[0064] In the process STb, the time series TS Ｍ The time series TS1, TS2, or TS3 is used as the time series TS2. The time series TS1 is a time series TS3 that is obtained by subtracting the phase shift amount from the period CY from the basic time series TS2. Ｂ The time series TS2 is a frequency time series obtained by applying the basic time series TS Ｂ The time series TS3 is a time series of frequencies obtained by scaling (i.e., expanding or contracting) the basic time series TS in the frequency direction. Ｂ The time series TS3 is a time series of frequencies that contains the same number of frequencies as the basic time series TS. Ｂ It is a time series of frequencies obtained by scaling (expanding or contracting) two or more of the multiple time zones in the time direction.

[0065] The evaluation value is determined by the control unit 35 from the above-mentioned measured values. The evaluation value is a single representative value determined from the measured values ​​during the evaluation period. The evaluation period is a period during which each time series of frequencies is continuously used, and may have a time length equal to or longer than the time length of the period CY. The evaluation value may be an integral, average, or peak value of the measured values ​​during the evaluation period or values ​​obtained from the measured values.

[0066] [Source frequency f ＲＦFourth example of adjustment of

[0067] 11 and 12 will be referred to below. Fig. 11 is a flow chart of a fourth example of adjusting the source frequency. Fig. 12 is a diagram for explaining the fourth example shown in Fig. 11. In Fig. 12, the horizontal axis represents time, and the vertical axis represents the electrical bias energy BE and the source frequency f of the source high frequency power RF. ＲＦ 12 shows a waveform of the electrical bias energy BE in a cycle CY. Also, FIG. 12 shows a waveform of the source frequency f of the source radio frequency power RF in each of a plurality of phase periods SP in the cycle CY. ＲＦ The basic time series TS used as Ｂ and the modified time series TS Ｍ 11 can be used as the process ST3 shown in FIG. 10. In the process ST3A, the modified time series TS Ｍ The above-described time series TS1 is used as the time series TS1.

[0068] The process ST3A starts with a process STa11 as shown in FIG. 11. In the process STa11, the basic time series TS Ｂ That is, the basic time series TS Ｂ The multiple frequencies included in are the source frequency f of the source radio frequency power RF for the multiple phase periods SP within the cycle CY. ＲＦ It is used as.

[0069] Next, step STa12 is performed. In step STa12, the basic time series TS Ｂ The control unit 35 determines the evaluation value from the measurement values ​​when the above is used.

[0070] Next, step STp11 is performed. In step STp11, the basic time series TS is calculated for the period CY. Ｂ The time series TS obtained by applying a phase shift to Ｍ is prepared. Ｍ is prepared by the control unit 35.

[0071] Next, step STb11 is performed. In step STb11, the prepared time series TS ＭThat is, the time series TS Ｍ The multiple frequencies included in are the source frequency f of the source radio frequency power RF in each of the multiple phase periods SP in the cycle CY. ＲＦ Then, in step STc1, step STb11 is repeated while changing the amount of phase shift.

[0072] In the process STc1, the process STb12 is performed after the process STb11. In the process STb12, the control unit 35 acquires an evaluation value during the period in which the process STb11 is performed, that is, during the evaluation period.

[0073] After the process STc1, the process STJ11 is subsequently performed. In the process STJ11, it is determined whether or not a termination condition is satisfied. The determination of the process STJ11 is performed by the control unit 35. In the process STJ11, the termination condition is satisfied when the main control unit 2 issues an instruction to terminate the plasma processing.

[0074] If it is determined in process STJ11 that the termination condition is not satisfied, process STJ12 is performed. In process STJ12, it is determined whether the evaluation value acquired in process STb12 is equal to or less than a specified value. The determination of process STJ12 is performed by the control unit 35. The evaluation value being equal to or less than the specified value indicates that the degree of reflection of the source high frequency power RF from the load is sufficiently small. If it is determined in process STJ12 that the evaluation value is equal to or less than the specified value, the processing from process STb11 is repeated. On the other hand, if it is determined in process STJ12 that the evaluation value is greater than the specified value, process STJ13 is performed.

[0075] In step STJ13, the evaluation value acquired in step STb12 is compared with the evaluation value acquired immediately before that to determine whether the degree of reflection of source high frequency power RF from the load has decreased. The determination of step STJ13 is made by the control unit 35. If it is determined in step STJ13 that the degree of reflection of source high frequency power RF from the load has decreased, step STc11 is performed. On the other hand, if it is determined in step STJ13 that the degree of reflection of source high frequency power RF from the load has not decreased, step STc12 is performed.

[0076] In step STc11, the phase shift amount is changed in the same direction as the phase shift amount used immediately before. If the phase shift amount used immediately before is increased compared to the phase shift amount used previously, the phase shift amount is increased in step STc11 as shown by the right-pointing arrow in FIG. 12. If the phase shift amount used immediately before is decreased compared to the phase shift amount used previously, the phase shift amount is decreased in step STc11. Then, the changed phase shift amount is added to the basic time series TS. Ｂ The time series TS obtained by Ｍ is prepared. Ｍ is prepared by the control unit 35. Then, step STb11 is performed again.

[0077] In step STc12, the phase shift amount is changed in the opposite direction to the phase shift amount used immediately before. If the phase shift amount used immediately before is increased compared to the phase shift amount used previously, the phase shift amount is decreased in step STc12 as shown by the left-pointing arrow in FIG. 12. If the phase shift amount used immediately before is decreased compared to the phase shift amount used previously, the phase shift amount is increased in step STc12. Then, the changed phase shift amount is added to the basic time series TS. Ｂ The time series TS obtained by Ｍ is prepared. Ｍ is prepared by the control unit 35. Then, step STb11 is performed again.

[0078] Step STb11 is repeated, and when it is determined in step STJ11 that the termination condition is satisfied, step ST3A is terminated.

[0079] [Source frequency f ＲＦ Fifth example of adjustment of

[0080] 13 to 17 will be referred to below. FIG. 13 is a flow chart of a fifth example of adjusting the source frequency. Each of FIGS. 14 to 17 is a diagram for explaining the fifth example. In each of FIGS. 14 to 17, the horizontal axis represents time, and the vertical axis represents the electrical bias energy BE and the source frequency f of the source high frequency power RF. ＲＦ 14 to 17 show waveforms of the electrical bias energy BE in a cycle CY. Also, each of FIGS. 14 to 17 shows waveforms of the source frequency f of the source radio frequency power RF in each of a plurality of phase periods SP within the cycle CY. ＲＦ The basic time series TS used as Ｂ and the modified time series TS Ｍ 13 can be used as the process ST3 shown in FIG. 10. In the process ST3B, the modified time series TS Ｍ The above-described time series TS2 is used as the time series TS2.

[0081] 13, process ST3B starts with process STa11, similar to process ST3A, followed by process STa12, similar to process ST3A.

[0082] Next, step STp21 is performed. In step STp21, the basic time series TS Ｂ The time series TS obtained by scaling, i.e., expanding or contracting, Ｍ is prepared. Ｍ is prepared by the control unit 35.

[0083] Time series TS prepared in process STp21 Ｍ is a basic time series TS as shown in FIG. Ｂ The lowest frequency f ｍｉｎ While maintaining the basic time series TS Ｂ14 in the frequency direction. In the following description, the time series changed as shown in FIG. 14 is referred to as time series TS21. Ｍ is a basic time series TS as shown in FIG. Ｂ The highest frequency f ｍａｘ While maintaining the basic time series TS Ｂ 15 in the frequency direction. In the following description, the time series changed as shown in FIG. 15 is referred to as a time series TS22. Ｍ As shown in FIG. 16, Ｂ At the specified frequency f ｓｐ While maintaining the following frequency, the basic time series TS Ｂ In the following description, the time series TS prepared in step STp21 may be obtained by scaling the time series TS in the frequency direction. Ｍ is a basic time series TS as shown in FIG. Ｂ At the specified frequency f ｓｐ While maintaining the above frequency, the basic time series TS Ｂ In the following description, the time series changed as shown in FIG. 17 is referred to as time series TS24.

[0084] Next, the step STb21 is performed. In the step STb21, the prepared time series TS is Ｍ That is, the time series TS Ｍ The multiple frequencies included in are the source frequency f of the source radio frequency power RF in each of the multiple phase periods SP in the cycle CY. ＲＦ Then, in step STc2, step STb21 is repeated. In the repetition of step STb21, the control unit 35 uses the basic time series TS Ｂ Change the scaling factor in the frequency direction for

[0085] In the repetition of step STb21, any one of the time series TS21 to TS24 may be used, and the scaling factor may be changed. In the repetition of step STb21, the time series TS21 to TS24 may be used in order while the scaling factor is changed.

[0086] In the process STc2, the process STb22 is performed after the process STb21. The process STb22 is the same as the process STb12.

[0087] In process STc2, process STJ21 is performed after process STb22. In process STJ21, it is determined whether a scaling termination condition is satisfied. The determination of process STJ21 is performed by the control unit 35. In process STJ21, the scaling termination condition is satisfied when process STb21 has been repeated a predetermined number of times.

[0088] If it is determined in step STJ21 that the scaling termination condition is not satisfied, step STc21 is performed. Ｂ The scaling factor in the frequency direction for the time series TS is changed as shown by the arrows in FIGS. 14 to 17. Ｍ is prepared. Ｍ is prepared by the control unit 35. On the other hand, if it is determined in step STJ21 that the scaling termination condition is satisfied, step STd21 is performed.

[0089] In step STd21, a time series TS that minimizes the degree of reflection of the source high frequency power RF is generated. Ｍ The control unit 35 selects the first time series TS based on the obtained evaluation values. Ｍ The multiple frequencies included in are defined as the source frequency f of the source radio frequency power RF in each of the multiple phase periods SP within the cycle CY. ＲＦ After this step STd21, the step ST3B may be ended. Alternatively, the step STe21 may be performed after the step STd21. In the step STe21, the time series TS selected in the step STd21 is used as the time series TS ＭThe process ST3A is performed using the above as a basic time series.

[0090] [Source frequency f ＲＦ Sixth Example of Adjustment

[0091] 18 and 19 will be referred to below. Fig. 18 is a flow chart of a sixth example of adjusting the source frequency. Fig. 19 is a diagram for explaining the sixth example. In Fig. 19, the horizontal axis represents time, and the vertical axis represents the electrical bias energy BE and the source frequency f of the source high frequency power RF. ＲＦ 19 shows the waveform of the electrical bias energy BE in a cycle CY. Also, FIG. 19 shows the waveform of the source frequency f of the source radio frequency power RF in each of a plurality of phase periods SP in the cycle CY. ＲＦ The basic time series TS used as Ｂ and the modified time series TS Ｍ 18 can be used as the process ST3 shown in FIG. 10. In the process ST3C, the modified time series TS Ｍ The above-mentioned time series TS3 is used as the time series TS3.

[0092] The process ST3C starts with a process STp31. Ｂ Then, a process STp32 is performed. In the process STp32, the time series TS that minimizes the degree of reflection of the source high frequency power RF is selected from the plurality of time series used in the process STp31. Ｍ (First time series) is identified based on the multiple evaluation values ​​obtained in step STp31 and selected as the basic time series.

[0093] Next, step STp33 is performed. In step STp33, step ST3B is performed using the basic time series selected in step STp32. Next, step STp34 is performed. In step STp34, the time series TS that minimizes the degree of reflection of the source high frequency power RF is selected from the multiple time series used in step STp33. Ｍ (second time series) is identified based on the multiple evaluation values ​​obtained in step STp33 and selected as the basic time series.

[0094] Next, step STp35 is executed. In step STp35, two or more of the time zones of the basic time series selected in step STp34 are scaled (enlarged or reduced) in the time direction to obtain the basic time series TS. Ｂ The modified time series TS contains the same number of frequencies as Ｍ In step STp35, the time series TS Ｍ is prepared by the control unit 35. Note that instead of the steps STp31 to STp34, steps STa11 and STa12 are performed, and in step STp35, the basic time series TS Ｂ Time series TS Ｍ may be prepared.

[0095] The plurality of time zones may include zones Z1 to Z6 as shown in Fig. 19. To determine the zones Z1 to Z6, the lowest frequency f of the basic time series used in step STp35 is ｍｉｎ , highest frequency f ｍａｘ , and the average frequency f ａｖｅ Then, the lowest frequency f included in the fundamental time series is identified. ｍｉｎ and maximum frequency f ｍａｘ The difference between the minimum frequency f ｍｉｎ to the minimum frequency f ｍｉｎ The time zone corresponding to the range up to the sum of the maximum frequency f and 10% of the frequency width is determined as zone Z2. ｍａｘ The maximum frequency f is calculated by subtracting 10% of the frequency width from ｍａｘ The time zone corresponding to the range from the start of the cycle CY to the start of the zone Z2 is determined as the zone Z1. The time zone corresponding to the range from the end of the zone Z2 to the average frequency f ａｖｅ The time zone up to the point corresponding to the average frequency f is determined as the zone Z3. ａｖｅ The time zone from the time corresponding to the period CY to the start of the zone Z5 is determined as the zone Z4. The time zone from the end of the zone Z5 to the end of the period CY is determined as the zone Z6.

[0096] In step STp35, the zone Z2 of the basic time series may be expanded in the time direction. Ｂ The modified time series TS contains the same number of frequencies as Ｍ Zones Z1 and Z3 of the base time series may be compressed in time to generate

[0097] Next, the step STb31 is performed. In the step STb31, the prepared time series TS is Ｍ That is, the time series TS Ｍ The multiple frequencies included in are the source frequency f of the source radio frequency power RF in each of the multiple phase periods SP in the cycle CY. ＲＦ Then, in step STc3, step STb31 is repeated. In the repetition of step STb31, the control unit 35 changes the scaling factor in the time direction for two or more of the multiple time zones of the basic time series.

[0098] In process STc3, process STb32 is performed after process STb31. Process STb32 is the same as process STb12. Next, process STJ31 is performed. In process STJ31, it is determined whether a scaling termination condition is satisfied. In process STJ31, the scaling termination condition is satisfied when process STb31 has been repeated a predetermined number of times.

[0099] If it is determined in step STJ31 that the scaling termination condition is not satisfied, step STc31 is performed. In step STc31, the scaling magnification in the time direction of two or more of the multiple time zones of the basic time series is changed, thereby Ｍ is prepared. Ｍ is prepared by the control unit 35. The prepared time series TS Ｍ is used in step STb31. On the other hand, if it is determined in step STJ31 that the scaling termination condition is satisfied, step STd31, which will be described later, is performed.

[0100] In the repetition of step STb31, similarly to step STp35, zone Z2 of the basic time series may be expanded in the time direction, and zones Z1 and Z3 of the basic time series may be contracted in the time direction while changing the scaling factor of zone Z2 in the time direction. This process is performed until it is determined from the evaluation value acquired in step STb32 that the degree of reflection of the source high frequency power RF is no longer decreasing.

[0101] Next, in repeating step STb31, zone Z5 of the basic time series may be expanded in the time direction, and zones Z4 and Z6 of the basic time series may be contracted in the time direction while changing the scaling factor of zone Z5 in the time direction. This process is performed until it is determined from the evaluation value acquired in step STb32 that the degree of reflection of the source high frequency power RF is no longer decreasing.

[0102] In step STd31, a time series TS that minimizes the degree of reflection of the source high frequency power RF is selected from the multiple evaluation values ​​obtained in step STc3. Ｍ is identified and selected as the third time series. The selection of the third time series in step STd31 is performed by the control unit 35. Then, the multiple frequencies included in the selected time series (third time series) are determined to be the source frequencies f of the source radio frequency power RF in each of the multiple phase periods SP within the cycle CY. ＲＦ The third time series may be used as a basic time series, and the processing from step STp31 onwards may be repeated.

[0103] [Source frequency f ＲＦ Seventh Example of Adjustment

[0104] Reference will now be made to Figures 20(a), 20(b), 21(a), 21(b), and 22. Figures 20(a), 20(b), 21(a), and 21(b) are timing charts showing examples of source RF power and electrical bias energy. Figure 22 is a timing chart related to a seventh example of source frequency adjustment. In these figures, "ON" for source RF power RF indicates that source RF power RF is being supplied to the RF electrode, and "OFF" for source RF power RF indicates that the supply of source RF power RF is stopped. "HIGH" for source RF power RF indicates that source RF power RF having a level higher than the level of source RF power RF indicated by "LOW" is being supplied to the RF electrode. Furthermore, "ON" for electrical bias energy BE indicates that electrical bias energy BE is being applied to the bias electrode, and "OFF" for electrical bias energy BE indicates that electrical bias energy BE is not being applied to the bias electrode. Furthermore, "HIGH" for the electric bias energy BE indicates that electric bias energy BE having a level higher than the level of the electric bias energy BE indicated by "LOW" is being applied to the bias electrode.

[0105] In any of the examples of Figures 20(a), 20(b), 21(a), and 21(b), the electrical bias energy BE is supplied to the bias electrode as an ON / OFF pulse or a HIGH / LOW pulse. The frequency of the ON / OFF pulse or the HIGH / LOW pulse is lower than the bias frequency, for example, not less than 1 kHz and not more than 100 kHz.

[0106] The bias power supply 32 supplies electric bias energy BE in an ON or HIGH state during a period in which the first control signal provided from the main controller 2 has a first state (e.g., an ON state). The bias power supply 32 sets the electric bias energy BE to an OFF or LOW state during a period in which the first control signal has a second state (e.g., an OFF state). The period in which the first control signal has the first state may or may not be synchronized with the first clock signal.

[0107] When the period during which the first control signal has the first state and the first clock signal are not synchronized, the supply of the electric bias energy BE in the ON or HIGH state may be started at a timing designated by the first clock signal immediately after the state of the first control signal becomes the first state. On the other hand, when the period during which the first control signal has the first state and the first clock signal are synchronized, the bias power supply 32 starts supplying the electric bias energy BE when the state of the first control signal becomes the first state.

[0108] The bias power supply 32 may set the electric bias energy BE to the OFF or LOW state when the state of the first control signal changes from the first state to the second state, or the bias power supply 32 may set the electric bias energy BE to the OFF or LOW state at the timing when the period CY of the ongoing electric bias energy BE ends when the state of the first control signal changes from the first state to the second state.

[0109] As shown in Figure 20(a), the source radio frequency power RF may be supplied to the radio frequency electrode as a continuous wave. In the example shown in Figure 20(a), the source radio frequency power RF and the ON or HIGH state electrical bias energy BE are supplied simultaneously in multiple overlapping periods OP.

[0110] Alternatively, as shown in Figures 20(b), 21(a), and 21(b), the source radio frequency power RF may be supplied to the radio frequency electrode as an ON / OFF pulse or a HIGH / LOW pulse. The radio frequency power supply 31 supplies the source radio frequency power RF in an ON or HIGH state during a period in which the second control signal provided by the main controller 2 is in a first state (e.g., an ON state). Note that if the second control signal becomes the first state during a period in which the electrical bias energy BE is being supplied, the radio frequency power supply 31 may start supplying the source radio frequency power RF in an ON or HIGH state in synchronization with the first cycle CY of the electrical bias energy BE after the second control signal becomes the first state. Furthermore, the radio frequency power supply 31 sets the source radio frequency power RF to an OFF or LOW state during a period in which the second control signal is in a second state (e.g., an OFF state).

[0111] 20(b), the period during which the pulse of the electrical bias energy BE is supplied and the period during which the pulse of the source radio frequency power RF is supplied may be the same, in which case the multiple overlap periods OP coincide with the period during which the pulse of the electrical bias energy BE is supplied and with the period during which the pulse of the source radio frequency power RF is supplied.

[0112] 21(a) and 21(b), each of the multiple periods during which a pulse of source radio frequency power RF is supplied may partially overlap one of the multiple periods during which a pulse of electrical bias energy BE is supplied, i.e., each of the multiple overlap periods OP is a portion of the period during which a pulse of source radio frequency power RF is simultaneously supplied within the period during which a pulse of electrical bias energy BE is supplied.

[0113] As shown in (a) of Figure 21, if the source radio frequency power RF is being supplied when the supply of the pulse of the electrical bias energy BE starts, the level of the electrical bias energy BE may be set to a low level until the timing specified by the first clock signal for the first time after the state of the first control signal becomes the first state. Also, as shown in (a) of Figure 21, the level of the electrical bias energy BE may be set to a low level immediately after the overlap period OP.

[0114] In the following description, overlap period OP(k) represents the kth overlap period among the multiple overlap periods OP. That is, overlap period OP(k) represents any overlap period among the multiple overlap periods OP. The multiple overlap periods OP include multiple (M) cycles CY. Each cycle CY includes multiple (N) phase periods SP. Cycle CY(m) represents the mth cycle among the multiple cycles CY in each of the multiple overlap periods OP. Furthermore, cycle CY(k, m) represents the mth cycle within the kth overlap period.

[0115] Source frequency f ＲＦ In the seventh example of the adjustment, the control unit 35 adjusts the source frequency f of the source radio frequency power RF in each of the plurality of phase periods SP in each of the plurality of cycles CY included in each of the plurality of overlap periods OP. ＲＦ is adjusted.

[0116] First, the setting of the frequency of the source radio frequency power RF in the first overlap period OP, i.e., overlap period OP(1), will be described below. The control unit 35 sets the source frequency f of the source radio frequency power RF in the phase period SP(1, m, n) in the cycle CY(1, m) in the overlap period OP(1). ＲＦ is adjusted according to the change in the representative value RV(n). Note that the phase period SP(k, m, n) represents the nth phase period SP in the cycle CY(k, m) within the kth overlap period OP(k). The adjustment of the frequency of the source radio frequency power RF in the phase period SP(1, m, n) is performed by adjusting the source frequency f of the source radio frequency power RF in the phase period SP(m, n) in the second example. ＲＦ This is the same process as the adjustment of

[0117] Hereinafter, the source frequency f of the source radio frequency power RF in the second to (T-1) overlapping periods OP(k) ＲＦ Here, T is an integer equal to or greater than 3 and smaller than K. The source frequency f of the source radio frequency power RF in the multiple phase periods SP in the multiple cycles CY within the overlap period OP(k) is set as follows: ＲＦ is the source frequency f of the source radio frequency power RF in the multiple phase periods SP in the multiple cycles CY within the overlap period OP(1). ＲＦ The source frequency f of the source radio frequency power RF in the multiple phase periods SP in the cycle CY(1) in the overlap period OP(k) may be set using the same setting process as the setting process described above. ＲＦ In setting the frequency of the source radio frequency power RF in the plurality of phase periods SP in CY(2) within the overlap period OP(k), the period CY(M-1) within the overlap period OP(k-1) and the period CY(M) within the overlap period OP(k-1) may be used as the first period and the second period. In setting the frequency of the source radio frequency power RF in the plurality of phase periods SP in CY(2) within the overlap period OP(k), the period CY(M) within the overlap period OP(k-1) and the period CY(1) within the overlap period OP(k) may be used as the first period and the second period.

[0118] Alternatively, the source frequency f of the source radio frequency power RF in the multiple phase periods SP in the multiple cycles CY within the overlap period OP(k) ＲＦ may be set using each frequency registered in a table prepared in advance.

[0119] Referring to FIG. 22, the source frequency f of the source radio frequency power RF in the Tth to Kth overlapping periods OP(k) is ＲＦ The control unit 35 sets the source frequency f of the source radio frequency power RF in the phase period SP(n) in the cycle CY(m) in the overlap period OP(k), i.e., in the phase period SP(k, m, n). ＲＦ The change in the representative value RV(n) is adjusted according to the change in the source frequency f of the source radio frequency power RF that differs from each other in the corresponding phase period SP(n) in the period CY(m) in two or more overlap periods OP before the overlap period OP(k). ＲＦ It is identified by using

[0120] The two or more overlap periods OP before the overlap period OP(k) include a first overlap period and a second overlap period. The first overlap period is overlap period OP(k-Q(2)), and the second overlap period is the overlap period after the first overlap period and is overlap period OP(k-Q(1)). Q(1) is an integer greater than or equal to 1, Q(2) is an integer greater than or equal to 2, and Q(1)<Q(2) is satisfied.

[0121] The control unit 35 imparts one frequency shift from the frequency of the source radio frequency power RF in the phase period SP(k-Q(1),m,n) to the frequency f(k-Q(1),m,n) of the source radio frequency power RF in the phase period SP(k-Q(2),m,n). Here, f(k,m,n) represents the frequency of the source radio frequency power RF used in the phase period SP(k,m,n). f(k,m,n) is expressed as f(k,m,n) = f(k-Q(1),m,n) + Δ(k,m,n). Δ(k,m,n) represents the amount of the frequency shift. One frequency shift is either a frequency decrease or a frequency increase. If one frequency shift is a frequency decrease, Δ(k,m,n) has a negative value. If one frequency shift is a frequency increase, Δ(k,m,n) has a positive value.

[0122] The control unit 35 determines whether the degree of reflection of the source high frequency power RF (e.g., the power level Pr of the reflected wave) due to the frequency shift increases or decreases from the change between the representative value RV(k-Q(2),m,n) and the representative value RV(k-Q(1),m,n). If the degree of reflection of the source high frequency power RF decreases due to one frequency shift, the control unit 35 sets the frequency f(k,m,n) to a frequency that has one frequency shift relative to the frequency f(k-Q(1),m,n). Note that RV(k,m,n) represents the representative value RV in the phase period SP(k,m,n).

[0123] The frequency of the source radio frequency power RF in each phase period SP(m,n) of two or more overlap periods prior to the overlap period OP(k) may be updated to have one frequency shift relative to the frequency of the source radio frequency power RF in the phase period SP(m,n) of the previous overlap period. In this case, if the degree of reflection of the source radio frequency power RF in each phase period SP(m,n) of the two or more overlap periods is tending to increase, the other frequency shift may be imparted to the frequency of the source radio frequency power RF in the phase period SP(m,n) of the overlap period OP(k). For example, the frequency of the source radio frequency power RF in the phase period SP(m,n) of the overlap period OP(k) may be set to a frequency having the other frequency shift relative to the frequency of the source radio frequency power RF in the earliest overlap period of the two or more overlap periods.

[0124] One amount of frequency shift Δ(m,n) in phase period SP(k,m,n) may be the same as one amount of frequency shift Δ(k−Q(1),m,n) in phase period SP(k−Q(1),m,n). That is, the absolute value of the amount of frequency shift Δ(k,m,n) may be the same as the amount of frequency shift Δ(k−Q(1),m,n). Alternatively, the absolute value of the amount of frequency shift Δ(k,m,n) may be greater than the amount of frequency shift Δ(k−Q(1),m,n). Alternatively, the absolute value of the amount of frequency shift Δ(k,m,n) may be set to increase as the degree of reflection in phase period SP(k−Q(1),m,n) increases. For example, the absolute value of the amount of frequency shift Δ(k,m,n) may be determined by a function of the degree of reflection.

[0125] There may be cases where one frequency shift causes the degree of reflection of the source high frequency power RF in the phase period SP(k-Q(1), m, n) to increase from the degree of reflection of the source high frequency power RF in the phase period SP(k-Q(2), m, n). In this case, the control unit 35 may set the frequency f(k, m, n) to a frequency that has the other frequency shift relative to the frequency f(k-Q(1), m, n).

[0126] Furthermore, one of the frequency shifts may cause the degree of reflection of the source radio frequency power RF in the phase period SP(k, m, n) to increase from the degree of reflection of the source radio frequency power RF in the phase period SP(k-Q(1), m, n). In this case, the control unit 35 may set the frequency of the source radio frequency power RF in the phase period SP(k+Q(1), m, n) to an intermediate frequency. That is, in this case, the frequency of the source radio frequency power RF in the phase period SP(n) in the cycle CY(m) within the overlap period OP(k+Q(1)) may be set to an intermediate frequency. The overlap period OP(k+Q(1)) is the third overlap period after the overlap period OP(k). The intermediate frequency that can be set in the phase period SP(k+Q(1),m,n) is a frequency between f(k-Q(1),m,n) and f(k,m,n), and may be the average value of f(k-Q(1),m,n) and f(k,m,n).

[0127] Furthermore, when an intermediate frequency is used in the phase period SP(k+Q(1),m,n), the degree of reflection of the source radio frequency power RF may exceed a predetermined threshold. In this case, the control unit 35 may set the frequency of the source radio frequency power RF in the phase period SP(k+Q(2),m,n) to a frequency having the other frequency shift relative to the intermediate frequency. That is, in this case, the other frequency shift may be imparted to the frequency of the source radio frequency power RF in the phase period SP(n) in the cycle CY(m) within the overlap period OP(k+Q(2)). The overlap period OP(k+Q(2)) is the fourth overlap period after the overlap period OP(k+Q(1)). The threshold is set in advance. The absolute value of the other frequency shift amount Δ(k+Q(2),m,n) is greater than the absolute value of one frequency shift amount Δ(k,m,n). In this case, it is possible to prevent the reflection amount of the source radio frequency power RF from being unable to decrease from a local minimum value. The threshold values ​​for the multiple phase periods SP in each of the multiple cycles CY within the multiple overlap periods OP may be the same as or different from each other.

[0128] The source frequency f of the source radio frequency power RF supplied during periods other than the multiple overlap periods OP ＲＦmay be fixed. Alternatively, multiple overlap periods OP may be used, similar to multiple overlap periods OP. ＨＬ Even in this case, the source frequency f of the source high frequency power RF ＲＦ may be adjusted. ＨＬ is a period during which the source radio frequency power RF in a HIGH or ON state and the electrical bias energy BE in a LOW state are simultaneously supplied. ＬＬ Even in this case, the source frequency f of the source high frequency power RF ＲＦ may be adjusted. ＬＬ is a period during which the source radio frequency power RF in a low state and the electrical bias energy BE in a low state are simultaneously supplied. ＬＨ Even in this case, the source frequency f of the source high frequency power RF ＲＦ may be adjusted. ＬＨ is a period during which the source radio frequency power RF in the LOW state and the electrical bias energy BE in the HIGH state are supplied simultaneously.

[0129] [Source frequency f ＲＦ Eighth Example of Adjustment

[0130] In the eighth example, the source frequency f of the source radio frequency power RF for each of the plurality of phase periods SP of each cycle CY is ＲＦ Specifically, in each phase period SP within the cycle CY, the frequency determined by adding each of the multiple frequency offsets and the reference frequency is equal to the source frequency f of the source radio frequency power RF. ＲＦEach of the multiple frequency offsets has a positive or negative value. Then, a frequency offset for each phase period SP that maximizes the power level of the source high frequency power RF delivered to the plasma is determined. The power level of the source high frequency power RF delivered to the plasma may be the difference between the power level of the forward wave and the power level of the reflected wave of the source high frequency power RF. The frequency offsets determined for each of the multiple phase periods SP are stored in a table. The control unit 35 calculates, in each phase period SP within each cycle CY, a frequency determined by adding the reference frequency and the corresponding frequency offset stored in the table as the source frequency f of the source high frequency power RF. ＲＦ Used as.

[0131] Although various exemplary embodiments have been described above, the present invention is not limited to the above-described exemplary embodiments, and various additions, omissions, substitutions, and modifications may be made. Furthermore, elements in different embodiments may be combined to form other embodiments.

[0132] In other embodiments, the plasma processing apparatus may be an inductively coupled plasma processing apparatus, an ECR plasma processing apparatus, a helicon wave excited plasma processing apparatus, or a surface wave plasma processing apparatus, in which source radio frequency power RF is used to generate the plasma.

[0133] Various exemplary embodiments included in the present disclosure are now described in [E1] to [E16] below.

[0134] [E1] A plasma processing apparatus comprising: a chamber; a substrate support provided within the chamber; a bias power supply electrically coupled to the substrate support and configured to generate electrical bias energy having a bias frequency at a timing specified by a first clock signal; and a radio frequency power supply configured to generate source radio frequency power having a source frequency to generate plasma from a gas in the chamber, wherein the radio frequency power supply is configured to output the source radio frequency power having the source frequency adjusted at a timing specified by a second clock signal when the electrical bias energy is supplied to the substrate support, and the second clock signal has a frequency higher than the bias frequency and is synchronized to the first clock signal.

[0135] In the embodiment of E1, the source frequency of the source radio frequency power is adjusted at multiple phases within a period of the electrical bias energy. The timing at which the source frequency of the source radio frequency power is adjusted is specified by a second clock signal. The second clock signal is synchronized with a first clock signal that specifies the timing at which the electrical bias energy is generated. Therefore, according to the embodiment of E1, it is possible to accurately synchronize the phase within a period of the electrical bias energy and the timing at which the source frequency of the source radio frequency power is adjusted.

[0136] [E2] The plasma processing apparatus of E1, further comprising: a reference clock signal generator configured to generate a reference clock signal; and a frequency divider configured to generate the second clock signal by dividing the frequency of the reference clock signal, wherein the first clock signal is the reference clock signal or is generated by dividing the frequency of the reference clock signal in another frequency divider.

[0137] [E3] The plasma processing apparatus according to E2, wherein the divider and / or the other divider that generates the second clock signal includes a PLL circuit that is a frequency multiplier, and a divider connected between a reference input of the PLL circuit and an output of the reference clock signal generator.

[0138] [E4] The plasma processing apparatus according to E2 or E3, further comprising: a sensor configured to output an electrical signal reflecting a degree of reflection of the source high frequency power from a load; and an analog-to-digital converter connected to the output of the sensor, wherein the analog-to-digital converter is configured to perform analog-to-digital conversion on the electrical signal to generate a digital signal at a timing specified by a third clock signal, and the third clock signal is the reference clock signal or is generated by dividing the reference clock signal by another frequency divider.

[0139] [E5] The plasma processing apparatus according to E4, wherein the frequency divider that generates the third clock signal includes a PLL circuit that is a frequency multiplier, and a frequency divider connected between the output of the reference clock signal generator and a reference input of the PLL circuit.

[0140] [E6] The plasma processing apparatus described in E4 or E5, further comprising a control unit configured to generate a representative value from the digital signal in each of a plurality of phase periods synchronized with the second clock signal, and to set the source frequency of the source high frequency power so as to suppress reflection of the source high frequency power based on the representative value in each of the plurality of phase periods.

[0141] [E7] The plasma processing apparatus according to any one of E2 to E6, wherein the high frequency power supply includes: a digital-to-analog converter configured to perform digital-to-analog conversion of waveform data of the source high frequency power at a timing specified by a fourth clock signal synchronized with the first clock signal; and an amplifier connected to the output of the digital-to-analog converter and configured to output the source high frequency power, and the fourth clock signal is the reference clock signal or is generated by dividing the reference clock signal in another frequency divider.

[0142] [E8] The plasma processing apparatus according to E7, wherein the frequency divider that generates the fourth clock signal includes a PLL circuit that is a frequency multiplier, and a frequency divider connected between an output of the reference clock signal generator and a reference input of the PLL circuit.

[0143] [E9] The plasma processing apparatus according to any one of E2 to E8, wherein the electric bias energy is a bias high frequency power having the bias frequency or a voltage generated periodically at a time interval that is the reciprocal of the bias frequency, and the bias power supply includes: a digital-to-analog converter configured to perform digital-to-analog conversion of waveform data of the electric bias energy at a timing specified by the first clock signal; and an amplifier connected to the output of the digital-to-analog converter of the bias power supply and configured to output the electric bias energy.

[0144] [E10] The plasma processing apparatus according to any one of E2 to E8, wherein the electrical bias energy is a voltage pulse generated periodically at a time interval that is the reciprocal of the bias frequency, and the bias power supply includes: a DC power supply; and a pulse unit configured to couple the DC power supply to an output of the bias power supply at one of the rising and falling edges of the first clock signal, and to connect the output of the bias power supply to ground at the other of the rising and falling edges.

[0145] [E11] A control method comprising: (a) a step of supplying electric bias energy having a bias frequency from a bias power supply to a substrate support provided in a chamber of a plasma processing apparatus; and (b) a step of supplying source high frequency power having a source frequency from a high frequency power supply to generate plasma from a gas in the chamber, wherein in (a), the electric bias energy is generated at a timing specified by a first clock signal; and while the electric bias energy is being supplied to the substrate support, in (b), the high frequency power supply outputs the source high frequency power having the adjusted source frequency at a timing specified by a second clock signal, and the second clock signal has a frequency higher than the bias frequency and is synchronized with the first clock signal.

[0146] [E12] The control method according to E11, wherein the second clock signal is generated by dividing a reference clock signal generated by a reference clock signal generator using a divider, and the first clock signal is the reference clock signal or is generated by dividing the reference clock signal in another divider.

[0147] [E13] A power supply system comprising: a bias power supply configured to generate electrical bias energy supplied to a substrate support provided in a chamber of a plasma processing apparatus at a timing specified by a first clock signal; and a radio frequency power supply configured to generate source radio frequency power for generating plasma from a gas in the chamber, wherein the radio frequency power supply is configured to output the source radio frequency power having a source frequency adjusted at a timing specified by a second clock signal when the electrical bias energy is supplied to the substrate support, and the second clock signal has a frequency higher than the bias frequency of the electrical bias energy and is synchronized with the first clock signal.

[0148] [E14] The power supply system according to E13, further comprising: a reference clock signal generator configured to generate a reference clock signal; and a frequency divider configured to generate the second clock signal by dividing the frequency of the reference clock signal, wherein the first clock signal is the reference clock signal or is generated by dividing the frequency of the reference clock signal in another frequency divider.

[0149] [E15] A program executed by a computer of a plasma processing apparatus to cause the plasma processing apparatus to execute the control method according to E11.

[0150] [E16] A storage medium storing the program according to E15.

[0151] From the foregoing, it will be understood that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

[0152] 1... plasma processing apparatus, 10... chamber, 11... substrate support part, 30... power supply system, 31... high frequency power supply, 32... bias power supply

Claims

1. A chamber; a substrate support disposed within the chamber; a bias power supply electrically coupled to the substrate support and configured to generate electrical bias energy having a bias frequency at a timing dictated by a first clock signal; a radio frequency power source configured to generate a source radio frequency power having a source frequency to generate a plasma from the gas in the chamber; a reference clock signal generator configured to generate a reference clock signal; a frequency divider configured to generate a second clock signal by dividing the frequency of the reference clock signal; Equipped with the first clock signal is the reference clock signal or is generated by dividing the reference clock signal in a separate divider; the high frequency power source is configured to output the source high frequency power having the source frequency adjusted at a timing specified by the second clock signal when the electrical bias energy is supplied to the substrate support; the second clock signal has a frequency higher than the bias frequency and is synchronized to the first clock signal; Plasma processing equipment.

2. 2. The plasma processing apparatus of claim 1, wherein the divider and / or the another divider that generates the second clock signal includes a PLL circuit that is a frequency multiplier, and a divider connected between a reference input of the PLL circuit and an output of the reference clock signal generator.

3. a sensor configured to output an electrical signal reflective of a degree of reflection of the source radio frequency power from a load; an analog-to-digital converter connected to an output of the sensor; Further comprising: the analog-to-digital converter is configured to perform analog-to-digital conversion on the electrical signal to generate a digital signal at a timing designated by a third clock signal; the third clock signal is the reference clock signal or is generated by dividing the reference clock signal by another frequency divider; The plasma processing apparatus according to claim 1 .

4. 4. The plasma processing apparatus of claim 3, wherein the frequency divider generating the third clock signal includes a PLL circuit that is a frequency multiplier, and a frequency divider connected between an output of the reference clock signal generator and a reference input of the PLL circuit.

5. 4. The plasma processing apparatus of claim 3, further comprising a control unit configured to generate a representative value from the digital signal in each of a plurality of phase periods synchronized with the second clock signal, and to set the source frequency of the source high frequency power so as to suppress reflection of the source high frequency power based on the representative value in each of the plurality of phase periods.

6. The high frequency power source is a digital-to-analog converter configured to perform digital-to-analog conversion of the waveform data of the source high frequency power at a timing designated by a fourth clock signal synchronized with the first clock signal; an amplifier connected to an output of the digital-to-analog converter and configured to output the source radio frequency power; Including, the fourth clock signal is the reference clock signal or is generated by dividing the reference clock signal in another frequency divider; The plasma processing apparatus according to any one of claims 1 to 5.

7. 7. The plasma processing apparatus of claim 6, wherein the frequency divider generating the fourth clock signal includes a PLL circuit that is a frequency multiplier, and a frequency divider connected between an output of the reference clock signal generator and a reference input of the PLL circuit.

8. the electrical bias energy is a bias radio frequency power having the bias frequency or a voltage periodically generated at a time interval that is the inverse of the bias frequency; The bias power supply includes: a digital-to-analog converter configured to perform digital-to-analog conversion of the waveform data of the electrical bias energy at a timing designated by the first clock signal; an amplifier connected to an output of the digital-to-analog converter of the bias power supply and configured to output the electrical bias energy; Including, The plasma processing apparatus according to any one of claims 1 to 5.

9. the electrical bias energy being pulses of voltage generated periodically at a time interval that is the inverse of the bias frequency; The bias power supply includes: A DC power source; a pulse unit configured to couple the DC power supply to an output of the bias power supply at one of a rising edge and a falling edge of the first clock signal, and to connect the output of the bias power supply to ground at the other of the rising edge and the falling edge; Including, The plasma processing apparatus according to any one of claims 1 to 5.

10. (a) providing electrical bias energy having a bias frequency from a bias power supply to a substrate support disposed within a chamber of a plasma processing apparatus; (b) providing a source radio frequency power having a source frequency from a radio frequency power source to generate a plasma from the gas in the chamber; Including, In the step (a), the electrical bias energy is generated at a timing designated by a first clock signal; When the electrical bias energy is supplied to the substrate support, in (b), the high frequency power supply outputs the source high frequency power having the source frequency adjusted at a timing designated by a second clock signal; the second clock signal has a frequency higher than the bias frequency and is synchronized to the first clock signal; the second clock signal is generated by dividing a reference clock signal generated by a reference clock signal generator using a frequency divider; the first clock signal is the reference clock signal or is generated by dividing the reference clock signal in a separate divider; Control methods.

11. a bias power supply configured to generate electrical bias energy supplied to a substrate support disposed within a chamber of the plasma processing apparatus at a timing designated by a first clock signal; a radio frequency power source configured to generate a source radio frequency power to generate a plasma from a gas in the chamber; a reference clock signal generator configured to generate a reference clock signal; a frequency divider configured to generate a second clock signal by dividing the frequency of the reference clock signal; Equipped with the first clock signal is the reference clock signal or is generated by dividing the reference clock signal in a separate divider; the high frequency power source is configured to output the source high frequency power having a source frequency timed according to a second clock signal when the electrical bias energy is supplied to the substrate support; the second clock signal has a frequency higher than a bias frequency of the electrical bias energy and is synchronized to the first clock signal; Power supply system.

12. A program executed by a computer of a plasma processing apparatus to cause the plasma processing apparatus to execute the control method according to claim 10.

13. A storage medium storing the program according to claim 12.