Semiconductor apparatus

Abstract

This semiconductor apparatus comprises: a plurality of first switching elements which are lined up in a Y direction and include first gate wires extending in an X direction; and a back gate guard ring that surrounds the plurality of first switching elements. The plurality of first switching elements, in a state of being connected to each other in parallel, connect an output pad and a ground pad. From among the plurality of first switching elements, at least one first switching element which is disposed between first edge switching elements disposed at the two edges thereof in the Y direction forms a first driver switching element. The first gate wires of the first switching elements other than said first switching element are connected to the ground pad so as to form a first protection switching element.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Some semiconductor devices have a protection circuit for electrostatic discharge (ESD). The protection circuit is configured, for example, with a metal-oxide-semiconductor field-effect transistor (MOSFET) (see, for example, Patent Document 1).

[0003] JP 2014-241497 A

[0004] Some protection circuits are composed of multiple MOS transistors. In such protection circuits, variations in the operation timing of the multiple MOS transistors can occur. Such variations can lead to current concentration in the faster-operating MOS transistors, which can damage the MOS transistors.

[0005] A semiconductor device according to one aspect of the present disclosure includes a plurality of first switching elements, each composed of a MOSFET, arranged side by side in a first direction and having a first gate wiring extending in a second direction intersecting the first direction, and a back gate guard ring surrounding the plurality of first switching elements, wherein three or more of the first switching elements are provided, the plurality of first switching elements being connected in parallel with each other and between a first pad and a second pad, at least one of the plurality of first switching elements arranged between first end switching elements arranged at both ends in the first direction is a driver switching element, and the first switching elements of the plurality of first switching elements other than the driver switching element are first protection switching elements, the first gate wiring of which is connected to the first pad or the second pad.

[0006] A semiconductor device according to one aspect of the present disclosure can suppress current concentration.

[0007] FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device of a first embodiment. FIG. 2 is a circuit diagram showing the driver switching element and the protection switching element of FIG. 1. FIG. 3 is a circuit diagram showing the driver switching element and the protection switching element of FIG. 1. FIG. 4 is a schematic cross-sectional view illustrating the operation of the protection element. FIG. 5 is a schematic plan view showing the driver switching element and the protection switching element of FIG. 2. FIG. 6 is a cross-sectional view taken along line F6-F6 of FIG. 5, illustrating the operation of a first switching element in the semiconductor device of FIG. 1. FIG. 7 is a schematic cross-sectional view illustrating the operation of a first switching element in a semiconductor device of a comparative example. FIG. 8 is a block diagram showing a semiconductor device of a second embodiment. FIG. 9 is a circuit diagram showing the driver switching element and the protection switching element of FIG. 8. FIG. 10 is a circuit diagram showing the driver switching element and the protection switching element of FIG. 8. FIG. 11 is a schematic plan view showing the driver switching element and the protection switching element of FIG. 9. FIG. 12 is a circuit diagram showing a driver switching element and a protection switching element of a modified example. FIG. 13 is a circuit diagram showing a driver switching element and a protection switching element of a modified example.

[0008] Hereinafter, embodiments of a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Furthermore, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and are not used to rank the objects.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B." (First Embodiment) Hereinafter, a first embodiment will be described with reference to FIGS.

[0011] 1, the semiconductor device 10 includes an internal circuit 11 and an output circuit 12. The semiconductor device 10 includes an output pad 22 as a first pad, and a power supply pad 21 and a ground pad 23 as second pads.

[0012] The internal circuit 11 includes a logic circuit that performs operations for functions provided by the semiconductor device 10. The internal circuit 11 is connected between a power supply pad 21 and a ground pad 23. The power supply pad 21 is configured so that a power supply voltage VDD can be supplied from outside the semiconductor device 10. The ground pad 23 is configured so that it can be connected to a ground potential GND. The internal circuit 11 operates using the supplied power supply voltage VDD. The internal circuit 11 outputs an output signal SO based on a logical operation.

[0013] An output terminal of the internal circuit 11 is connected to an output pad 22 via an output circuit 12. The output pad 22 is configured to be connectable to other semiconductor devices, etc. The output circuit 12 outputs an output signal OUT to the output pad 22, which serves as a first pad. The output circuit 12 of the first embodiment outputs the output signal OUT in response to an output signal SO.

[0014] The output circuit 12 includes an output buffer circuit 13 and a protection circuit 16. The output buffer circuit 13 includes a first driver switching element 14 and a second driver switching element 15. The first driver switching element 14 and the second driver switching element 15 are configured with MOS transistors (MOSFETs). The first driver switching element 14 in the first embodiment is an N-channel MOS transistor (hereinafter referred to as an "NMOS transistor"). The second driver switching element 15 in the first embodiment is a P-channel MOS transistor (hereinafter referred to as a "PMOS transistor"). Therefore, the output buffer circuit 13 in the first embodiment is an inverter circuit with a CMOS configuration.

[0015] The first driver switching element 14 is connected between the output pad 22 and the ground pad 23. The source terminal of the first driver switching element 14 is connected to the ground pad 23. The drain terminal of the first driver switching element 14 is connected to the output pad 22. The gate terminal (control terminal) of the first driver switching element 14 is supplied with an output signal SO.

[0016] The second driver switching element 15 is connected between the power supply pad 21 and the output pad 22. The source terminal of the second driver switching element 15 is connected to the power supply pad 21. The drain terminal of the second driver switching element 15 is connected to the output pad 22. The gate terminal (control terminal) of the second driver switching element 15 is supplied with the output signal SO.

[0017] The protection circuit 16 includes a first protection element 17 and a second protection element 18. The first protection element 17 is connected between an output pad 22 and a ground pad 23. The second protection element 18 is connected between a power supply pad 21 and an output pad 22. The first protection element 17 and the second protection element 18 protect the internal circuit 11 from ESD current flowing into the power supply pad 21 and the output pad 22.

[0018] 1 shows one output pad 22, and the output buffer circuit 13 and protection circuit 16 connected to the output pad 22. The semiconductor device 10 may be configured to include multiple output pads 22. The semiconductor device 10 may also be configured to include one or multiple input pads. The semiconductor device 10 may also be configured to input a signal from the output pad 22. In this case, the output pad 22 functions as an input / output pad (I / O pad).

[0019] 2 , the first driver switching element 14 is an NMOS transistor. The first driver switching element 14 is connected between an output pad 22 and a ground pad 23. The back gate terminal of the first driver switching element 14 is connected to the ground pad 23. In other words, the back gate terminal of the first driver switching element 14 is connected to the source terminal of the first driver switching element 14.

[0020] The first protection element 17 includes a first protection switching element 17a and a second protection switching element 17b. The first protection switching element 17a and the second protection switching element 17b are NMOS transistors. The source terminal of the first protection switching element 17a is connected to the ground pad 23. The drain terminal of the first protection switching element 17a is connected to the output pad 22. The gate terminal and the back gate terminal of the first protection switching element 17a are connected to the source terminal of the first protection switching element 17a. The source terminal of the second protection switching element 17b is connected to the ground pad 23. The drain terminal of the second protection switching element 17b is connected to the output pad 22. The gate terminal and the back gate terminal of the second protection switching element 17b are connected to the source terminal of the second protection switching element 17b.

[0021] The first driver switching element 14 and the first protection element 17 constitute a first output circuit 12L connected between the output pad 22 and the ground pad 23. The first output circuit 12L is turned on and off based on an output signal SO, and draws a current from the output pad 22 to the ground pad 23.

[0022] 3 , the second driver switching element 15 is a PMOS transistor. The second driver switching element 15 is connected between a power supply pad 21 and an output pad 22. The back gate terminal of the second driver switching element 15 is connected to the power supply pad 21. In other words, the back gate terminal of the second driver switching element 15 is connected to the source terminal of the second driver switching element 15.

[0023] The second protection element 18 includes a third protection switching element 18a and a fourth protection switching element 18b. The third protection switching element 18a and the fourth protection switching element 18b are PMOS transistors. The source terminal of the third protection switching element 18a is connected to the power supply pad 21. The drain terminal of the third protection switching element 18a is connected to the output pad 22. The gate terminal and the back gate terminal of the third protection switching element 18a are connected to the source terminal of the third protection switching element 18a. The source terminal of the fourth protection switching element 18b is connected to the power supply pad 21. The drain terminal of the fourth protection switching element 18b is connected to the output pad 22. The gate terminal and the back gate terminal of the fourth protection switching element 18b are connected to the source terminal of the fourth protection switching element 18b.

[0024] The second driver switching element 15 and the second protection element 18 constitute a second output circuit 12U connected between the power supply pad 21 and the output pad 22. The second output circuit 12U is turned on and off based on the output signal SO, and causes a current to flow from the power supply pad 21 to the output pad 22.

[0025] (Configuration of driver switching element and protection switching element) Figure 5 is a partial plan view of the semiconductor device 10 shown in Figure 1, and is a schematic plan view showing the configuration of the first driver switching element 14 and the first protection element 17 (first protection switching element 17a, second protection switching element 17b) shown in Figure 2. Figure 6 is a partial cross-sectional view of the semiconductor device 10, and is a schematic cross-sectional view showing the configuration of the first well region 31, the second well region 32, the back-gate guard ring 33, and the first switching element 41 shown in Figure 5. Note that in Figure 5 and other figures, wiring connecting elements and the like is shown by solid lines, and contacts are shown by black circles.

[0026] The semiconductor device 10 has a semiconductor substrate 30. The first driver switching element 14 and the first protection element 17 shown in FIG. 1 are formed on the semiconductor substrate 30. That is, FIG. 5 is a plan view of the semiconductor substrate 30 as viewed from the thickness direction. In the following description, the thickness direction of the semiconductor substrate 30 is referred to as the "Z direction," and two directions that are perpendicular to the Z direction and perpendicular to each other are referred to as the "X direction" and the "Y direction." In the first embodiment, the X direction corresponds to the "second direction," and the Y direction corresponds to the "first direction."

[0027] 5 and 6 , the semiconductor device 10 has an N-type first well region 31. When viewed from the Z direction, the first well region 31 is formed in a rectangular shape that is long in the X direction. A P-type second well region 32 is formed in the first well region 31. When viewed from the Z direction, the second well region 32 is formed in a rectangular shape that is long in the X direction. A P-type back gate guard ring 33 is formed in the second well region 32. When viewed from the Z direction, the back gate guard ring 33 is formed in a rectangular frame shape that is long in the X direction. The back gate guard ring 33 is connected to the ground pad 23 by wiring 65 and 63.

[0028] 5 are connected to the power supply pad 21. The wires 64 and 61 are wires for supplying the power supply voltage VDD supplied from the power supply pad 21 to the internal circuit 11, the second output circuit 12U, etc. shown in FIG.

[0029] 5, a plurality of first switching elements 41 and a plurality of second switching elements 42 are formed inside the back gate guard ring 33. The second well region 32 and the back gate guard ring 33 form back gate terminals of the plurality of first switching elements 41 and the plurality of second switching elements 42. The plurality of first switching elements 41 form the first driver switching element 14 and the first protection switching element 17a shown in FIG. 2. The plurality of second switching elements 42 form the second protection switching element 17b shown in FIG. 2.

[0030] The plurality of first switching elements 41 are arranged in the Y direction. Similarly, the plurality of second switching elements 42 are arranged in the Y direction. The plurality of second switching elements 42 are arranged next to the plurality of first switching elements 41 in the X direction.

[0031] The multiple first switching elements 41 are configured by MOSFETs (NMOS transistors). Each of the multiple first switching elements 41 has a first gate wiring 41G extending in the X direction. Each of the multiple first switching elements 41 has an N-type first source region 41S and a first drain region 41D arranged to sandwich the first gate wiring 41G. Two first switching elements 41 adjacent to each other in the Y direction are arranged so that their first drain regions 41D are continuous.

[0032] The second switching elements 42 are configured by MOSFETs (NMOS transistors). Each of the second switching elements 42 has a second gate wiring 42G extending in the X direction. Each of the second switching elements 42 has an N-type second source region 42S and a second drain region 42D arranged on either side of the second gate wiring 42G. Two second switching elements 42 adjacent to each other in the Y direction are arranged so that their second drain regions 42D are continuous.

[0033] The X-direction length of the plurality of first gate wirings 41G is different from the X-direction length of the plurality of second gate wirings 42G. In the first embodiment, the X-direction length of the plurality of second gate wirings 42G is set to be longer than the X-direction length of the plurality of first gate wirings 41G. The X-direction length of the first gate wiring 41G is set in accordance with the gate width of the first switching element 41. The X-direction length of the second gate wiring 42G is set in accordance with the gate width of the second switching element 42. Therefore, the gate width of the second switching element 42 is set to be longer than the gate width of the first switching element 41.

[0034] The first drain regions 41D of the plurality of first switching elements 41 and the second drain regions 42D of the plurality of second switching elements 42 are connected to the output pad 22 by wiring 62. The first source regions 41S of the plurality of first switching elements 41 and the second source regions 42S of the plurality of second switching elements 42 are connected to the ground pad 23 by wiring 65 and 63.

[0035] Of the multiple first switching elements 41, the first switching elements 41 arranged at both ends in the Y direction are referred to as first end switching elements 41b. The first driver switching element 14 shown in FIG. 2 is composed of at least one first switching element 41 arranged between the first end switching elements 41b at both ends of the multiple first switching elements 41. The first driver switching element 14 is preferably composed of the first switching element 41 arranged at the center in the Y direction among the multiple first switching elements 41. In the first embodiment, the first driver switching element 14 is composed of two first switching elements 41a arranged at the center in the Y direction among the multiple first switching elements 41. Note that the first driver switching element 14 may be composed of one first switching element 41 or three or more first switching elements 41.

[0036] The first gate wirings 41G of the two first switching elements 41a are connected to each other by wiring 66, and are also connected to the internal circuit 11 shown in Fig. 1 by wiring 67. Therefore, the first driver switching element 14 shown in Fig. 2 is composed of the two first switching elements 41a shown in Fig. 5. It can be said that the first switching element 41a is the first driver switching element 14.

[0037] The first gate wirings 41G of the first switching elements 41, excluding the two first switching elements 41a, are each connected by wiring 68 to the second gate wirings 42G of the second switching elements 42 arranged in the X direction. The second gate wirings 42G of all second switching elements 42 are connected to the ground pad 23 by wirings 69 and 63. Therefore, the first gate wirings 41G of the first switching elements 41, excluding the two first switching elements 41a, are connected to the ground pad 23. As a result, all second switching elements 42 constitute the second protection switching elements 17b shown in FIG. 2. The second switching elements 42 can be said to be the second protection switching elements 17b. Furthermore, the first switching elements 41, excluding the two first switching elements 41a constituting the first driver switching element 14, constitute the first protection switching element 17a shown in FIG. 2. The first switching elements 41, excluding the first switching elements 41a, can be said to be the first protection switching elements 17a.

[0038] In the example shown in FIG. 5 , the first gate wirings 41G of the two first switching elements 41a are connected to the internal circuit 11 shown in FIG. 1 by wirings 66 and 67. The multiple first switching elements 41 have the same electrical characteristics. Therefore, the number of first switching elements 41 connected to the internal circuit 11 can be changed as needed by changing the design (layout) of the wirings 66 and 67. The number of first switching elements 41 connected to the internal circuit 11 corresponds to the amount of current flowing from the output pad 22 to the ground pad 23. This amount of current corresponds to, for example, the number of elements connected to the output pad 22 and driven by the first driver switching element 14. Therefore, it can be said that the multiple first switching elements 41 are configured so that the drive capacity of the first driver switching element 14 can be set by the number of first switching elements 41 connected to the wirings 66 and 67.

[0039] Examples of setting the driving capacity based on the number of first switching elements 41a other than the configuration shown in FIG. 5 will be described. As a first setting example of the driving capacity, for example, the first driver switching element 14 can be configured with one first switching element 41a connected to the wiring 67. As a second setting example of the driving capacity, for example, the first driver switching element 14 can be configured with four first switching elements 41a connected to the wirings 66 and 67. In contrast, the first switching elements 41 not connected to the wiring 67 constitute the first protection switching elements 17a by connecting the first gate wiring 41G to the ground pad 23. The first switching element 41a connected to the wiring 67 is formed in the same second well region 32 as the other first switching elements 41. Therefore, it also functions as a protection switching element. In other words, the multiple first switching elements 41 are switching elements that serve both as the first driver switching element 14 and the first protection switching elements 17a. In contrast, all of the second switching elements 42 are dedicated switching elements that constitute the second protection switching elements 17b.

[0040] The first driver switching element 14 and the first protection element 17 (first protection switching element 17a, second protection switching element 17b) shown in Figures 1 and 2 have been described above. The second driver switching element 15 and the second protection element 18 shown in Figures 1 and 3 are configured similarly to the first driver switching element 14 and the first protection element 17. For example, the semiconductor device 10 includes a plurality of third switching elements and a plurality of fourth switching elements formed in an N-type third well region. The third well region, the third switching elements, and the fourth switching elements have different conductivity types, but are configured similarly to the second well region 32, the first switching element 41, and the second switching element 42 described above.

[0041] (Operation) Next, a description will be given of the operation of the semiconductor device 10 of the first embodiment. (Operation of the Protection Switching Element) First, the operation of one protection switching element will be described.

[0042] 4 shows one protection switching element 71. This protection switching element 71 is formed in the P-type second well region 32. The protection switching element 71 is surrounded by a back gate guard ring 33. A drain region 71D of the protection switching element 71 is connected to the output pad 22. A source region 71S and gate wiring 71G of the protection switching element 71, and the back gate guard ring 33 are connected to the ground pad 23.

[0043] The drain region 71D and source region 71S of the protection switching element 71 and the second well region 32 constitute an NPN-type parasitic transistor 75. This parasitic transistor 75 includes a PN junction (parasitic diode) between the second well region 32 and the source region 71S, and a PN junction (parasitic diode) between the second well region 32 and the drain region 71D. The base of the parasitic transistor 75 is connected to the back-gate guard ring 33 via a resistor 76 formed by the resistance component of the second well region 32.

[0044] An ESD current flows into the output pad 22. At this time, a potential difference occurs between the cathode and anode of the parasitic diode formed by the drain region 71D of the protection switching element 71 and the second well region 32, causing an ESD current, indicated by arrow 72a, to flow to the base of the parasitic transistor 75. This current increases the base voltage of the parasitic transistor 75. This increase in the base voltage of the parasitic transistor 75 causes a current, indicated by arrow 72b, to flow toward the source region 71S of the protection switching element 71. This turns on the parasitic transistor 75, causing a current, indicated by arrow 72c, to flow from the drain region 71D through the second well region 32 to the source region 71S. In other words, the protection switching element 71 turns on as a protection element, causing an ESD current to flow from the output pad 22, through the protection switching element 71, toward the ground pad 23 to which the source region 71S is connected.

[0045] 5, the first drain region 41D of the first switching element 41 and the second drain region 42D of the second switching element 42 are connected to the output pad 22. Therefore, the first switching element 41 and the second switching element 42 function as protective switching elements that operate in the same manner with respect to an ESD current applied to the output pad 22. As described above, of the multiple first switching elements 41, the first switching element 41a that is centrally disposed in the Y direction is the first driver switching element 14. The multiple first switching elements 41 are first protective switching elements 17a. The multiple second switching elements 42 are second protective switching elements 17b.

[0046] FIG. 6 is a cross-sectional view taken along line F6-F6 in FIG. 5 , illustrating the operation of the first switching element 41. As shown in FIG. 6 , multiple first switching elements 41 are arranged side by side in the Y direction. Each first switching element 41 has a first gate wiring 41G and a first source region 41S and a first drain region 41D arranged on either side of the first gate wiring 41G. A parasitic transistor 45 is formed by the P-type second well region 32 and the first source region 41S and first drain region 41D of the first switching element 41. The bases of the parasitic transistors 45 are connected to each other in the Y direction via a resistor 46 formed by the resistance component of the second well region 32. The base of the parasitic transistor 45 corresponding to the first switching element 41a arranged at the end in the Y direction is connected to the back-gate guard ring 33 via the resistor 46.

[0047] (Semiconductor Device of Comparative Example) Here, a description will be given of a semiconductor device 10X that is a comparative example to the semiconductor device 10 of the first embodiment. Note that the components of the semiconductor device 10X of the comparative example are the same as those of the semiconductor device 10 of the first embodiment, and therefore will be described using the same reference numerals.

[0048] 7 shows a partial cross-sectional view of a semiconductor device 10X of the comparative example. In this semiconductor device 10X of the comparative example, the first gate wiring 41G of the first end switching element 41b arranged at the end in the Y direction is connected to the internal circuit 11 shown in Fig. 1. Therefore, the first end switching element 41b arranged at the end in the Y direction constitutes the first driver switching element 14 shown in Figs. 1 and 2.

[0049] An ESD current flows into the output pad 22 shown in FIG. 7 . This ESD current flows from the output pad 22 toward the first drain region 41D. At this time, the first end switching element 41b constituting the first driver switching element 14 shown in FIG. 2 may operate earlier than the other first switching elements 41. This case will be described. The ESD current flows from the first drain region 41D of the first end switching element 41b to the base of the parasitic transistor 45, i.e., the second well region 32, which is the back gate of the first end switching element 41b. The first end switching element 41b of the parasitic transistor 45 is disposed near the back gate guard ring 33. Therefore, the resistance value between the base of the parasitic transistor 45 and the back gate guard ring 33 is lower than that of the other parasitic transistors 45. Therefore, the base voltages of the other parasitic transistors 45 are less likely to rise and are less likely to be turned on. Therefore, the ESD current that has flowed into the second well region 32 flows toward the first source region 41S of the first-end switching element 41b via the turned-on parasitic transistor 45. In other words, the ESD current concentrates in the parasitic transistor 45 of the first-end switching element 41b. As a result, the first-end switching element 41b arranged at the end may be damaged.

[0050] (Operation of Semiconductor Device of First Embodiment) The semiconductor device 10 of the first embodiment includes a plurality of first switching elements 41 arranged side by side in the Y direction and having first gate wiring 41G extending in the X direction, and a back gate guard ring 33 surrounding the plurality of first switching elements 41. The plurality of first switching elements 41 are connected in parallel to one another and are connected between the output pad 22 and the ground pad 23. Of the plurality of first switching elements 41, at least one first switching element 41a arranged between first end switching elements 41b arranged at both ends in the Y direction constitutes the first driver switching element 14. The first gate wiring 41G of the first switching elements 41 other than this first switching element 41a is connected to the ground pad 23 and constitutes the first protection switching element 17a.

[0051] 6, the first gate wiring 41G of the first switching element 41a is connected to the internal circuit 11 shown in Fig. 1. Five first switching elements 41 are arranged between the first switching element 41a and the back gate guard ring 33. In the parasitic transistors 45 corresponding to each first switching element 41, the bases of two parasitic transistors 45 adjacent to each other in the Y direction are connected to each other via a resistor 46 formed by the resistance component of the second well region 32.

[0052] An ESD current flows into the output pad 22 shown in FIG. 6 . This ESD current causes the first switching element 41a constituting the driver switching element 14 shown in FIG. 2 to operate earlier than the other first switching elements 41. At this time, the ESD current flows from the first drain region 41D of the first switching element 41a to the base of the parasitic transistor 45, i.e., the second well region 32, which serves as the back gate of the first switching element 41a. A plurality of other parasitic transistors 45 are disposed between the parasitic transistor 45 and the back gate guard ring 33. Therefore, the base voltages of the plurality of parasitic transistors 45 near the first switching element 41a rise. As a result, the plurality of parasitic transistors 45 are turned on. The ESD current flows through these on-state parasitic transistors 45. This prevents the ESD current from concentrating on the parasitic transistor 45 of the first switching element 41a. As a result, damage to the first switching element 41a due to the ESD current concentrating can be prevented. Furthermore, the first switching element 41 allows the ESD current to flow to the ground pad 23, thereby protecting the internal circuit 11 shown in FIG.

[0053] 5, the plurality of first switching elements 41 are formed in one second well region 32. The plurality of second switching elements 42 are formed in the second well region 32 alongside the plurality of first switching elements 41. As described above, the ESD current applied to the output pad 22 flows from the first drain region 41D of the first switching element 41a into the second well region 32.

[0054] The second switching elements 42 are configured similarly to the first switching elements 41. Therefore, the semiconductor device 10 includes parasitic transistors corresponding to the second switching elements 42. Like the parasitic transistor 45, the base voltage of the parasitic transistors of the second switching elements 42 increases due to an ESD current, causing a base current to flow, turning the parasitic transistors on and allowing the ESD current to flow. Therefore, the concentration of the ESD current in the parasitic transistor 45 of the first switching element 41a can be further suppressed. As a result, damage to the first switching element 41a due to the concentration of the ESD current can be suppressed. Furthermore, the first switching element 41 and the second switching element 42 operate as protective switching elements, thereby protecting the internal circuit 11 shown in FIG. 1 even when an excessive ESD current is applied to the output pad 22.

[0055] Note that FIG. 6 illustrates the first switching element 41a that is disposed at the center in the Y direction and that constitutes the first driver switching element 14. The first driver switching element 14 may instead be a first switching element 41 disposed between the first end switching elements 41b at both ends in the Y direction. For example, in FIG. 6, the first switching element 41 adjacent to the first end switching element 41b may be the first driver switching element 14. In this case, an ESD current flows into the first drain region 41D of the first switching element 41 that constitutes the first driver switching element 14. The ESD current then flows through that first switching element 41 and the parasitic transistor 45 of a nearby first switching element 41, such as the first end switching element 41b. This prevents current concentration in the first switching element 41 that constitutes the first driver switching element 14. The closer the first switching element 41 is to the center in the Y direction, the more parasitic transistors 45 of the first switching element 41 are activated by the ESD current. Therefore, current concentration in the first switching element 41 can be further suppressed.

[0056] The above has described the first switching element 41 and the second switching element 42 that constitute the first driver switching element 14 and the first protection element 17 (first protection switching element 17a, second protection switching element 17b) shown in FIGS. 1 and 2 . The second driver switching element 15 and the second protection element 18 shown in FIGS. 1 and 3 are configured similarly to the first driver switching element 14 and the first protection element 17. Therefore, the third switching element and the fourth switching element that constitute the second driver switching element 15 and the second protection element 18 can similarly suppress the concentration of ESD current in the third switching element whose gate wiring is connected to the internal circuit 11. This suppresses damage to the third switching element due to the concentration of ESD current. Furthermore, the third switching element and the fourth switching element operate as protection switching elements, thereby protecting the internal circuit 11 shown in FIG. 1 .

[0057] (Effects) As described above, the first embodiment provides the following effects. (1-1) The semiconductor device 10 includes a plurality of first switching elements 41 arranged side by side in the Y direction and having first gate wiring 41G extending in the X direction, and a back-gate guard ring 33 surrounding the plurality of first switching elements 41. The plurality of first switching elements 41 are connected in parallel to one another and are connected between the output pad 22 and the ground pad 23. Of the plurality of first switching elements 41, at least one first switching element 41a arranged between the first end switching elements 41b arranged at both ends in the Y direction constitutes the first driver switching element 14. The first gate wiring 41G of the first switching elements 41 other than this first switching element 41a is connected to the ground pad 23 and constitutes the first protection switching element 17a.

[0058] When an ESD current is applied to the output pad 22, the voltage of the second well region 32 of the first switching element 41a that becomes the first driver switching element 14 and of the other first switching elements 41 near the first switching element 41a rises. This turns on the parasitic transistors 45 of the first switching element 41a and the nearby first switching elements 41, allowing the ESD current to flow. This makes it possible to suppress current concentration in the parasitic transistors 45 of the first switching elements 41.

[0059] (1-2) The first switching element 41a arranged in the center in the Y direction constitutes the first driver switching element 14. This allows ESD current to flow through a larger number of parasitic transistors 45 of the first switching element 41 compared to when the first switching elements 41 arranged at the ends in the Y direction are used as the first driver switching elements 14. This makes it possible to further reduce current concentration in the parasitic transistors 45 of the first switching elements 41.

[0060] (1-3) The first drain regions 41D of the multiple first switching elements 41 are connected to the output pad 22. The first switching element 41a and the multiple other first switching elements 41 that constitute the first driver switching element 14 function as protective switching elements. This allows the ESD current applied to the output pad 22 to flow to the ground pad 23, thereby protecting the internal circuit 11.

[0061] (1-4) The semiconductor device 10 includes a plurality of second switching elements 42 surrounded by the back gate guard ring 33. The second gate wiring 42G of the plurality of second switching elements 42 is connected to the ground pad 23 to form the second protective switching element 17b. Therefore, the plurality of first switching elements 41 and the plurality of second switching elements 42 function as protective switching elements. This allows excessive ESD current applied to the output pad 22 to flow to the ground pad 23, thereby further protecting the internal circuit 11.

[0062] (1-5) The second gate wiring 42G of the second switching element 42 is longer than the first gate wiring 41G of the first switching element 41. This allows a larger amount of current to flow through the second protection switching element 17b formed by the second switching element 42. This allows excessive ESD current applied to the output pad 22 to flow to the ground pad 23, thereby further protecting the internal circuit 11.

[0063] (1-6) The second gate wiring 42G of the second switching element 42 is longer than the first gate wiring 41G of the first switching element 41. In other words, the first gate wiring 41G of the first switching element 41 is shorter than the second gate wiring 42G of the second switching element 42. The length of the first gate wiring 41G corresponds to the gate width of the first switching element 41 and determines the amount of current passed by the first switching element 41. With the short first gate wiring 41G, the first switching element 41a operating as the first driver switching element 14 passes a small amount of current relative to the output signal SO from the output pad 22 to the ground pad 23. This makes it possible to provide a semiconductor device 10 that consumes a small amount of current, i.e., consumes less power when outputting a signal.

[0064] Second Embodiment A second embodiment will be described below with reference to Figures 8 to 11. In this embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and some or all of the description may be omitted.

[0065] 8, a semiconductor device 110 according to the second embodiment includes an internal circuit 11 and an output circuit 112. The output circuit 112 includes an output buffer circuit 113 and a protection circuit .

[0066] The output buffer circuit 113 includes a first driver switching element 114 and a second driver switching element 115. The first driver switching element 114 and the second driver switching element 115 are configured by MOS transistors (MOSFETs). The first driver switching element 114 of the second embodiment is an NMOS transistor. The second driver switching element 115 of the second embodiment is a PMOS transistor. Therefore, the output buffer circuit 113 of the second embodiment is an inverter circuit with a CMOS configuration.

[0067] The first driver switching element 114 is connected between the output pad 22 and the ground pad 23. The source terminal of the first driver switching element 114 is connected to the ground pad 23. The drain terminal of the first driver switching element 114 is connected to the output pad 22. The gate terminal (control terminal) of the first driver switching element 114 is supplied with the output signal SO.

[0068] The second driver switching element 115 is connected between the power supply pad 21 and the output pad 22. The source terminal of the second driver switching element 115 is connected to the power supply pad 21. The drain terminal of the second driver switching element 115 is connected to the output pad 22. The gate terminal (control terminal) of the second driver switching element 115 is supplied with the output signal SO.

[0069] The protection circuit 116 includes a first protection element 117 and a second protection element 118. The first protection element 117 is connected between the output pad 22 and the ground pad 23. The second protection element 118 is connected between the power supply pad 21 and the output pad 22. The first protection element 117 and the second protection element 118 protect the internal circuit 11 from ESD current flowing into the power supply pad 21 and the output pad 22.

[0070] 8 shows one output pad 22, and an output buffer circuit 113 and a protection circuit 116 connected to the output pad 22. The semiconductor device 110 may be configured to include a plurality of output pads 22. The semiconductor device 110 may also be configured to include one or a plurality of input pads. The semiconductor device 110 may also be configured to input a signal from the output pad 22. In this case, the output pad 22 functions as an input / output pad (I / O pad).

[0071] 9 , the first driver switching element 114 is an NMOS transistor. The first driver switching element 114 is connected between the output pad 22 and the ground pad 23. The back gate terminal of the first driver switching element 114 is connected to the ground pad 23. In other words, the back gate terminal of the first driver switching element 114 is connected to the source terminal of the first driver switching element 114.

[0072] The first protection element 117 includes a first protection switching element 117a. The first protection switching element 117a is an NMOS transistor. A source terminal of the first protection switching element 117a is connected to the ground pad 23. A drain terminal of the first protection switching element 117a is connected to the output pad 22. A gate terminal and a back gate terminal of the first protection switching element 117a are connected to the source terminal of the first protection switching element 117a.

[0073] 10 , the second driver switching element 115 is a PMOS transistor. The second driver switching element 115 is connected between the power supply pad 21 and the output pad 22. The back gate terminal of the second driver switching element 115 is connected to the power supply pad 21. In other words, the back gate terminal of the second driver switching element 115 is connected to the source terminal of the second driver switching element 115.

[0074] The second protection element 118 includes a second protection switching element 118a. The second protection switching element 118a is a PMOS transistor. A source terminal of the second protection switching element 118a is connected to the power supply pad 21. A drain terminal of the second protection switching element 118a is connected to the output pad 22. A gate terminal and a back gate terminal of the second protection switching element 118a are connected to the source terminal of the second protection switching element 118a.

[0075] (Configuration of driver switching element and protection switching element) FIG. 11 is a partial plan view of the semiconductor device 110, and is a schematic plan view showing the configuration of the first driver switching element 114 and the first protection element 117 (first protection switching element 117a) shown in FIG. 9.

[0076] The semiconductor device 110 has a semiconductor substrate 30. The first driver switching element 114 and the first protection element 117 shown in Fig. 8 are formed on the semiconductor substrate 30. That is, Fig. 11 is a plan view of the semiconductor substrate 30 as viewed from the thickness direction. In Fig. 11, wiring connecting elements and the like is indicated by solid lines, and contacts are indicated by black circles.

[0077] 8 are formed on the semiconductor substrate 30, similar to the first driver switching element 114 and the first protection element 117. In FIG. 11 and other figures, the wiring and contacts connecting the elements are shown in a simplified manner.

[0078] The plurality of switching elements 141 shown in Fig. 11 constitute the first driver switching element 114 and the first protection switching element 117a shown in Fig. 9. This will be described in detail below.

[0079] 11 , the semiconductor device 110 has an N-type first well region 31. When viewed from the Z direction, the first well region 31 is formed in a rectangular shape that is long in the X direction. A P-type second well region 32 is formed in the first well region 31. When viewed from the Z direction, the second well region 32 is formed in a rectangular shape that is long in the X direction. A P-type back gate guard ring 33 is formed in the second well region 32. When viewed from the Z direction, the back gate guard ring 33 is formed in a rectangular frame shape that is long in the X direction. The back gate guard ring 33 is connected to the ground pad 23 by wiring 65 and 63.

[0080] 11, a plurality of switching elements 141 are formed inside the back gate guard ring 33. The plurality of switching elements 141 are arranged in the Y direction.

[0081] The multiple switching elements 141 are configured by MOSFETs (NMOS transistors). Each of the multiple switching elements 141 has a gate wiring 141G extending in the X direction. Each of the multiple switching elements 141 has an N-type source region 141S and a drain region 141D arranged on either side of the gate wiring 141G. Two switching elements 141 adjacent in the Y direction are arranged so that their drain regions 141D are continuous. The multiple gate wirings 141G extend in the Y direction over the range inside the back gate guard ring 33.

[0082] The drain regions 141D of the switching elements 141 are connected to the output pad 22 by wiring 62. The source regions 141S of the switching elements 141 are connected to the ground pad 23 by wiring 65 and 63.

[0083] Of the multiple switching elements 141, the switching elements 141 arranged at both ends in the Y direction are referred to as first-end switching elements 141b. The first driver switching element 114 shown in FIG. 9 is composed of at least one switching element 141 arranged between the first-end switching elements 141b at both ends of the multiple switching elements 141. The first driver switching element 114 is preferably composed of the switching element 141a arranged at the center in the Y direction among the multiple switching elements 141. In the second embodiment, the first driver switching element 114 is composed of two switching elements 141a arranged at the center in the Y direction among the multiple switching elements 141. Note that the first driver switching element 114 may be composed of one switching element 141 or three or more switching elements 141.

[0084] The gate wirings 141G of the two switching elements 141a are connected to each other by wiring 66, and are also connected to the internal circuit 11 shown in Fig. 8 by wiring 67. The gate wirings 141G of the switching elements 141 other than the two switching elements 141a are connected to the ground pad 23 by wirings 69 and 63. As a result, the switching elements 141 other than the two switching elements 141a that constitute the first driver switching element 114 constitute the first protection switching element 117a shown in Fig. 9.

[0085] In the example shown in FIG. 11 , the gate wiring 141G of the two switching elements 141a is connected to the internal circuit 11 shown in FIG. 8 by wirings 66 and 67. The multiple switching elements 141 have the same electrical characteristics. Therefore, the number of switching elements 141 connected to the internal circuit 11 can be changed as needed by changing the design (layout) of the wirings 66 and 67. The number of switching elements 141 connected to the internal circuit 11 corresponds to the amount of current flowing from the output pad 22 to the ground pad 23. This amount of current corresponds to, for example, the number of elements connected to the output pad 22 and driven by the first driver switching element 114. Therefore, it can be said that the multiple switching elements 141 are configured so that the drive capacity of the first driver switching element 114 can be set by the number of switching elements 141 connected to the wirings 66 and 67.

[0086] Examples of setting the driving capacity based on the number of switching elements 141a other than the configuration shown in FIG. 11 will be described. As a first setting example of the driving capacity, for example, the first driver switching element 114 can be configured with one switching element 141a connected to the wiring 67. As a second setting example of the driving capacity, for example, the first driver switching element 114 can be configured with four switching elements 141a connected to the wirings 66 and 67. In contrast, the switching elements 141 not connected to the wirings 66 and 67 configure the first protection switching elements 117a by connecting the gate wiring 141G to the ground pad 23. The switching elements 141a connected to the wirings 66 and 67 are formed in the same second well region 32 as the other switching elements 141. Therefore, they also function as protection switching elements. In other words, the multiple switching elements 141 are switching elements that serve as both the first driver switching element 114 and the first protection switching elements 117a.

[0087] The above has described the first driver switching element 114 and the first protection element 117 (first protection switching element 117a) shown in Figures 8 and 9. The second driver switching element 115 and the second protection element 118 shown in Figures 8 and 10 are configured similarly to the first driver switching element 114 and the first protection element 117. For example, the semiconductor device 110 includes a plurality of third switching elements formed in an N-type third well region. The third well region and the third switching elements have different conductivity types, but are configured similarly to the second well region 32 and the first switching element 41 described above.

[0088] (Operation) Next, the operation of the semiconductor device 110 of the second embodiment will be described. As shown in FIG. 11 , the switching elements 141 of the second embodiment are arranged in the Y direction in the same manner as the first switching elements 41 of the first embodiment. Therefore, the parasitic transistors for the multiple switching elements 141 formed in the second well region 32 and the resistances between the bases of the parasitic transistors are similar to the parasitic transistors 45 and resistors 46 for the first switching elements 41 of the first embodiment. Of the switching elements 141 arranged in the Y direction, at least one switching element 141 excluding the first end switching elements 141b at both ends constitutes the first driver switching element 114. Therefore, when an ESD current is applied to the output pad 22, current concentration in the parasitic transistors of the switching elements 141 constituting the first driver switching element 114 can be suppressed. This also suppresses damage to the switching elements 141 due to ESD current concentration.

[0089] The switching element 141 of the second embodiment includes a gate wiring 141G that is longer than the first gate wiring 41G of the first switching element 41 of the first embodiment. Therefore, the gate width of the switching element 141 is longer than the gate width of the first switching element 41. This allows the switching element 141 of the second embodiment to pass a larger current than the first switching element 41 of the first embodiment. Therefore, it is possible to provide a semiconductor device 110 that includes a first driver switching element 114 that is configured with a switching element 141 having a large driving capability.

[0090] (Effects) As described above, the second embodiment provides the following effects: (2-1) The same effects as those of the semiconductor device 10 of the first embodiment are provided.

[0091] (2-2) The gate wiring 141G of the switching element 141 extends in the Y direction over the range inside the back gate guard ring 33. Therefore, the gate wiring 141G of the second embodiment is longer than the first gate wiring 41G of the first switching element 41 that constitutes the first driver switching element 14 in the first embodiment. Therefore, it is possible to provide a semiconductor device 110 with higher driving capability than the semiconductor device 10 of the first embodiment.

[0092] (Modifications) The above embodiment can be modified, for example, as follows. The above embodiment and each of the following modifications can be combined with each other as long as no technical contradiction occurs. In the following modifications, parts that are common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0093] 12, the gate terminal of the first protection switching element 17a constituting the first protection element 17 may be connected to the source terminal of the first protection switching element 17a by a resistor 81a. Also, the gate terminal of the second protection switching element 17b constituting the first protection element 17 may be connected to the source terminal of the second protection switching element 17b by a resistor 81b.

[0094] 13, the gate terminal of the third protection switching element 18a constituting the second protection element 18 may be connected to the source terminal of the third protection switching element 18a by a resistor 82a. Also, the gate terminal of the fourth protection switching element 18b constituting the second protection element 18 may be connected to the source terminal of the fourth protection switching element 18b by a resistor 82b.

[0095] In the first embodiment, the semiconductor device 10 is configured to include the output buffer circuit 13 having a CMOS structure. However, the semiconductor device 10 may be configured to include an output circuit (open-drain output circuit) in which the second driver switching element 15 between the power supply pad 21 and the output pad 22 is omitted. In this case, the second protection element 18 may be omitted. The same can be said for the semiconductor device 110 of the second embodiment.

[0096] In the above embodiments, the semiconductor devices 10 and 110 are described as outputting an output signal OUT to the output pad 22. The output pad 22 may be a pad for inputting a signal and a pad for outputting a signal, that is, an input / output pad (I / O pad).

[0097] The gate terminals of the first protection switching element 17a and the second protection switching element 17b shown in Fig. 2 may be diode-connected to the output pad 22, i.e., the drain terminal. The gate terminals of the third protection switching element 18a and the fourth protection switching element 18b shown in Fig. 3 may be diode-connected to the output pad 22, i.e., the drain terminal. Similarly, the gate terminal of the first protection switching element 117a shown in Fig. 9 may be diode-connected to the output pad 22, i.e., the drain terminal. The gate terminal of the second protection switching element 118a shown in Fig. 10 may be diode-connected to the output pad 22, i.e., the drain terminal.

[0098] (Supplementary Notes) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the Supplementary Notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each Supplementary Note should not be limited to the components indicated by the reference symbols.

[0099] (Supplementary Note 1) A semiconductor device including: a plurality of first switching elements (41) constituted by MOSFETs, arranged side by side in a first direction, and having first gate wiring (41G) extending in a second direction intersecting the first direction; and a back gate guard ring (33) surrounding the plurality of first switching elements (41), wherein three or more of the first switching elements (41) are provided, the plurality of first switching elements (41) are connected in parallel with each other and between a first pad (22) and a second pad (23), among the plurality of first switching elements (41), at least one of the first switching elements (41 a) arranged between first end switching elements (41 b) arranged at both ends in the first direction is a driver switching element, and the first switching elements of the plurality of first switching elements (41) excluding the driver switching element (41 a) are first protection switching elements whose first gate wiring (41G) is connected to the first pad (22) or the second pad (23).

[0100] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the driver switching element is the first switching element (41a) arranged at the center in the first direction.

[0101] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or Supplementary Note 2, wherein the number of the driver switching elements is smaller than the number of the first protection switching elements.

[0102] (Supplementary Note 4) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, further comprising: a plurality of second switching elements (42) arranged in the second direction relative to the plurality of first switching elements (41), configured by MOSFETs, arranged side by side in the first direction, and having second gate wiring (42G) extending in the second direction; the back gate guard ring (33) is formed to surround the plurality of first switching elements (42) and the plurality of second switching elements (42); the number of second switching elements (42) is the same as the number of first switching elements (41); and the plurality of second switching elements (42) are second protective switching elements whose second gate wiring (42G) is connected to the first pad (22) or the second pad (23).

[0103] (Supplementary Note 5) The semiconductor device according to Supplementary Note 4, wherein the plurality of first switching elements (41) and the plurality of second switching elements (42) are N-channel MOSFETs, the first pad (22) is an output pad, and the second pad (23) is a ground pad.

[0104] (Supplementary Note 6) The semiconductor device according to Supplementary Note 4, wherein the plurality of first switching elements (41) and the plurality of second switching elements (42) are P-channel MOSFETs, the first pad (22) is an output pad, and the second pad (21) is a power supply pad.

[0105] (Supplementary Note 7) The semiconductor device according to any one of Supplementary Note 4 to Supplementary Note 6, wherein the second gate wiring (42G) is longer than the first gate wiring (41G).

[0106] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Note 4 to Supplementary Note 7, wherein the first gate wiring (41G) and the second gate wiring (42G) are arranged side by side in the second direction.

[0107] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Note 4 to Supplementary Note 8, wherein back gate terminals of the plurality of first switching elements (41) and the plurality of second switching elements (42) are connected to the second pad (23).

[0108] (Supplementary Note 10) The semiconductor device according to any one of Supplementary Note 4 to Supplementary Note 9, wherein the plurality of first switching elements (41) and the plurality of second switching elements (42) are formed in a single well region (32).

[0109] (Appendix 11) The semiconductor device according to any one of appendices 1 to 10, further comprising a resistive element (81a) connected between the first gate wiring (41G, 141G) of the protection switching element (41, 141) and the first pad (22) or the second pad (21, 23).

[0110] (Supplementary Note 12) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 11, wherein the second pad includes a first power supply pad (23) and a second power supply pad (21), a first transistor (14, 114) and a first protection element (17, 117) connected between the first power supply pad (23) and the first pad (22), and a second transistor (15, 115) and a second protection element (18, 118) connected between the first pad (22) and the second power supply pad (21), wherein each of the first transistor (14, 114) and the second transistor (15, 115) includes a plurality of the driver switching elements, and each of the first protection element (17, 117) and the second protection element (18, 118) includes the first protection switching element (17a, 117a).

[0111] (Supplementary Note 13) The semiconductor device according to Supplementary Note 12, wherein the first transistor (14, 114) is configured by an N-channel MOSFET, and the second transistor (15, 115) is configured by a P-channel MOSFET.

[0112] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims and appended notes.

[0113] 10 Semiconductor device 11 Internal circuit 12 Output circuit 12L First output circuit 12U Second output circuit 13 Output buffer circuit 14 First driver switching element 15 Second driver switching element 16 Protection circuit 17 First protection element 17a First protection switching element 17b Second protection switching element 18 Second protection element 18a Third protection switching element 18b Fourth protection switching element 21 Power supply pad 22 Output pad 23 Ground pad 30 Semiconductor substrate 31 First well region 32 Second well region 33 Back gate guard ring 41 First switching element 41a First switching element 41b First end switching element 41D First drain region 41G First gate wiring 41S First source region 42 Second switching element 42D Second drain region 42G Second gate wiring 42S Second source region 45 Parasitic transistor 46 Resistor 61 to 69 Wiring 71 Protection switching element 71D Drain region 71G Gate wiring 71S Source region 72a to 72c Arrows 75 Parasitic transistor 76 Resistor 81a Resistor 81b Resistor 82a Resistor 82b Resistor 110 Semiconductor device 112 Output circuit 113 Output buffer circuit 114 First driver switching element 115 Second driver switching element 116 Protection circuit 117 First protection element 117a First protection switching element 118 Second protection element 118a Second protection switching element 141 Switching element 141a Switching element 141b First end switching element 141D Drain region 141G Gate wiring 141S Source region OUT Output signal SO Output signal VDD Power supply voltage

Claims

1. a plurality of first switching elements each composed of a MOSFET, arranged in a first direction, and having a first gate wiring extending in a second direction intersecting the first direction; a back gate guard ring surrounding the first switching elements; Including, Three or more first switching elements are provided, the first switching elements are connected in parallel to one another between a first pad and a second pad, Among the plurality of first switching elements, at least one of the first switching elements arranged between first end switching elements arranged at both ends in the first direction is a driver switching element, The first switching elements excluding the driver switching element among the plurality of first switching elements are first protection switching elements in which the first gate wiring is connected to the first pad or the second pad. Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein said driver switching element is said first switching element arranged at a center in said first direction.

3. The semiconductor device according to claim 1 , wherein the number of said driver switching elements is smaller than the number of said first protection switching elements.

4. a plurality of second switching elements, each of which is configured by a MOSFET, arranged in the second direction with respect to the plurality of first switching elements, and has a second gate wiring extending in the second direction; The back gate guard ring is provided between the first switching elements. a first switching element and a second switching element, The second switching elements are provided in the same number as the first switching elements, 2 . The semiconductor device according to claim 1 , wherein the plurality of second switching elements are second protection switching elements having the second gate wiring connected to the first pad or the second pad.

5. 5. The semiconductor device according to claim 4, wherein said plurality of first switching elements and said plurality of second switching elements are N-channel MOSFETs, said first pad is an output pad, and said second pad is a ground pad.

6. 5. The semiconductor device according to claim 4, wherein said plurality of first switching elements and said plurality of second switching elements are P-channel MOSFETs, said first pad is an output pad, and said second pad is a power supply pad.

7. The semiconductor device according to claim 4 , wherein the second gate wiring is longer than the first gate wiring.

8. The semiconductor device according to claim 4 , wherein the first gate wiring and the second gate wiring are arranged side by side in the second direction.

9. 7. The semiconductor device according to claim 4, wherein back gate terminals of the first switching elements and the second switching elements are connected to the second pad.

10. 7. The semiconductor device according to claim 4, wherein the plurality of first switching elements and the plurality of second switching elements are formed in a single well region.