Semiconductor device, storage apparatus, and electronic equipment

Abstract

A semiconductor device having a high storage density is applied in the present invention. This semiconductor device has a first layer and a first insulating material. The first layer has a first oxide semiconductor, first to ninth conductors, and second to fifth insulating materials. The first layer is positioned on the first insulating material, and the first oxide semiconductor is positioned above the first insulating material. The first and sixth conductors are positioned on the top and lateral surfaces of the first oxide semiconductor and on the top surface of the first insulating material, respectively. Further, the second and fourth conductors are positioned on the top surface of the first oxide semiconductor. The second insulating material and the third conductor are positioned between the first conductor and the second conductor, the third insulating material and the fifth conductor are positioned between the second conductor and the fourth conductor, and the fourth insulating material and the seventh conductor are positioned between the fourth conductor and the sixth conductor. The fifth insulating material and the eighth conductor are positioned on the first conductor, in the stated order, in a region that does not overlap the first oxide. Further, the ninth conductor is positioned on the second conductor.

Description

Semiconductor device, memory device and electronic device

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] In recent years, with the increase in the amount of data handled, there has been a demand for memory devices with larger storage capacities. In order to increase the storage capacity per unit area, it is effective to form memory cells by stacking them, as in 3D NAND type memory devices (see Patent Documents 1 to 3). By stacking memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells.

[0004] US Patent Application Publication No. 2011 / 0065270 US Patent Application Publication No. 2016 / 0149004 US Patent Application Publication No. 2013 / 0069052

[0005] An object of one embodiment of the present invention is to provide a semiconductor device with large storage capacity.An object of one embodiment of the present invention is to provide a semiconductor device with high storage density.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide a novel memory device including the semiconductor device.An object of one embodiment of the present invention is to provide a novel electronic device including the memory device.

[0006] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems. Note that one embodiment of the present invention does not necessarily solve all of the above problem and other problems.

[0007] (1) One embodiment of the present invention is a semiconductor device including a first layer and a first insulator, wherein the first layer includes a first oxide semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a second insulator, a third insulator, a fourth insulator, and a fifth insulator.

[0008] The first layer is located on the first insulator. The first oxide semiconductor is located above the first insulator. The first conductor is located on the top surface and side surfaces of the first oxide semiconductor and on the top surface of the first insulator, and the second conductor is located on the top surface of the first oxide semiconductor. The second insulator is located between the first conductor and the second conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the third conductor is located on the top surface of the second insulator. The fourth conductor is located on the top surface of the first oxide semiconductor. The third insulator is located between the second conductor and the fourth conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the fifth conductor is located on the top surface of the third insulator. The sixth conductor is located on the top surface and side surfaces of the first oxide semiconductor and on the top surface of the first insulator. The fourth insulator is located between the fourth conductor and the sixth conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the seventh conductor is located on the top surface of the fourth insulator. The fifth insulator is located on the first conductor in a region that does not overlap with the first oxide semiconductor but overlaps with the first insulator, the eighth conductor is located on the fifth insulator, and the ninth conductor is located on the second conductor.

[0009] (2) Alternatively, in one aspect of the present invention, in the above-mentioned (1), the first layer may have a second oxide semiconductor, a tenth conductor, an eleventh conductor, a twelfth conductor, a thirteenth conductor, and a sixth insulator. In particular, it is preferable that the second oxide semiconductor is located above the first insulator, the tenth conductor is located on the top surface and side surfaces of the second oxide semiconductor and on the top surface of the first insulator, and the eleventh conductor is located on the top surface of the second oxide semiconductor. It is also preferable that the sixth insulator is located between the tenth conductor and the eleventh conductor in a cross-sectional view and on the top surface of the second oxide semiconductor, and the twelfth conductor is located on the sixth insulator. It is also preferable that the thirteenth conductor is located on the first conductor and on the twelfth conductor.

[0010] (3) Alternatively, according to one aspect of the present invention, in the above-described (2), the semiconductor device may further include a second layer and a seventh insulator. In particular, the second layer preferably includes a third oxide semiconductor, a fourteenth conductor, a seventh insulator, and an eighth insulator. The seventh insulator is preferably located on the first layer, and the second layer is preferably located on the seventh insulator. The third oxide semiconductor preferably has a region overlapping with the eighth conductor and the thirteenth conductor, the eighth insulator is preferably overlapping with the eighth conductor and located on the top surface of the third oxide semiconductor, and the fourteenth conductor is preferably located on the eighth insulator.

[0011] (4) Alternatively, in one embodiment of the present invention, in the above (3), each of the first oxide semiconductor, the second oxide semiconductor, and the third oxide semiconductor may contain one or more elements selected from indium, zinc, and an element M.

[0012] The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.

[0013] (5) Another embodiment of the present invention is a memory device including the semiconductor device according to any one of (1) to (4) above and a driver circuit, wherein the first insulator is located above the driver circuit.

[0014] (6) Another embodiment of the present invention is an electronic device including the storage device according to (5) above and a housing.

[0015] (7) Another embodiment of the present invention is a semiconductor device including a first layer, a second layer, a first insulator, a second insulator, and a first conductor. Each of the first layer and the second layer includes a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator. The first layer is located on the first insulator, the second insulator is located on the first layer, and the second layer is located on the second insulator.

[0016] In each of the first layer and the second layer, the second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, and the third conductor is located on the top surface of the first oxide semiconductor. The fourth insulator is located between the second conductor and the third conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the fourth conductor is located on the top surface of the fourth insulator. The fifth conductor is located on the top surface of the first oxide semiconductor, the fifth insulator is located between the third conductor and the fifth conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the sixth conductor is located on the top surface of the fifth insulator. The seventh conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, the sixth insulator is located between the fifth conductor and the seventh conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the eighth conductor is located on the top surface of the sixth insulator. The seventh insulator is located in a region of the upper surface of the seventh conductor that does not overlap with the first oxide semiconductor, the ninth conductor is located on the upper surface of the seventh insulator, and the tenth conductor is located on the upper surface of the fifth conductor.

[0017] The second insulator has an opening, the first conductor is located in the opening, the first conductor is located on the top surface of the fourth conductor of the first layer, and a portion of the seventh conductor of the second layer is located on the top surface of the first conductor.

[0018] (8) Another embodiment of the present invention is a semiconductor device including a first layer, a second layer, a third layer, a first insulator, a second insulator, a third insulator, and a first conductor. Each of the first layer, the second layer, and the third layer includes a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator. The first layer is located on the first insulator, the second insulator is located on the first layer, the second layer is located on the second insulator, the third insulator is located on the second layer, and the third layer is located on the third insulator.

[0019] In each of the first layer, the second layer, and the third layer, the second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, and the third conductor is located on the top surface of the first oxide semiconductor. The fourth insulator is located between the second conductor and the third conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the fourth conductor is located on the top surface of the fourth insulator. The fifth conductor is located on the top surface of the first oxide semiconductor, the fifth insulator is located between the third conductor and the fifth conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the sixth conductor is located on the top surface of the fifth insulator. The seventh conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, the sixth insulator is located between the fifth conductor and the seventh conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the eighth conductor is located on the top surface of the sixth insulator. The seventh insulator is located in a region of the upper surface of the seventh conductor that does not overlap with the first oxide semiconductor, the ninth conductor is located on the upper surface of the seventh insulator, and the tenth conductor is located on the upper surface of the fifth conductor.

[0020] The second insulator has an opening, and the first conductor is located in the opening. The first conductor is located on an upper surface of the fourth conductor of the first layer, a portion of the seventh conductor of the second layer is located on the upper surface of the first conductor, and the ninth conductor of the second layer is located in a region overlapping the eighth conductor of the third layer.

[0021] (9) Another embodiment of the present invention is a semiconductor device having a configuration different from that of the semiconductor device of (7), which includes a first layer, a second layer, a first insulator, a second insulator, and a first conductor. Each of the first layer and the second layer includes a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator. The first layer is located on the first insulator, the second insulator is located on the first layer, and the second layer is located on the second insulator.

[0022] In each of the first layer and the second layer, the second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, and the third conductor is located on the top surface of the first oxide semiconductor. The fourth insulator is located between the second conductor and the third conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the fourth conductor is located on the top surface of the fourth insulator. The fifth conductor is located on the top surface of the first oxide semiconductor, the fifth insulator is located between the third conductor and the fifth conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the sixth conductor is located on the top surface of the fifth insulator. The seventh conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, the sixth insulator is located between the fifth conductor and the seventh conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the eighth conductor is located on the top surface of the sixth insulator. The seventh insulator is located in a region of the upper surface of the seventh conductor that does not overlap with the first oxide semiconductor, the ninth conductor is located on the upper surface of the seventh insulator, and the tenth conductor is located on the upper surface of the fifth conductor.

[0023] The second insulator has an opening, the first conductor is located in the opening, the first conductor is located on an upper surface of the sixth conductor of the first layer, and a portion of the seventh conductor of the second layer is located on an upper surface of the first conductor.

[0024] (10) Another embodiment of the present invention is a semiconductor device having a first layer, a second layer, a third layer, a first insulator, a second insulator, a third insulator, and a first conductor, the semiconductor device having a configuration different from that of (8). The first layer, the second layer, and the third layer each have a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator. The first layer is located on the first insulator, the second insulator is located on the first layer, the second layer is located on the second insulator, the third insulator is located on the second layer, and the third layer is located on the third insulator.

[0025] In each of the first layer, the second layer, and the third layer, the second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, and the third conductor is located on the top surface of the first oxide semiconductor. The fourth insulator is located between the second conductor and the third conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the fourth conductor is located on the top surface of the fourth insulator. The fifth conductor is located on the top surface of the first oxide semiconductor, the fifth insulator is located between the third conductor and the fifth conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the sixth conductor is located on the top surface of the fifth insulator. The seventh conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, the sixth insulator is located between the fifth conductor and the seventh conductor in a cross-sectional view and on the top surface of the first oxide semiconductor, and the eighth conductor is located on the top surface of the sixth insulator. The seventh insulator is located in a region of the upper surface of the seventh conductor that does not overlap with the first oxide semiconductor, the ninth conductor is located on the upper surface of the seventh insulator, and the tenth conductor is located on the upper surface of the fifth conductor.

[0026] The second insulator has an opening, and the first conductor is located in the opening. The first conductor is located on an upper surface of the sixth conductor of the first layer, a portion of the seventh conductor of the second layer is located on the upper surface of the first conductor, and the ninth conductor of the second layer is located in a region overlapping the eighth conductor of the third layer.

[0027] (11) Alternatively, in one embodiment of the present invention, in any one of the above (7) to (10), the first oxide semiconductor may contain one or more elements selected from indium, zinc, and an element M.

[0028] The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.

[0029] (12) Another embodiment of the present invention is a memory device including the semiconductor device according to (11) above and a driver circuit, wherein the first insulator is located above the driver circuit.

[0030] (13) Another embodiment of the present invention is an electronic device including the storage device according to (12) and a housing.

[0031] According to one embodiment of the present invention, a semiconductor device with large storage capacity can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high storage density can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a novel memory device including the semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a novel electronic device including the memory device can be provided.

[0032] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the above-described effects in some cases.

[0033] FIG. 1 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 2 is a cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 3 is a cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 4 is a perspective view showing an example of the configuration of a semiconductor device. FIG. 5 is a cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 6 is a perspective view showing an example of the configuration of a semiconductor device. FIG. 7 is a layout view showing an example of the configuration of a semiconductor device. FIG. 8A is a plan view showing an example of the configuration of a semiconductor device, and FIGS. 8B to 8D are cross-sectional views showing an example of the configuration of a semiconductor device. FIG. 9A is a plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 9B to 9D are cross-sectional views showing an example of the method for manufacturing a semiconductor device. FIG. 10A is a plan view showing an example of the method for manufacturing a semiconductor device, and FIGS. 10B to 10D are cross-sectional views showing an example of the method for manufacturing a semiconductor device. FIG. 11A is a plan view showing an example of the method for manufacturing a semiconductor device, and FIGS. 11B to 11D are cross-sectional views showing an example of the method for manufacturing a semiconductor device. FIG. 12A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 12B to 12D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device. FIG. 13A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 13B to 13D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device. FIG. 14A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 14B to 14D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device. FIG. 15A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 15B to 15D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device. FIG. 16A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 16B to 16D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device. FIG. 17A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 17B to 17D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device. Fig. 18A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Fig. 18B to Fig. 18D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device, Fig. 19A is a schematic plan view showing the example of a method for manufacturing a semiconductor device, and Fig. 19B to Fig. 19D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device.FIG. 20A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 20B to 20D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device. FIG. 21A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 21B to 21D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device. FIG. 22A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 22B to 22D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device. FIG. 23 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 24 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 25 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 26 is a schematic perspective view showing an example of the configuration of a semiconductor device. FIG. 27 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 28 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. FIGS. 29A and 29B are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device. 30A and 30B are cross-sectional schematic views illustrating an example of a method for manufacturing a semiconductor device. FIG. 31 is a cross-sectional schematic view illustrating an example of a method for manufacturing a semiconductor device. FIG. 32A is a perspective view illustrating an example of a configuration of a memory device, and FIG. 32B is a block diagram illustrating an example of a configuration of a semiconductor device. FIG. 33 is a block diagram illustrating an example of a configuration of a memory device. FIG. 34 is a cross-sectional schematic view illustrating an example of a configuration of a memory device. FIGS. 35A and 35B are diagrams illustrating an example of an electronic component. FIGS. 36A and 36B are diagrams illustrating an example of an electronic device, and FIGS. 36C to 36E are diagrams illustrating an example of a mainframe computer. FIG. 37 is a diagram illustrating an example of space equipment. FIG. 38 is a diagram illustrating an example of a storage system applicable to a data center. FIG. 39A is a graph illustrating source-drain breakdown voltage characteristics of a transistor, and FIG. 39B is a graph illustrating gate breakdown voltage characteristics of a transistor. FIG. 40 is a circuit diagram illustrating a memory cell of an example. FIG. 41 is a circuit diagram illustrating a memory device of an example. FIG. 42 is a timing chart illustrating an example of the operation of the memory device of an example. Figure 43 is a top view photograph of a memory die with memory devices. Figure 44A is a graph showing the voltage written to the memory device versus the voltage read from the memory device.Figure 44B is a graph showing the relationship between the voltage written to a memory device and three times the standard deviation σ of the voltage read from the memory device. Figures 45A and 45B are schematic diagrams of threshold voltage distributions of write voltages to a memory device. Figure 46A is a graph showing changes in read voltage over retention time in a memory device into which a voltage has been written, and Figure 46B is a graph showing the relationship between the initial read voltage and the amount of change in read voltage after a certain time in a memory device into which a voltage has been written. Figures 47A and 47B are schematic diagrams of threshold voltage distributions of write voltages to a memory device.

[0034] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are all examples of a semiconductor device. Furthermore, for example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device or may include a semiconductor device.

[0035] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film or a layer).

[0036] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, and a load) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0037] Note that when both an element and a power supply line (for example, VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or a wiring that provides a desired potential) are arranged between X and Y, it is not specified that X and Y are electrically connected. Note that when only a power supply line is arranged between X and Y, there is no other element between X and Y, so X and Y are directly connected. Therefore, when only a power supply line is arranged between X and Y, it can also be said that "X and Y are electrically connected." However, when both an element and a power supply line are arranged between X and Y, it can be said that X and the power supply line are electrically connected (via the element) and Y and the power supply line are electrically connected, but it is not specified that X and Y are electrically connected. Note that when the gate and source of a transistor are connected between X and Y, it is not specified that X and Y are electrically connected. Note that when the gate and drain of a transistor are connected between X and Y, it is not specified that X and Y are electrically connected. That is, in the case of a transistor, if there is a connection between X and Y via the drain and source of the transistor, it is defined that X and Y are electrically connected. Note that if a capacitive element is disposed between X and Y, it may or may not be defined that X and Y are electrically connected. For example, in the configuration of a digital circuit or logic circuit, if a capacitive element is disposed between X and Y, it may not be defined that X and Y are electrically connected. On the other hand, for example, in the configuration of an analog circuit, if a capacitive element is disposed between X and Y, it may be defined that X and Y are electrically connected.

[0038] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (for example, inverters, NAND circuits, and NOR circuits), signal conversion circuits (for example, digital-analog conversion circuits, analog-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (for example, power supply circuits such as step-up circuits or step-down circuits, and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (for example, circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0039] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0040] Furthermore, for example, it can be expressed as follows: "X, Y, the source (sometimes referred to as either the first terminal or the second terminal) and the drain (sometimes referred to as the other of the first terminal or the second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y." Or, it can be expressed as follows: "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in the circuit configuration, it is possible to distinguish between the source and drain of the transistor and determine the technical scope. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

[0041] Note that even when independent components are shown electrically connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has both the function of a wiring and the function of an electrode. Therefore, in this specification, the term "electrically connected" also includes such a case where one conductive film has the functions of multiple components.

[0042] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0043] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," or "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," or "gate capacitance." A "capacitance" (including a "capacitance" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0044] Furthermore, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification.

[0045] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0046] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0047] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. Also, a terminal, a wiring, etc. can be referred to as a node.

[0048] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0049] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0050] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0051] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0052] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0053] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0054] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0055] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" or "insulating film" may be changed to the term "insulator".

[0056] Furthermore, the terms "electrode," "wiring," and "terminal" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0057] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." The term "potential" applied to wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0058] In addition, timing charts may be used in this specification and the like to explain an operation method of a semiconductor device. The timing charts used in this specification and the like illustrate ideal operation examples, and the periods, magnitudes of signals (e.g., potentials or currents), and timings described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including nodes) in the timing charts described in this specification and the like can be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other period is shown as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long.

[0059] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0060] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0061] In this specification and the like, the term "semiconductor impurities" refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. When the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0062] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0063] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0064] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0065] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0066] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and one or more other content (or even part of the content) described in another embodiment.

[0067] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0068] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0069] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0070] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0071] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0072] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0073] 1 is a circuit diagram illustrating a configuration example of a semiconductor device DEV according to one embodiment of the present invention. The semiconductor device DEV includes, for example, a memory layer ALYa and a memory layer ALYb. Note that in FIG. 1, the memory layer ALYb is located above the memory layer ALYa.

[0074] Each of the memory layers ALYa and ALYb has a plurality of memory cells. In particular, as an example, each of the memory layers ALYa and ALYb has a plurality of memory cells arranged in an array. In FIG. 1, as an example, the memory layer ALYa has memory cells MCa arranged in a matrix of m rows and n columns (m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1). Similarly, in FIG. 1, as an example, the memory layer ALYb has memory cells MCb arranged in a matrix of m rows and n columns (m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1).

[0075] In this specification and drawings, for example, a memory cell located in the first row and first column of the matrix of the memory layer ALYa will be referred to as memory cell MCa[1,1], and a memory cell located in the mth row and nth column of the matrix of the memory layer ALYb will be referred to as memory cell MCb[m,n]. For example, FIG. 1 illustrates a memory cell MCa[i,j] located in the ith row and jth column (i is an integer from 1 to m, and j is an integer from 1 to n-1) of the matrix of the memory layer ALYa, and a memory cell MCa[i,j+1] located in the ith row and j+1th column. Also illustrated are a memory cell MCb[i,j] located in the ith row and jth column of the matrix of the memory layer ALYb, and a memory cell MCb[i,j+1] located in the ith row and j+1th column.

[0076] 1, the memory cells MCa and MCb have similar circuit configurations, and therefore, in this specification and drawings, when describing matters common to the memory cells MCa and MCb, the memory cells MCa and MCb will each be described as a memory cell MC.

[0077] The number of rows and columns of the matrix of the memory layer ALYa and the number of rows and columns of the matrix of the memory layer ALYb may be the same or different from each other.

[0078] 1 is an example of a memory cell called a gain cell, and includes a transistor M1, a transistor M2, a transistor M3, and a capacitor C1. In particular, in this specification and the like, a memory cell MC in which the transistors M1 to M3 are OS transistors may be referred to as a nonvolatile oxide semiconductor random access memory (NOSRAM (registered trademark)).

[0079] For example, OS transistors are preferably used as the transistors M1 to M3. Examples of metal oxides included in the channel formation regions of OS transistors include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes one or more elements selected from indium, the element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony. The element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0080] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium (In), tin (Sn), and zinc (Zn) (also referred to as ITZO (registered trademark)) is preferably used. Alternatively, an oxide containing indium (In), gallium (Ga), tin (Sn), and zinc (Zn) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) is preferably used. Note that an OS transistor will be described in detail when describing an example of a cross-sectional structure of a semiconductor device.

[0081] The transistors M1 to M3 may be transistors other than OS transistors. For example, the transistors M1 to M3 may be transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors). Silicon may be, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon (including low-temperature polycrystalline silicon).

[0082] In addition to OS transistors and Si transistors, the transistors M1 to M3 can be, for example, transistors including germanium in a channel formation region, transistors including a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, transistors including carbon nanotubes in a channel formation region, or transistors including an organic semiconductor in a channel formation region.

[0083] Although the transistors M1 to M3 shown in FIG. 1 are n-channel transistors, they may be p-channel transistors depending on the situation or in some cases. Furthermore, when an n-channel transistor is replaced with a p-channel transistor, the potential input to the memory cell MC must be appropriately changed so that the memory cell MC operates normally. This also applies to transistors described elsewhere in the specification and transistors shown in other drawings, not just FIG. 1. In this embodiment, the configuration of the memory cell MC will be described assuming that the transistors M1 to M3 are n-channel transistors.

[0084] Furthermore, when each of the transistors M1 to M3 is on, it is preferable that they operate in the saturation region. For example, when the gate-source voltage of any one of the transistors M1 to M3 is constant, the current flowing between the source and drain of that transistor is larger than when that transistor operates in the linear region. Increasing the amount of current in this way increases the signal transmission speed, which ultimately increases the operating speed of the circuit.

[0085] Depending on the situation, one or more selected from the transistors M1 to M3 may operate in the linear region, or one or more selected from the transistors M1 to M3 may operate in the subthreshold region.

[0086] As an example, the transistor M1 has a structure having a pair of gates sandwiching a channel, and the transistor M1 has a first gate and a second gate. For convenience, as an example, the first gate is described as a gate (sometimes referred to as a front gate) and the second gate is described as a back gate, but the first gate and the second gate can be interchanged. As a specific example, a connection configuration in which "the gate is electrically connected to a first wiring, and the back gate is electrically connected to a second wiring" can be replaced with a connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring."

[0087] The transistors M2 and M3 may have a structure without a back gate.

[0088] Note that the above description of the transistors can be applied not only to the transistors M1 to M3 but also to other transistors described in the specification and in the drawings.

[0089] Next, the circuit configuration of the memory cell MCa[i, j] and the memory cell MCa[i, j+1] will be described.

[0090] In the memory cells MCa[i,j] and MCa[i,j+1] of the memory layer ALYa, the first terminal of the transistor M1 is electrically connected to the gate of the transistor M2 and the first terminal of the capacitive element C1, and the first terminal of the transistor M2 is electrically connected to the first terminal of the transistor M3.

[0091] In the memory cell MCa[i,j] of the memory layer ALYa, the second terminal of the transistor M1 is electrically connected to the wiring WRBLa[j], the second terminal of the transistor M2 is electrically connected to the wiring SLa[j], the second terminal of the transistor M3 is electrically connected to the wiring WRBLa[j+1], the gate of the transistor M1 is electrically connected to the wiring WWLa[i], the second terminal of the capacitor C1 is electrically connected to the wiring CLa[i], and the gate of the transistor M3 is electrically connected to the wiring RWLa[i].

[0092] In the memory cell MCa[i,j+1] of the memory layer ALYa, the second terminal of the transistor M1 is electrically connected to the wiring WRBLa[j+1], the second terminal of the transistor M2 is electrically connected to the wiring SLa[j+1], and the second terminal of the transistor M3 is electrically connected to the wiring WRBLa[j+2]. In addition, the gate of the transistor M1 is electrically connected to the wiring WWLa[i], the second terminal of the capacitor C1 is electrically connected to the wiring CLa[i], and the gate of the transistor M3 is electrically connected to the wiring RWLa[i].

[0093] In each of the memory cells MCa[i, j] and MCa[i, j+1] of the memory layer ALYa, the back gate of the transistor M1 may be electrically connected, for example, to a wiring extending below the memory layer ALYa (not shown).

[0094] The wiring WWLa[i] functions as, for example, a write word line for the memory cell MCa[i,j] and the memory cell MCa[i,j+1] included in the memory layer ALYa. That is, the wiring WWLa[i] functions as a wiring that transmits a selection signal (which may be a current, a variable potential, or a pulse voltage) for selecting the memory cell MCa to be written to. Note that the wiring WWLa[i] may also function as a wiring that applies a fixed potential depending on the situation.

[0095] The wiring RWLa[i] functions as, for example, a read word line for the memory cell MCa[i,j] and the memory cell MCa[i,j+1] included in the memory layer ALYa. That is, the wiring RWLa[i] functions as a wiring that transmits a selection signal (which may be a current, a variable potential, or a pulse voltage) for selecting the memory cell MCa to be read. Note that the wiring RWLa[i] may also function as a wiring that applies a fixed potential depending on the situation.

[0096] The wiring WRBLa[j] functions as, for example, a write bit line for the memory cell MCa[i,j] included in the memory layer ALYa. That is, the wiring WRBLa[j] functions as a wiring that transmits write data to the selected memory cell MCa[i,j]. Also, the wiring WRBLa[j+1] functions as a write bit line for the memory cell MCa[i,j+1] included in the memory layer ALYa. That is, the wiring WRBLa[j+1] functions as a wiring that transmits write data to the selected memory cell MCa[i,j+1].

[0097] In addition, the wiring WRBLa[j+1] also functions as a read bit line for the memory cell MCa[i, j] included in the memory layer ALYa, for example. That is, the wiring WRBLa[j+1] functions as a wiring that transmits read data from the selected memory cell MCa[i, j]. In addition, the wiring WRBLa[j+2] functions as a write bit line for the memory cell MCa[i, j+1] included in the memory layer ALYa. That is, the wiring WRBLa[j+2] functions as a wiring that transmits read data from the selected memory cell MCa[i, j+1].

[0098] The wiring WRBLa[j] functions as, for example, a read bit line for a memory cell MCa[i, j-1] (not shown in FIG. 1 , where j is an integer equal to or greater than 2) included in the memory layer ALYa. The wiring WRBLa[j+1] functions as, for example, a write bit line for a memory cell MCa[i, j+2] (not shown in FIG. 1 , where j is an integer equal to or less than n-2) included in the memory layer ALYa.

[0099] That is, the wiring WRBLa functions as a write bit line for one of the memory cells adjacent to each other via the wiring WRBLa, and also functions as a read bit line for the other of the memory cells adjacent to each other via the wiring WRBLa.

[0100] Note that the wirings WRBLa[j] to WRBLa[j+2] may function as wirings that apply a fixed potential depending on the situation.

[0101] The wiring SLa[j] functions as a wiring that applies a fixed potential to the memory cell MCa[i,j] included in the memory layer ALYa, for example. The wiring SLa[j+1] functions as a wiring that applies a fixed potential to the memory cell MCa[i,j+1] included in the memory layer ALYa, for example. Note that the wiring SLa[j] and the wiring SLa[j+1] may each function as a wiring that applies a variable potential depending on the situation.

[0102] The wiring CLa[i] functions as a wiring that applies a fixed potential to the memory cell MCa[i, j] and the memory cell MCa[i, j+1] included in the memory layer ALYa, for example. Note that the wiring CLa[i] may also function as a wiring that applies a variable potential depending on the situation.

[0103] 1 , the configuration of the memory layer ALYb can be the same as that of the memory layer ALYa. Therefore, in the configuration of the memory cell MCb, in the above description of the configuration of the memory cell MCa, the wiring WWLa[i] can be replaced with the wiring WWLb[i], the wiring RWLa[i] can be replaced with the wiring RWLb[i], the wirings WRBLa[j] to WRBLa[j+2] can be replaced with the wirings WRBLb[j] to WRBLb[j+2], the wirings SLa[j] and SLa[j+1] can be replaced with the wirings SLb[j] and SLb[j+1], and the wiring CLa[i] can be replaced with the wiring CLb[i].

[0104] Furthermore, the back gate of the transistor M1 included in each of the memory cells MCb[i,j] and MCb[i,j+1] arranged in the memory layer ALYb is electrically connected to, for example, a wiring CLa extending to the memory layer ALYa. Furthermore, the second terminal of the capacitance element C1 included in each of the memory cells MCb[i,j] and MCb[i,j+1] arranged in the memory layer ALYb may be electrically connected to, for example, a wiring (not shown) extending to a memory layer above the memory layer ALYb.

[0105] Next, writing data to and reading data from memory cells MC in the semiconductor device DEV shown in Fig. 1 will be described. Here, as an example, writing data to and reading data from memory cells MCa[i, j] of a memory layer ALYa of the semiconductor device DEV will be described.

[0106] 1 , data is written to the memory cell MCa[i,j], for example, by first applying a first potential (e.g., ground potential) to the wiring CLa[i]. Next, a high-level potential is applied to the wiring WWLa[i] to turn on the transistor M1 included in the memory cell MCa[i,j]. A low-level potential is applied to the wirings WWLa[1] to WWLa[m] other than the wiring WWLa[i] to turn off the transistor M1 included in the memory cells MCa in the first to m-th rows other than the i-th row. A low-level potential is also applied to the wirings RWLa[1] to RWLa[m] to turn off the transistor M3 included in the memory cell MCa[i,j].

[0107] Then, write data is sent to the wiring WRBLa[j], and a potential corresponding to the data is written to the first terminal of the capacitance element C1 of the memory cell MCa[i,j]. After writing the data to the first terminal of the capacitance element C1 of the memory cell MCa[i,j], a low-level potential is applied to the wiring WWLa[i], turning off the transistor M1 included in the memory cell MCa[i,j]. This completes writing the data to the memory cell MCa[i,j].

[0108] To read data from the memory cell MCa[i,j] of the semiconductor device DEV shown in FIG. 1 , for example, first, a second potential (e.g., a high-level potential higher than the first potential) is applied to the wiring WRBLa[j+1]. Next, a high-level potential is applied to the wiring RWLa[i] to turn on the transistor M3 included in the memory cell MCa[i,j]. At this time, if the transistor M2 of the memory cell MCa[i,j] operates in the saturation region, a current corresponding to the gate-source voltage of the transistor M2 (the potential difference between the gate potential of the transistor M2 and the potential of the wiring SLa[j]) flows. As a result, the current flows from the wiring WRBLa[j+1] to the wiring SLa[j] via the transistor M2. The current flowing through the wiring WRBLa[j+1] can be input to a read circuit to read out the data written in the memory cell MCa[i,j]. Here, the data written to the memory cell MCa[i,j] is read from the amount of current, but the data written to the memory cell MCa[i,j] may also be read from the voltage change of the wiring WRBLa[j+1].

[0109] Note that data can be written to or read from other memory cells MCa in the same manner as above.

[0110] Note that the circuit configuration of the semiconductor device of one embodiment of the present invention is not limited to the configuration in FIG. 1. The circuit configuration of the semiconductor device may be changed depending on the situation.

[0111] 1, the wirings SLa[j] and SLa[j+1] extend in the column direction of the matrix of the memory layer ALYa, but the wirings SLa[j] and SLa[j+1] may also extend in the row direction of the matrix of the memory layer ALYa. Similarly, the wirings extending in one of the row direction or the column direction may be changed to extend in the other of the row direction or the column direction.

[0112] <Example of Cross-Sectional Configuration of Semiconductor Device> Next, an example of the configuration of the semiconductor device DEV will be described.

[0113] 2 is a cross-sectional schematic diagram showing a configuration example of a semiconductor device DEV according to one embodiment of the present invention. In FIG. 2, the semiconductor device DEV is configured to include not only memory layers ALYa and ALYb, but also a memory layer ALYc above the memory layer ALYb. The memory layer ALYc includes a memory cell MCc having a configuration similar to that of the memory cell MCa and the memory cell MCb. Also, in FIG. 2, the semiconductor device DEV is configured to include memory layers below the memory layer ALYa and above the memory layer ALYc.

[0114] 3 is a schematic cross-sectional view focusing on the memory layer ALYa and the memory layer ALYb in the configuration example of the semiconductor device DEV of FIG. 2, and the schematic cross-sectional view of FIG. 3 shows, as an example, symbols indicating the components of the memory layer ALYa and the memory layer ALYb.

[0115] 3 shows a configuration example in which the memory layer ALYa is provided on the insulator 122a, the insulator 122b is provided on the memory layer ALYa, and the memory layer ALYb is provided on the insulator 122b. Details of the insulators 122a and 122b will be described later.

[0116] 2 to 22D is parallel to the channel length directions of the transistors M1, M2, and M3, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions. The X, Y, and Z directions shown in FIGS. 2 to 22D are right-handed.

[0117] Fig. 4 is a schematic perspective view showing a configuration example of a portion of the memory layer ALYa of the semiconductor device DEV of Fig. 3. Note that in order to make the structure of the memory layer ALYa easier to see, the insulators 122b, 180, 180_0, and 175 are not shown in Fig. 4. Note that the details of the insulators 122b, 180, 180_0, and 175 will be described later.

[0118] In the memory layer ALYa of FIG. 4, the conductors 160_0, 160_1, 160_2, 160_3, 160_4, 170_2, 170_4, and 170_5 described below are, for example, extended in the Y direction.

[0119] In order to simply explain a configuration example of the semiconductor device DEV, attention will first be focused on the memory layer ALYa in FIG.

[0120] In the memory layer ALYa, the memory cell MCa is provided on the insulator 122a.

[0121] As described in the circuit configuration example, the memory cell MCa includes a transistor M1, a transistor M2, a transistor M3, and a capacitor C1. Note that in FIG. 3, the transistors M1 to M3 are OS transistors, for example. That is, the semiconductor layers of the transistors M1 to M3 contain metal oxide.

[0122] 3 , each of the transistors M1 to M3 includes an insulator 124 and an oxide 130. The transistor M1 includes a conductor 142a, a conductor 142d, a conductor 160_2, a conductor 170_0, a conductor 160_0, an insulator 153_2, and an insulator 154_2. The transistor M2 includes a conductor 142b, a conductor 142c, a conductor 160_3, an insulator 153_3, and an insulator 154_3. The transistor M3 includes a conductor 142c, a conductor 142d, a conductor 160_4, an insulator 153_4, and an insulator 154_4. The capacitor C1 includes a conductor 142a, a conductor 160_1, an insulator 153_1, and an insulator 154_1.

[0123] For example, the conductors 160_2 to 160_4 are provided so as to overlap with the oxide 130. The conductors 160_2 to 160_4 are arranged in order in the X direction so as not to overlap with each other. The conductor 160_2 functions as the gate of the transistor M1, the conductor 160_3 functions as the gate of the transistor M2, and the conductor 160_4 functions as the gate of the transistor M3. Each gate may be referred to as a first gate. In this specification and the like, the conductors 160_2 to 160_4 may be referred to as a gate electrode or a first gate electrode. The conductor 160_2 functions as, for example, the wiring WWLa[i] in FIG. 1. The conductor 160_4 functions as, for example, the wiring RWLa[i] in FIG. 1.

[0124] The insulators 153_2 and 154_2 function as first gate insulating films in the transistor M1. The insulators 153_3 and 154_3 function as first gate insulating films in the transistor M2. The insulators 153_4 and 154_4 function as first gate insulating films in the transistor M3.

[0125] The insulator 124 is provided on the insulator 122a. The insulator 122a and the insulator 124 function as a second gate insulating film of the transistor M1.

[0126] For example, the oxide 130 is provided over the insulator 124. The oxide 130 functions as a semiconductor included in the channel formation regions of the transistors M1 to M3.

[0127] The conductor 160_0 and the conductor 170_0 function as back gates (sometimes referred to as second gates) of the transistor M1. Therefore, in this specification and the like, the conductor 160_0 and the conductor 170_0 may be referred to as back gate electrodes or second gate electrodes, respectively. The conductor 160_0 and the conductor 170_0 also function as one of a pair of electrodes of a capacitor included in a memory cell in a memory layer located below the memory layer ALYa.

[0128] Note that Figure 3 illustrates an insulator 153_0 and an insulator 154_0 formed around the conductor 160_0 in a memory layer located below the memory layer ALYa, and an insulator 180_0 (sometimes called a planarizing film or an interlayer film) that embeds them.

[0129] In the transistor M1, the conductor 142a is provided on the top surface and side surface of the oxide 130 and in a region that does not overlap with the oxide 130, for example. Specifically, the conductor 142a is provided on part of the oxide 130 and part of the insulator 122a. The conductor 142d is provided on part of the oxide 130, for example. In particular, the conductor 142a and the conductor 142d are physically separated from each other by the insulators 153_2 and 154_2. The conductor 142a functions as one of the source and drain of the transistor M1, and the conductor 142d functions as the other of the source and drain of the transistor M1. For this reason, in this specification and the like, the conductor 142a may be referred to as one of the source and drain electrodes, and the conductor 142d may be referred to as the other of the source and drain electrodes. The conductor 142d functions as, for example, any one of the wirings WRBLa[j], WRBLa[j+1], and WRBLa[j+2] in FIG. 1 or a conductor electrically connected to the wiring. Note that an insulator 175 is provided over the conductor 142a and the conductor 142d to prevent oxygen from diffusing into the conductor 142a and the conductor 142d.

[0130] In the transistor M2, the conductor 142b is provided on the top surface and side surface of the oxide 130 and in a region that does not overlap with the oxide 130, for example. Specifically, the conductor 142b is provided on part of the oxide 130 and part of the insulator 122a. Similarly, the conductor 142c is provided on part of the oxide 130, for example. In particular, the conductor 142b and the conductor 142c are physically separated from each other by the insulators 153_3 and 154_3. The conductor 142b functions as one of the source and the drain of the transistor M2, and the conductor 142c functions as the other of the source and the drain of the transistor M2. The conductor 142b functions as one of the wirings SLa[j] and SLa[j+1] in FIG. 1 or as a conductor electrically connected to the wiring SLa. Note that an insulator 175 is provided over the conductor 142b and the conductor 142c to prevent oxygen from diffusing into the conductor 142b and the conductor 142c.

[0131] In addition, in the transistor M3, the conductor 142c is provided, for example, on a portion of the oxide 130. Similarly, the conductor 142d is provided, for example, on a portion of the oxide 130. In particular, the conductor 142c and the conductor 142d are physically separated from each other by insulators 153_4 and 154_4. The conductor 142c functions as one of the source and the drain of the transistor M3, and the conductor 142d functions as the other of the source and the drain of the transistor M3.

[0132] In a region of the top surface of the conductor 142a that does not overlap with the oxide 130, an insulator 153_1, an insulator 154_1, and a conductor 160_1 are provided in this order. In particular, a capacitor C1 is formed in a region where the conductor 142a and the conductor 160_1 overlap with each other with the insulators 153_1 and 154_1 interposed therebetween. That is, part of the conductor 142a functions as one of a pair of electrodes of the capacitor C1, and part of the conductor 160_1 functions as the other of the pair of electrodes of the capacitor C1. Part of the insulator 153_1 and part of the insulator 154_1 function as dielectrics of the capacitor C1.

[0133] Note that the conductors 160_1 to 160_4 may be formed in separate steps, or may be formed collectively in the same step.

[0134] The memory layer ALYa also includes an insulator 180 that functions as a planarization film or an interlayer film. The insulator 180 is formed to cover the transistors M1 to M3. The conductors 160_1 to 160_4 are formed to be embedded in the insulator 180.

[0135] The same insulating material can be used for the insulators 180_0 and 180. Specific insulating materials that can be used for the insulators 180_0 and 180 will be described later.

[0136] The insulator 180 has a first opening in a region that overlaps with the conductor 142a but does not overlap with the oxide 130. A conductor 170_3 is provided inside the first opening and in a part of the insulator 180. The conductor 170_3 is electrically connected to the conductor 160_3.

[0137] The insulator 180 has a second opening in a region overlapping with the conductor 142d. A conductor 170_5 is provided inside the second opening and on a part of the insulator 180. The conductor 170_5 functions as, for example, any one of the wirings WRBLa[j], WRBLa[j+1], and WRBLa[j+2] in FIG.

[0138] A conductor 170_1 is provided over the insulator 180, the insulator 153_1, the insulator 154_1, and the conductor 160_1. The conductor 170_1 or the conductor 160_1 functions as, for example, the wiring CLa[i] in FIG. 1. The conductor 170_1 also functions as a backgate electrode of the transistor M1 included in the memory layer ALYb.

[0139] The conductor 170_2 is provided over the insulator 180, the insulator 153_2, the insulator 154_2, and the conductor 160_2. The conductor 170_2 or the conductor 160_2 functions as, for example, the wiring WWLa[i] in FIG.

[0140] The conductor 170_4 is provided over the insulator 180, the insulator 153_4, the insulator 154_4, and the conductor 160_4. The conductor 170_4 or the conductor 160_4 functions as, for example, the wiring RWLa[i] in FIG.

[0141] Note that the conductors 170_1 to 170_5 may be formed in separate steps, or may be formed collectively in the same step.

[0142] In addition, an insulator 122b is provided above the insulator 180 and the conductors 170_1 to 170_5.

[0143] The insulators 122a and 122b can be formed using the same insulating material. Specific insulating materials that can be used for the insulators 122a and 122b will be described later.

[0144] A memory layer ALYb is provided on the insulator 122b.

[0145] 2 and 3, the memory layer ALYb can be formed in the same manner as the memory layer ALYa. In particular, the memory layer ALYb is formed so that the conductor 170_1 and the gate electrode of the transistor M1 of the memory layer ALYb (corresponding to the conductor 160_2 in the memory layer ALYa) overlap. Note that in FIGS. 2 and 3, the cross-sectional configuration of the memory layer ALYb is a configuration obtained by rotating the cross-sectional configuration of the memory layer ALYa by 180 degrees in the X-Y plane.

[0146] 2 and 3, by configuring the semiconductor device DEV, it is possible to simultaneously form a conductor corresponding to the back gate electrode of the transistor M1 in the memory layer ALYb and a conductor corresponding to the other of the pair of electrodes of the capacitive element C1 in the memory layer ALYa. In other words, the configuration shown in FIG. 2 and 3 has the effect of reducing the number of photomasks for fabricating the semiconductor device DEV compared to conventional methods and the effect of shortening the fabrication process of the semiconductor device DEV.

[0147] 2 may be modified depending on the situation. For example, although the semiconductor device DEV in FIG. 2 has a configuration including a plurality of memory layers, the semiconductor device DEV according to one embodiment of the present invention may have only one memory layer.

[0148] 2 (FIG. 3) may be modified to have the configuration of the semiconductor device DEV shown in FIG. 5. The semiconductor device DEV in FIG. 5 differs from the semiconductor device DEV in FIG. 2 (FIG. 3) in that the conductor 170_1 (the conductor 170_0 on the conductor 160_0) is not provided over the conductor 160_1. As described above, in FIG. 2 (FIG. 3), the conductor 170_1 (the conductor 170_0) functions as the backgate electrode of the transistor M1. However, if the conductor 160_1 (the conductor 160_0) alone functions as the backgate electrode of the transistor M1, the conductor 170_1 (the conductor 170_0) does not need to be provided, as in the configuration of the semiconductor device DEV in FIG. 5.

[0149] 4 may be changed to the configuration of the memory layer ALYa shown in Fig. 6. The memory layer ALYa in Fig. 4 has a configuration in which the conductor 160_1 extends in the Y direction, but in the memory layer ALYa in Fig. 6, the conductor 170_1 extends in the Y direction instead of the conductor 160_1. Note that in the memory layer ALYa in Fig. 6, the insulator 153_1, the insulator 154_1, and the conductor 160_1 are formed inside the opening of the insulator 180 (not shown) that overlaps with the insulator 122a.

[0150] 2 and 3, for example, one of a pair of electrodes of the capacitance element C1 of the memory layer ALYa and the back gate electrode of the transistor M1 of the memory layer ALYb are shared by each other, thereby making it possible to reduce the area occupied by the memory cell MC. This allows the semiconductor device to be miniaturized or highly integrated, and as a result, makes it possible to increase the memory density.

[0151] 2 and 3 , three transistors are formed on one oxide 130, thereby reducing the area occupied by the transistors. Specifically, the three transistors share the oxide 130, the second terminal of the transistor M1 and the second terminal of the transistor M3 share the conductor 142d, and the first terminal of the transistor M2 and the first terminal of the transistor M3 share the conductor 142c. This allows the transistors M1 to M3 to be formed in an area smaller than the area of ​​three transistors (for example, the area of ​​2.5 transistors). Furthermore, when multiple transistors are electrically connected, wirings (which may be referred to as electrodes or terminals) such as gates, sources, and drains, and contact holes (which may be referred to as vias) for electrically connecting to the wirings, are required. For example, when the source of a first transistor and the drain of a second transistor are electrically connected, a first contact hole is formed on the wiring corresponding to the source of the first transistor and a second contact hole is formed on the wiring corresponding to the drain of the second transistor, thereby forming a wiring that electrically connects the first contact hole and the second contact hole. 2 and 3, it is possible to reduce the number of contact holes, etc., by forming three transistors on one oxide 130. As a result, the area occupied by the memory cell can be reduced, which allows the semiconductor device to be miniaturized or highly integrated, and as a result, the memory density can be increased.

[0152] <Layout Example of Semiconductor Device> Next, the layout of a memory layer included in the semiconductor device DEV will be described.

[0153] 7 is a layout diagram (plan view) showing, as an example, the circuit configuration of the memory layer ALYa of the semiconductor device DEV shown in FIG. 6. In particular, FIG. 7 illustrates memory cell MCa[i, j], memory cell MCa[i+1, j], a portion of memory cell MCa[i, j-1], a portion of memory cell MCa[i+1, j-1], a portion of memory cell MCa[i, j+1], a portion of memory cell MCa[i+1, j+1], and a portion of memory cell MCa[i+1, j+1], as well as their peripheral areas. For convenience, FIG. 7 also illustrates wiring (conductor 170_0) extending below the memory layer ALYa. Furthermore, FIG. 7 does not illustrate insulators included in the semiconductor device DEV.

[0154] In the plan view shown in FIG. 7 , a conductor 170_0 is provided below the memory layer ALYa. An oxide 130 is provided on a region including the conductor 170_0. A conductor 142a and a conductor 142d are provided so as to cover part of the oxide 130. A conductor 160_2 is provided above a region between the conductor 142a and the conductor 142d, including a range where the conductor 170_0 and the oxide 130 overlap. This forms the transistor M1. A conductor 170_2 is provided on the conductor 160_2.

[0155] An opening PLa provided in an interlayer film (not shown) is located above the conductor 142a. An opening PLd provided in the interlayer film is located above the conductor 142d. A conductor 170_3 is buried in the opening PLa, and a conductor 170_5 is buried in the opening PLd. As a result, the conductor 170_3 buried in the opening PLa and the conductor 170_5 buried in the opening PLd function as wiring or a plug. In particular, the conductor 170_5 extends along the Y direction.

[0156] 7, the conductor 142b and the conductor 142c are provided so as to cover part of the oxide 130. A conductor 160_3 is provided in a region between the conductor 142b and the conductor 142c that overlaps with the oxide 130. This completes the formation of the transistor M2. A conductor 170_3 is provided over the conductor 160_3.

[0157] 7, a conductor 160_4 is provided in a region between the conductor 142c and the conductor 142d that overlaps with the oxide 130. This completes the transistor M3. A conductor 170_4 is provided on the conductor 160_4.

[0158] 7, an insulator (not shown) is provided on a part of the conductor 142a, and the conductor 160_1 is provided on the insulator. The insulator functions as a dielectric, thereby forming a capacitor C1 in which the part of the conductor 142a and the conductor 160_1 form a pair of electrodes. The conductor 170_1 is provided on the conductor 160_1.

[0159] The conductor 170_1 included in the memory layer ALYa also functions as a back gate electrode of the transistor M1 in the memory layer ALYb.

[0160] 7, the memory layer ALYa has conductors 142e, 142f, and 142g extending in the row direction. The conductor 142a of the transistor M1 also has a region extending in the row direction. Note that the conductors 142e, 142f, and 142g can be formed simultaneously with the conductors 142a, 142b, 142c, and 142d.

[0161] An opening PLc provided in an interlayer film (not shown) is located above the conductor 142e. A conductor 170_4 is buried in the opening PLc. As a result, the conductor 170_4 buried in the opening PLc functions as a wiring or a plug. Therefore, the conductor 142e and the conductor 160_4 of the transistor M3 are electrically connected to each other.

[0162] An opening PLb provided in an interlayer film (not shown) is located above the conductor 142f. A conductor 170_2 is buried in the opening PLb. As a result, the conductor 170_2 buried in the opening PLb functions as a wiring or a plug. Therefore, the conductor 142f and the conductor 160_2 of the transistor M1 are electrically connected to each other.

[0163] An opening PLe provided in an interlayer film (not shown) is located above the conductor 142g. The opening PLe is filled with a conductor 170_1. This allows the conductor 170_1 filled in the opening to function as a wiring or a plug. This electrically connects the conductor 142g and the conductor 160_1 of the capacitor C1 to each other.

[0164] As shown in FIG. 7, the conductor 142e functions as a wiring RWLa[i] or a wiring RWLa[i+1] extending in the row direction.

[0165] As shown in FIG. 7, the conductor 142f functions as a wiring WWLa[i] or a wiring WWLa[i+1] extending in the row direction.

[0166] As shown in FIG. 7, the conductor 142g functions as a wiring CLa[i] or a wiring CLa[i+1] extending in the row direction.

[0167] 1, the wirings SLa[j] and SLa[j+1] are described as wirings extending in the column direction, but the wirings SLa may extend in the row direction instead of the column direction. For example, as shown in FIG. 7, the conductor 142b of the transistor M2 may function as the wirings SLa[i] and SLa[i+1] extending in the row direction.

[0168] As shown in FIG. 7, the conductor 170_5 functions as a wiring WRBLa[j] and a wiring WRBLa[j+1] extending in the column direction.

[0169] The oxide 130, the conductor 142a, the conductor 142b, the conductor 142c, the conductor 142d, the conductor 142e, the conductor 142f, the conductor 142g, the conductors 160_1 to 160_4, and the conductors 170_1 to 170_5 can be formed by, for example, lithography. Specifically, for example, in the case of forming the conductor 142a, a conductive material to be the conductor 142a may be formed by one or more methods selected from a sputtering method, a chemical vapor deposition (CVD) method, a pulsed laser deposition (PLD) method, and an atomic layer deposition (ALD) method, and then a desired pattern may be formed by lithography. The oxide 130, the conductor 142b, the conductor 142c, the conductor 142d, the conductor 142e, the conductor 142f, the conductor 142g, the conductors 160_1 to 160_4, and the conductors 170_1 to 170_5 can also be formed by a method similar to that described above.

[0170] Furthermore, for example, an insulator is provided between the oxide 130 and the conductor 160_2, between the oxide 130 and the conductor 160_3, and between the oxide 130 and the conductor 160_4. In particular, the insulator may function as a first gate insulating film (which may be referred to as a gate insulating film or a front-gate insulating film).

[0171] Furthermore, in the process of forming the memory layer ALYa, in order to align the height of the film surface on which one or more materials selected from an insulator, a conductor, and a semiconductor are formed, planarization may be performed by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0172] <<Configuration Example of Memory Cell>> Next, a configuration example of the memory layer ALYa of the semiconductor device DEV shown in FIG. 3 will be described.

[0173] 8A to 8D are schematic plan views and cross-sectional views of a memory layer ALYa including transistors M1, M2, and M3 and a capacitive element C1 in the semiconductor device DEV of FIG. 3. FIG. 8A is a schematic plan view of the memory layer ALYa. Also, FIGS. 8B to 8D are cross-sectional views of the memory layer ALYa. Here, FIG. 8B is a cross-sectional view of the portion taken along dashed dotted line A1-A2 in FIG. 8A and is also a cross-sectional view in the channel length direction of the transistor M1. Also, FIG. 8C is a cross-sectional view of the portion taken along dashed dotted line A3-A4 in FIG. 8A and is also a cross-sectional view in the channel width direction of the transistor M1. Also, FIG. 8D is a cross-sectional view of the portion taken along dashed dotted line A5-A6 in FIG. 8A and is also a cross-sectional view of the capacitive element C1. Note that some elements are omitted from the plan view of FIG. 8A for clarity.

[0174] The memory layer located below the memory layer ALYa has an insulator 180_0, an insulator 153_0, an insulator 154_0, and a conductor 160_0 on a substrate (not shown). 8B also illustrates a first gate electrode and a first gate insulating film of a transistor included in the memory layer located below the memory layer ALYa.

[0175] The semiconductor device DEV also has a conductor 170_0 on a portion of the conductor of the memory layer located below the memory layer ALYa and on a portion of the insulator 180_0. The semiconductor device DEV also has an insulator 122a that covers the insulator 180_0, the conductor located on the insulator 180_0, the insulator 153_0, the insulator 154_0, the conductor 160_0, and the conductor 170_0.

[0176] The memory layer ALYa has an insulator 124 located in a region on the insulator 122a that includes the area overlapping with the conductor 160_0, an oxide 130 (oxide 130a and oxide 130b) located on the top surface of the insulator 124, a conductor 142a (conductor 142a1 and conductor 142a2) located on the top surface and side surface of the oxide 130, a conductor 142b (conductor 142b1 and conductor 142b2) located on the top surface and side surface of the oxide 130, a conductor 142c (conductor 142c1 and conductor 142c2) located on the top surface of the oxide 130, and a conductor 142d (conductor 142d1 and conductor 142d2) located on the top surface of the oxide 130. In addition, the memory layer ALYa has insulators 175 located on the upper surface of the insulator 122a, the upper surface of the conductor 142a, the upper surface of the conductor 142b, the upper surface of the conductor 142c, and the upper surface of the conductor 142d, and also has an insulator 180 located on the upper surface of the insulator 175.

[0177] The memory layer ALYa also includes an insulator 153_2 located on the top surface and side surfaces of the oxide 130, an insulator 154_2 located on the top surface of the insulator 153_2, and a conductor 160_2 (conductor 160a_2 and conductor 160b_2) located on the top surface of the insulator 154_2. The memory layer ALYa also includes conductors 170_2 (conductor 170a_2 and conductor 170b_2) located on the top surface of the insulator 153_2, the top surface of the insulator 154_2, the top surface of the conductor 160_2, and the top surface of the insulator 180. The memory layer ALYa also includes an insulator 153_3 located on the top surface and side surfaces of the oxide 130, an insulator 154_3 located on the top surface of the insulator 153_3, and a conductor 160_3 (conductor 160a_3 and conductor 160b_3) located on the top surface of the insulator 154_3. The memory layer ALYa also includes conductors 170_3 (conductor 170a_3 and conductor 170b_3) located on the top surface of the insulator 153_3, the top surface of the insulator 154_3, the top surface of the conductor 160_3, and the top surface of the insulator 180. The memory layer ALYa also includes an insulator 153_4 located on the top surface and side surfaces of the oxide 130, an insulator 154_4 located on the top surface of the insulator 153_4, and a conductor 160_4 (conductor 160a_4 and conductor 160b_4) located on the top surface of the insulator 154_4. The memory layer ALYa also includes conductors 170_4 (conductor 170a_4 and conductor 170b_4) located on the top surface of the insulator 153_4, the top surface of the insulator 154_4, the top surface of the conductor 160_4, and the top surface of the insulator 180. The memory layer ALYa also includes an insulator 153_1 located in a region that overlaps with the insulator 122a but does not overlap with the oxide 130, an insulator 154_1 located on the top surface of the insulator 153_1, and a conductor 160_1 (conductor 160a_1 and conductor 160b_1) located on the top surface of the insulator 154_1. The memory layer ALYa also includes a conductor 170_1 (conductor 170a_1 and conductor 170b_1) located on the top surface of the insulator 153_1, the top surface of the insulator 154_1, the top surface of the conductor 160_1, and the top surface of the insulator 180.

[0178] In the memory layer ALYa, the insulator 180 has an opening in a region that overlaps with the conductor 142a but does not overlap with the oxide 130. Conductors 170_3 (conductors 170a_3 and 170b_3) are located inside the opening and on the top surface of the insulator 180. In the memory layer ALYa, the insulator 180 also has an opening in a region that overlaps with the conductor 142d. Conductors 170_5 (conductors 170a_5 and 170b_5) are located inside the opening and on the top surface of the insulator 180.

[0179] In particular, the transistor M1, the transistor M2, the transistor M3, and the capacitive element C1 are disposed and embedded in the insulator 180.

[0180] In the region where the transistor M1 is formed, the insulator 180 and the insulator 175 have an opening 158_2 that reaches the oxide 130b. That is, the opening 158_2 can be said to have a region that overlaps with the oxide 130b. Furthermore, the insulator 175 can be said to have an opening that overlaps with the opening of the insulator 180. That is, the opening 158_2 includes the opening of the insulator 180 and the opening of the insulator 175.

[0181] The opening 158_2 includes an insulator 153_2, an insulator 154_2, and a conductor 160_2. That is, the conductor 160_2 has a region overlapping with the oxide 130b with the insulators 153 and 154 interposed therebetween. The conductor 160_2, the insulator 153_2, and the insulator 154_2 are provided between the conductor 142a and the conductor 142d in the channel length direction of the transistor M1 (or the transistor M2). The insulator 154_2 has a region in contact with a side surface of the conductor 160_2 and a region in contact with a bottom surface of the conductor 160_2. As shown in FIG. 8C , the insulator 122a and the insulator 153_2 are in contact with each other in a region of the opening 158_2 that does not overlap with the oxide 130.

[0182] 8A to 8D , in the region where the transistor M2 is formed, the insulator 180 and the insulator 175 have an opening 158_3 that reaches the oxide 130b, and in the region where the transistor M3 is formed, the insulator 180 and the insulator 175 have an opening 158_4 that reaches the oxide 130b. Similar to the opening 158_2, the opening 158_3 and the opening 158_4 can be said to include an opening in the insulator 180 and an opening in the insulator 175. Similar to the opening 158_2, the insulator 153_3, the insulator 154_3, and the conductor 160_3 are disposed in the opening 158_3, and the insulator 153_4, the insulator 154_4, and the conductor 160_4 are disposed in the opening 158_4. Note that the channel width configurations of the transistors M2 and M3 can be referred to the cross-sectional view of the channel width of the transistor M1 shown in FIG. 8C.

[0183] The oxide 130 preferably includes an oxide 130a disposed on the insulator 124 and an oxide 130b disposed on the oxide 130a. By having the oxide 130a below the oxide 130b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 130a to the oxide 130b.

[0184] Note that although the oxide 130 in each of the transistors M1 to M3 has a stacked structure of two layers, the oxide 130a and the oxide 130b, the present invention is not limited to this. For example, the oxide 130b may have a single layer or a stacked structure of three or more layers, or each of the oxide 130a and the oxide 130b may have a stacked structure.

[0185] 8A to 8D , the transistor M1 includes an oxide 130 that functions as a semiconductor layer, a conductor 160_2 that functions as a first gate (also referred to as a gate, top gate, or front gate) electrode, a conductor 170_0 that functions as a second gate (also referred to as a back gate) electrode, a conductor 142a that functions as one of a source electrode and a drain electrode, and a conductor 142d that functions as the other of the source electrode and the drain electrode. The transistor M1 also includes an insulator 153_2 and an insulator 154_2 that function as a first gate insulator. The transistor M1 also includes an insulator 122a and an insulator 124 that function as a second gate insulator. The gate insulator may also be referred to as a gate insulating layer or a gate insulating film. At least a part of a region of the oxide 130 that overlaps with the conductor 160_2 functions as a channel formation region.

[0186] The first gate electrode and the first gate insulating film are disposed in the opening 158_2 formed in the insulator 180 and the insulator 175. That is, the conductor 160_2, the insulator 154_2, and the insulator 153_2 are disposed in the opening 158_2.

[0187] The transistor M2 also includes an oxide 130 that functions as a semiconductor layer, a conductor 160_3 that functions as a gate (also referred to as a top gate or a front gate) electrode, a conductor 142b that functions as one of a source electrode and a drain electrode, and a conductor 142c that functions as the other of the source electrode and the drain electrode. The transistor M2 also includes an insulator 153_3 and an insulator 154_3 that function as gate insulators. The transistor M2 also includes an insulator 122a and an insulator 124. At least a part of a region of the oxide 130 that overlaps with the conductor 160_3 functions as a channel formation region.

[0188] The transistor M3 also includes an oxide 130 that functions as a semiconductor layer, a conductor 160_4 that functions as a gate (also referred to as a top gate or a front gate) electrode, a conductor 142c that functions as one of a source electrode and a drain electrode, and a conductor 142d that functions as the other of the source electrode and the drain electrode. The transistor M3 also includes an insulator 153_4 and an insulator 154_4 that function as gate insulators. The transistor M3 also includes an insulator 122a and an insulator 124. At least a part of a region of the oxide 130 that overlaps with the conductor 160_4 functions as a channel formation region.

[0189] The capacitor C1 includes a conductor 142a functioning as a lower electrode, an insulator 153_1 and an insulator 154_1 functioning as dielectrics, and a conductor 160_1 functioning as an upper electrode. That is, the capacitor C1 constitutes a metal-insulator-metal (MIM) capacitor.

[0190] The upper electrode and dielectric of the capacitor C1 are disposed in the opening 159 formed in the insulator 180 and the insulator 175. That is, the conductor 160_1, the insulator 153_1, and the insulator 154_1 are disposed in the opening 159.

[0191] Furthermore, in a region of the conductor 142a that does not overlap with the insulator 124 and the oxide 130b, openings in the insulators 175 and 180 that reach the conductor 142a are provided. The conductor 170_3 (the conductor 170a_3 and the conductor 170b_3) is disposed in the opening. The conductor 170_3 functions as a wiring or a plug.

[0192] As described above, the conductor 170_3 is also located over the insulator 180, the insulator 153_3, the insulator 154_3, and the conductor 160_3. Therefore, the conductor 170_3 and the conductor 160_3 are electrically connected to each other.

[0193] Furthermore, an opening in the insulator 175 and the insulator 180 that reaches the conductor 142d is provided on the top surface of the conductor 142d. The conductor 170_5 (the conductor 170a_5 and the conductor 170b_5) is disposed in the opening. The conductor 170_5 functions as a wiring or a plug.

[0194] As described above, the conductor 170_2 is located over the insulator 180, the insulator 153_2, the insulator 154_2, and the conductor 160_2. Therefore, the conductor 170_2 and the conductor 160_2 are electrically connected to each other. The conductor 170_2 functions as a wiring or a plug.

[0195] Similarly, as described above, the conductor 170_4 is located over the insulator 180, the insulator 153_4, the insulator 154_4, and the conductor 160_4. Therefore, the conductor 170_4 and the conductor 160_4 are electrically connected to each other. The conductor 170_4 also functions as a wiring or a plug.

[0196] The memory layer ALYa including the transistors M1, M2, and M3 and the capacitor C1 described in this embodiment can be used for a memory device.

[0197] <<Example of Manufacturing Method of Semiconductor Device>> Next, an example of a manufacturing method of the memory layer ALYa of the semiconductor device DEV shown in Fig. 8A to Fig. 8D will be described. Note that Fig. 9A to Fig. 22D will be used to describe the example of the manufacturing method.

[0198] 9A to 22D, A in each figure is a schematic plan view. B in each figure is a schematic cross-sectional view corresponding to the portion indicated by dashed dotted line A1-A2 in each figure A, and is also a schematic cross-sectional view in the channel length direction of transistors M1 to M3. C in each figure is a schematic cross-sectional view corresponding to the portion indicated by dashed dotted line A3-A4 in each figure A, and is also a schematic cross-sectional view in the channel width direction of transistor M1. D in each figure is a schematic cross-sectional view of the portion indicated by dashed dotted line A5-A6 in each figure A. Note that some elements are omitted from the schematic plan view A in each figure for clarity.

[0199] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE (Molecular Beam Epitaxy) method, a PLD method, or an ALD method.

[0200] First, a substrate (not shown) is prepared, and a memory layer below the memory layer ALYa is formed on the substrate. For example, the insulators 180_0, 153_0, 154_0, conductors 160_0, conductors 170_0, and insulators 122a are formed on the substrate (see FIGS. 9A to 9D ). Note that in addition to the insulators 180_0, 153_0, 154_0, conductors 160_0, conductors 170_0, and insulators 122a, FIGS. 9A to 9D also illustrate the first gate electrodes and first gate insulating films of the transistors M1 to M3 included in the memory layer below the memory layer ALYa.

[0201] For example, an insulator 180_0 is formed over the substrate, and then openings are formed in the insulator 180_0 in regions where the insulator 153_0, the insulator 154_0, and the conductor 160_0 are to be formed. After the openings are formed, a first insulating film to be the insulator 153_0, a second insulating film to be the insulator 154_0, and a first conductive film to be the conductor 160_0 are sequentially formed in the openings. Next, planarization treatment such as chemical mechanical polishing is performed to remove parts of the first insulating film, the second insulating film, and the first conductive film, thereby exposing the insulator 180_0. This allows the insulator 153_0, the insulator 154_0, and the conductor 160_0 to be formed only in the openings formed in the insulator 180_0.

[0202] Note that for the methods for forming the insulator 180_0, the insulator 153_0, the insulator 154_0, and the conductor 160_0, refer to the methods for forming the insulator 180, the insulators 153_1 to 153_4, the insulators 154_1 to 154_4, and the conductors 160_1 to 160_4 described later (see Figures 14A to 19D).

[0203] The first gate electrodes and first gate insulating films of the transistors M1 to M3 included in the memory layer below the memory layer ALYa can also be formed in the same manner as described above. The first gate insulating films of the transistors M1 to M3 can be formed simultaneously with the insulators 153_0 and 154_0. The first gate electrodes of the transistors M1 to M3 can be formed simultaneously with the conductor 160_0.

[0204] After that, a second conductive film to be the conductor 170 is formed on the top surfaces of the insulator 180, the insulator 153, the insulator 154, and the conductor 160, and the second conductive film is processed by lithography to form the conductor 170. Note that the formation of the conductor 170 can be performed by referring to the method for forming the conductors 170 to 5 described later (see FIGS. 20A to 22D).

[0205] Next, the insulator 122a is formed over the insulator 180_0, the insulator 153_0, the insulator 154_0, the conductor 160_0, and the conductor 170_0 (see FIGS. 9A to 9D). The insulator 122a can be an insulator containing one or both of an oxide of aluminum and hafnium. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of an oxide of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 122a has barrier properties against hydrogen and water, the hydrogen and water contained in the structures provided around the transistors M1 to M3 are prevented from diffusing into the inside of the transistors M1 to M3 through the insulator 122a, thereby preventing the generation of oxygen vacancies in the oxide 130.

[0206] The insulator 122a can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, hafnium oxide is formed as the insulator 122a by an ALD method. In particular, it is preferable to use a method for forming hafnium oxide with a reduced hydrogen concentration.

[0207] Note that the insulating material used for the insulator 122a may be a high-k material with a high dielectric constant. Examples of high-k materials with a high dielectric constant include metal oxides containing one or more of aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium, in addition to the above-mentioned hafnium oxide. Alternatively, the insulator 122a may be an insulator containing oxides of one or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or hafnium aluminate. Alternatively, the insulator 122a may be a material applicable to the insulators 153_1 to 153_4 or the insulators 154_1 to 154_4 described later. The insulator 122a may have a stacked structure containing two or more of the above-mentioned materials.

[0208] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0209] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being taken into the insulator 122a and the like as much as possible.

[0210] In this embodiment, after the insulator 122a is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. This heat treatment can remove impurities such as water or hydrogen contained in the insulator 122a. When an oxide containing hafnium is used as the insulator 122a, the heat treatment may cause part of the insulator 122a to crystallize. The heat treatment can also be performed at a timing such as after the insulator 124 is formed.

[0211] The transistors M1 to M3 and the capacitor C1 are formed over the insulator 122a in a later step. Therefore, the insulator 122a is preferably subjected to planarization treatment such as CMP.

[0212] Next, the insulating film 124Af is formed over the insulator 122a (see FIGS. 10A to 10D). The insulating film 124Af can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon oxide is formed as the insulating film 124Af by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulating film 124Af can be reduced. Because the insulating film 124Af will come into contact with the oxide 130a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0213] The insulating film 124Af may be made of an insulating material other than silicon oxide, such as silicon oxynitride.

[0214] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0215] Next, an oxide film 130Af and an oxide film 130Bf are formed in this order on the insulating film 124Af (see FIGS. 10A to 10D). It is preferable to form the oxide films 130Af and 130Bf consecutively without exposing them to the atmospheric environment. By forming them without exposing them to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide films 130Af and 130Bf, and to keep the vicinity of the interface between the oxide films 130Af and 130Bf clean.

[0216] The oxide films 130Af and 130Bf can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, the oxide films 130Af and 130Bf are formed by a sputtering method.

[0217] For example, when the oxide films 130Af and 130Bf are formed by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide films are formed by sputtering, the above-mentioned In-M-Zn oxide target or the like can be used.

[0218] In particular, during the formation of the oxide film 130Af, part of the oxygen contained in the sputtering gas may be supplied to the insulating film 124Af. Therefore, the proportion of oxygen contained in the sputtering gas may be set to 70% or more, preferably 80% or more, and more preferably 100%.

[0219] When the oxide film 130Bf is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 130Bf is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.

[0220] In this embodiment, for example, the oxide film 130Af is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4. The oxide film 130Bf is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2, or an oxide target with an atomic ratio of In:Ga:Zn = 1:1:2. Each oxide film may be formed according to the desired characteristics of the oxide 130a and the oxide 130b by appropriately selecting the film formation conditions and atomic ratios.

[0221] It is preferable to form the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf by sputtering without exposing them to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This can reduce the amount of hydrogen mixed into the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf between film formation steps.

[0222] The oxide films 130Af and 130Bf may be formed by ALD. By using ALD to form the oxide films 130Af and 130Bf, films with a uniform thickness can be formed even in trenches or openings with a large aspect ratio. Furthermore, by using PEALD (Plasma Enhanced Atomic Layer Deposition), the oxide films 130Af and 130Bf can be formed at a lower temperature than by thermal ALD.

[0223] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide films 130Af and 130Bf do not become polycrystallized, such as 250° C. to 650° C., preferably 400° C. to 600° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0224] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the oxide film 130Af and the oxide film 130Bf as much as possible.

[0225] In this embodiment, the heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. This heat treatment using oxygen gas can reduce impurities such as carbon, water, or hydrogen in the oxide films 130Af and 130Bf. Reducing the impurities in the films in this manner improves the crystallinity of the oxide films 130Bf, resulting in a denser, more compact structure. This increases the crystalline regions in the oxide films 130Af and 130Bf, reducing in-plane variations in the crystalline regions in the oxide films 130Af and 130Bf. This reduces in-plane variations in the electrical characteristics of the transistors M1 to M3.

[0226] Furthermore, by performing the heat treatment, hydrogen in the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf moves to the insulator 122a and is absorbed into the insulator 122a. In other words, hydrogen in the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf diffuses into the insulator 122a. Therefore, the hydrogen concentration in the insulator 122a increases, but the hydrogen concentrations in the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf decrease.

[0227] In particular, the insulating film 124Af functions as a gate insulator of the transistor M1. In some cases, the insulating film 124Af may also function as a gate insulator of the transistors M2 and M3. The oxide films 130Af and 130Bf function as channel formation regions of the transistors M1 to M3. Therefore, the transistors M1 to M3 including the insulating film 124Af, the oxide films 130Af, and the oxide films 130Bf with reduced hydrogen concentrations are preferable because they have good reliability.

[0228] Next, the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf are processed into strips using lithography to form the insulating layer 124A, the oxide layer 130A, and the oxide layer 130B (see FIGS. 11A to 11D ). The insulating layer 124A, the oxide layer 130A, and the oxide layer 130B are formed to extend in a direction parallel to the dashed-dotted line A3-A4 (the channel width direction of the transistor M1, or the Y direction shown in FIG. 11A ). The insulating layer 124A, the oxide layer 130A, and the oxide layer 130B are formed so that at least a portion of each overlaps with the conductor 160_0. This processing can be performed using dry etching or wet etching. Dry etching is suitable for microfabrication. The insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf may be processed under different conditions. Furthermore, the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf may be processed into a shape other than a strip shape.

[0229] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Next, a conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or ion beam may also be used instead of the light described above. When an electron beam or ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0230] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed on the oxide film 130Bf, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape. Etching of the oxide film 130Bf or the like may be performed after removing the resist mask, or may be performed while leaving the resist mask in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the oxide film 130Bf or the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0231] Next, a conductive film 142Af and a conductive film 142Bf are deposited in this order over the insulator 122a and the oxide layer 130B (see FIGS. 12A to 12D ). The conductive films 142Af and 142Bf can be deposited by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, tantalum nitride may be deposited as the conductive film 142Af by a sputtering method, and tungsten may be deposited as the conductive film 142Bf. Note that heat treatment may be performed before the deposition of the conductive film 142Af. The heat treatment may be performed under reduced pressure, and the conductive film 142Af may be deposited successively without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide layer 130B can be removed and the moisture and hydrogen concentrations in the oxide layers 130A and 130B can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment mode, the temperature of the heat treatment is set to 200° C.

[0232] Note that, other than tantalum nitride, the conductive film 142Af may be formed using a conductive material such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. Alternatively, a conductive material such as ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even after absorbing oxygen.

[0233] In addition to tungsten, the conductive film 142Bf may be made of a conductive material such as a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining the above metal elements. For example, a conductive material such as titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0234] The conductive films 142Af and 142Bf may be made of materials that are mutually applicable to each other. The conductive films 142Af and 142Bf may be made of the same material. That is, in the memory cell MCa, the conductor 142a1 and the conductor 142a2 may be one conductor. Similarly, the conductor 142b1 and the conductor 142b2 may be one conductor. Similarly, the conductor 142c1 and the conductor 142c2 may be one conductor. Similarly, the conductor 142d1 and the conductor 142d2 may be one conductor.

[0235] Next, the insulating layer 124A, the oxide layer 130A, the oxide layer 130B, the conductive film 142Af, and the conductive film 142Bf are processed by lithography to form an island-shaped stack of the insulator 124, the oxide 130a, and the oxide 130b, and the conductive layer 142A and the conductive layer 142B located on the stack and on the insulator 122a (see Figures 13A to 13D). For example, the insulating layer 124A, the oxide layer 130A, the oxide layer 130B, the conductive film 142Af, and the conductive film 142Bf are processed to form island-shaped insulators 124, oxides 130a, and oxides 130b, and conductive layers 142A and 142B extending in a direction parallel to the dotted-dash line A1-A2 (the channel length direction of transistor M1, or the X direction shown in FIG. 13A), and then the conductive layers 142A and 142B are processed to form the island-shaped conductive layers 142A and 142B.

[0236] Here, the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B are formed so as to at least partially overlap with the conductor 160_0. The openings in the conductive layer 142A and the conductive layer 142B are formed at positions that do not overlap with the oxide 130b. The above processing can be performed by dry etching or wet etching. Dry etching is suitable for microfabrication. The insulating layer 124A, the oxide layer 130A, the oxide layer 130B, the conductive film 142Af, and the conductive film 142Bf may be processed under different conditions.

[0237] 13B to 13D , the side surfaces of the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B may be tapered. The insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B may have a taper angle of, for example, 60° or more and less than 90°. Tapering the side surfaces in this manner improves coverage by the insulator 175 and the like formed in a subsequent process, and reduces defects such as voids.

[0238] In this specification and the like, a tapered shape refers to a shape in which at least a portion of a side surface of a structure is inclined with respect to the substrate surface. The angle between the inclined side surface and the substrate surface is referred to as a taper angle. In particular, in this specification and the like, a tapered shape having a taper angle greater than 0° and equal to or less than 90° is referred to as a forward taper shape, and a tapered shape having a taper angle greater than 90° and less than 180° is referred to as a reverse taper shape.

[0239] However, the present invention is not limited to the above, and the side surfaces of the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B may be substantially perpendicular to the top surface of the insulator 122a. With such a structure, it is possible to reduce the area and increase the density when providing a plurality of transistors M1, M2, and M3.

[0240] Furthermore, by-products generated in the etching process may be formed in layers on the side surfaces of the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B. In this case, the layer-like by-products are formed between the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B and the insulator 175. Therefore, it is preferable to remove the layer-like by-products formed in contact with the top surface of the insulator 122a.

[0241] Note that the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B are not limited to the shapes shown in FIGS. 13A to 13D and may be processed into other shapes.

[0242] Next, an insulator 175 is formed to cover the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B (see FIGS. 14A to 14D ). The insulator 175 is preferably in contact with the top surface of the insulator 122a and the side surface of the insulator 124. The insulator 175 can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 175 is preferably an insulating film that has a function of suppressing oxygen permeation. For example, a silicon nitride film may be formed as the insulator 175 by an ALD method. Alternatively, an aluminum oxide film may be formed as the insulator 175 by a sputtering method and then a silicon nitride film may be formed thereon by a PEALD method. The insulator 175 having such a stacked structure may improve the function of suppressing the diffusion of impurities such as water or hydrogen and oxygen.

[0243] In this way, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B can be covered with the insulator 175, which has a function of suppressing oxygen diffusion. This makes it possible to reduce the direct diffusion of oxygen from the insulator 180, which will be formed later, into the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B in a later process.

[0244] Next, an insulating film to be the insulator 180 is deposited over the insulator 175 (see FIGS. 14A to 14D ). The insulating film can be deposited by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, a silicon oxide film may be deposited as the insulating film by a sputtering method. The insulator 180 containing excess oxygen can be formed by depositing the insulating film by a sputtering method in an oxygen-containing atmosphere. Note that the excess oxygen here refers to oxygen released from the insulator 180 by heat treatment of the insulator 180, for example. The hydrogen concentration in the insulator 180 can be reduced by using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas. Note that heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited successively without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 175 can be removed, and the moisture and hydrogen concentrations in the oxide 130a, the oxide 130b, and the insulator 124 can be reduced. The heat treatment conditions described above can be used for this heat treatment.

[0245] Note that it is preferable to use a material with a low dielectric constant for the insulating film that becomes the insulator 180. Specifically, examples of materials with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, and silicon nitride. Other examples of materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0246] Next, the insulating film that will become the insulator 180 is subjected to planarization treatment such as CMP to form the insulator 180 with a flat upper surface (see FIGS. 14A to 14D). Note that a silicon nitride film may be formed on the insulator 180 by, for example, sputtering, and then CMP treatment may be performed on the silicon nitride until it reaches the insulator 180.

[0247] Next, in the region that does not overlap with the insulator 124 and the oxide 130 but overlaps with a portion of the conductive layer 142A and a portion of the conductive layer 142B, a portion of the insulator 180 and a portion of the insulator 175 are processed to form an opening 159 that reaches the conductive layer 142B (see Figures 15A to 15D).

[0248] A part of the insulator 180 and a part of the insulator 175 can be processed by dry etching or wet etching. The processing may be performed under different conditions. For example, a part of the insulator 180 may be processed by dry etching, and a part of the insulator 175 may be processed by wet etching.

[0249] The opening 159 is preferably configured to extend in a direction parallel to the dashed dotted line A5-A6 shown in Fig. 15A (the channel width direction of the transistor or the Y direction shown in Fig. 15D ). By forming the opening 159 in this manner, the conductor 160_1, which will be formed later, can be provided extending in the above direction, and the conductor 160_1 can function as a wiring.

[0250] Next, in the region where the conductor 160_0 overlaps with the oxide 130, part of the insulator 180, part of the insulator 175, part of the conductive layer 142A, and part of the conductive layer 142B are processed to form an opening 158_2 that reaches the oxide 130b. Furthermore, in the region including the oxide 130, part of the insulator 180, part of the insulator 175, part of the conductive layer 142A, and part of the conductive layer 142B are processed to form openings 158_3 and 158_4 that reach the oxide 130b and are different from the opening 158_2.

[0251] By forming openings 158_2 to 158_4, conductors 142a1, 142b1, 142c1, and 142d1 can be formed from the conductive layer 142A, and conductors 142a2, 142b2, 142c2, and conductor 142d2 can be formed from the conductive layer 142B (see Figures 16A to 16D).

[0252] Note that the conductive layers 142A and 142B are hardly processed when the opening 159 is formed, whereas the conductive layers 142A and 142B are processed when the openings 158_2 to 158_4 are formed. That is, the conditions for forming the opening 159 are preferably different from the conditions for forming the openings 158_2 to 158_4. Specifically, for example, the opening 159 is preferably formed using an etching method with a high selectivity to the conductor 142 (the conductors 142A and 142B are collectively referred to as conductors 142) (an etching method using the conductor 142 as a stopping film), and the openings 158_2 to 158_4 are preferably formed using an etching method with a high selectivity to the oxide 130b (an etching method using the oxide 130b as a stopping film).

[0253] Furthermore, processing by dry etching is suitable for fine processing. Furthermore, the processing may be performed under different conditions. For example, part of the insulator 180 may be processed by dry etching, part of the insulator 175 may be processed by wet etching, and part of the conductor 142 may be processed by dry etching.

[0254] The openings 158_2 to 158_4 are preferably formed to extend in a direction parallel to the dashed dotted line A3-A4 shown in Fig. 16A (the channel width direction of the transistor, or the Y direction shown in Fig. 16A). By forming the openings 158_2 to 158_4 in this manner, the conductors 160_2 to 160_4, which will be formed later, can be provided to extend in the above direction, and the conductors 160_2 to 160_4 can function as wirings. In particular, the opening 158_2 is preferably formed to overlap with the conductor 160_0.

[0255] The widths of the openings 158_2 to 158_4 are preferably minute because they are reflected in the channel lengths of the transistors M1 to M3. For example, the widths of the openings 158_2 to 158_4 are preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more. Depending on the situation, the widths of the openings 158_2 to 158_4 may be 1 μm or less, 0.6 μm or less, 0.5 μm or less, 0.4 μm or less, 0.3 μm or less, 0.2 μm or less, or 0.1 μm or less, and 10 nm or more or 50 nm or more. In this way, to finely process the openings 158_2 to 158_4, it is preferable to use lithography using short-wavelength light such as EUV light or an electron beam.

[0256] When the openings 158_2 to 158_4 are finely processed, a part of the insulator 180, a part of the insulator 175, a part of the conductive layer 142B, and a part of the conductive layer 142A are preferably processed by anisotropic etching. In particular, dry etching is preferable because it is suitable for fine processing. The processing may be performed under different conditions.

[0257] By processing the insulator 180, the insulator 175, the conductive layer 142B, and the conductive layer 142A using anisotropic etching, for example, the opposing side surfaces of the conductor 142a and the conductor 142d in the transistor M1 can be formed to be approximately perpendicular to the top surface of the oxide 130b. With this structure, so-called Loff regions can be formed in the regions of the oxide 130 near the ends of the conductor 142a and the conductor 142d. Therefore, the frequency characteristics of the transistor M1 can be improved, and the operating speed of the semiconductor device according to one embodiment of the present invention can be increased. Note that although the above description relates to the transistor M1, the same description also applies to the transistors M2 and M3.

[0258] However, the above is not the only option, and the side surfaces of the insulator 180, the insulator 175, and the conductor 142 (for example, the conductor 142a and the conductor 142d) may be tapered. The taper angle of the insulator 180 may be larger than the taper angle of the conductor 142. When the openings 158_2 to 158_4 are formed, the upper portion of the oxide 130b may be removed.

[0259] The etching process may cause impurities to adhere to or diffuse into the side surfaces of the oxide 130a, the top surface and side surfaces of the oxide 130b, the side surfaces of the conductors 142a to 142d, and the side surface of the insulator 180. A process for removing such impurities may be performed. Furthermore, the dry etching may cause damaged regions to form on the surface of the oxide 130b. Such damaged regions may be removed. Examples of such impurities include those derived from components contained in the insulator 180, the insulator 175, the conductive layer 142B, and the conductive layer 142A, components contained in materials used in the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0260] In particular, impurities such as aluminum and silicon may reduce the crystallinity of the oxide 130b. Therefore, it is preferable to remove impurities such as aluminum and silicon from the surface of the oxide 130b and its vicinity. It is also preferable to reduce the concentration of the impurities. For example, the concentration of aluminum atoms on the surface of the oxide 130b and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0261] In addition, in the region where the crystallinity of the oxide 130b is low due to impurities such as aluminum or silicon, the density of the crystal structure is reduced. Ｏ H (V Ｏ is an oxygen vacancy, and V Ｏ H is V ＯA large amount of defects (which refer to defects in which hydrogen enters the oxide 130b) is formed, and the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Ｏ H is reduced, or V Ｏ Preferably, H is removed.

[0262] In contrast, it is preferable that the oxide 130b has a layered CAAC structure. In particular, it is preferable that the oxide 130b has the CAAC structure up to the bottom edge of the drain. Here, in the transistor M1, the conductor 142a or the conductor 142d and its vicinity function as the drain. In other words, it is preferable that the oxide 130b near the bottom edge of the conductor 142a (conductor 142d) has the CAAC structure. In this way, even at the drain edge, which significantly affects the drain breakdown voltage, the low-crystalline region of the oxide 130b is removed, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor M1 can be further suppressed. Furthermore, the reliability of the transistor M1 can be improved.

[0263] In order to remove impurities and the like that have adhered to the surface of the oxide 130b during the etching process, a cleaning process is performed. Cleaning methods include wet cleaning using a cleaning solution (also called wet etching), plasma processing using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0264] For wet cleaning, an aqueous solution prepared by diluting one or more selected from ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with carbonated water or pure water can be used. Alternatively, wet cleaning may be performed using pure water or carbonated water. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0265] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0266] In addition, ultrasonic cleaning preferably uses a frequency of 200 kHz or more, and more preferably uses a frequency of 900 kHz or more, since use of such a frequency can reduce damage to the oxide 130b and the like.

[0267] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0268] In this embodiment, wet cleaning is performed using diluted ammonia water as the cleaning treatment. By performing the cleaning treatment, impurities attached to the surfaces of the oxide 130a, the oxide 130b, and the like or diffused into the oxide 130a, the oxide 130b, and the like can be removed. Furthermore, the crystallinity of the oxide 130b can be improved.

[0269] Heat treatment may be performed after the etching or the cleaning. The heat treatment may be performed at a temperature of 100° C. to 450° C., preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 130a and the oxide 130b, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the oxide 130b. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, the heat treatment may be successively performed in a nitrogen atmosphere without exposure to the air.

[0270] The openings 158_2 to 158_4 and the opening 159 may be formed after the openings 158_2 to 158_4 are formed. Alternatively, one or more selected from the openings 158_2 to 158_4 and the opening 159 may be formed first, and the remaining may be formed later. Note that the openings 158_2 to 158_4 are preferably formed so that the oxide 130b is exposed at the bottom thereof, and the opening 159 is preferably formed so that the conductor 142a is exposed at the bottom thereof. For this reason, the openings 158_2 to 158_4 and the opening 159 are preferably formed using processing methods with different conditions.

[0271] Next, the insulating film 153A is formed (see FIGS. 17A to 17D ). The insulating film 153A is an insulating film that will become the insulators 153_1 to 153_4 in a later process. The insulating film 153A can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating film 153A is preferably formed by the ALD method. In particular, the insulating film 153A is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, thereby enabling precise film thickness adjustment. Furthermore, as shown in FIGS. 17B and 17C , the insulating film 153A needs to be formed with good coverage on the bottom surfaces and side surfaces of the openings 158_2 to 158_4 and the opening 159. In the openings 158_2 to 158_4, the oxide 130 is preferably deposited with good coverage on the top surface and side surfaces thereof. In the opening 159, the oxide 130 is preferably deposited with good coverage on the top surface and side surfaces thereof. In the opening 159, the oxide 130 is preferably deposited with good coverage on the top surface and side surfaces thereof. By using the ALD method, atomic layers can be deposited one by one on the bottom surface and side surfaces thereof. In this way, the insulating film 153A can be deposited with good coverage on each opening.

[0272] When the insulating film 153A is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using the above-mentioned oxidizing agent as an oxidizing agent, it is possible to reduce hydrogen diffusing into the oxide 130b.

[0273] In this embodiment, the insulating film 153A is formed by depositing hafnium oxide using a thermal ALD method.

[0274] Alternatively, the insulating material used for the insulating film 153A may be a high-k material with a high relative dielectric constant. Examples of high-k materials with a high relative dielectric constant include metal oxides containing one or more elements selected from aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium, in addition to the above-mentioned hafnium oxide. Alternatively, the insulating film 153A may be made of aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which are insulators containing oxides of one or both of aluminum and hafnium.

[0275] The insulating film 153A can be formed using an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride oxide. Alternatively, the insulating film 153A can be formed using an insulating material. Examples of such insulating materials include silicon oxide to which fluorine is added and silicon oxide to which carbon is added. Alternatively, the insulating film 153A can be formed using silicon oxide to which carbon and nitrogen are added. Alternatively, the insulating film 153A can be formed using silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferable because they are stable against heat. Alternatively, the insulating film 153A can have a stacked structure including two or more materials selected from the above materials.

[0276] Next, microwave treatment is preferably performed in an atmosphere containing oxygen (see FIGS. 17A to 17D ). Here, microwave treatment refers to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. In this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Note that when the insulating film 153A has a stacked structure, microwave treatment may be performed after part of the insulating film 153A is formed. For example, when the insulating film 153A includes a silicon oxide film or a silicon oxynitride film, the microwave treatment may be performed after the silicon oxide film or the silicon oxynitride film is formed.

[0277] The dotted arrows in Figures 17B to 17D indicate high-frequency waves such as microwaves or RF, oxygen plasma, oxygen radicals, etc. For the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device may be 300 MHz to 300 GHz, preferably 2.4 GHz to 2.5 GHz, e.g., 2.45 GHz. High-density plasma can generate high-density oxygen radicals. The power of the power supply that applies microwaves to the microwave treatment device may be 1000 W to 10,000 W, preferably 2000 W to 5,000 W. The microwave treatment device may also have a power supply that applies RF to the substrate side. Furthermore, applying RF to the substrate side can efficiently guide oxygen ions generated by high-density plasma into the oxide 130b. Due to the action of plasma, microwaves, etc., the V included in the regions of the oxide 130 that do not overlap with the conductors 142a to 142d can be reduced. Ｏ H can be split off and hydrogen can be removed from the region. Ｏ This reduces the oxygen vacancies and V in the region. Ｏ By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the region, the oxygen vacancies in the region can be further reduced, and the carrier concentration can be lowered.

[0278] 17B to 17D, the conductors 142a to 142d shield the oxide 130b from microwaves, RF, oxygen plasma, and other high-frequency waves, so that these effects do not reach the oxide 130b regions that overlap the conductors 142a to 142d. Ｏ Since the amount of H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0279] An insulating film 153A is provided in contact with the side surfaces of the conductors 142a to 142d. Note that the insulating film 153A preferably has, for example, a barrier property against oxygen, which can prevent an oxide film from being formed on the side surfaces of the conductors 142a to 142d by microwave treatment.

[0280] Furthermore, the film quality of the insulator 153A can be improved, which improves the reliability of the transistors M1 to M3.

[0281] In this manner, oxygen vacancies and V Ｏ By removing H, the regions can be made i-type or substantially i-type. Furthermore, excessive oxygen can be prevented from being supplied to the regions of the oxide 130 that overlap with the conductors 142a to 142d, which function as source or drain regions, and thus conductivity can be maintained. This can suppress fluctuations in the electrical characteristics of the transistors M1 to M3, and can suppress variations in the electrical characteristics of the transistors M1 to M3 within the substrate surface.

[0282] In microwave processing, thermal energy may be transferred directly to the oxide 130b due to electromagnetic interaction between the microwaves and molecules in the oxide 130b. This thermal energy may heat the oxide 130b. Such a heat treatment may be called microwave annealing. Performing microwave processing in an oxygen-containing atmosphere may produce an effect equivalent to that of oxygen annealing. Furthermore, if the oxide 130b contains hydrogen, this thermal energy may be transferred to the hydrogen in the oxide 130b, which may activate the hydrogen and release it from the oxide 130b.

[0283] Note that the microwave treatment may be performed before the formation of the insulating film 153A, rather than after the formation of the insulating film 153A.

[0284] After the microwave treatment after the formation of the insulating film 153A, heat treatment may be performed while the reduced pressure state is maintained. By performing such treatment, hydrogen can be efficiently removed from the insulating film 153A, the oxide 130b, and the oxide 130a. Part of the hydrogen may be gettered to the conductor 142 (the conductors 142a to 142d). Alternatively, the step of performing heat treatment while the reduced pressure state is maintained after the microwave treatment may be repeated multiple times. Repeating the heat treatment can more efficiently remove hydrogen from the insulating film 153A, the oxide 130b, and the oxide 130a. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 130b and the like are sufficiently heated by microwave annealing, the heat treatment is not necessary.

[0285] Furthermore, by modifying the film quality of the insulating film 153A by microwave treatment, diffusion of impurities such as hydrogen or water can be suppressed. Therefore, in a post-process such as deposition of conductive films to be the conductors 160_1 to 160_4 or post-treatment such as heat treatment, diffusion of impurities such as hydrogen or water into the oxide 130b, the oxide 130a, and the like through the insulator 153 can be suppressed.

[0286] Next, the insulating film 154A to be the insulators 154_1 to 154_4 is formed (see FIGS. 18A to 18D). The insulating film 154A can be formed by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating film 154A is preferably formed by an ALD method, similar to the insulating film 153A. By using the ALD method, the insulating film 154A can be formed to a thin thickness with good coverage. In this embodiment, silicon nitride is formed as the insulating film 154A by a PEALD method.

[0287] The insulating film 154A may be made of an insulating material that can be used for the insulating film 153A.

[0288] The insulating film 154A may be formed using the same material as the insulating film 153A. That is, in the memory cell MCa, the insulators 153_1 to 153_4 and the insulators 154_1 to 154_4 may each be formed using a single insulator.

[0289] Next, a conductive film 160A to be the conductors 160a_1 to 160a_4 and a conductive film 160B to be the conductors 160b_1 to 160b_4 are sequentially formed (see FIGS. 18A to 18D ). The conductive films 160A and 160B can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, titanium nitride is formed as the conductive film 160A by a CVD method or an ALD method, and tungsten is formed as the conductive film 160B by a CVD method.

[0290] Note that the conductive film 160A may be made of a conductive material other than titanium nitride, such as tantalum, tantalum nitride, titanium, ruthenium, or ruthenium oxide. Alternatively, the conductive film 160A may have a stacked structure including two or more of the above-mentioned materials. The conductive film 160B may be made of a conductive material other than tungsten, such as copper or aluminum. Alternatively, the conductive film 160B may have a stacked structure including two or more of the above-mentioned materials.

[0291] Next, the insulating film 153A, the insulating film 154A, the conductive film 160A, and the conductive film 160B are polished by planarization treatment such as CMP until the insulator 180 is exposed. That is, portions of the insulating film 153A, the insulating film 154A, the conductive film 160A, and the conductive film 160B exposed from the openings 158_2 to 158_4 and the opening 159 are removed. As a result, an insulator 153_2, an insulator 154_2, and a conductor 160_2 (conductor 160a_2 and conductor 160b_2) are formed in the opening 158_2, an insulator 153_3, an insulator 154_3, and a conductor 160_3 (conductor 160a_3 and conductor 160b_3) are formed in the opening 158_3, and an insulator 153_4, an insulator 154_4, and a conductor 160_4 (conductor 160a_4 and conductor 160b_4) are formed in the opening 158_4. Furthermore, an insulator 153_1, an insulator 154_1, and a conductor 160_1 (conductor 160a_1 and conductor 160b_1) are formed in the opening 159 (see FIGS. 19A to 19D).

[0292] As a result, the insulator 153_2 is provided in contact with the inner wall and side surface of the opening 158_2 overlapping with the oxide 130b, and the conductor 160_2 is arranged to fill the opening 158_2 with the insulators 153_2 and 154_2 interposed therebetween. In this manner, the transistor M1 is formed. Similarly, the insulator 153_3 is provided in contact with the inner wall and side surface of the opening 158_3 overlapping with the oxide 130b, and the conductor 160_3 is arranged to fill the opening 158_3 with the insulators 153_3 and 154_3 interposed therebetween. In this manner, the transistor M2 is formed. Similarly, the insulator 153_4 is provided in contact with the inner wall and side surface of the opening 158_4 overlapping with the oxide 130b, and the conductor 160_4 is arranged to fill the opening 158_4 with the insulators 153_4 and 154_4 interposed therebetween. In this way, the transistor M3 is formed.

[0293] The insulator 153_1 is provided in contact with the inner wall and side surface of the opening 159 overlapping with the conductor 142a, and the conductor 160_1 is arranged to fill the opening 159 with the insulators 153_1 and 154_1 interposed therebetween. In this manner, the capacitor C1 is formed.

[0294] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 180. Note that after the heat treatment, the conductors 170_1 to 170_5, which will be described later, may be formed successively without exposure to the air.

[0295] Next, in a region that overlaps with the conductor 142a but does not overlap with the insulator 124 or the oxide 130, part of the insulator 180 and part of the insulator 175 are processed to form an opening 157_3 that reaches the conductor 142a. Similarly, in a region that overlaps with the conductor 142d, part of the insulator 180 and part of the insulator 175 are processed to form an opening 157_5 that reaches the conductor 142d (see FIGS. 20A to 20D ).

[0296] Furthermore, a portion of the insulator 180 and a portion of the insulator 175 can be processed by dry etching or wet etching. Processing by dry etching is suitable for fine processing. The processing may be performed under different conditions. For example, a portion of the insulator 180 may be processed by dry etching, and a portion of the insulator 175 may be processed by wet etching.

[0297] Alternatively, as a method for forming one or both of the openings 157_3 and 157_5, a processing method capable of forming the openings 158_2 to 158_4 or the opening 159 may be used.

[0298] Next, a conductive film 170A to be the conductors 170a_1 to 170a_5 and a conductive film 170B to be the conductors 170b_1 to 170b_5 are sequentially formed over the insulators 153_1 to 153_4, the insulators 154_1 to 154_4, and the conductors 160_1 to 160_4 (see FIGS. 21A to 21D). The conductive film 170A and the conductive film 170B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In particular, the conductive film 170A is preferably formed on the bottom and side surfaces of the openings 157_3 and 157_5 with good film coverage. For this reason, the conductive film 170A is preferably formed by a CVD method or an ALD method, for example. Moreover, the conductive film 170B is preferably formed by using a CVD method, for example.

[0299] Note that the conductive film 170A can be formed using a material that can be used for the conductive film 160A. The conductive film 170B can be formed using a material that can be used for the conductive film 160B. Note that because the conductive films 170A and 170B are processed in a later step, the materials used for the conductive films 170A and 170B are preferably different from those of the conductive films 160A and 160B. Specifically, for example, when etching is used as processing, the materials used for the conductive films 170A and 170B are preferably materials that have a higher etching rate than the conductor 160_2.

[0300] Next, the conductive films 170A and 170B are processed by lithography to form island-shaped conductors 1701 (conductors 170a1 and 170b1), 1702 (conductors 170a2 and 170b2), 1703 (conductors 170a3 and 170b3), 1704 (conductors 170a4 and 170b4), and 1705 (conductors 170a5 and 170b5) (see FIGS. 22A to 22D). In particular, this processing makes the conductor 1703 a wiring that connects the conductor 142a of the transistor M1 and the conductor 1603 of the transistor M3.

[0301] Next, the insulator 122b is formed over the insulator 180, the insulators 153_1 to 153_4, the insulators 154_1 to 154_4, the conductors 160_1 to 160_4, and the conductors 170_1 to 170_5 (see FIGS. 8A to 8D ). The insulator 122b can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 122b is preferably formed by depositing hafnium oxide with a reduced hydrogen concentration by an ALD method, for example, as in the case of the insulator 122a.

[0302] For other materials and other formation methods of the insulator 122b, refer to the description of the insulator 122a.

[0303] Furthermore, the transistors M1, M2, and M3 included in the memory layer ALYb and the capacitor C1 may be formed over the insulator 122b in a later step. For this reason, the insulator 122b is preferably subjected to planarization treatment such as CMP.

[0304] 2 or 3 can be manufactured. As shown in FIGS. 9A to 22D, by using the manufacturing method of the semiconductor device described in this embodiment, the capacitor C1 and the transistors M1 to M3 can be manufactured in the same process. This reduces the number of manufacturing steps for the semiconductor device including the capacitor C1 and the transistors M1 to M3.

[0305] 2 or 3, the area occupied by the memory cell can be reduced, which means that the recording density of the semiconductor device can be increased.

[0306] Note that the method for manufacturing a semiconductor device according to one embodiment of the present invention is not limited to the methods illustrated in Figures 8A to 22D. Materials and steps in the method for manufacturing a semiconductor device may be changed depending on the situation.

[0307] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0308] Embodiment Mode 2 In this embodiment mode, a semiconductor device having a different structure from the semiconductor device described in the above embodiment mode will be described.

[0309] <Circuit Configuration Example of Semiconductor Device> FIG. 23 is a circuit diagram showing a configuration example of a semiconductor device DEVA according to one embodiment of the present invention. The semiconductor device DEVA includes, as an example, a plurality of memory layers. Note that FIG. 23 illustrates memory layers ALYa, ALYb, and ALYc as an example of the plurality of memory layers. Furthermore, the memory layer ALYb is located above the memory layer ALYa, and the memory layer ALYc is located above the memory layer ALYb. Furthermore, a memory layer different from the memory layers ALYb and ALYc may be located below the memory layer ALYa, and a memory layer different from the memory layers ALYa and ALYb may be located above the memory layer ALYc.

[0310] The semiconductor device DEVA has a plurality of memory cells. In particular, the memory layers ALYa and ALYb share a plurality of memory cells MCA, and the memory layers ALYb and ALYc share a plurality of memory cells MCB. The memory layer ALYa and the memory layer located below the memory layer ALYa share a plurality of memory cells MCZ, and the memory layer ALYc and the memory layer located above the memory layer ALYc share a plurality of memory cells MCC. Note that, as an example, FIG. 23 illustrates memory cells MCA[i,j] and MCA[i,j+2] as memory cells MCA, memory cell MCB[i,j+1] as memory cell MCB, memory cell MCZ[i,j+1] as memory cell MCZ, and memory cell MCC[i,j] and MCC[i,j+2] as memory cells MCC. Note that i and j will be described later.

[0311] As an example, the plurality of memory cells MCA are arranged in an array in the memory layers ALYa and ALYb. For example, in FIG. 23 , N memory cells MCA are arranged in the row direction (N is an integer of 1 or more) and M memory cells MCA are arranged in the column direction (M is an integer of 1 or more), that is, in an M×N matrix. Similarly, as an example, the plurality of memory cells MCB are arranged in an M×N matrix in the memory layers ALYb and ALYc, as an example, the plurality of memory cells MCC are arranged in an M×N matrix in the memory layer ALYc and a memory layer located above the memory layer ALYc, and as an example, the plurality of memory cells MCZ are arranged in an M×N matrix in the memory layer ALYa and a memory layer located below the memory layer ALYa.

[0312] Here, the memory cell MCA is the memory cell arranged in the i-th row and 2k-1-th column (k is an integer greater than or equal to 1 and less than or equal to N) in the memory layers ALYa and ALYb. The memory cell MCB is the memory cell arranged in the i-th row and 2k-1-th column in the memory layers ALYb and ALYc. The memory cell MCC is the memory cell arranged in the i-th row and 2k-1-th column in the memory layer ALYc and the memory layer above the memory layer ALYc. The memory cell MCZ is the memory cell arranged in the i-th row and 2k-1-th column in the memory layer ALYa and the memory layer below the memory layer ALYa.

[0313] In Fig. 23, i is an integer between 1 and M. Furthermore, j is a number that satisfies 2k-1=j or 2k-1=j+2. In this case, j shown in Fig. 23 is an odd number between 1 and 2N-3. In this case, 2k=j+1 is satisfied, and j+1 shown in Fig. 23 is an even number between 2 and 2N-2.

[0314] A transistor M2 and a transistor M3 are arranged in the i-th row and 2k-1-th column of the memory layer ALYa. That is, in Fig. 23, a transistor M2 and a transistor M3 are arranged in the i-th row and j-th column and the i-th row and j+2-th column of the memory layer ALYa, respectively. Furthermore, a transistor M1 and a capacitance element C1 are arranged in the i-th row and 2k-1-th column of the memory layer ALYb. That is, in Fig. 23, a transistor M1 and a capacitance element C1 are arranged in the i-th row and j-th column and the i-th row and j+2-th column of the memory layer ALYb, respectively.

[0315] To summarize the above, in the memory layers ALYa and ALYb, the memory cell MCA[i,j] has the transistor M2 and the transistor M3 in the i-th row and the j-th column of the memory layer ALYa, and the transistor M1 and the capacitance element C1 in the i-th row and the j-th column of the memory layer ALYb. Also, the memory cell MCA[i,j+2] has the transistor M2 and the transistor M3 in the i-th row and the j+2-th column of the memory layer ALYa, and the transistor M1 and the capacitance element C1 in the i-th row and the j+2-th column of the memory layer ALYb.

[0316] Furthermore, a transistor M2 and a transistor M3 are arranged in the i-th row and 2k-th column of the memory layer ALYb. That is, in Fig. 23, a transistor M2 and a transistor M3 are arranged in the i-th row and j+1-th column of the memory layer ALYb. Also, a transistor M1 and a capacitance element C1 are arranged in the i-th row and 2k-th column of the memory layer ALYc. That is, in Fig. 23, a transistor M1 and a capacitance element C1 are arranged in the i-th row and j+1-th column of the memory layer ALYc.

[0317] To summarize the above, in the memory layer ALYb and the memory layer ALYc, the memory cell MCB[i, j+1] has a transistor M2 and a transistor M3 in the i-th row and j+1-th column of the memory layer ALYb, and a transistor M1 and a capacitive element C1 in the i-th row and j+1-th column of the memory layer ALYc.

[0318] Similarly, in the memory layer ALYc and the memory layer located above the memory layer ALYc, the memory cell MCC has a transistor M2 and a transistor M3 arranged in the memory layer ALYc, and a transistor M1 and a capacitive element C1 arranged in the memory layer located above the memory layer ALYc. Similarly, in the memory layer ALYa and the memory layer located below the memory layer ALYa, the memory cell MCC has a transistor M1 and a capacitive element C1 arranged in the memory layer ALYa, and a transistor M2 and a transistor M3 arranged in the memory layer located below the memory layer ALYa.

[0319] Note that the transistors M1 to M3 and the capacitor C1 described in Embodiment 1 can be referred to for the transistors M1 to M3 and the capacitor C1 included in the semiconductor device DEVA in FIG.

[0320] 23, in each of the memory cells MCA, MCB, MCC, and MCZ included in the semiconductor device DEVA, the first terminal of the transistor M1 is electrically connected to the gate of the transistor M2 and the first terminal of the capacitance element C1, and the first terminal of the transistor M2 is electrically connected to the first terminal of the transistor M3.

[0321] That is, each of the memory cells MCA, MCB, MCC, and MCZ included in the semiconductor device DEVA of FIG. 23 has the configuration of a gain cell called NOSRAM (registered trademark) described in the first embodiment.

[0322] 23 , a wiring SLa is provided in the (2k−1)th column of the memory layer ALYa. Specifically, a wiring SLa[j] is provided in the jth column of the memory layer ALYa, and a wiring SLa[j+2] is provided in the j+2th column. Furthermore, a wiring SLb is provided in the 2kth column of the memory layer ALYb. Specifically, a wiring SLb[j+1] is provided in the j+1th column of the memory layer ALYb. Furthermore, a wiring SLc is provided in the 2k−1th column of the memory layer ALYc. Specifically, a wiring SLc[j] is provided in the jth column of the memory layer ALYc, and a wiring SLc[j+2] is provided in the j+2th column.

[0323] 23 , a wiring WRBLa extends in the 2k-th column of the memory layer ALYa. Specifically, a wiring WRBLa[j+1] extends in the j+1-th column of the memory layer ALYa. Furthermore, a wiring WRBLb extends in the 2k-1-th column of the memory layer ALYb. Specifically, a wiring WRBLb[j] extends in the j-th column of the memory layer ALYb, and a wiring WRBLb[j+2] extends in the j+2-th column. Furthermore, a wiring WRBLc extends in the 2k-th column of the memory layer ALYc. Specifically, a wiring WRBLc[j+1] extends in the j+1-th column of the memory layer ALYc. In FIG. 23, for convenience, a wiring WRBLa[j+3] is extended to the memory layer ALYa, and a wiring WRBLc[j+3] is extended to the memory layer ALYc.

[0324] 23, the wiring WWLa[i], wiring RWLa[i], and wiring CLa[i] extend in the i-th row of the memory layer ALYa. The wiring WWLb[i], wiring RWLb[i], and wiring CLb[i] extend in the i-th row of the memory layer ALYb. The wiring WWLc[i], wiring RWLc[i], and wiring CLc[i] extend in the i-th row of the memory layer ALYc.

[0325] 23, the wiring WWLa functions as a write word line for the memory cell MCZ, the wiring WWLb functions as a write word line for the memory cell MCA, and the wiring WWLc functions as a write word line for the memory cell MCB. The wiring RWLa functions as a read word line for the memory cell MCA, the wiring WWLb functions as a read word line for the memory cell MCB, and the wiring WWLc functions as a read word line for the memory cell MCC. The wiring WRBLa functions as a write bit line for the memory cell MCZ and also functions as a read bit line for the memory cell MCA. The wiring WRBLb functions as a write bit line for the memory cell MCA and also functions as a read bit line for the memory cell MCB. The wiring WRBLc functions as a write bit line for the memory cell MCB and also functions as a read bit line for the memory cell MCC.

[0326] Furthermore, for a description of the signals (e.g., potential or current) transmitted to each of the wirings WWLa to WWLc, the wirings RWLa to RWLc, and the wirings WRBLa to WRBLc, refer to the description of the signals transmitted to each of the wirings WWLa and WWLb, the wirings RWLa and RWLb, and the wirings WRBLa and WRBLb described in Embodiment 1.

[0327] Also, in Figure 23, wiring SLa functions as wiring that applies a fixed potential to memory cells MCA and MCZ, wiring SLb functions as wiring that applies a fixed potential to memory cells MCA and MCB, and wiring SLc functions as wiring that applies a fixed potential to memory cells MCB and MCC.

[0328] Note that the wirings CLa to CLc may function as wirings that apply a variable potential depending on the situation.

[0329] In the memory cell MCA[i,j], the second terminal of the transistor M1 is electrically connected to the wiring WRBLb[j], the gate of the transistor M1 is electrically connected to the wiring WWLb[i], and the back gate of the transistor M1 is electrically connected to the wiring CLa[i]. The second terminal of the capacitor C1 is electrically connected to the wiring CLb[i]. The second terminal of the transistor M2 is electrically connected to the wiring SLa[j]. The second terminal of the transistor M3 is electrically connected to the wiring WRBLa[j+1], and the gate of the transistor M3 is electrically connected to the wiring RWLa[i].

[0330] Similarly, in the memory cell MCB[i, j+1], the second terminal of the transistor M1 is electrically connected to the wiring WRBLc[j+1], the gate of the transistor M1 is electrically connected to the wiring WWLc[i], and the back gate of the transistor M1 is electrically connected to the wiring CLb[i]. The second terminal of the capacitor C1 is electrically connected to the wiring CLc[i]. The second terminal of the transistor M2 is electrically connected to the wiring SLb[j+1]. The second terminal of the transistor M3 is electrically connected to the wiring WRBLb[j+2], and the gate of the transistor M3 is electrically connected to the wiring RWLb[i].

[0331] Next, a description will be given of writing data to the memory cells MCA to MCC and the memory cell MCZ and reading data from the memory cells MCA to MCC and the memory cell MCZ in the semiconductor device DEVA shown in Fig. 23. Here, as an example, a description will be given of writing data to the memory cells MCA[i, j] of the memory layers ALYa and ALYb of the semiconductor device DEVA and reading data from the memory cells MCA[i, j].

[0332] 23 , data is written to the memory cell MCA[i,j] of the semiconductor device DEVA by, for example, first applying a first potential (e.g., ground potential) to the wiring CLb[i]. Next, a high-level potential is applied to the wiring WWLb[i] to turn on the transistor M1 included in the memory cell MCA[i,j]. A low-level potential is applied to the wirings WWLb[1] to WWLb[m] other than the wiring WWLb[i] to turn off the transistor M1 included in the memory cells MCA in the first to mth rows other than the i-th row. A low-level potential is also applied to the wirings RWLa[1] to RWLa[m] to turn off the transistor M3 included in all the memory cells MCA.

[0333] Then, write data is sent to the wiring WRBLb[j], and a potential corresponding to the data is written to the first terminal of the capacitance element C1 of the memory cell MCA[i,j]. After the data is written to the first terminal of the capacitance element C1 of the memory cell MCA[i,j], a low-level potential is applied to the wiring WWLb[i], turning off the transistor M1 included in the memory cell MCA[i,j]. This completes the writing of data to the memory cell MCA[i,j].

[0334] To read data from the memory cell MCA[i,j] of the semiconductor device DEV shown in FIG. 23 , for example, first, a second potential (e.g., a high-level potential higher than the first potential) is applied to the wiring WRBLa[j+1]. Next, a high-level potential is applied to the wiring RWLa[i] to turn on the transistor M3 included in the memory cell MCA[i,j]. At this time, if the transistor M2 of the memory cell MCA[i,j] operates in the saturation region, a current corresponding to the gate-source voltage of the transistor M2 (the potential difference between the gate potential of the transistor M2 and the potential of the wiring SLa[j]) flows. As a result, the current flows from the wiring WRBLa[j+1] to the wiring SLa[j] via the transistor M2. The current flowing through the wiring WRBLa[j+1] can be input to a read circuit to read out the data written in the memory cell MCA[i,j]. Here, the data written to the memory cell MCA[i,j] is read from the amount of current, but the data written to the memory cell MCA[i,j] may also be read from the voltage change of the wiring WRBLa[j+1].

[0335] In addition, writing data to other memory cells MCA, MCB, MCC, and MCZ, or reading data from other memory cells MCA, MCB, MCC, and MCZ can be performed using the same operations as above.

[0336] Note that the circuit configuration of the semiconductor device of one embodiment of the present invention is not limited to the configuration in Figure 23. The circuit configuration of the semiconductor device may be changed depending on the situation.

[0337] 23 , the number of memory cells MCA, memory cells MCB, memory cells MCC, and memory cells MCZ is M×N, but the number of memory cells MCA and memory cells MCC may be M×N, and the number of memory cells MCB and memory cells MCC may be M×N−1. Specifically, the number of columns of memory cells MCA in the memory layer ALYa and the memory layer ALYb may be N, the number of columns of memory cells MCC in the memory layer ALYc and the memory layer located above the memory layer ALYc may be N, the number of columns of memory cells MCB in the memory layer ALYb and the memory layer ALYc may be N−1, and the number of columns of memory cells MCZ in the memory layer ALYa and the memory layer located below the memory layer ALYa may be N−1.

[0338] <Example of Cross-Sectional Configuration of Semiconductor Device> Next, an example of the configuration of the semiconductor device DEVA will be described.

[0339] 24 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device DEVA according to one embodiment of the present invention. In FIG. 24, the semiconductor device DEVA is configured such that not only memory layers ALYa, ALYb, and ALYc are provided, but also memory layers are provided above the memory layer ALYc and below the memory layer ALYa.

[0340] Moreover, Figure 25 is a cross-sectional schematic diagram focusing on the memory layer ALYa and the memory layer ALYb in the configuration example of the semiconductor device DEVA of Figure 24, and the cross-sectional schematic diagram of Figure 25 shows, as an example, symbols indicating the respective components of the memory layer ALYa, the memory layer ALYb, and the memory layer ALYc.

[0341] 25 shows a configuration example in which the memory layer ALYa is provided over the insulator 122a, the insulator 122b is provided over the memory layer ALYa, the memory layer ALYb is provided over the insulator 122b, the insulator 122c is provided over the memory layer ALYb, and the memory layer ALYc is provided over the insulator 122c. Note that for the insulators 122a to 122c, the insulators 122a and 122b described in Embodiment 1 can be referred to.

[0342] 24 to 31 is parallel to the channel length directions of the transistors M1, M2, and M3, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions. The X, Y, and Z directions shown in FIGS. 24 to 31 are right-handed.

[0343] 26 is a schematic perspective view showing a configuration example of a portion of the memory layer ALYa and the memory layer ALYb of the semiconductor device DEV of FIG. 24. Note that in order to make the structures of the memory layer ALYa and the memory layer ALYb easier to see, the insulator 180 and the insulator 175 are not shown in FIG. 26. Note that for details of the insulator 180 and the insulator 175, the insulator 180 and the insulator 175 described in the first embodiment can be referred to.

[0344] In the memory layer ALYa in FIG. 26, a conductor 160_1, a conductor 160_2, a conductor 160_3, a conductor 160_4, and a conductor 170_5, which will be described later, are extended in the Y direction, for example.

[0345] In the memory layers ALYa and ALYb shown in FIGS. 24 and 25, the memory cells MCA are provided above the insulator 122a.

[0346] As described in the circuit configuration example, the memory cell MCA includes a transistor M1, a transistor M2, a transistor M3, and a capacitor C1. In particular, the transistors M2 and M3 are provided above the insulator 122a, and the transistor M1 and the capacitor C1 are provided above the insulator 122b. Note that in Figures 24 and 25, the transistors M1 to M3 are OS transistors, for example. That is, the semiconductor layers of the transistors M1 to M3 contain metal oxide.

[0347] Next, components of the semiconductor device DEVA will be described. For the sake of simplicity, attention will be focused on the memory layer ALYa in Fig. 25. Furthermore, descriptions of portions that overlap with the semiconductor device DEV shown in Figs. 2 and 3 described in the first embodiment may be omitted.

[0348] 24 and 25 , each of the transistors M1 to M3 includes an insulator 124 and an oxide 130. The transistor M1 includes a conductor 142a, a conductor 142d, a conductor 160_2, an insulator 153_2, and an insulator 154_2. The transistor M2 includes a conductor 142b, a conductor 142c, a conductor 160_3, an insulator 153_3, and an insulator 154_3. The transistor M3 includes a conductor 142c, a conductor 142d, a conductor 160_4, an insulator 153_4, and an insulator 154_4. The capacitor C1 includes a conductor 142a, a conductor 160_1, an insulator 153_1, and an insulator 154_1.

[0349] The transistor M1 also includes a conductor 171_1 embedded in the insulator 122a.

[0350] For example, the conductors 160_2 to 160_4 are provided so as to overlap with the region including the oxide 130. The conductor 160_2 functions as the gate of the transistor M1, the conductor 160_3 functions as the gate of the transistor M2, and the conductor 160_4 functions as the gate of the transistor M3. Note that each gate may be referred to as a first gate. Furthermore, in this specification and the like, each of the conductors 160_2 to 160_4 may be referred to as a gate electrode or a first gate electrode. The conductor 160_2 functions as, for example, the wiring WWLa[i] in FIG. 23. The conductor 160_4 functions as, for example, the wiring RWLa[i] in FIG. 23.

[0351] The insulators 153 and 154_2 function as a first gate insulating film in the transistor M1. The insulators 153_3 and 154_3 function as a first gate insulating film in the transistor M2. The insulators 153_4 and 154_4 function as a first gate insulating film in the transistor M3.

[0352] The insulator 124 is provided on the insulator 122a. The insulator 122a and the insulator 124 function as a second gate insulating film of the transistor M1.

[0353] For example, the oxide 130 is provided over the insulator 124. The conductors 160_2 to 160_4 are provided so as to overlap with a region including the oxide 130. The oxide 130 functions as a semiconductor included in the channel formation regions of the transistors M1 to M3.

[0354] The conductor 171_1 embedded in the insulator 122a functions as a back gate (sometimes referred to as a second gate) of the transistor M1. Therefore, in this specification and the like, the conductor 171_1 may be referred to as a back gate electrode or a second gate electrode. The conductor 171_1 also functions as one of a pair of electrodes of a capacitor included in a memory cell in a memory layer located below the memory layer ALYa.

[0355] 25 , in the memory layer located below the memory layer ALYa, conductors 160_2 to 160_4, insulators 153 (insulators 153_2 to 153_4), insulator 154 (insulators 154_2 to 154_4), and an insulator 180 are provided, similar to the memory layer ALYa. Furthermore, in the memory layer located below the memory layer ALYa, the conductors 160_2 to 160_4, the insulator 153, and the insulator 154 are embedded in the insulator 180. In particular, the conductor 160_1, the insulator 153_1, and the insulator 154_1 are located below the conductor 171_1 embedded in the insulator 122a.

[0356] For the conductor 142a, the conductor 142b, the conductor 142c, the conductor 142d, and the insulator 175, the conductor 142a, the conductor 142b, the conductor 142c, the conductor 142d, and the insulator 175 described in Embodiment 1 can be referred to.

[0357] In particular, the conductor 170_5 is provided over the conductor 142d. The conductor 170_5 functions as, for example, the wiring WRBLa[j+1] or the wiring WRBLa[j+3] in FIG.

[0358] The conductor 142b functions as, for example, the wiring SLa[j] or the wiring SLa[j+2] in FIG. 23, or a conductor electrically connected to the wiring SLa.

[0359] A conductor 171_3 embedded in the insulator 122a is located below a region that overlaps with the conductor 142a but does not overlap with the oxide 130. The conductor 171_3 embedded in the insulator 122a functions as a wiring for electrically connecting the insulator 122a included in the memory layer ALYa and the conductor 160_3 included in a memory layer located below the memory layer ALYa.

[0360] In addition, in a region that overlaps with the conductor 142a but does not overlap with the oxide 130, an insulator 153_1, an insulator 154_1, and a conductor 160_1 are provided in this order. In particular, a capacitor C1 is formed in a region where the conductor 142a and the conductor 160_1 overlap. That is, part of the conductor 142a functions as one of a pair of electrodes of the capacitor C1, and part of the conductor 160_1 functions as the other of the pair of electrodes of the capacitor C1.

[0361] The conductor 171_1 is located above the conductor 160_1. In particular, the conductor 171_1 is embedded in the insulator 122b. The conductor 171_1 embedded in the insulator 122b also functions as a backgate electrode of the transistor M1 included in the memory layer ALYb.

[0362] In Figure 25, the conductor 171_1 embedded in the insulator 122b is also located above the insulator 153_1 and the insulator 154_1, but the conductor 171_1 embedded in the insulator 122b may be located above the conductor 160_1 and may not be located above the insulator 153_1 and the insulator 154_1.

[0363] Furthermore, the conductor 171_3 is located above the conductor 160_3. In particular, the conductor 171_3 is embedded in the insulator 122b. The conductor 171_3 embedded in the insulator 122b functions as a wiring for electrically connecting the conductor 160_3 included in the memory layer ALYa and the conductor 142a included in the memory layer ALYb.

[0364] Note that in FIG. 25, the conductor 171_1 embedded in the insulator 122b may also be located above the insulators 153_1 and 154_1.

[0365] The conductor 171_1 and the conductor 171_3 can be formed using the same conductive material. Note that specific conductive materials that can be used for the conductor 171_1 and the conductor 171_3 will be described later.

[0366] The conductor 171_1 and the conductor 171_3 may be formed in separate steps, or may be formed collectively in the same step.

[0367] 24 and 25, by configuring the semiconductor device DEVA, it is possible to simultaneously form a conductor corresponding to the back gate electrode of the transistor M1 in the memory layer ALYb and a conductor corresponding to the other of the pair of electrodes of the capacitive element C1 in the memory layer ALYa. In other words, the configuration shown in FIG. 24 and 25 has the effects of reducing the number of photomasks for fabricating the semiconductor device DEVA compared to conventional methods and shortening the fabrication process of the semiconductor device DEVA.

[0368] The configuration of the semiconductor device DEVA in FIG. 24 may be changed depending on the situation.

[0369] For example, the semiconductor device DEVA of FIG. 24 (FIG. 25) may be modified to have the configuration of the semiconductor device DEVA shown in FIG. 27. The semiconductor device DEVA of FIG. 27 differs from the semiconductor device DEVA of FIG. 24 (FIG. 25) in that, for example, the conductor 160_3 included in the memory layer ALYb and the conductor 171_3 embedded in the insulator 122c do not overlap with the conductor 160_1 of the memory layer ALYc. In other words, the semiconductor device DEVA of FIG. 27 has a configuration in which the transistor M2 of the lower memory layer and the capacitive element C1 of the upper memory layer do not overlap with each other. By applying the configuration of the semiconductor device DEVA of FIG. 27, the degree of freedom in circuit design, such as routing of wiring, may be increased compared to the semiconductor device DEVA of FIG. 24 (FIG. 25).

[0370] 24 (FIG. 25) may be modified to have the same configuration as the semiconductor device DEVA shown in FIG. 28. The semiconductor device DEVA shown in FIG. 28 differs from the semiconductor device DEVA shown in FIG. 24 (FIG. 25) in that, for example, the conductor 160_4 included in the memory layer ALYb and the conductor 171_3 embedded in the insulator 122c overlap with the conductor 160_1 of the memory layer ALYc. That is, the semiconductor device DEVA shown in FIG. 28 has a configuration in which the positions of the transistors M2 and M3 formed in the oxide 130 are swapped in the semiconductor device DEVA shown in FIG. 24 (FIG. 25). The semiconductor device DEVA shown in FIG. 28 also has a configuration in which the transistors M2 and M3 are swapped in the circuit diagram of FIG. 23. The configuration of the semiconductor device DEVA shown in FIG. 28 also allows data to be written and read, similar to the semiconductor device DEVA shown in FIG. 24 (FIG. 25).

[0371] 24 and 25, for example, by providing the other of the pair of electrodes of the capacitive element C1 of the memory layer ALYa and the back gate electrode of the transistor M1 of the memory layer ALYb so as to be shared by each other, it is possible to reduce the area occupied by the memory cell MCA (the memory cell MCB, the memory cell MCC, and the memory cell MCZ). This makes it possible to miniaturize or highly integrate the semiconductor device, and as a result, it is possible to increase the memory density.

[0372] 24 and 25, the area occupied by the transistors can be reduced by forming three transistors in one oxide 130. That is, the area occupied by the memory cell can be reduced, and therefore the semiconductor device can be miniaturized or highly integrated, and as a result, the memory density can be increased.

[0373] <<Example of Manufacturing Method of Semiconductor Device>> Next, an example of a manufacturing method of the memory layer ALYa of the semiconductor device DEVA shown in Fig. 24 and Fig. 25 will be described. Note that in the description of the example of the manufacturing method, Fig. 29A to Fig. 31 will be used.

[0374] 29A to 31 are schematic cross-sectional views, respectively. In particular, Fig. 29A to Fig. 31 are schematic cross-sectional views of the transistors M1 to M3 in the channel length direction.

[0375] In the manufacturing method of the semiconductor device DEVA shown in Figures 24 and 25, the description of the parts that overlap with the manufacturing method of the semiconductor device DEV shown in Figures 2 and 3 described in embodiment 1 may be omitted.

[0376] First, a substrate (not shown) is prepared, and a memory layer below the memory layer ALYa is formed on the substrate. For example, insulators and conductors included in the memory layer below the memory layer ALYa are formed on the substrate. Note that the insulators and conductors can be made of the same materials as the insulator 180, the insulators 153_1 to 153_4, the insulators 154_1 to 154_4, the conductors 160_1 to 160_4, the conductor 170_5, the insulator 122a, the conductor 171_1, and the conductor 171_3 included in the memory layer ALYa. Furthermore, by forming the insulators and the conductors, the transistors M1 to M3 and the capacitor C1 are formed in the memory layer below the memory layer ALYa.

[0377] Next, an insulating film that becomes the insulator 122a is formed so as to cover the insulator and the conductor. Then, an opening is formed in the insulating film, reaching the gate electrode of the transistor M2 in a region overlapping the gate electrode, and an opening is formed in the insulating film, reaching the upper electrode of the pair of electrodes of the capacitor C1 in a region overlapping the upper electrode, thereby forming the insulator 122a (see FIG. 29A ). Regarding the insulator 122a, the description of the insulator 122a in the first embodiment can be referred to.

[0378] A conductor 171_3 is buried in an opening of the insulator 122a that overlaps with the gate electrode of the transistor M2. A conductor 171_1 is buried in an opening of the insulator 122a that overlaps with the upper electrode of the pair of electrodes of the capacitor C1 (see FIG. 29A). The conductors 171_1 and 171_3 will be described later.

[0379] Next, the transistors M1 to M3 and the capacitor C1 are formed over the insulator 122a, the conductor 171_1, and the conductor 171_3 by referring to the manufacturing methods shown in FIGS. 10A to 19D (see FIG. 29B).

[0380] 20A to 20D, an opening reaching the conductor 142d is provided in a region of the insulator 180 overlapping with the conductor 142d (corresponding to the opening 157_5 in FIG. 20B).

[0381] 21A to 22D, the conductor 170_5 is formed in the opening (see FIG. 29B). Note that as shown in FIG. 29B, the conductor 170_5 may also be formed on a part of the insulator 180.

[0382] After that, the insulating film 122B to be the insulator 122b is formed to cover the insulators 153_1 to 153_4, the insulators 154_1 to 154_4, the conductors 160_1 to 160_4, the insulator 180, and the conductor 170_5 (see FIG. 29B). Note that the description of the insulator 122b in Embodiment 1 can be referred to for a method for forming the insulating film 122B.

[0383] Next, the insulating film 122B is processed to form an insulator 122b having openings in a region overlapping with the conductor 160_1 included in the memory layer ALYa and a region overlapping with the conductor 160_3 included in the memory layer ALYa (see FIG. 30A). Note that the above processing can be performed by dry etching or wet etching.

[0384] Furthermore, conductive films 171A and 171B are sequentially formed on the insulator 122b and in the openings of the insulator 122b (see FIG. 30B ). Note that the conductive films 171A and 171B are preferably formed in succession without being exposed to the air. By forming the conductive films 171A and 171B without being exposed to the air, impurities or moisture from the air can be prevented from adhering to the conductive films 171A and 171B, and the vicinity of the interface between the conductive films 171A and 171B can be kept clean.

[0385] The conductive films 171A and 171B can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, the conductive films 171A and 171B are formed by a CVD method.

[0386] The conductive film 171A can be formed using, for example, a material that can be used for the conductors 160a_1 to 160a_4. The conductive film 171B can be formed using, for example, a material that can be used for the conductors 160b_1 to 160b_4.

[0387] The conductive films 171A and 171B may be formed using materials that are mutually applicable to each other. Alternatively, the conductive films 171A and 171B may be formed using the same material. In other words, the conductive films 171A and 171B may be formed using a single conductor.

[0388] Next, the conductive films 171A and 171B are polished by planarization treatment such as CMP until the insulator 122b is exposed. That is, the portions of the conductive films 171A and 171B exposed from the openings of the insulator 122b are removed. As a result, a conductor 171_3 is formed in the opening of the insulator 122b that overlaps with the conductor 160_3 included in the memory layer ALYa, and a conductor 171_1 is formed in the opening of the insulator 122b that overlaps with the conductor 160_1 included in the memory layer ALYa (see FIG. 31 ).

[0389] After the conductors 171_1 and 171_3 are formed, the heat treatment described in Embodiment 1 may be performed.

[0390] 29A to 31, the memory layer ALYa of the semiconductor device DEVA can be formed. When the memory layer ALYb is formed over the insulator 122b, the transistors M1 to M3 and the capacitor C1 can be formed by referring to the manufacturing methods of FIGS.

[0391] Note that the method for manufacturing a semiconductor device according to one embodiment of the present invention is not limited to the methods illustrated in Figures 29A to 31. Materials and steps in the method for manufacturing a semiconductor device may be changed depending on the situation.

[0392] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0393] Embodiment Mode 3 In this embodiment mode, a structural example of a memory device including the semiconductor device described in the above embodiment mode will be described.

[0394] FIG. 32A shows a schematic perspective view illustrating an example configuration of the memory device 100. FIG. 32B shows a block diagram illustrating an example configuration of the memory device 100. The memory device 100 has a drive circuit layer 50 and N memory layers 60 (N is an integer of 1 or greater). Each memory layer 60 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns. FIG. 32B shows an example in which memory layer 60_k includes memory cell 10[1,1], memory cell 10[m,1] (where m is an integer of 1 or greater), memory cell 10[1,n] (where n is an integer of 1 or greater), memory cell 10[m,n], and memory cell 10[i,j] (where i is an integer of 1 or greater and m or less, and j is an integer of 1 or greater and n or less).

[0395] The memory layer 60 corresponds to the memory layer ALYa, the memory layer ALYb, or the memory layer ALYc described in embodiment 1. The memory cell 10 corresponds to the memory cell MCa or the memory cell MCb described in embodiment 1. The multiple memory layers 60 may include the memory layers ALYa to ALYc described in embodiment 2.

[0396] The N memory layers 60 are provided on the drive circuit layer 50. By providing the N memory layers 60 on the drive circuit layer 50, the area occupied by the memory device 100 can be reduced. In addition, the memory capacity per unit area can be increased.

[0397] In the present embodiment and the like, the first memory layer 60 is referred to as memory layer 60_1, the second memory layer 60 is referred to as memory layer 60_2, and the third memory layer 60 is referred to as memory layer 60_3. Furthermore, the kth memory layer 60 (k is an integer of 1 to N) is referred to as memory layer 60_k, and the Nth memory layer 60 is referred to as memory layer 60_N. Note that in the present embodiment and the like, when describing matters relating to all N memory layers 60 or when indicating matters common to each of the N memory layers 60, the term "memory layer 60" may be used.

[0398] <Configuration Example of Drive Circuit Layer 50> The drive circuit layer 50 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0399] In the storage device 100, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0400] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0401] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 100. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation or read operation) of the memory device 100. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0402] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0403] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0404] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed.

[0405] The row driver 43 has a function of selecting a write and read word line specified by the row decoder 42 (for example, any one of the wirings WL[1] to WL[m] shown in FIG. 33, which will be described later).

[0406] The column driver 45 has a function of writing data to the memory cells 10, a function of reading data from the memory cells 10, and a function of holding the read data. The column driver 45 has a function of selecting write and read bit lines (for example, wirings BL[1] to BL[n] shown in FIG. 33, which will be described later) designated by the column decoder 44.

[0407] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 (referred to as first data in the above embodiment) is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. Note that in the above embodiment, the read data (Dout) is treated as data resulting from calculation. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 100. The data output from the output circuit 48 is a signal RDA.

[0408] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device 100 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. Signal PON1 switches PSW22 between the ON and OFF states, and signal PON2 switches PSW23 between the ON and OFF states. In FIG. 32B, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0409] Next, the electrical connection between the peripheral circuit 41 and the memory layer 60 will be described.

[0410] 33 is a block diagram showing a configuration example of the peripheral circuit 41 and the memory layer 60_k. In FIG. 33, a row decoder 42 and a row driver 43 are electrically connected to the wirings WL[1] to WL[m], respectively, and a column decoder 44, a column driver 45, and a sense amplifier 46 are electrically connected to the wirings BL[1] to BL[n], respectively.

[0411] Note that the wirings WL[1] to WL[m] correspond to the wirings WWLa[i], RWLa[i], WWLb[i], and RWLb[i] described in Embodiment 1. That is, the wirings WL[1] to WL[m] function as word lines.

[0412] The wirings BL[1] to BL[n] correspond to the wirings WRBLa[j], WRBLa[j+1], WRBLa[j+2], WRBLb[j], WRBLb[j+1], and WRBLb[j+2] described in Embodiment 1. That is, the wirings BL[1] to BL[n] function as bit lines.

[0413] The memory cell 10[i,j] arranged in the i-th row and j-th column is electrically connected to a wiring WL[i] and a wiring BL[j].

[0414] As shown in FIG. 33, by electrically connecting the memory layer 60 — k and the peripheral circuit 41, it is possible to write data to the memory layer 60 — k and read data from the memory layer 60 — k.

[0415] Next, a cross-sectional structure example of a memory device 100 according to one embodiment of the present invention is shown in Figure 34. The memory device 100 shown in Figure 34 includes multiple memory layers 60 (the memory layer ALYa, the memory layer ALYb, or the memory layer ALYc in Figure 2 described in Embodiment 1) above the driver circuit layer 50. To reduce repetition, description of the memory layer 60 in this embodiment will be omitted.

[0416] 34 illustrates a transistor 400 included in the driver circuit layer 50. The transistor 400 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including part of the substrate 311, a low-resistance region 314a functioning as one of a source region and a drain region, and a low-resistance region 314b functioning as the other of the source region and the drain region. The transistor 400 may be a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single crystal silicon substrate.

[0417] Here, in the transistor 400 shown in FIG. 34 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a FIN-type transistor because it utilizes a convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI (Silicon On Insulator) substrate.

[0418] Note that the transistor 400 illustrated in FIG. 34 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0419] A wiring layer having an interlayer film, wiring, and plugs may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0420] For example, an insulator 320, an insulator 301, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 400. A conductor 328 or the like is embedded in the insulator 320 and the insulator 301. A conductor 330 or the like is embedded in the insulator 324 and the insulator 326. The conductors 328 and 330 function as contact plugs or wirings.

[0421] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 301 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0422] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 34 , an insulator 350, an insulator 357, and an insulator 352 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 357, and the insulator 352. The conductor 356 functions as a contact plug or a wiring. For example, the transistor 400 is electrically connected to the wiring WL or the wiring BL through the conductor 356, the conductor 330, or the like.

[0423] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0424] In this embodiment, a transistor having an oxide semiconductor in a channel formation region (OS transistor) will be described. Note that in the description of the OS transistor, a comparison with a transistor having silicon in a channel formation region (also referred to as a Si transistor) will also be briefly described.

[0425] [OS Transistor] An OS transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３ less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0426] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Charges trapped in trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0427] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0428] Furthermore, when impurities and oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and reliability may be reduced. Ｏ H) and generate electrons that become carriers. Ｏ When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on (a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0429] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as off-leak current or Ioff) of the transistor can be reduced.

[0430] Furthermore, as the size of Si transistors is reduced, a short channel effect (also referred to as SCE) occurs. This makes it difficult to reduce the size of Si transistors. One of the reasons for the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0431] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0432] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0433] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0434] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or ＋ / n − / n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0435] By using an OS transistor with the above structure, good electrical characteristics can be obtained even when the semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, or 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty in achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length refers to the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.

[0436] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0437] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0438] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0439] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0440] [Electronic Component] FIG. 35A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 35A has semiconductor device 710 inside mold 711. FIG. 35A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0441] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which a plurality of memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0442] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0443] Furthermore, it is preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0444] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0445] 35B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on interposer 731.

[0446] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0447] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0448] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0449] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0450] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0451] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSVs, a space such as the width of the terminal pitch is required. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0452] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0453] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 35B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0454] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0455] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 36A . The electronic device 6500 shown in FIG. 36A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0456] 36B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 described above is preferable because power consumption can be reduced.

[0457] [Mainframe] Next, Fig. 36C shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 36C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0458] The computer 5620 can have the configuration shown in the perspective view in Fig. 36D, for example. In Fig. 36D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, and each terminal is connected to the motherboard 5630.

[0459] A PC card 5621 shown in Figure 36E is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that although Figure 36E illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to for the semiconductor devices.

[0460] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0461] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0462] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0463] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0464] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0465] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0466] [Space Equipment] The semiconductor device of one embodiment of the present invention can be used in space equipment as equipment that processes and stores information.

[0467] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0468] Fig. 37 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 37, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0469] 37 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0470] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0471] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0472] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0473] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0474] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0475] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0476] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0477] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage and servers for storing a huge amount of data, a stable power supply for maintaining the data, and cooling equipment required for maintaining the data.

[0478] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0479] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0480] Fig. 38 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 38 has a plurality of servers 7001sb as hosts 7001. It also has a plurality of storage devices 7003md as storage 7003. The host 7001 and storage 7003 are shown connected via a storage area network 7004 and a storage control circuit 7002.

[0481] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0482] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0483] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0484] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0485] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0486] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0487] This example also describes an OS transistor included in a semiconductor device of one embodiment of the present invention. Also, a memory cell array and its peripheral circuits that can be applied to the semiconductor device of one embodiment of the present invention will be described. In this example, the memory cell array and the peripheral circuits are referred to as a memory device for convenience. Furthermore, the memory device was actually fabricated, and the results of measuring its data retention characteristics will also be described.

[0488] <OS Transistor> As described in the above embodiment, when the band gap of the oxide semiconductor included in the OS transistor is made larger than that of silicon, the off-state current of the OS transistor can be reduced.

[0489] Furthermore, OS transistors have higher voltage tolerance than Si transistors. FIG. 39A is a graph showing the source-drain breakdown voltage characteristics of an OS transistor, where the horizontal axis represents the source-drain voltage (Vd [V]) and the vertical axis represents the amount of leakage current (Id [A]) flowing between the source and drain. FIG. 39B is a graph showing the gate breakdown voltage characteristics of an OS transistor, where the horizontal axis represents the gate-source (drain) voltage (Vg [V]) and the vertical axis represents the amount of leakage current (Ig [A]) flowing between the gate and source (drain). Note that the size of the OS transistor used in the measurements of FIGS. 39A and 39B was a channel length of 0.5 μm and a channel width of 0.5 μm. As shown in FIGS. 39A and 39B , the source-drain breakdown voltage and gate breakdown voltage of the OS transistor were both 13.5 V or higher, and the leakage current was 1 pA (1×10 −１２ A) The following is true.

[0490] Since an OS transistor can be formed by one or both of a chemical vapor deposition method and a physical vapor deposition method, for example, an OS transistor can be stacked over a CMOS circuit formed on a semiconductor substrate using silicon, that is, a monolithic stacked semiconductor device in which an OS transistor is formed over a CMOS circuit can be manufactured.

[0491] <Circuit Configuration of Memory Device> Fig. 40 shows a memory cell MC that can be applied to the memory cell array. The memory cell MC shown in Fig. 40 has a 3Tr1C NOSRAM (registered trademark) configuration similar to the memory cell MCa (memory cell MCb) shown in Fig. 1, and includes transistors M11 to M13 and a capacitance element C11.

[0492] In the memory cell MC, the first terminal of the transistor M11 is electrically connected to the gate of the transistor M12 and the first terminal of the capacitor C11, the second terminal of the transistor M11 is electrically connected to the wiring WBL, and the gate of the transistor M11 is electrically connected to the wiring WWL. The second terminal of the capacitor C11 is electrically connected to the wiring CL. The first terminal of the transistor M12 is electrically connected to the wiring RBL, and the second terminal of the transistor M12 is electrically connected to the first terminal of the transistor M13. The second terminal of the transistor M13 is electrically connected to the wiring WBL, and the gate of the transistor M13 is electrically connected to the wiring RWL.

[0493] As described above, the transistor M11 corresponds to the transistor M1 of the memory cell MCa (memory cell MCb) of FIG. 1, the transistor M12 corresponds to the transistor M2 of the memory cell MCa (memory cell MCb) of FIG. 1, the transistor M13 corresponds to the transistor M3 of the memory cell MCa (memory cell MCb) of FIG. 1, and the capacitive element C11 corresponds to the capacitive element C1 of the memory cell MCa (memory cell MCb) of FIG. 1. Note that the memory cell MCa (memory cell MCb) differs from the memory cell MCa (memory cell MCb) shown in FIG. 1 in that the second terminal of the transistor M11 is electrically connected to the wiring WBL, and the second terminal of the transistor M13 is electrically connected to the wiring WBL. Furthermore, the transistor M11 may be configured to have a back gate, similar to the transistor M1 of the memory cell MCa (memory cell MCb) of FIG. 1.

[0494] The wiring WWL functions as a write word line, and the wiring RWL functions as a read word line. The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WBL also functions as a wiring that applies a predetermined potential during reading. The wiring CL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element C11, similar to the description of the memory cell MCa (memory cell MCb) in FIG. 1. During writing and reading of data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CL.

[0495] In particular, the transistor M11 is an OS transistor whose active layer is made of In—Ga—Zn oxide (hereinafter referred to as CAAC-IGZO), which is CAAC-OS. Transistors using CAAC-IGZO for their active layers are known to exhibit very low off-state current. For example, the off-state current of the transistor is 100 zA or less per 1 μm of channel width (z: zepto, 10 −２１ ), 1zA or less or 10yA or less (y: Yocto, 10 −２４ ) can be obtained. Therefore, by using this transistor as the transistor M11, it is possible to prevent loss of data held in the first terminal of the capacitive element C11 due to current leakage. In other words, data written to the memory cell MC can be held for a long time.

[0496] The transistors M12 and M13, including the transistors M21 to M23 described later, use transistors whose active layers are made of silicon. Transistors whose active layers are made of silicon exhibit high on-state current characteristics and are therefore suitable for use in signal conversion circuits, amplifier circuits, etc. The silicon may be amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like.

[0497] The memory device of this embodiment has a configuration in which the above-described transistors are formed on a semiconductor substrate made of single crystal silicon, and the transistors M11 to M13 and the capacitor C11 are formed above the transistors with an insulating film or the like interposed therebetween.

[0498] Next, the configuration of a memory cell array MA to which the memory cells MC are applied and its peripheral circuits is shown in FIG.

[0499] The memory cell array MA has memory cells MC arranged in a matrix. Note that FIG. 41 illustrates memory cells MC arranged at addresses m rows and n columns, m rows and n+1 columns, m+1 rows and n columns, and m+1 rows and n+1 columns (where m and n are integers equal to or greater than 1). The reference numeral for the memory cell arranged at the address m rows and n columns is denoted as MC[m, n]. Similarly, the reference numerals for the memory cells arranged at the addresses m rows and n+1 columns, m+1 rows and n+1 columns, and m+1 rows and n+1 columns are denoted as MC[m, n+1], MC[m+1, n], and MC[m+1, n+1], respectively. Note that in this embodiment, one or more memory cells included in the memory cell array MA may be collectively referred to as memory cells MC, without the address notation.

[0500] In FIG. 41, a node FN is illustrated as an electrical connection point between the first terminal of the transistor M11, the first terminal of the capacitor C11, and the gate of the transistor M12 in each memory cell MC.

[0501] The wirings WWL[m] and WWL[m+1] are electrically connected to memory cells MC located in the mth and m+1th rows, respectively, and have the function of the wiring WWL in FIG. 40 . The wirings RWL[m] and RWL[m+1] are electrically connected to memory cells MC located in the mth and m+1th rows, respectively, and have the function of the wiring RWL in FIG. 40 . The wirings WBL[n] and WBL[n+1] are electrically connected to memory cells MC located in the nth and n+1th rows, respectively, and have the function of the wiring WBL in FIG. 40 . The wirings RBL[n] and RBL[n+1] are electrically connected to memory cells MC located in the nth and n+1th rows, respectively, and have the function of the wiring RBL in FIG. 40 . Note that in this embodiment, the notation of addresses may be omitted for one or more wirings included in the memory cell array MA. For example, the wiring WBL[n] and the wiring WBL[n+1] may be collectively referred to as the wiring WBL, and the wiring WWL[m] and the wiring WWL[m+1] may be collectively referred to as the wiring WWL.

[0502] As peripheral circuits of the memory cell array MA, FIG. 41 shows a circuit CD, a circuit RD, a circuit RS and a read circuit ROC.

[0503] The circuit CD has a column decoder and a column driver, and is electrically connected to the wirings WBL and RBL. The circuit CD has the functions of receiving 4-bit write data from the outside as a signal IN[3:0], selecting the wirings WBL of the column including the memory cells MC to which the data is to be written and applying a write voltage according to the data, and selecting the wirings WBL of the column including the memory cells MC to which the data is to be read and applying a predetermined potential.

[0504] The circuit RD includes a row decoder and a row driver, and is electrically connected to the wirings WWL and RWL. The circuit RD has a function of selecting the wiring WWL of a row including a memory cell MC to which data is written and applying a predetermined potential to the wiring WWL, and a function of selecting the wiring RWL of a row including a memory cell MC to which data is read and applying a predetermined potential to the wiring RWL.

[0505] The circuit RS is electrically connected to the wiring RBL and the wiring SRL. The circuit RS has a function of selecting the wiring RBL of a column including the memory cell MC from which data is read and electrically connecting the wiring RBL to the wiring SRL.

[0506] The read circuit ROC includes transistors M21 to M23 and an operational amplifier OP.

[0507] A first terminal of the transistor M21 is electrically connected to the wiring SRL and the gate of the transistor M23, a second terminal of the transistor M21 is electrically connected to the wiring VSS, and a gate of the transistor M21 is electrically connected to the wiring Vb1.

[0508] The wiring VSS is a wiring that applies a low-level potential, and the wiring Vb1 is a wiring that applies a voltage higher than the threshold voltage of the transistor M21.

[0509] 41, the connection configuration of transistor M12 and transistor M21 constitutes a source follower circuit SF1. When reading data from memory cell MC[m+1,n], a high-level potential (for example, a potential provided by wiring VDD, which will be described later) is applied to wiring WBL[n], and a predetermined potential is applied to wiring RWL[m+1] to turn on transistor M13. This allows the source follower circuit SF1 to provide the gate of transistor M23 with a potential that is approximately the same as the potential input to the gate of transistor M12 (the potential held in capacitor C11).

[0510] A first terminal of the transistor M22 is electrically connected to a first terminal of the transistor M23 and a non-inverting input terminal of the operational amplifier OP, a second terminal of the transistor M22 is electrically connected to the wiring VDD, a gate of the transistor M22 is electrically connected to the wiring Vb2, and a second terminal of the transistor M23 is electrically connected to the wiring VSS.

[0511] The wiring VDD is a wiring that applies a high-level potential that is higher than the low-level potential applied by the wiring VSS, and the wiring Vb2 is a wiring that applies a voltage that is lower than the threshold voltage of the transistor M22.

[0512] The transistors M22 and M23 are connected as described above to form a source follower circuit SF2. Therefore, a potential substantially equal to the potential input to the gate of the transistor M23 is input to the non-inverting input terminal of the operational amplifier OP.

[0513] The inverting input terminal of the operational amplifier OP is electrically connected to the output terminal of the operational amplifier OP. In other words, the operational amplifier OP has a voltage follower connection configuration. Although detailed specifications of the storage device of this embodiment will be described later, the signal AOUT output from the operational amplifier OP is an analog potential.

[0514] Note that the error between the read voltage and the write voltage can be reduced by adjusting the potentials applied to the wirings Vb1 and Vb2.

[0515] An operation example of the memory device illustrated in Fig. 41 is shown in a timing chart of Fig. 42. Fig. 42 shows changes in the potentials of the wiring WWL, the wiring WBL, the wiring RWL, the wiring RBL, the node FN, and the signal AOUT.

[0516] As shown in FIG. 42, data is written by inputting 4-bit write data DT to the circuit CD as a signal DIN[3:0]. The circuit CD also performs digital-to-analog conversion on the data DT to generate a potential corresponding to the data DT and applies the potential corresponding to the data DT to the wiring WBL. Next, the circuit RD applies a high-level potential to the wiring WWL to turn on the transistor M11. This allows the potential of the wiring WBL (an analog potential corresponding to the data DT) to be written to the first terminal of the capacitor C11. After that, a low-level potential is applied to the wiring WWL to turn off the transistor M11, thereby maintaining the potential of the first terminal of the capacitor C11 and the potential of the gate (node ​​FN) of the transistor M12. A low-level potential is applied to the wiring RWL and the wiring RBL. At this time, the transistor M13 is turned off.

[0517] It is assumed that the 4-bit write data DT is converted into an analog potential of 16 levels by a digital-to-analog conversion circuit included in the circuit CD.

[0518] 42, data is read by applying a predetermined potential to the wiring WBL and a high-level potential to the wiring RWL to turn on the transistor M13. At this time, the potential of the wiring RBL is determined by the potential of the first terminal of the capacitor C11 and the potential of the gate (node ​​FN) of the transistor M12. The potential of the wiring RBL is input to the circuit RS and the read circuit ROC, and the read circuit ROC outputs a signal AOUT corresponding to the potential of the wiring RBL, i.e., the data written to the node FN. This allows the information written in the memory cell to be read.

[0519] <Fabrication of Memory Device> The circuit configuration of the memory device described above was actually formed on a semiconductor substrate and prototyped as a memory die. Figure 43 is an image of the top surface of the memory die.

[0520] The specifications of the memory die are shown in the table below. Note that in the Technology Size section of the table below, CMOS indicates transistors M12, M13, and M21 to M23, and OSFET indicates transistor M11. The Density section indicates that the memory cell array MA has circuits arranged in a matrix of 2 rows and 8 columns, and that each circuit includes 8 memory cells that can be accessed in parallel at one time.

[0521]

[0522] 41, one memory cell MC was selected, 16 levels of voltage converted from 4-bit digital data by a digital-to-analog converter (DAC) were written to the memory cell MC, and the read voltages for each write voltage were measured. Similar measurements were then performed on another 15 memory cells MC, and the average and standard deviation σ of the voltages at each level read from a total of 16 memory cells MC were obtained.

[0523] The results are shown in Figure 44A. Figure 44A shows the relationship between the 16-level write voltage (DAC input 4-bit digital data [HEX]) and the average ±3σ of the read voltage (Mean Read Voltage) (Mean read data ±3σ [V]). Note that in Figure 44A, the 16 levels of write voltage are denoted as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. As shown in Figure 44A, good linearity was confirmed between the write voltage and the read voltage. Furthermore, among the adjacent write voltages, write voltage "E" and write voltage "F" had the narrowest voltage distribution within the range of their respective "average read voltage ±3σ." Note that the voltage distribution at this time was 0.291V.

[0524] 44B is a graph showing 16 levels of write voltage (DAC input 4-bit digital data [HEX]) on the horizontal axis and 3σ on the vertical axis. From FIG. 44B, 3σ is maximized when the write voltage is "F," at 3σ = 0.101 V. The voltage range from -3σ to 3σ is 0.202 V.

[0525] From the above results, it is possible to increase the number of levels of the write voltage beyond 16, since the voltage range of 0.202 V from -3σ to 3σ when 3σ is at its maximum is lower than the narrowest voltage between distributions in the range of "the average value of the read voltage for adjacent write voltages ±3σ".

[0526] For example, a schematic diagram of threshold voltage distributions at write voltages "E" and "F" is shown in FIG. 45A. From the above results, the voltage between the distributions of write voltages "E" and "F" is 0.291 V, and the voltage range from -3σ to 3σ at write voltage "F" where 3σ is maximum is 0.202 V, so the threshold voltage distributions at write voltages "E" and "F" are as shown in FIG. 45A. Therefore, a new level of write voltage can be set between write voltages "E" and "F" as shown in the schematic diagram of threshold voltage distributions in FIG. 45B. In FIG. 45B, the new level of write voltage is set to "F". ３２ ” and is shown by a broken line. In FIG. 45B, the write voltage “F ３２ The voltage range from -3σ to 3σ of " is set to 0.202V.

[0527] Next, the data retention characteristics of the fabricated memory device were measured. Specifically, the 16-level write voltage used in the above measurement was written to memory cells MC included in the memory cell array MA of the memory device, and the time fluctuation of each read voltage at room temperature was measured ( FIG. 46A ). The graph shown in FIG. 46A shows the amount of fluctuation in read voltage with respect to retention time, and it can be seen from this graph that the 16-level voltage written to the memory cell MC continued to be retained without fluctuation for approximately 3 hours.

[0528] The graph in Figure 46B shows the variation in read voltage after 3 hours relative to the write voltage (DAC input 4-bit digital data [HEX]) to the memory cell MC. The graph in Figure 46B shows that the variation in read voltage (Voltage variation after 3 hours [V]) ranges from 0 V to -0.05 V, confirming that data is accurately retained even after 3 hours. The largest variation was 0.038 V at write voltage "F."

[0529] When the above fluctuations are taken into consideration, the voltage range from -3σ to 3σ when 3σ is at its maximum is 0.202 + 0.038 = 0.240 V, and the voltage between the distributions in the range of "the average value of the read voltage for adjacent write voltages ± 3σ" is 0.291 - 0.038 = 0.253 V. Even when the above fluctuations are taken into consideration, the voltage range from -3σ to 3σ is lower than the voltage between the distributions in the range of "the average value of the read voltage for adjacent write voltages ± 3σ", so the number of levels of the write voltage that can be held in the memory cell MC can be made greater than 16 levels. Furthermore, from the voltage range from -3σ to 3σ and the voltage between the distributions in the range of "the average value of the read voltage for adjacent write voltages ± 3σ", it can be estimated that the memory cell MC can hold 32 levels of analog potential (i.e., equivalent to 5-bit digital data) for three hours.

[0530] For example, a schematic diagram of threshold voltage distributions at write voltages "E" and "F" is shown in FIG. 47A. From the above results, the voltage range from -3σ to 3σ at write voltage "F" after the change is 0.240 V, and the voltage between the distributions in the range of "the average value of read voltages for adjacent write voltages ±3σ" is 0.291-0.038=0.251 V, so the threshold voltage distributions at write voltages "E" and "F" are as shown in FIG. 47A. In FIG. 47A, the voltage distributions after the change are shown by dashed lines.

[0531] Therefore, even if the above fluctuation amount is taken into consideration, as shown in FIG. 47B, a new level of write voltage can be provided between the write voltage "E" and the write voltage "F" in the same manner as in FIG. 45B. FIG. 47B shows a case where a new level of write voltage "F" is provided between the write voltage "E" and the write voltage "F" in FIG. ３２ 45B is a schematic diagram of a threshold voltage distribution in which a write voltage "F" before the change is set. ３２ " is shown by a broken line, and the write voltage "F ３２ ” is indicated by a dashed line. In FIG. 47B, the write voltage “F ３２ The voltage range from -3σ to 3σ of " is set to 0.240V.

[0532] From the above results, by applying a transistor having CAAC-IGZO in the active layer as a write transistor in the circuit configuration shown in FIG. 41, it is possible to configure a memory device that can handle 5 bits of data per cell and retain that data for 3 hours.

[0533] DEV: semiconductor device, DEVA: semiconductor device, ALYa: memory layer, ALYb: memory layer, ALYc: memory layer, MC: memory cell, MCa: memory cell, MCa[i,j]: memory cell, MCa[i,j-1]: memory cell, MCa[i,j+1]: memory cell, MCa[i+1,j+1]: memory cell, MCa[i+1,j]: memory cell, MCa[i+1,j-1]: memory cell, MCb: memory cell, MCb[i,j]: memory cell, MCb[i,j+1]: memory cell, MCc: memory cell, MCA[i,j]: memory cell, MCA[i,j+2]: Memory cell, MCB[i,j+1]: Memory cell, MCC[i,j]: Memory cell, MCC[i,j+2]: Memory cell, MCZ[i,j+1]: Memory cell, WWLa[i]: Wiring, WWLa[i+1]: Wiring, WWLb[i]: Wiring, WWLc[i]: Wiring, RWLa[i]: Wiring, RWLa[i+1]: Wiring, RWLb[i]: Wiring, RWLc[i]: Wiring, CLa[i]: Wiring, CLa[i+1]: Wiring, CLb[i]: Wiring, CLc[i]: Wiring, WRBLa[j]: Wiring, WRBLa[j+1]: Wiring, WRBLa[j+2]: Wiring, WRB La[j+3]: wiring, WRBLb[j]: wiring, WRBLb[j+1]: wiring, WRBLb[j+2]: wiring, WRBLc[j+1]: Wiring, WRBLc[j+3]: Wiring, SLa[j]: Wiring, SLa[j+1]: Wiring, SLa[j+2]: Wiring, SLb[j]: Wiring, S Lb[j+1]: Wiring, SLc[j]: Wiring, SLc[j+2]: Wiring, WL[1]: Wiring, WL[i]: Wiring, WL[m]: Wiring, BL [1]: Wiring, BL[j]: Wiring, BL[n]: Wiring, WWL: Wiring, WWL[m]: Wiring, WWL[m+1]: Wiring, WBL: Wiring, WB L[n]: wiring, WBL[n+1]: wiring, RWL: wiring, RWL[m]: wiring, RWL[m+1]: wiring, RBL: wiring, RBL[n]: wiring, RBL[n+1]: wiring, CL: wiring, Vb1: wiring, Vb2: wiring, CD: circuit, RD: circuit, RS: circuit, ROC: readout circuit, OP: operational amplifier, M1: transistor, M2: transistor, M3: transistor, M11: transistor, M12: transistor, M13: transistor, M21: transistor, M22: transistor, M23: transistor, C1: capacitor, C11: capacitor,FN: node, PLa: opening, PLb: opening, PLc: opening, PLd: opening, PLe: opening, 10: memory cell, 10[1,1]: memory cell, 10[m,1]: memory cell, 10[1,n]: memory cell, 10[m,n]: memory cell, 10[i,j]: memory cell, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 50: drive circuit layer, 60_k: Memory layer, 60_1: memory layer, 60_2: memory layer, 60_3: ​​memory layer, 60_N: memory layer, 100: memory device, 122a: insulator, 122b: insulator, 122c: insulator, 124: insulator, 130: oxide, 130a: oxide, 130b: oxide, 142a: conductor, 142b: conductor, 142c: conductor, 142d: conductor, 142e: conductor, 142f: conductor, 142g: conductor, 153_0: insulator, 153_1: insulator, 153_2: insulator, 153_3: insulator, 153_4: insulator, 154_0: insulator, 154_1: insulator, 154_2: insulator Insulator, 154_3: Insulator, 154_4: Insulator, 157_3: Opening, 157_5: Opening, 158_2: Opening, 158_3: Opening, 158_4: Opening, 159: Opening, 160_0: Conductor, 160_1: Conductor, 160_2: Conductor, 160_3: ​​Conductor, 160_4: Conductor, 160a_1: Conductor, 160a_2: Conductor, 160a_3: Conductor, 160a_4: Conductor, 160b_1: Conductor, 160b_2: Conductor, 160b_3: Conductor, 160b_4: Conductor, 170_0: Conductor, 170_1: Conductor, 170_2: Conductor, 170_3: Conductor conductor, 170_4: conductor, 170_5: conductor, 170a_1: conductor, 170a_2: conductor, 170a_3: conductor, 170a_4: conductor, 170a_5: conductor, 170b_1: conductor, 170b_2: conductor, 170b_3: conductor, 170b_4: conductor, 170b_5: conductor, 171_1: conductor, 171_3: conductor, 175: insulator, 180: insulator, 180_0: insulator, 301: insulator, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator,324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 356: conductor, 357: insulator, 400: transistor, 700: electronic component, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer , 732: package substrate, 735: semiconductor device, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot , 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7004: storage area network,

Claims

1. A first insulator and a first layer having a region disposed above the first insulator, The first layer comprises a first oxide semiconductor, a first to ninth conductor, and a second to fifth insulator. The first oxide semiconductor has a region located above the first insulator, The first conductor has a region located above the first insulator and a region located above the first oxide semiconductor. The second conductor has a region located above the first oxide semiconductor, The second insulator has a region positioned above the first oxide semiconductor between the first conductor and the second conductor. The third conductor has a region located above the first oxide semiconductor via the second insulator, The fourth conductor has a region located above the first oxide semiconductor, The third insulator has a region located between the second conductor and the fourth conductor, above the first oxide semiconductor. The fifth conductor has a region located above the first oxide semiconductor via the third insulator, The sixth conductor has a region located above the first insulator and a region located above the first oxide semiconductor, The fourth insulator has a region positioned above the first oxide semiconductor between the fourth conductor and the sixth conductor, The seventh conductor has a region located above the first oxide semiconductor via the fourth insulator, The fifth insulator has a region that does not overlap with the first oxide semiconductor and is located above the first conductor. The eighth conductor has a region located above the first conductor via the fifth insulator, The ninth conductor has a region positioned above the second conductor and is electrically connected to the second conductor. Semiconductor equipment.

2. In Claim 1, The first layer comprises a second oxide semiconductor, a tenth to thirteenth conductor, and a sixth insulator. The second oxide semiconductor has a region located above the first insulator, The tenth conductor has a region located above the first insulator and a region located above the second oxide semiconductor, The 11th conductor has a region located above the second oxide semiconductor, The sixth insulator has a region located between the tenth conductor and the eleventh conductor, above the second oxide semiconductor. The twelfth conductor has a region disposed above the second oxide semiconductor via the sixth insulator, The thirteenth conductor has a region positioned above the first conductor and is electrically connected to the first conductor. The thirteenth conductor has a region positioned above the twelfth conductor and is electrically connected to the twelfth conductor. Semiconductor equipment.

3. In Claim 2, The material comprises a seventh insulator having a region positioned above the first layer, and a second layer having a region positioned above the seventh insulator. The second layer comprises a third oxide semiconductor, a fourteenth conductor, and an eighth insulator. The third oxide semiconductor has a region located above the eighth conductor via the seventh insulator, and a region located above the thirteenth conductor via the seventh insulator. The 14th conductor has a region located above the 3 oxide semiconductor via the 8th insulator, The 14th conductor has a region that overlaps with the 8th conductor. Semiconductor equipment.

4. In claim 3, Each of the first to third oxide semiconductors comprises one or more elements selected from indium, zinc, and element M. The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, or antimony. Semiconductor equipment.

5. A semiconductor device according to any one of claims 1 to 4, and a drive circuit, The first insulator has a region located above the drive circuit. storage device.

6. A storage device according to claim 5, and a housing comprising, electronic equipment.

7. A first insulator, a first layer having a region disposed above the first insulator, a second insulator and a first conductor having a region disposed above the first layer, and a second layer having a region disposed above the second insulator, The first layer comprises a first oxide semiconductor, a second to tenth conductor, and a third to sixth insulator. The second layer comprises a second oxide semiconductor, an eleventh to a thirteenth conductor, and a seventh insulator. The first oxide semiconductor has a region located above the first insulator, The second conductor has a region positioned above the first insulator and a region positioned above the first oxide semiconductor, The third conductor has a region located above the first oxide semiconductor, The third insulator has a region located between the second conductor and the third conductor, above the first oxide semiconductor. The fourth conductor has a region located above the first oxide semiconductor via the third insulator, The fifth conductor has a region located above the first oxide semiconductor, The fourth insulator has a region located between the third conductor and the fifth conductor, above the first oxide semiconductor. The sixth conductor has a region located above the first oxide semiconductor via the fourth insulator, The seventh conductor has a region located above the first insulator and a region located above the first oxide semiconductor, The fifth insulator has a region positioned above the first oxide semiconductor between the fifth conductor and the seventh conductor, The eighth conductor has a region located above the first oxide semiconductor via the fifth insulator, The sixth insulator has a region that does not overlap with the first oxide semiconductor and is located above the seventh conductor. The ninth conductor has a region located above the seventh conductor via the sixth insulator, The tenth conductor has a region positioned above the fifth conductor and is electrically connected to the fifth conductor. The second oxide semiconductor has a region located above the second insulator, The 11th conductor has a region located above the second insulator and a region located above the second oxide semiconductor, The twelfth conductor has a region located above the first oxide semiconductor, The seventh insulator has a region located between the eleventh conductor and the twelfth conductor, above the second oxide semiconductor. The 13th conductor has a region disposed above the second oxide semiconductor via the 7th insulator, The second insulator has an opening, The first conductor has a region located in the opening, The first conductor has a region positioned above the fourth conductor and is electrically connected to the fourth conductor. The first conductor has a region located below the eleventh conductor and is electrically connected to the fourth conductor. Semiconductor equipment.

8. In claim 7, The first oxide semiconductor comprises one or more elements selected from indium, zinc, and element M. The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, or antimony. Semiconductor equipment.

9. The device comprises the semiconductor device described in claim 8 and a drive circuit, The first insulator has a region located above the drive circuit. storage device.

10. A device comprising the storage device and housing described in claim 9, electronic equipment.