Pulse transmission circuit, signal transmission device, and electronic device

Abstract

This pulse transmission circuit is built into a signal transmission device of the capacitance insulation type and causes the logic level of a transmitted pulse signal (INPUT, XINPUT), which is to be transmitted to a subsequent capacitor, to transition gradually when the logic level of an input pulse signal switches. For example, the pulse transmission circuit may trigger the transmitted pulse signal for a plurality of times so as to repeatedly rise and fall while causing the logic level of the transmitted pulse signal to transition gradually.

Description

Pulse transmitting circuit, signal transmission device, electronic device

[0001] The present disclosure relates to a pulse transmitting circuit, a signal transmission device, and an electronic device.

[0002] 2. Description of the Related Art A signal transmission device using a capacitive insulation system is known as a means for transmitting a pulse signal between a primary circuit system and a secondary circuit system while isolating the primary circuit system from the secondary circuit system.

[0003] An example of the related prior art is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] JP 2014-176045 A

[0005] However, conventional signal transmission devices using the capacitive isolation method have room for improvement in common mode transient immunity (CMTI).

[0006] For example, the pulse transmission circuit disclosed in this specification is incorporated into a signal transmission device using a capacitive isolation method, and is configured (first configuration) to gradually transition the logic level of the transmission pulse signal transmitted to the downstream capacitor when the logic level of the input pulse signal switches.

[0007] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

[0008] According to the present disclosure, it is possible to improve the common-mode transient immunity of a signal transmission device using a capacitive isolation method.

[0009] FIG. 1 is a diagram illustrating a signal transmission device using a magnetic isolation system. FIG. 2 is a diagram illustrating a signal transmission device using a capacitive isolation system. FIG. 3 is a diagram illustrating an example of an electronic device including a signal transmission device. FIG. 4 is a diagram illustrating how signal amplitude attenuates between input / output nodes. FIG. 5 is a diagram illustrating how potential fluctuations propagate between substrate nodes. FIG. 6 is a diagram illustrating a verification pattern for common-mode transient immunity. FIG. 7 is a diagram illustrating a first embodiment for improving common-mode transient immunity. FIG. 8 is a diagram for explaining signal decomposition of common-mode noise. FIG. 9 is a diagram illustrating a second embodiment for improving common-mode transient immunity. FIG. 10 is a diagram illustrating a third embodiment for improving common-mode transient immunity. FIG. 11 is a diagram illustrating an example configuration of a pulse transmission circuit. FIG. 12 is a diagram illustrating an example configuration of a DAC. FIG. 13 is a diagram illustrating the relationship between a selector selection state and a DAC output value. FIG. 14 is a diagram illustrating an example of a received pulse signal.

[0010] <Signal Transmission Device (Magnetic Insulation Type)> Fig. 1 shows a signal transmission device using a magnetic insulation type. The signal transmission device 1 shown in the figure is a semiconductor integrated circuit device (a so-called isolated gate driver IC) that transmits pulse signals between a primary circuit system and a secondary circuit system while electrically isolating the primary circuit system and the secondary circuit system through magnetic coupling.

[0011] Referring to the figure, the signal transmission device 1 includes a controller chip 10 , a driver chip 20 , and a transformer 30 .

[0012] The controller chip 10 is provided in the primary circuit system, converts an input pulse signal IN (e.g., a PWM (pulse width modulation) signal) into a transmission pulse signal, and controls the primary current flowing through the primary coil of the transformer 30 in accordance with this transmission pulse signal. In other words, a primary current loop exists in the controller chip 10.

[0013] The driver chip 20 is provided in the secondary circuit system, generates a received pulse signal in response to a secondary current flowing through the secondary coil of the transformer 30, converts this received pulse signal into an output pulse signal OUT, and outputs it to a load (e.g., a power transistor). In other words, a secondary current loop exists in the driver chip 20.

[0014] The transformer 30 is provided between the primary circuit system and the secondary circuit system, and transmits a change in the primary current flowing in the primary coil as a change in the secondary current flowing in the secondary coil. That is, the transformer 30 converts the electric signal of the primary circuit system (= primary current) into magnetic energy and then transmits it as an electric signal of the secondary circuit system (= secondary current).

[0015] The magnetically isolated signal transmission device 1 has high common mode transient immunity (CMTI), which is one of its important characteristics, but requires the use of the transformer 30, which increases costs.

[0016] <Signal Transmission Device (Capacitive Isolation Type)> Fig. 2 shows a signal transmission device using the capacitive isolation type. The signal transmission device 1 shown in the figure is a semiconductor integrated circuit device (a so-called isolated gate driver IC) that transmits pulse signals between a primary circuit system and a secondary circuit system while electrically isolating the primary circuit system and the secondary circuit system through capacitive coupling.

[0017] Referring to the figure, the signal transmission device 1 comprises a pulse transmission circuit TX, a pulse reception circuit RX, and capacitors C1 and C2.

[0018] The pulse transmitting circuit TX is provided in the primary circuit system, and generates a transmission pulse signal according to the input pulse signal IN and outputs it to the capacitors C1 and C2. The pulse transmitting circuit TX may be integrated into the controller chip 10.

[0019] The capacitors C1 and C2 are provided between the primary circuit system and the secondary circuit system, and receive a transmission pulse signal output by the pulse transmission circuit TX and transmit a reception pulse signal corresponding to the transmission pulse signal to the pulse reception circuit RX. By passing the capacitors C1 and C2 in this way, a direct electrical signal is not transmitted, but a signal is transmitted as a transient current change. In other words, a current loop is formed across the controller chip 10 and the driver chip 20.

[0020] Both the capacitors C1 and C2 may be integrated into the driver chip 20. The capacitors C1 and C2 can generally be formed inexpensively using metal wiring (aluminum wiring, etc.).

[0021] The pulse receiving circuit RX is provided in the secondary circuit system and outputs an output pulse signal OUT in response to a received pulse signal transmitted via the capacitors C1 and C2. The pulse receiving circuit RX may be integrated into the driver chip 20.

[0022] The capacitively isolated signal transmission device 1 has excellent EMC (electromagnetic compatibility) and EMI (electromagnetic interference) characteristics, both of which are important characteristics, and also has high responsiveness. Therefore, for example, the capacitively isolated signal transmission device 1 is suitable for applications that require high-speed operation of GaN devices.

[0023] 3 is a diagram showing an example of an electronic device including a signal transmission device using a capacitive isolation system. Electronic device A of this configuration example includes a signal transmission device 1, an upper switch HS, and a lower switch LS.

[0024] 2, the signal transmission device 1 transmits a pulse signal between the primary circuit system and the secondary circuit system while electrically isolating the primary circuit system and the secondary circuit system through capacitive coupling. Note that the signal transmission device 1 may be a semiconductor integrated circuit device in which, for example, a controller chip 10 (corresponding to the first chip) that mainly integrates circuit elements of the primary circuit system, and driver chips 20H and 20L (corresponding to the second chips, respectively) that mainly integrate circuit elements of the secondary circuit system are sealed in a single package.

[0025] Referring to the figure, the signal transmission device 1 comprises pulse transmitting circuits TX1 to TX4, pulse receiving circuits RX1 and RX2, and capacitors Ca1 to Ca4.

[0026] The pulse transmitting circuits TX1 to TX4 are all provided in the primary circuit system and generate transmission pulse signals IN1 to IN4 according to the input pulse signal IN. The pulse transmitting circuits TX1 to TX4 may all be integrated into the controller chip 10.

[0027] The input terminal of the pulse transmitting circuit TX1 is connected to the application terminal of the input pulse signal IN. The output terminal of the pulse transmitting circuit TX1 is connected to the pad T11 of the controller chip 10. The pulse transmitting circuit TX1 may be a buffer. Note that a pad capacitance Cp1 is provided between the pad T11 of the controller chip 10 and the substrate node sub1 (= the application terminal of the ground voltage GND).

[0028] The input terminal of the pulse transmitting circuit TX2 is connected to the application terminal of the input pulse signal IN. The output terminal of the pulse transmitting circuit TX2 is connected to the pad T12 of the controller chip 10. The pulse transmitting circuit TX2 may be an inverter. Note that a pad capacitance Cp2 is provided between the pad T12 of the controller chip 10 and the substrate node sub1.

[0029] The input terminal of the pulse transmitting circuit TX3 is connected to the application terminal of the input pulse signal IN. The output terminal of the pulse transmitting circuit TX3 is connected to the pad T13 of the controller chip 10. The pulse transmitting circuit TX2 may be an inverter. Note that a pad capacitance Cp3 is provided between the pad T13 of the controller chip 10 and the substrate node sub1.

[0030] The input terminal of the pulse transmitting circuit TX4 is connected to the application terminal of the input pulse signal IN. The output terminal of the pulse transmitting circuit TX4 is connected to the pad T14 of the controller chip 10. The pulse transmitting circuit TX1 may be a buffer. Note that a pad capacitance Cp4 is provided between the pad T14 of the controller chip 10 and the substrate node sub1.

[0031] The capacitors Ca1 and Ca2 are provided between the primary circuit system and the secondary circuit system, receive the transmission pulse signals IN1 and IN2 output from the pulse transmission circuits TX1 and TX2, respectively, and transmit the reception pulse signals OUT1 and OUT2 corresponding to the transmission pulse signals IN1 and IN2 to the pulse reception circuit RX1. Both the capacitors Ca1 and Ca2 may be integrated into the driver chip 20H.

[0032] A first end of the capacitor Ca1 is connected to a pad T21 (= an application terminal of the transmission pulse signal IN1) of the driver chip 20H. The pad T11 of the controller chip 10 and the pad T21 of the driver chip 20H are bonded via a wire W1. A second end of the capacitor Ca1 (= an application terminal of the reception pulse signal OUT1) is connected to a first differential input terminal of the pulse reception circuit RX1. A sub-capacitor Cs1 is provided between the second end of the capacitor Ca1 and a substrate node sub2 (= an application terminal of the switch voltage SW) of the driver chip 20H.

[0033] A first end of the capacitor Ca2 is connected to the pad T22 (= the application end of the transmission pulse signal IN2) of the driver chip 20H. The pad T12 of the controller chip 10 and the pad T22 of the driver chip 20H are bonded via a wire W2. A second end of the capacitor Ca2 (= the application end of the reception pulse signal OUT2) is connected to the second differential input end of the pulse reception circuit RX1. A sub-capacitor Cs2 is provided between the second end of the capacitor Ca2 and the substrate node sub2 of the driver chip 20H.

[0034] The capacitors Ca3 and Ca4 are provided between the primary circuit system and the secondary circuit system, receive the transmission pulse signals IN3 and IN4 output from the pulse transmission circuits TX3 and TX4, and transmit the reception pulse signals OUT3 and OUT4 corresponding to the transmission pulse signals IN3 and IN4 to the pulse reception circuit RX2. Both the capacitors Ca3 and Ca4 may be integrated into the driver chip 20L.

[0035] A first end of the capacitor Ca3 is connected to a pad T23 (= an application terminal of the transmission pulse signal IN3) of the driver chip 20L. The pad T13 of the controller chip 10 and the pad T23 of the driver chip 20L are bonded via a wire W3. A second end of the capacitor Ca3 (= an application terminal of the reception pulse signal OUT3) is connected to a first differential input terminal of the pulse reception circuit RX2. A sub-capacitor Cs3 is provided between the second end of the capacitor Ca3 and a substrate node sub3 (= an application terminal of the ground voltage PGND) of the driver chip 20L.

[0036] A first end of the capacitor Ca4 is connected to the pad T24 (= the application end of the transmission pulse signal IN4) of the driver chip 20L. The pad T14 of the controller chip 10 and the pad T24 of the driver chip 20L are bonded via a wire W4. A second end of the capacitor Ca4 (= the application end of the reception pulse signal OUT4) is connected to the second differential input end of the pulse reception circuit RX2. A sub-capacitor Cs4 is provided between the second end of the capacitor Ca4 and the substrate node sub3 of the driver chip 20L.

[0037] The above-mentioned capacitors Ca1 to Ca4 can generally be formed inexpensively using metal wiring (aluminum wiring, etc.).

[0038] In this way, by passing through capacitors Ca1 to Ca4, direct electrical signals are not transferred, but rather signals are transferred as transient current changes. In other words, in the signal transmission device 1, current loops are formed so as to extend between the controller chip 10 and the driver chip 20H, and between the controller chip 10 and the driver chip 20L.

[0039] The pulse receiving circuit RX1 is provided in the secondary circuit system and outputs an output pulse signal OUTH corresponding to the received pulse signals OUT1 and OUT2 transmitted via the capacitors Ca1 and Ca2. The pulse receiving circuit RX1 may be integrated into the driver chip 20H.

[0040] The pulse receiving circuit RX2 is provided in the secondary circuit system and outputs an output pulse signal OUTL corresponding to the received pulse signals OUT3 and OUT4 transmitted via the capacitors Ca3 and Ca4. The pulse receiving circuit RX2 may be integrated into the driver chip 20L.

[0041] The upper switch HS and the lower switch LS are connected in series between a power system power supply terminal (= terminal to which the power supply voltage PVIN is applied) and a power system ground terminal (= terminal to which the ground voltage PGND is applied), and are complementarily turned on / off in response to the output pulse signals OUTH and OUTL output from the signal transmission device 1. In other words, from the perspective of the signal transmission device 1, the upper switch HS and the lower switch LS correspond to loads (= objects to be driven) that are turned on / off in response to the output pulse signals OUTH and OUTL.

[0042] The switch voltage SW output from the connection node between the upper switch HS and the lower switch LS is a square wave signal that is pulse-driven between the power supply voltage PVIN and the ground voltage PGND. A half-bridge output stage that generates such a switch voltage SW can be used, for example, as the output stage of a switching power supply or a motor drive device.

[0043] <Considerations Regarding Common Mode Transient Immunity (CMTI)> In order to increase the common mode transient immunity (CMTI) of the signal transmission device 1 using the capacitive isolation method, it is necessary to consider the signal amplitude between input / output nodes and between board nodes.

[0044] 4 is a diagram showing how signal amplitude attenuates between input and output nodes. Note that the pad capacitance Cp, capacitor Ca, and paired sub-capacitance Cs in the diagram correspond to the pad capacitances Cp1 to Cp4, capacitors Ca1 to Ca4, and paired sub-capacitances Cs1 to Cs4 in FIG. 3, respectively. Also, the input node "input" and the output node "output" correspond to the application terminals of the transmission pulse signals IN1 to IN4 and the application terminals of the reception pulse signals OUT1 to OUT4 in FIG. 3, respectively.

[0045] When the transmission pulse signal applied to the input node "input" rises from a low level (e.g., 0 V) ​​to a high level (5 V), a current flows from the input node "input" through the capacitor Ca and the pair of sub-capacitors Cs to the substrate node "sub2" or "sub3" (see the dashed arrow in the figure). Therefore, the reception pulse signal applied to the output node "output" is a signal obtained by capacitively dividing the transmission pulse signal. For this reason, the logic decision threshold for the reception pulse signal must be set to a low level (e.g., 0.425 V), which makes it susceptible to the influence of common-mode noise, which will be described later.

[0046] 5 is a diagram showing how potential fluctuations propagate between substrate nodes. For example, in a CMTI test performed on the signal transmission device 1, potential fluctuations (e.g., up to 150 V / ns) occurring at the substrate node sub1 (=GND) of the primary circuit system leak into the substrate node sub3 (=PGND) of the secondary circuit system. Therefore, measures to prevent erroneous detection of received pulse signals are essential.

[0047] 6 shows a test pattern for common-mode transient immunity (CMTI). The upper part of the diagram depicts the transmission pulse signal (corresponding to the transmission pulse signals IN1 to IN4 in FIG. 3) applied to the input node "input." The lower part of the diagram depicts the potential fluctuation (so-called common-mode noise) occurring at the substrate node "sub1."

[0048] In the signal transmission device 1 using the capacitive isolation method, the pulse edge of the transmission pulse signal applied to the input node "input" (and hence the pulse edge of the reception pulse signal applied to the output node "output") in Fig. 4 or 5 is detected as a trigger for switching the logic level of the output pulse signal OUTH (or OUTL). Therefore, in order to verify the common-mode transient immunity (CMTI), it is necessary to verify patterns A to D in this figure.

[0049] Pattern A is a case where the potential of the substrate node sub1 fluctuates while the potential of the input node input is stable. In this diagram, the substrate node sub1 rises from low level (0V) to high level (150V) during the high level period (5V) of the input node input, and also falls from high level (150V) to low level (0V) during the low level period (0V) of the input node input. In such a case, there is no problem with trigger detection.

[0050] Pattern B, like the previous pattern A, is a case where the potential of the substrate node sub1 fluctuates when the potential of the input node input is stable. In this diagram, the substrate node sub1 rises from low level (0V) to high level (150V) during the low level period (0V) of the input node input, and also falls from high level (150V) to low level (0V) during the high level period (5V) of the input node input. In such a case, there is no problem with trigger detection. This is the same as the previous pattern A.

[0051] Pattern C is a case where the potential fluctuation of the input node "input" and the potential fluctuation of the substrate node "sub1" occur simultaneously. In this diagram, the substrate node "sub1" falls from high level (150V) to low level (0V) at the timing when the input node "input" rises from low level (0V) to high level (5V), and the substrate node "sub1" rises from low level (0V) to high level (150V) at the timing when the input node "input" falls from high level (5V) to low level (0V). In such a case, the pulse edge of the received pulse signal applied to the output node "output" is drowned out by common mode noise, which may cause problems with trigger detection.

[0052] Pattern D, like the previous pattern C, is a case in which a potential fluctuation at input node "input" and a potential fluctuation at substrate node "sub1" occur simultaneously. In this diagram, at the same time that input node "input" rises from low level (0V) to high level (5V), substrate node "sub1" rises from low level (0V) to high level (150V), and at the same time that input node "input" falls from high level (5V) to low level (0V), substrate node "sub1" falls from high level (150V) to low level (0V). In such a case, the pulse edge of the received pulse signal applied to output node "output" is buried in common mode noise, which may interfere with trigger detection.

[0053] In the following, in view of the above verification, a new embodiment (example of a CMTI countermeasure) for improving common-mode transient immunity (CMTI) will be proposed.

[0054] 7 is a diagram showing a first embodiment for improving common-mode transient immunity (CMTI). The upper (left) section of the diagram depicts a transmission pulse signal INPUT and an inverted transmission pulse signal XINPUT without countermeasures, while the upper (right) section of the diagram depicts a reception pulse signal OUTPUT and an inverted reception pulse signal XOUTPUT without countermeasures. The lower (left) section of the diagram depicts the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT of the first embodiment, while the lower (right) section of the diagram depicts the reception pulse signal OUTPUT and the inverted reception pulse signal XOUTPUT of the first embodiment.

[0055] The transmission pulse signal INPUT corresponds to the transmission pulse signal IN1 or IN3 in Fig. 3. The inverted transmission pulse signal XINPUT corresponds to the transmission pulse signal IN2 or IN4 in Fig. 3.

[0056] The received pulse signal OUTPUT corresponds to the received pulse signal OUT1 or OUT3 in Fig. 3. The inverted received pulse signal XOUTPUT corresponds to the received pulse signal OUT2 or OUT4 in Fig. 3.

[0057] In the signal transmission device 1 using the capacitive insulation method, it is necessary to detect the pulse edges of the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT, and further the pulse edges of the reception pulse signal OUTPUT and the inverted reception pulse signal XOUTPUT.

[0058] However, as shown in the upper part of this figure, when the logic levels of the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are switched abruptly, the period during which the pulse edges of the reception pulse signal OUTPUT and the inverted reception pulse signal XOUTPUT can be detected (= the trigger pulse width) becomes very short.

[0059] Therefore, if common mode noise is superimposed at the timing when a pulse edge occurs in each of the received pulse signal OUTPUT and the inverted received pulse signal XOUTPUT, the pulse edges of each of the received pulse signal OUTPUT and the inverted received pulse signal XOUTPUT may be drowned out or buried by the common mode noise, which may interfere with trigger detection.

[0060] Therefore, in the first embodiment, as shown in the lower part of the figure, the logic levels of the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are gradually transitioned.

[0061] Applying this to the aforementioned Figure 3, it is preferable that the pulse transmission circuits TX1 to TX4 gradually transition the logic levels of the transmission pulse signals IN1 to IN4 that are transmitted to the subsequent capacitors Ca1 to Ca4 when the logic level of the input pulse signal IN switches.

[0062] By adopting the first embodiment, the period during which the pulse edges of the received pulse signal OUTPUT and the inverted received pulse signal XOUTPUT can be detected becomes longer (=the trigger pulse width becomes wider), making it less likely that common mode noise will cause malfunctions in trigger detection.

[0063] As a simple implementation method for the first embodiment, for example, it is conceivable to insert a resistor at the output terminal of each of the pulse transmitting circuits TX1 to TX4 and set the time constant τ to a large value.

[0064] However, even when the first embodiment is adopted, the potential fluctuations of the received pulse signal OUTPUT and the inverted received pulse signal XOUTPUT due to a single trigger are the same as those of the conventional embodiment. Therefore, if the common mode noise rises gradually over the same transition time as the transmitted pulse signal INPUT and the inverted transmitted pulse signal XINPUT, the signal with the larger potential fluctuation will prevail. Therefore, as before, the pulse edges of the received pulse signal OUTPUT and the inverted received pulse signal XOUTPUT may be drowned out or buried by the common mode noise, which may interfere with trigger detection.

[0065] In other words, it is difficult to deal with various signal patterns of common-mode noise simply by gradually transitioning the logic levels of the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT. Further consideration is needed to break away from this theory of probability.

[0066] 8 is a diagram for explaining the signal decomposition of common mode noise CMT. As a premise for the explanation, in this diagram, the potential fluctuation of the transmission pulse signal INPUT due to one trigger is 5 V / ns, while the potential fluctuation of the common mode noise CMT is up to 150 V / ns (= the maximum value of the specifications that must be met).

[0067] For example, consider a case where the common mode noise CMT rises slowly and its potential fluctuation is 150 V / 30 ns. In this case, the potential fluctuation per 1 ns is 5 V / ns, which is equivalent to the potential fluctuation of the transmission pulse signal INPUT due to one trigger.

[0068] Consider a case where the common mode noise CMT increases more slowly and its potential fluctuation is 150 V / 75 ns. In this case, the potential fluctuation per ns is 2 V / ns, which is smaller than the potential fluctuation of the transmission pulse signal INPUT due to a single trigger.

[0069] In view of this, it can be seen that by triggering the transmission pulse signal INPUT multiple times (5 V / ns x 30 times in this figure) over a period of 30 ns or more (preferably 40 ns to 90 ns), at least one of the multiple triggered pulse edges can be correctly detected, regardless of whether the potential fluctuation of the common mode noise CMT is steep or gradual.

[0070] The above operation will be described in detail below with reference to specific embodiments.

[0071] Second Embodiment Fig. 9 is a diagram showing a second embodiment for improving common-mode transient immunity (CMTI). The upper part (left side) of this diagram depicts the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT of the first embodiment (the lower part of Fig. 7) described above, while the upper part (right side) of this diagram depicts the reception pulse signal OUT and the inverted reception pulse signal XOUTPUT of the first embodiment. The middle and lower parts (left sides) of this diagram depict the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT of the second embodiment, respectively, while the middle and lower parts (right sides) of this diagram depict the reception pulse signal OUTPUT and the inverted reception pulse signal XOUTPUT of the second embodiment, respectively.

[0072] In the second embodiment, as shown in the middle and bottom sections of the figure, while the logical levels of the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are gradually transitioned, the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are each triggered multiple times so that the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are repeatedly pulled up and down.

[0073] That is, on-off keying (OOK) of the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT is performed. This operation provides multiple trigger detection timings. Therefore, it is possible to more reliably transmit each of the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT to the next stage.

[0074] Furthermore, by triggering the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT multiple times over a predetermined period (e.g., 30 ns or more), trigger detection is less likely to be hindered regardless of whether the potential fluctuation of the common mode noise CMT is steep or gradual, thereby making it possible to improve common mode transient immunity (CMTI).

[0075] When the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are raised from a low level (0 V) to a high level (5 V), the amount of reduction for each trigger can be set to be equal to or less than the amount of increase. When the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are lowered from a high level (5 V) to a low level (0 V), the amount of increase for each trigger can be set to be equal to or less than the amount of reduction.

[0076] Referring to the transmission pulse signal INPUT in the middle of the figure, when rising from a low level (0 V) to a high level (5 V), the amount of increase for each trigger is set to +2 V, while the amount of decrease for each trigger is set to -1 V. Therefore, the transmission pulse signal INPUT repeats potential fluctuations in which it rises by 2 V and falls by 1 V for each trigger, and finally transitions from a low level (0 V) to a high level (5 V) with four triggers.

[0077] Conversely, when falling from a high level (5 V) to a low level (0 V), the amount of pull-up for each trigger is set to +1 V, while the amount of pull-down for each trigger is set to -2 V. Therefore, the transmission pulse signal INPUT repeats potential fluctuations in which it drops by 2 V and rises by 1 V for each trigger, and finally transitions from a high level (5 V) to a low level (0 V) with four triggers.

[0078] According to such a setting, the potential fluctuations of the received pulse signal OUTPUT and the inverted received pulse signal XOUTPUT are accumulated, and therefore it is possible to artificially increase the trigger detection level.

[0079] Referring to the transmission pulse signal INPUT in the lower part of the figure, when rising from a low level (0 V) to a high level (5 V), the amount of increase for each trigger is set to +3 V, while the amount of decrease for each trigger is set to -2 V. Therefore, the transmission pulse signal INPUT repeats potential fluctuations, rising by 3 V and falling by 2 V for each trigger, and finally transitions from a low level (0 V) to a high level (5 V) with three triggers.

[0080] Conversely, when falling from a high level (5 V) to a low level (0 V), the amount of pull-up for each trigger is set to +2 V, while the amount of pull-down for each trigger is set to -3 V. Therefore, the transmission pulse signal INPUT repeats potential fluctuations, dropping by 3 V and rising by 2 V for each trigger, and finally transitions from a high level (5 V) to a low level (0 V) with three triggers.

[0081] In the middle part of the figure, the trigger interval tr is constant, whereas in the bottom part of the figure, the trigger interval tr is changed (tr → 2tr → 4tr). That is, the slopes (frequency components) of the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are changed for each trigger.

[0082] Looking at the rising edge of the transmission pulse signal INPUT, the slope of the first pulse is +3V / tr, the slope of the second pulse is 1 / 2 of the slope of the first pulse (=+3V / 2tr), and the slope of the third pulse is 1 / 4 of the slope of the first pulse (=+4V / 4tr).

[0083] With such settings, even if the transition time of the common mode noise CMT is the same, it is possible to prevent malfunction of trigger detection due to differences in the slopes (frequency components) of the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT.

[0084] Note that, when one focuses on the period during which the pulse edges of the received pulse signal OUTPUT and the inverted received pulse signal XOUTPUT can be detected, it is clear that the period is longer in the middle than in the upper part of the figure, and is even longer in the lower part.

[0085] Next, two different setting examples will be given and considered for trigger settings when the trigger interval is constant.

[0086] First, in a first setting example, the amount of pull-up for each trigger is set to +2 V, the amount of pull-down for each trigger is set to -1 V, and the trigger interval is set to 30 ns. In this case, the transmission pulse signal INPUT is triggered four times over a period of 90 ns.

[0087] In this case, the potential fluctuation of the common mode noise CMT is 150V / 90ns (=1.66V / ns). Therefore, for each trigger boost (+2V), a difference of 0.33V remains as the effective transmission pulse signal INPUT. As a result, a trigger pulse of approximately 26mV is generated in the reception pulse signal OUTPUT, and this is transmitted to the next stage.

[0088] In this way, if the difference between the amount of increase and the amount of decrease per trigger (= the amount of potential change per trigger) is set relatively large, the number of triggers required to transition the transmission pulse signal INPUT from low level (0 V) to high level (5 V) will be reduced. Therefore, in order to deal with common mode noise CMT, which has a gradual potential change, a sufficient trigger interval must be ensured. As a result, the time required to complete multiple trigger transmissions will be longer. In addition, it is also necessary to increase the accuracy of the trigger interval setting.

[0089] Next, in a second setting example, the amount of pull-up for each trigger is set to +4 V, the amount of pull-down for each trigger is set to -3.9 V, and the trigger interval is set to 4 ns. In this case, the transmission pulse signal INPUT is triggered 11 times over a period of 40 ns.

[0090] In this case, the potential fluctuation of the common mode noise CMT is 150V / 40ns (=3.75V / ns). Therefore, for the amount of boost per trigger (+4V), a difference of 0.25V remains as the effective transmission pulse signal INPUT. As a result, a trigger pulse of approximately 20mV is generated in the reception pulse signal OUTPUT, and this is transmitted to the next stage.

[0091] In this way, when the difference between the amount of increase and the amount of decrease per trigger (= the amount of potential change per trigger) is set relatively small, the number of triggers required to transition the transmission pulse signal INPUT from low level (0 V) to high level (5 V) increases. Therefore, compared to the first setting example described above, the trigger interval can be shortened, and the time required to complete multiple trigger transmissions is shortened. However, because the difference between the amount of increase and the amount of decrease per trigger is small, care must be taken to avoid erroneous detection of unintended logic inversion of the transmission pulse signal INPUT.

[0092] 10 is a diagram showing a third embodiment for improving common-mode transient immunity (CMTI). The left side of the diagram shows a transmission pulse signal INPUT and an inverted transmission pulse signal XINPUT of the third embodiment, and the right side of the diagram shows a reception pulse signal OUT and an inverted reception pulse signal XOUTPUT of the third embodiment.

[0093] In the third embodiment, as in the previous second embodiment (FIG. 9), while the logic levels of the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are gradually transitioned, the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are each triggered multiple times so that the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are repeatedly pulled up and pulled down.

[0094] In particular, in the third embodiment, following the first setting example described above, the amount of pull-up for each trigger is set to +2 V, the amount of pull-down for each trigger is set to -1 V, and the trigger interval tx is set to 30 ns. Therefore, the transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT are each triggered four times over a period of 90 ns (=3 tx). The transmission pulse signal INPUT and the inverted transmission pulse signal XINPUT each have a stepped waveform as shown in the figure.

[0095] With this setting, as described above, the potential fluctuations of the received pulse signal OUTPUT and the inverted received pulse signal XOUTPUT are accumulated, and therefore it is possible to artificially increase the trigger detection level.

[0096] 11 is a diagram showing an example of the configuration of the pulse transmission circuit TX. The pulse transmission circuit TX* (for example, *=1, 2, 3, 4) of this configuration example includes a logic 11 and a DAC (digital-to-analog converter) 12.

[0097] The logic 11 receives an input pulse signal IN and generates an n-bit (for example, n=5) digital signal SD.

[0098] The DAC 12 sets the analog value of the transmission pulse signal IN* in accordance with the n-bit digital signal SD.

[0099] 12 is a diagram showing an example of the configuration of the DAC 12. The DAC 12 in this example is an R-2R ladder type with 5-bit resolution, and includes resistors 120 to 123 (each with a resistance value of R), resistors 124 to 129 (each with a resistance value of 2R), and selectors 12A to 12E.

[0100] A first end of resistor 120 is connected to a first end of resistors 124 and 125. A second end of resistor 120 is connected to a first end of resistors 121 and 126. A second end of resistor 121 is connected to a first end of resistors 122 and 127. A second end of resistor 122 is connected to a first end of resistors 123 and 128. A second end of resistor 123 and a first end of resistor 129 are connected to the output terminal of the transmit pulse signal IN*.

[0101] The second terminal of resistor 124 is connected to the ground terminal. The second terminal of resistor 125 is connected to the common terminal of selector 12A. The second terminal of resistor 126 is connected to the common terminal of selector 12B. The second terminal of resistor 127 is connected to the common terminal of selector 12C. The second terminal of resistor 128 is connected to the common terminal of selector 12D. The second terminal of resistor 129 is connected to the common terminal of selector 12E.

[0102] The first selection terminal (0) of each of the selectors 12A to 12E is connected to the ground terminal. The second selection terminal (1) of each of the selectors 12A to 12E is connected to the power supply terminal (= the terminal to which the power supply voltage VDD is applied). Note that each of the selectors 12A to 12E switches between connecting the common terminal and the first selection terminal (0) or connecting the common terminal and the second selection terminal (1) in accordance with the digital signal SD.

[0103] FIG. 13 is a diagram showing the relationship between the selection states of the selectors 12A to 12E and the DAC output value (=transmission pulse signal IN*).

[0104] As shown in the first row, when the common terminals of all the selectors 12A to 12E are connected to the first selection terminals (0), the transmission pulse signal IN* becomes 0 V. Hereinafter, this state will be referred to as the "first state."

[0105] As shown in the second row, when the common terminals of the selectors 12A to 12C are connected to the second selection terminal (1), and the common terminals of the selectors 12D and 12E are connected to the first selection terminal (0), the transmission pulse signal IN* becomes (7 / 32)×VDD (for example, IN*=1.060 V). Hereinafter, this state will be referred to as the "second state."

[0106] As shown in the third row, when the common terminals of the selectors 12A, 12C, and 12D are connected to the second selection terminal (1), and the common terminals of the selectors 12B and 12E are connected to the first selection terminal (0), the transmission pulse signal IN* becomes (13 / 32)×VDD (for example, IN*=1.969 V). Hereinafter, this state will be referred to as the "third state."

[0107] As shown in the fourth row, when the common terminals of the selectors 12A, 12B, and 12E are connected to the second selection terminal (1), and the common terminals of the selectors 12C and 12D are connected to the first selection terminal (0), the transmission pulse signal IN* becomes (19 / 32)×VDD (for example, IN*=2.878 V). Hereinafter, this state will be referred to as the "fourth state."

[0108] As shown in the fifth row, when the common terminals of the selectors 12B, 12D, and 12E are connected to the second selection terminal (1), and the common terminals of the selectors 12A and 12C are connected to the first selection terminal (0), the transmission pulse signal IN* becomes (25 / 32)×VDD (for example, IN*=3.939 V). Hereinafter, this state will be referred to as the "fifth state."

[0109] As shown in the sixth row, when the common terminals and second selection terminals (1) of all the selectors 12A to 12E are connected, the transmission pulse signal IN* becomes (31 / 32)×VDD (for example, IN*=4.848 V). Hereinafter, this state will be referred to as the "sixth state."

[0110] For example, as shown in FIG. 10 above, when the transmission pulse signal INPUT (=transmission pulse signal IN*) is switched in a stepwise manner, the digital signal SD may be generated so that the selection states of the selectors 12A to 12E transition in the following order: first state (0 V) → third state (2 V) → second state (1 V, tx held) → fourth state (3 V) → third state (2 V, tx held) → fifth state (4 V) → fourth state (3 V, tx held) → fifth state (5 V).

[0111] The slope of the transmission pulse signal IN* is determined by the resistance values ​​(magnitude of R) of the resistors 120 to 129 and the pad capacitance Cp. When adjusting the slope of the transmission pulse signal IN*, adjustment of the switching bits and the like is not necessarily required; it is sufficient to simply adjust the resistance values ​​of the resistors 120 to 129 as appropriate.

[0112] 14 is a diagram showing an example of a received pulse signal OUTPUT (solid line) and an inverted received pulse signal XOUTPUT (dashed line). The received pulse signal OUTPUT corresponds to the received pulse signal OUT1 or OUT3 in FIG. 3. The inverted received pulse signal XOUTPUT corresponds to the received pulse signal OUT2 or OUT4 in FIG. 3.

[0113] By triggering the transmission pulse signal IN* multiple times, the reception pulse signal OUTPUT rises in a step-like manner. The resistance value of the DAC 12 may be adjusted so that the slopes d1 to d4 for each trigger are equal, or may be adjusted so that the slopes are different.

[0114] <Summary> The various embodiments described above will be summarized below.

[0115] For example, the pulse transmission circuit disclosed in this specification is incorporated into a signal transmission device using a capacitive isolation method, and is configured (first configuration) to gradually transition the logic level of the transmission pulse signal transmitted to the downstream capacitor when the logic level of the input pulse signal switches.

[0116] The pulse transmission circuit according to the first configuration may be configured (second configuration) to trigger the transmission pulse signal multiple times so as to repeatedly raise and lower the transmission pulse signal while gradually transitioning the logic level of the transmission pulse signal.

[0117] The pulse transmission circuit according to the second configuration may be configured (third configuration) such that when the transmission pulse signal rises from a low level to a high level, the amount of reduction for each trigger is set to be equal to or less than the amount of reduction, and when the transmission pulse signal falls from a high level to a low level, the amount of reduction for each trigger is set to be equal to or less than the amount of reduction.

[0118] The pulse transmission circuit according to the third configuration may be configured to change the gradient of the transmission pulse signal for each trigger (fourth configuration).

[0119] The pulse transmission circuit according to any one of the second to fourth configurations may be configured (fifth configuration) to include logic configured to receive the input pulse signal and generate a digital signal, and a DAC configured to set an analog value of the transmission pulse signal in accordance with the digital signal.

[0120] In the pulse transmission circuit according to the fifth configuration, the DAC may be configured as an R-2R ladder type (sixth configuration).

[0121] Furthermore, for example, the signal transmission device disclosed in this specification has a configuration (seventh configuration) that includes a pulse transmitting circuit having any of the first to sixth configurations that is provided in a primary circuit system and configured to generate the transmission pulse signal, the capacitor that is provided between the primary circuit system and a secondary circuit system and configured to output a reception pulse signal corresponding to the transmission pulse signal, and a pulse receiving circuit that is provided in the secondary circuit system and configured to output an output pulse signal corresponding to the reception pulse signal.

[0122] The signal transmission device according to the seventh configuration may be configured (eighth configuration) in which a first chip configured to integrate circuit elements of the primary circuit system and a second chip configured to integrate circuit elements of the secondary circuit system are sealed in a single package.

[0123] In the signal transmission device of the eighth configuration, the pulse transmitting circuit may be integrated into the first chip, and the capacitor and the pulse receiving circuit may be integrated into the second chip (ninth configuration).

[0124] Furthermore, for example, the electronic device disclosed in this specification may be configured (tenth configuration) to include a signal transmission device having any of the seventh to ninth configurations above and a load configured to receive the output pulse signal.

[0125] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0126] 1 Signal transmission device 10 Controller chip (first chip) 11 Logic 12 DAC 120 to 129 Resistors 12A to 12E Selectors 20, 20H, 20L Driver chip (second chip) 30 Transformer A Electronic device C1, C2, Ca, Ca1 to Ca4 Capacitor Cp, Cp1 to Cp4 Pad capacitance Cs, Cs1 to Cs4 Pair capacitance HS Upper switch input Input node LS Lower switch output Output node RX, RX1, RX2 Pulse receiving circuit sub1 to sub3 Substrate node T11 to T14, T21 to T24 Pad TX, TX1 to TX4 Pulse transmitting circuit W1 to W4 Wire

Claims

1. A pulse transmission circuit that is incorporated into a signal transmission device using a capacitive isolation method, and that gently transitions the logic level of a transmission pulse signal transmitted to a downstream capacitor when the logic level of an input pulse signal switches.

2. 2. The pulse transmitting circuit according to claim 1, wherein the transmission pulse signal is triggered multiple times so that the transmission pulse signal is repeatedly pulled up and pulled down while the logic level of the transmission pulse signal is gradually transitioned.

3. 3. The pulse transmission circuit according to claim 2, wherein when the transmission pulse signal rises from a low level to a high level, the amount of pull-down for each trigger is set to be equal to or less than the amount of pull-up, and when the transmission pulse signal falls from a high level to a low level, the amount of pull-up for each trigger is set to be equal to or less than the amount of pull-down.

4. 4. The pulse transmission circuit according to claim 3, wherein the slope of the transmission pulse signal is changed for each trigger.

5. logic configured to receive the input pulse signal and generate a digital signal; a DAC configured to set an analog value of the transmit pulse signal in response to the digital signal; The pulse transmission circuit of claim 2 .

6. 6. The pulse transmission circuit according to claim 5, wherein the DAC is an R-2R ladder type.

7. The pulse transmission circuit according to any one of claims 1 to 6, which is provided in a primary circuit system and configured to generate the transmission pulse signal; the capacitor provided between the primary circuit system and the secondary circuit system and configured to output a reception pulse signal corresponding to the transmission pulse signal; a pulse receiving circuit provided in the secondary circuit system and configured to output an output pulse signal corresponding to the received pulse signal; A signal transmission device comprising:

8. a first chip configured to integrate circuit elements of the primary circuit system; a second chip configured to integrate circuit elements of the secondary circuit system; The signal transmission device according to claim 7 , wherein the first and second electrodes are sealed in a single package.

9. the pulse transmitting circuit is integrated into the first chip; the capacitor and the pulse receiving circuit are integrated into the second chip; The signal transmission device according to claim 8.

10. A signal transmission device according to claim 7; a load configured to receive the output pulse signal; An electronic device comprising: