Semiconductor memory device

Abstract

The present invention is characterized in that, in a dynamic flash memory having a semiconductor parent p layer 1, an n+ layer 2 that is extended to one side, an n+ layer 3 that is adjacent to the p layer 1 on the opposite side, a first gate conductor layer 5 at which part of the p layer 1 is coated with a gate insulator layer 4 and which furthermore is adjacent thereto, and a second gate conductor layer 7 at which part of the p layer 1 is coated with a gate insulator layer 6 adjacent to the gate insulator layer 4 and which is electrically isolated from a gate electrode 5, the n+ layer 2, the n+ layer 3, and the gate conductor layers 5, 7 are connected to a source line, a bit line, a word line, and a plate line, and in that, during deletion in the memory, a voltage applied to terminals is normally 0 V or higher such that, e.g., 2 V is applied to the plate line and 0.6 V is applied to the bit line.

Description

[Technical field]

[0001] The present invention relates to semiconductor memory devices. [Background technology]

[0002] In recent years, in the development of LSI (Large Scale Integration) technology, there is a demand for memory elements with higher integration, higher performance, lower power consumption, and higher functionality.

[0003] Memory elements are becoming increasingly dense and highly functional. Examples include DRAMs (Dynamic Random Access Memories, see Non-Patent Document 2) that use SGTs (Surrounding Gate Transistors, see Patent Document 1 and Non-Patent Document 1) as selection transistors and connect a capacitor, PCMs (Phase Change Memories, see Non-Patent Document 3) that connect a resistance change element, RRAMs (Resistive Random Access Memories, see Non-Patent Document 4), and MRAMs (Magneto-resistive Random Access Memories, see Non-Patent Document 5) that change resistance by changing the direction of magnetic spins using a current.

[0004] There are also DRAM memory cells (see Non-Patent Documents 6 to 10) that are composed of a single MOS transistor without a capacitor. For example, a current between the source and drain of an N-channel MOS transistor generates holes and electrons in the channel due to impact ionization, and some or all of the holes are retained in the channel to write logical memory data "1". Then, the holes are removed from the channel to write logical memory data "0". In this memory cell, the reduction in the operating margin caused by the floating body channel voltage fluctuation is improved, and the signal stored in the channel is Career The problem is how to improve the degradation of data retention characteristics caused by the removal of a portion of the hole group.

[0005] There is also a Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in the SOI layer (see, for example, Patent Documents 2 and 3 and Non-Patent Document 11). In these elements, the N + The layer is formed in contact with the insulating layer on the substrate side. In this memory cell, the group of holes, which is the signal charge, is stored in the channel of one MOS transistor, so just like the memory cell consisting of one MOS transistor described above, there is an issue of improving the decrease in the operating margin, or improving the decrease in data retention characteristics caused by the removal of part of the group of holes, which is the signal charge stored in the channel.

[0006] There is also a memory that does not have a capacitor and is composed of MOS transistors, as shown in FIG. 4 (see Patent Document 2 and Non-Patent Document 12). As shown in FIG. 4(a), a floating body semiconductor body 102 is provided on a SiO2 layer 101 of an SOI substrate. At both ends of the floating body semiconductor body 102, an n+ layer 103 that is connected to a source line SL and an n+ layer 104 that is connected to a bit line BL are provided. n A + layer 104 is provided. A first gate insulating layer 109a is connected to the n+ layer 103 and covers the floating body semiconductor body 102, and a second gate insulating layer 109b is connected to the n+ layer 104 and covers the floating body semiconductor body 102. A first gate conductor layer 105a is connected to the plate line PL over the first gate insulating layer 109a, and a second gate conductor layer 105b is connected to the word line WL over the second gate insulating layer 109b. An insulating layer 110 is provided between the first gate conductor layer 105a and the second gate conductor layer 105b. This forms a memory cell 111 of the DFM. The source line SL may be connected to the n+ layer 104, and the bit line BL may be connected to the n+ layer 103.

[0007] 4(a), for example, zero voltage is applied to the n+ layer 103 and a positive voltage is applied to the n+ layer 104, so that the first N-channel MOS transistor region made of the floating body semiconductor body 102 surrounded by the first gate conductor layer 105a operates in the saturation region, and the second N-channel MOS transistor region made of the floating body semiconductor body 102 surrounded by the second gate conductor layer 105b operates in the linear region. As a result, there is no pinch-off point in the second N-channel MOS transistor region, and the second gate insulating layer 109 b An inversion layer 107b is formed on the entire surface in contact with the first N-channel MOS transistor region. The inversion layer 107b formed under the second gate conductor layer 105b connected to the word line WL acts as a substantial drain of the first N-channel MOS transistor region. As a result, the electric field becomes maximum at the boundary region of the channel region between the first N-channel MOS transistor region and the second N-channel MOS transistor region, and impact ionization occurs in this region. Then, as shown in FIG. 4(b), the electrons among the electron-hole group generated by the impact ionization are removed from the floating body semiconductor body 102, and a part or all of the hole group 106 is held in the floating body semiconductor body 102, thereby performing a memory write operation.

[0008] Then, as shown in FIG. 4(c), for example, a positive voltage is applied to the plate line PL, a zero voltage is applied to the word line WL and the bit line BL, and a negative voltage is applied to the source line SL, to remove the hole group 106 from the floating body semiconductor matrix 102, and an erase operation is performed. This state becomes logical storage data "0". Then, in data read, the voltage applied to the first gate conductor layer 105a connected to the plate line PL is set to be higher than the threshold voltage when the logical storage data is "1" and lower than the threshold voltage when the logical storage data is "0", so that a characteristic is obtained in which no current flows even if the voltage of the word line WL is increased when reading logical storage data "0", as shown in FIG. 4(d). This characteristic allows a significant expansion of the operating margin compared to memory cells. In this memory cell, the channels of the first and second N-channel MOS transistor regions, whose gates are the first gate conductor layer 105a connected to the plate line PL and the second gate conductor layer 105b connected to the word line WL, are connected by the floating body semiconductor body 102, so that the voltage fluctuation of the floating body semiconductor body 102 when a selection pulse voltage is applied to the word line WL is greatly suppressed. This greatly improves the problem of the decrease in the operating margin in the memory cell described above, or the decrease in data retention characteristics due to the removal of a part of the hole group, which is the signal charge accumulated in the channel. Further characteristic improvements are required for this memory element in the future. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2-188966 [Patent Document 2] US2008 / 0137394 A1 [Patent Document 3] US2003 / 0111681 A1 [Patent Document 4] Patent No. 7057032 [Non-patent literature]

[0010]

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[0011] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a method for stably erasing memory information from a dynamic flash memory, which is a memory device. [Means for solving the problem]

[0012] In order to achieve the above object, a memory device using a semiconductor device according to the present invention comprises: A semiconductor body extending horizontally or vertically on a substrate; A first impurity connected to both ends of the semiconductor body region and the second impurity region and, a first gate insulating layer covering the semiconductor body; a first gate conductor layer overlying the first gate insulating layer; a second gate insulating layer connected to the first gate insulating layer and covering the semiconductor body; a second gate conductor layer covering the second gate insulating layer without contacting the first gate conductor layer, The first impurity region and the second impurity region a voltage is applied so that a potential difference is created between the first gate conductor layer and the second gate conductor layer, and a voltage between 0V and a threshold voltage, including 0V, is applied to one of the first gate conductor layer and the second gate conductor layer, and a voltage of the same polarity and having an absolute value equal to or greater than the absolute value of the threshold voltage is applied to the other gate conductor layer, thereby reducing either holes or electrons, which are majority carriers remaining in the semiconductor body, and performing a memory erase operation. This is characterized by the above (first invention).

[0013] In the first aspect of the present invention, the first impurity region A source line is connected to the second impurity region a bit line is connected to the source line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line and the other is connected to a plate line, and voltages are applied to each of the source line, the bit line, the plate line and the word line to perform a memory write operation, a memory read operation and the memory erase operation, thereby operating the dynamic flash memory (a second invention).

[0014] In the second invention, when the majority carriers of the semiconductor body are holes during the erase operation of the dynamic flash memory, the first impurity region and the second impurity region The voltage applied to the first gate conductor layer and the second gate conductor layer is 0V or a positive potential (third invention).

[0015] In the second invention, in the erase operation of the dynamic flash memory, when the majority carriers of the semiconductor body are electrons, the first impurity region and the second impurity region The voltage applied to the first gate conductor layer and the second gate conductor layer is 0V or a negative potential (fourth invention).

[0016] In the second invention, either the source line or the bit line is at 0V during the memory erase operation of the dynamic flash memory (a fifth invention).

[0017] In the second invention, in the memory write operation of the dynamic flash memory, a voltage having an absolute value equal to or greater than the absolute value of the threshold voltage of a first MOS transistor region formed of the first gate insulating layer and the first gate conductor layer and having the same polarity as the threshold voltage is applied to the word line, a voltage having an absolute value equal to or greater than the absolute value of the threshold voltage of a second MOS transistor region formed of the second gate insulating layer and the second gate conductor layer and having the same polarity as the threshold voltage is applied to the plate line, a voltage is applied to the bit line such that the maximum electric field of the semiconductor body causes impact ionization during writing, 0V is applied to the source line, and region and the second impurity region An impact ionization phenomenon is generated by passing a current between the first impurity and the semiconductor body, and a group of electrons and a group of holes are ionized into the semiconductor body and the first impurity. regionand among the generated electron group and hole group, a part or all of either the electron group or the hole group, which are majority carriers in the semiconductor body, are allowed to remain in the semiconductor body (the sixth invention).

[0018] In the above second invention, the absolute value of the current flowing through the bit line during the memory erase operation of the dynamic flash memory is lower than the absolute value of the current flowing through the bit line during the memory write operation of the dynamic flash memory (seventh invention).

[0019] In the above-mentioned second invention, the voltages applied to the plate line, the word line, the source line, and the bit line during the memory write operation and the memory erase operation of the dynamic flash memory are 0V or all of the same polarity (8th invention). [Brief description of the drawings]

[0020] [Figure 1A] 1 is a diagram showing a cross-sectional structure of a memory device using a semiconductor element according to a first embodiment. [Figure 1B] 1 is a diagram showing a cross-sectional structure of a memory device using a semiconductor element according to a first embodiment. [Diagram 2] 4A to 4C are diagrams for explaining accumulation of hole carries and a cell current during a write operation of the memory device using the semiconductor element according to the first embodiment. [Diagram 3] 4A to 4C are diagrams illustrating an erase operation of the memory device using the semiconductor device according to the first embodiment. [Figure 4] 1A and 1B are diagrams illustrating the cross-sectional structure and operation of a conventional dynamic flash memory device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the structure, driving method, and behavior of stored carriers of a memory device using semiconductor elements according to one embodiment of the present invention will be described with reference to the drawings.

[0022] (First embodiment) The structure and operation mechanism of a memory cell using a semiconductor element according to a first embodiment of the present invention will be described with reference to Figures 1 to 3 (hereinafter, Figures 1A and 1B will be collectively referred to as Figure 1). The cell structure of a memory using a semiconductor element according to this embodiment will be described with reference to Figure 1. The write mechanism and carrier behavior of a memory cell using a semiconductor element will be described with reference to Figure 2, and the data erase mechanism will be described with reference to Figure 3.

[0023] FIG. 1 shows a memory using a semiconductor element according to a first embodiment of the present invention. cell FIG. 1 shows a structure of the above-mentioned. (a) in FIG. 1 shows a plan view, and (b) shows a vertical cross-sectional view taken along line X-X' in (a). (c) shows a cross-sectional view taken along line Y1-Y1', and (d) shows an additional example of the cross-sectional view taken along line Y1-Y1' in (c). (e) shows a cross-sectional view taken along line Y2-Y2' in (a), and (f) shows an additional example of the cross-sectional view taken along line Y2-Y2' in (e). The structure of (c) can be replaced with a structure like (d), and the structure of (e) can be replaced with a structure like (f).

[0024] On a substrate 20 (an example of the "substrate" in the claims), there is a p-layer 1 (an example of the "semiconductor body" in the claims), which is a silicon semiconductor body having a p-type or i-type (intrinsic) conductivity type containing acceptor impurities. On one side of the p-layer 1 in the horizontal direction, there is an n+ layer 2 (hereinafter, a semiconductor region containing a high concentration of donor impurities will be referred to as an "n+ layer") ("first impurity layer" in the claims). region On the opposite side of the n+ layer 2 is an n+ layer 3 (an example of the "second impurity regionA gate insulating layer 4 (an example of the "first gate insulating layer" in the claims) covers the p layer 1 and is in contact with or in the vicinity of the n+ layer 2. A first gate conductor layer 5 (an example of the "first gate conductor layer" in the claims) is in the vicinity of the n+ layer 2, surrounding a part or the whole of the gate insulating layer 4. A gate insulating layer 6 (an example of the "second gate insulating layer" in the claims) is formed on a part of the surface of the p layer 1 and in contact with or in the vicinity of the n+ layer 3. A second gate conductor layer 7 (an example of the "second gate conductor layer" in the claims) surrounds the gate insulating layer 6 and is in the vicinity of the n+ layer 3, without contacting the first gate conductor layer 5. As a result, the p layer 1, the n+ layer 2, the n+ layer 3, the gate insulating layer 4, the first gate conductor layer 5, the gate insulating layer 6, and the second gate conductor layer 7 form a cell of a dynamic flash memory.

[0025] Furthermore, the n+ layer 2 is connected to a source line SL (an example of the “source line” in the claims) which is a wiring conductor. 1. The gate conductor layer 5 is connected to a word line WL (an example of the word line in the claims) which is a wiring conductor. Second The gate conductor layer 7 is connected to a plate line PL (an example of a "plate line" in the claims) which is a wiring conductor. The n+ layer 3 is connected to a bit line BL (an example of a "bit line" in the claims) which is a wiring conductor. The dynamic flash memory is operated by manipulating the potentials of the source line, bit line, plate line, and word line. In the memory device of this embodiment, the above-mentioned multiple dynamic flash memory cells are arranged in a multiple two-dimensional or three-dimensional manner.

[0026] As shown in Figure 1(d), SecondA dynamic flash memory can also be configured with a structure in which the gate conductor layer 7 and the gate insulating layer 6 are divided above and below the p layer 1 and surround only a portion of the p layer 1. Also, as shown in (f) of FIG. 1, a dynamic flash memory can also be configured with a structure in which the first gate conductor layer 5 and the gate insulating layer 4 are divided above and below the p layer 1 and surround only a portion of the p layer 1.

[0027] Moreover, for the gate insulating layers 4 and 6, any insulating film used in a normal MOS process, such as a SiO2 film, a SiON film, a HfSiON film, or a laminated film of SiO2 / SiN, can be used.

[0028] In FIG. 1, the p-layer 1 is a p-type semiconductor, but the impurity concentration may have a profile. The n+ layer 2 and the n+ layer 3 may have an impurity concentration profile. t ly Doped Drain).

[0029] In addition, when n+ layer 2 and n+ layer 3 are formed from p+ layers in which holes are the majority carriers (hereinafter, a semiconductor region containing a high concentration of acceptor impurities will be referred to as a "p+ layer"), if p layer 1 is an n-type semiconductor, the dynamic flash memory will operate by using electrons as the write carriers.

[0030] Furthermore, as long as the first gate conductor layer 5 can change the potential of a portion of the memory cell via the gate insulating layer 4, and the second gate conductor layer 7 can change the potential of a portion of the memory cell via the gate insulating layer 6, they may be made of metals such as W, Pd, Ru, Al, TiN, TaN, and WN, metal nitrides, or alloys thereof (including silicides), such as a layered structure such as TiN / W / TaN, or may be made of a highly doped semiconductor.

[0031] In addition, in FIG. 1A, the memory cell has been described as having a rectangular cross section perpendicular to the plane of the page, but it may have a trapezoidal or polygonal shape, or the memory cell itself may have a cylindrical shape.

[0032] In addition, in Fig. 1(d), the second gate conductor layer 7 is present in two places on both the top and bottom of the p-layer 1, but the dynamic flash memory can operate even if only one of them is present. This is also true for the first gate conductor layer 5.

[0033] In addition, in FIG. 1, the first gate conductor layer 5 and the second gate conductor layer 7 are shown as being integral with each other in the memory cell, but they may be divided in the horizontal or vertical direction. The conductive layer is It's okay if it is. The dynamic flash memory can also be operated by dividing the first gate conductor layer 5, sandwiching the second gate conductor layer 7 between one side adjacent to the n+ layer 2 and the other side adjacent to the n+ layer 3 connected to the bit line BL. The same is true for the first gate conductor layer 5 and the second gate conductor layer 7. Also, the first gate conductor layer 5 and the second gate conductor layer 7 may be formed of different conductor material layers, and the gate insulating layer 4 and the gate insulating layer 6 may be formed of different insulating material layers.

[0034] The carrier behavior, accumulation, and cell current during a write operation of the dynamic flash memory according to the first embodiment of the present invention will be described with reference to Fig. 2. The first MOS transistor region having the portion with the first gate conductor layer 5 as the gate is shown as WL-FET (field effect MOS transistor region connected to the word line WL), and the second MOS transistor region having the second gate conductor layer 7 is shown as PL-FET (field effect MOS transistor region connected to the plate line PL). The threshold voltage of the WL-FET is shown as Vth-WL, and the threshold voltage of the PL-FET is shown as Vth-PL.

[0035] As shown in FIG. 2(a), first, the majority carriers in the n+ layer 2 and n+ layer 3 are electrons, and for example, n+ poly (hereinafter, poly Si containing high concentration of donor impurities is referred to as "n+ poly") is used for the first gate conductor layer 5 connected to the word line WL and the second gate conductor layer 7 connected to the plate line PL, and a p-type semiconductor is used for the p-layer 1. In dynamic flash memory, when writing, it is necessary to cause sufficient impact ionization in the WL-FET or PL-FET. To satisfy this, the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL are, for example, to apply a voltage 10% or more higher than the higher voltage of Vth-PL to the plate line, to form an inversion layer on a part or the entire surface of the interface between the second gate insulating layer 6 of the PL-FET and the p-layer 1, to transmit the potential of the bit line to the entire channel of the PL-FET, and, for example, to apply a voltage higher than WL-Vth to the word line so that a current flows from the bit line to the source line. In addition, the voltage applied to the bit line is set to a maximum electric field of, for example, 10 5 It is necessary to apply a voltage of at least 100 V / cm.

[0036] Based on the above, an example of the voltage applied when writing to the memory is described below. In this example, when Vth-WL=Vth-PL=0.8V, for example, 0V is input to the source line SL connected to the n+ layer 2, and for example, 1.0V is input to the bit line BL connected to the n+ layer 3. Second For example, 1.5 V is input to the plate line PL connected to the gate conductor layer 7, and 1. A voltage of, for example, 1.2 V is input to the gate conductor layer 5 .

[0037] In this voltage application state, the gate insulating layer 6 An inversion layer 14b is formed over the entire surface directly below the gate insulating layer 4. An inversion layer 14a is formed in a portion directly below the gate insulating layer 4. A pinch-off point 15 where the inversion layer 14a disappears exists directly below the gate insulating layer 4, and the electric field becomes maximum at this point. In this example, the maximum electric field is 4×10 5V / cm. Then, electrons flow from n+ layer 2 toward n+ layer 3. As a result, impact ionization occurs in the region near pinch-off point 15. Due to this impact ionization, electrons accelerated from n+ layer 2 connected to source line SL toward n+ layer 3 connected to bit line BL collide with the Si lattice, and electron-hole pairs are generated by the kinetic energy. Some of the generated electrons are 1. Some of it flows into the gate conductor layer 5, but most of it flows into the n+ layer 3 connected to the bit line BL.

[0038] FIG. 2(b) shows a group of holes 17 in the p-layer 1 when all biases become 0V immediately after writing. The generated group of holes 17 are the majority carriers in the p-layer 1, and are temporarily stored in the p-layer 1 surrounded by the depletion layer 16. In a non-equilibrium state, they essentially charge the p-layer 1, which is the substrate of the WL-FET or PL-FET, with a positive bias. As a result, 1. The threshold voltage of the WL-FET having the gate conductor layer 5 and Second The threshold voltage of the PL-FET having the gate conductor layer 7 is lowered from the initial state due to the positive substrate bias effect caused by holes temporarily stored in the p-layer 1. When a voltage higher than this lowered threshold voltage is applied to the PL, the PL-FET becomes conductive and the WL-FET operates as a MOS transistor. As a result, as shown in FIG. 2(c), 1. In the WL-FET having the gate conductor layer 5, a current having the voltage dependency of WL flows from the n+ layer 3 to the n+ layer 2. This write state is assigned to logical storage data "1".

[0039] In addition to the above examples, the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL may be combinations such as 1.0V(BL) / 0V(SL) / 2V(PL) / 2.0V(WL), 1.5V(BL) / 0V(SL) / 3V(PL) / 1V(WL), 1.0V(BL) / 0V(SL) / 1.2V(PL) / 2.0V(WL), etc. However, when 1.0V is applied to the bit line BL, 0V to the source line SL, 2V to the word line WL, and 1.2V to the plate line PL, the position of the pinch-off point 15 is Second Although the shift occurs toward the gate conductor layer 7, a similar phenomenon can occur.

[0040] Next, the erase operation mechanism of the dynamic flash memory of the first embodiment will be explained with reference to FIG. 3. When erasing information in a dynamic flash memory, it is necessary that the accumulated holes recombine with electrons in a short time, and that these recombined electrons are replenished from the electrodes to which the memory is connected. To satisfy this, the voltage conditions to be applied to the bit line BL, source line SL, word line WL, and plate line PL are as follows: Gate Insulator Layer 6 In order to form an inversion layer on the entire surface directly under the PL-FET, a voltage higher than the Vth-PL voltage is applied to the plate line, and the gate of the PL-FET is turned on. Insulation layer An inversion layer 14b is formed at the interface between the word line 6 and the p-layer 1 to increase the recombination area of ​​holes and electrons accumulated in the p-layer 1. A voltage lower than WL-Vth or 0V is applied to the word line to p layer 1 It is necessary to form a depletion layer in the bit line. line The electrons injected from the 4 A voltage that generates a maximum electric field of 100 V / cm or more may be applied.

[0041] An example of the erase operation of the dynamic flash memory of the first embodiment shown in FIG. 1 will be described with reference to FIG. 3. From the state shown in FIG. 2(b), a voltage of 0.6V is applied to the bit line BL, 0V to the source line SL, 2V to the plate line PL, and 0V to the word line WL. As a result, the concentration of holes 17 stored in the p layer 1 is sufficiently higher than the concentration of holes in the n+ layer 2, so that holes flow into the n+ layer 2 by diffusion due to the concentration gradient. Conversely, the concentration of electrons in the n+ layer 2 is higher than the concentration of electrons in the p layer 1, so that electrons 18 flow into the p layer 1 by diffusion due to the concentration gradient. The electrons that flow into the p layer 1 recombine with holes in the p layer 1 and disappear. However, not all of the injected electrons 18 disappear, and the remaining electrons 18 flow into the n+ layer 3 through the depletion layer 16 due to drift caused by the potential gradient of the bit line BL and the source line SL. Since electrons are supplied one after another from the source line SL, the excess holes recombine with the electrons in a very short time, returning to the initial state. The power consumed here is due to the electrons flowing in from the source line SL, and is much smaller than the power consumption during writing. As a result, as shown in Figure 3(b), 1. WL-FET having a gate conductor layer 5 Second The PL-FET with the gate conductor layer 7 returns to the original threshold voltage. b As shown in FIG. 1, the word line WL is connected to 1. Even if the WL voltage is increased, no current flows through the WL-FET having the gate conductor layer 5. The erased state of this memory element represents logical memory data "0".

[0042] The reason why the power consumption is much smaller than that during writing is because the current flowing between the bit line BL and the source line SL is lower than that during writing. Also, the voltage applied to the bit line BL is lower than that during writing. In the example of Figure 1-3, the case where the majority carriers for writing are holes and n+ layers 2 and 3 are provided is explained, but in the case where the majority carriers for writing are electrons and a p+ layer is used instead of the n+ layer, the power consumption during erasing is smaller than that during writing for the same reason. However, since the current can be positive or negative depending on the direction of flow, the expressions "high" and "low" are sometimes inaccurate. Therefore, it is more accurate to say that "the absolute value of the current flowing through the bit line BL during memory erase operation is lower than the absolute value of the current flowing through the bit line during memory write operation."

[0043] The voltage applied to the bit line is set so that the maximum electric field between the bit line and the source line is 10 4 Therefore, even if the voltage is higher or lower than 0.6 V / cm, it is sufficient to apply a voltage that is high enough to cause the drift of electrons in the depletion layer 16.

[0044] Also, the word line To It is also possible to erase data in the same way by applying a voltage 1.5 times or more higher than Vth-WL to form an inversion layer and applying a plate voltage of 0 V or a voltage lower than Vth-PL to prevent the inversion layer from being formed.

[0045] In the above, we have explained the case where the majority carriers for writing are holes, with n+ layers 2 and 3. In contrast, if the majority carriers for writing are electrons, with a p+ layer instead of an n+ layer, it should be written as "applying a plate voltage of 0V or a voltage higher than Vth-PL." In this way, depending on the type of MOS transistor, it may be inaccurate to say that the threshold is high or low. Therefore, it is more accurate to express the threshold value in terms of its "absolute value and polarity (positive or negative)." Using this expression, for example, it would be "applying a voltage that has an absolute value equal to or greater than the absolute value of the threshold value of the MOS transistor region and has the same polarity as the threshold value."

[0046] In addition, in the description of this embodiment, the first gate conductor layer 5 adjacent to the n+ layer 2 is connected to the word line WL, and the second gate conductor layer 7 adjacent to the n+ layer 3 is connected to the plate line PL. In contrast, the memory erase operation of the present invention can be performed even if the second gate conductor layer 7 connected to the plate line PL is adjacent to the n+ layer 2, and the first gate conductor layer 5 connected to the word line WL is adjacent to the n+ layer 3.

[0047] As a method of erasing data other than the examples given above, the voltage conditions applied to the bit lines BL, source lines SL, word lines WL, and plate lines PL may be combinations such as 0.6V(BL) / 0V(SL) / 2V(PL) / 0V(WL), 0V(BL) / 0.6V(SL) / 0V(PL) / 2V(WL), 0.6V(BL) / 0V(SL) / 2V(PL) / 0.2V(WL), or 1.5V(BL) / 0V(SL) / 2V(PL) / 0V(WL). The voltage conditions applied to the bit lines BL, source lines SL, word lines WL, and plate lines PL mentioned above are examples for performing a memory erase operation, and other operations capable of performing a memory erase operation are also possible. Voltage It may be a condition.

[0048] Also, when the PL-FET or WL-FET is a p-type channel type, the p-layer 1 becomes an n-type semiconductor, electronicbecome majority carriers, and the polarity of the potential applied to the bit line, word line, and plate line all becomes negative potential instead of the positive potential shown in the example.

[0049] As described in the present embodiment, the dynamic flash memory cell may have a structure that satisfies the condition that the hole group 17 generated by the impact ionization phenomenon is held in the p-layer 1. To achieve this, the p-layer 1 may have a floating body structure that is separated from the substrate 20. For this reason, for example, a GAA (Gate All Around) structure, which is one type of SGT, may be used. 13 The dynamic flash memory operation described above can be performed even if the p-layer 1 is formed horizontally to the substrate 20 using a technology such as a nanosheet technology (see, for example, non-patent documents 11 and 12). The device structure may also be a device structure using SOI (Silicon On Insulator) (see, for example, non-patent documents 7 to 10). In this device structure, the bottom of the channel region is in contact with the insulating layer of the SOI substrate, and is surrounded by a gate insulating layer and an element isolation insulating layer that surround other channel regions. In this structure, the channel region also has a floating body structure. In this way, the dynamic flash memory element provided by this embodiment only needs to satisfy the condition that the channel region has a floating body structure. In addition, even if a structure is used in which a Fin transistor (see, for example, non-patent document 13) is formed on an SOI substrate, the dynamic flash operation can be performed as long as the channel region has a floating body structure.

[0050] This embodiment has the following features. (Feature 1) In the memory erase operation of this embodiment, the memory erase operation can be performed with low power consumption. As shown in FIG. 3, the feature of the present invention is that during the memory erase operation, an inversion layer 14b is formed in the p layer 1 of the PL-FET, connected to the n+ layer 3. During memory retention, the area where holes stored in the memory cell recombine with electrons is determined by the contact portion between the n+ layer 3 and the p layer 1, whereas during memory erase, the entire surface of the inversion layer 14b formed directly under the gate insulating layer 6 electrically contacts the n+ layer 3, making the area where holes and electrons recombine larger than during memory retention, increasing the chance of the electron-hole recombination phenomenon. Furthermore, since the WL-FET is not in the on state at this time, no current flows from the bit line BL to the source line SL, and therefore no impact ionization that would hinder the erase operation occurs in the p layer 1. This not only ensures reliable memory erase operation, but also contributes to stable memory operation. In this memory erase operation, only electrons to replenish the electrons that have been lost due to the electron-hole recombination phenomenon are injected from the source line SL, so that only an extremely small current flows, and the memory erase operation can be performed with low power consumption. (Feature 2) In this embodiment, since the memory erase operation can be performed with small power consumption, in the overall operation, when the PL-FET and WL-FET operate as N-channel MOS transistors, a negative potential is not required, and operation can be performed at a positive potential or 0 V. This allows for simplification and reduction in the area of ​​the peripheral detection circuits and drive circuits.

[0051] (Feature 3) In the dynamic flash memory according to the first embodiment of the present invention, it is not necessary to apply voltages of opposite polarity to the source line SL, the word line WL, the plate line PL, and the bit line BL during the memory erase operation, which makes it possible to prevent a decrease in reliability of the oxide film caused by a large electric field being applied to the gate oxide film of the PL-FET.

[0052] In addition, the present invention allows various embodiments and modifications without departing from the broad spirit and scope of the present invention. Moreover, each of the above-mentioned embodiments is intended to explain one example of the present invention, and does not limit the scope of the present invention. The above-mentioned examples and modifications can be combined arbitrarily. Furthermore, even if some of the constituent elements of the above-mentioned embodiments are omitted as necessary, the scope of the technical idea of ​​the present invention will remain within the scope of the present invention. [Industrial Applicability]

[0053] By using the semiconductor element according to the present invention, it is possible to provide a semiconductor memory device which is denser, faster, and has a higher operating margin than conventional devices. [Explanation of symbols]

[0054] 1 p layer 2. The First Impurity region n+ layer (connected to SL) 3. The second impurity region n+ layer (connected to BL) 4. First gate insulating film 5 First gate conductor layer (connected to WL) 6 Second gate insulating film (connected to PL) 7 Second Gate Conductor Layer 10 Substrate 14a, 14b Inversion layer 15 Pinch-off point 16 Depletion Layer 17 Excess holes 18 Injected electrons 101 SiO2 layer 102 Semiconductor Motherboard 103 N+ layer (connected to SL) 104 N+ layer (connected to BL) 105a: First gate conductor layer (connected to PL) 105b Second gate conductor layer (connected to WL) 106 Hole group 107a, 107b Inversion layer 108 Pinch-off point 109a first gate insulating film 109b Second gate insulating film 110 Insulating layer 111 Dynamic Flash Memory Cell

Claims

1. A semiconductor body extending horizontally or vertically on a substrate; a first impurity region and a second impurity region connected to both ends of the semiconductor body; a first gate insulating layer covering the semiconductor body; a first gate conductor layer overlying the first gate insulating layer; a second gate insulating layer connected to the first gate insulating layer and covering the semiconductor body; a second gate conductor layer covering the second gate insulating layer without contacting the first gate conductor layer, a voltage between 0V and a threshold voltage, including 0V, is applied to one of the first gate conductor layer and the second gate conductor layer, and a voltage of the same polarity and an absolute value equal to or greater than the absolute value of the threshold voltage is applied to the other gate conductor layer, and a voltage is applied with the same polarity so that a potential difference is generated between the first impurity region and the second impurity region, thereby reducing either holes or electrons, which are majority carriers remaining in the semiconductor body, and performing a memory erase operation; A memory device using a semiconductor element.

2. a source line is connected to the first impurity region, a bit line is connected to the second impurity region, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a plate line; voltages are applied to the source line, the bit line, the plate line, and the word line, respectively, to perform a memory write operation, a memory read operation, and the memory erase operation, thereby operating the dynamic flash memory; 2. A memory device using the semiconductor element according to claim 1.

3. During the erase operation of the dynamic flash memory, when majority carriers in the semiconductor body are holes, a voltage applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer is 0 V or a positive potential.

3. A memory device using the semiconductor element according to claim 2.

4. In the erase operation of the dynamic flash memory, when the majority carriers of the semiconductor body are electrons, the voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer are 0 V or a negative potential.

3. A memory device using the semiconductor element according to claim 2.

5. During the memory erase operation of the dynamic flash memory, either the source line or the bit line is at 0 V.

3. A memory device using the semiconductor element according to claim 2.

6. an operation of generating a group of electrons and a group of holes in the semiconductor body and the first impurity region by applying an absolute value equal to or greater than the absolute value of a threshold voltage of a first MOS transistor region formed of the first gate insulating layer and the first gate conductor layer and having the same polarity as the threshold voltage to the word line, applying a voltage equal to or greater than the absolute value of a threshold voltage of a second MOS transistor region formed of the second gate insulating layer and the second gate conductor layer and having the same polarity as the threshold voltage to the plate line, applying a voltage to the bit line such that a maximum electric field of the semiconductor body causes impact ionization during writing, and applying 0 V to the source line, and causing an impact ionization phenomenon by a current flowing between the first impurity region and the second impurity region, and generating a group of electrons and a group of holes in the semiconductor body and the first impurity region; and leaving a part or all of the group of electrons or the group of holes, which are majority carriers in the semiconductor body, in the semiconductor body among the group of electrons and the group of holes generated, in the semiconductor body.

3. A memory device using the semiconductor element according to claim 2.

7. an absolute value of a current flowing through the bit line during the memory erase operation of the dynamic flash memory is lower than an absolute value of a current flowing through the bit line during the memory write operation of the dynamic flash memory; 3. A memory device using the semiconductor element according to claim 2.

8. During the memory write operation and the memory erase operation of the dynamic flash memory, voltages applied to the plate line, the word line, the source line, and the bit line are 0 V or all have the same polarity.

3. A memory device using the semiconductor element according to claim 2.