Semiconductor equipment

Abstract

Provided is a novel semiconductor device. In the present invention, a first circuit is electrically connected to a second circuit via a first wire, the first circuit is electrically connected to a fourth circuit via each of a third wire and a fourth wire, the second circuit is electrically connected to a third circuit via a fifth wire, the first circuit has a function for achieving a conductive state or non-conductive state between the first wire, a second wire, the third wire, and the fourth wire, the third circuit has a function for holding potential corresponding to first data, the second circuit has a function for applying the potential corresponding to the first data from the first wire to the fifth wire, a function for holding potential corresponding to second data, and a function for amplifying a change in potential of the fifth wire and outputting the change to the first wire, and the fourth circuit has a function for outputting the potential corresponding to the first data or the potential corresponding to the second data depending on a potential difference between the third wire and the fourth wire.

Description

Semiconductor device and storage device

[0001] One embodiment of the present invention relates to a semiconductor device and a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic devices, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, electronic computers, electronic devices, and driving methods thereof or manufacturing methods thereof.

[0003] In recent years, semiconductor devices have been developed and are mainly used in, for example, LSIs, CPUs, memories, etc. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] For example, semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards (for example, printed wiring boards) and used as one of the components of various electronic devices.

[0005] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0007] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide a plurality of overlapping memory cells.

[0008] JP 2012-257187 A JP 2011-151383 A International Publication No. 2021 / 053473

[0009] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be highly integrated. Another object is to provide a semiconductor device that can be manufactured at a reduced cost. Another object is to provide a semiconductor device that can consume less power. Another object is to provide a semiconductor device that can have an increased operating speed. Another object is to provide a semiconductor device that can be miniaturized. Another object is to provide a novel semiconductor device. Another object is to provide a memory device that includes any one or more of the semiconductor devices listed above.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description in this specification, drawings, claims, etc., and it is possible to extract other problems from the description in this specification, drawings, claims, etc.

[0012] (1) One aspect of the present invention includes a first circuit, a second circuit, a third circuit, a fourth circuit, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, wherein the first circuit is electrically connected to the second circuit via the first wiring, the first circuit is electrically connected to the fourth circuit via each of the third wiring and the fourth wiring, and the second circuit is electrically connected to the third circuit via the fifth wiring, and the first circuit establishes a state of conduction between each of the first wiring, the second wiring, the third wiring, and the fourth wiring. the third circuit has a function of putting the first wiring into a conductive state or a non-conductive state; the third circuit has a function of holding a potential corresponding to first data; the second circuit has a function of applying a potential corresponding to the first data from the first wiring to the fifth wiring, a function of holding a potential corresponding to second data, and a function of amplifying a change in the potential of the fifth wiring and outputting it to the first wiring; and the fourth circuit has a function of outputting a potential corresponding to the first data or the second data in accordance with a potential difference between the third wiring and the fourth wiring.

[0013] (2) In the above (1), the first circuit may include a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, the first transistor having a function of bringing the first wiring and the second wiring into a conductive state or a non-conductive state, the second transistor having a function of bringing the first wiring and the third wiring into a conductive state or a non-conductive state, the third transistor having a function of bringing the second wiring and the fourth wiring into a conductive state or a non-conductive state, the fourth transistor having a function of precharging the first wiring, and the fifth transistor having a function of precharging the second wiring.

[0014] (3) In the above (1), the first circuit may include a first transistor, a second transistor, a third transistor, a first capacitance, and a second capacitance, the first transistor having a function of bringing the first wiring and the second wiring into a conductive state or a non-conductive state, the second transistor having a function of bringing the first wiring and the third wiring into a conductive state or a non-conductive state, the third transistor having a function of bringing the second wiring and the fourth wiring into a conductive state or a non-conductive state, the first capacitance having a function of changing the potential of the first wiring, and the second capacitance having a function of changing the potential of the second wiring.

[0015] (4) In the above (1), the first circuit includes a first transistor, a second transistor, and a third transistor, the first transistor having a function of bringing the first wiring and the second wiring into a conductive state or a non-conductive state, the second transistor having a function of bringing the first wiring and the third wiring into a conductive state or a non-conductive state, and the third transistor having a function of bringing the second wiring and the fourth wiring into a conductive state or a non-conductive state, and the fourth circuit includes a sixth transistor and a seventh transistor, the sixth transistor having a function of precharging the third wiring, and the seventh transistor having a function of precharging the fourth wiring.

[0016] (5) In any one of (1) to (4), the fourth circuit may be provided on a substrate, the first circuit and the second circuit may be provided on a first layer disposed on the substrate, the third circuit may be provided on each of a plurality of second layers disposed on the substrate, the substrate may include a Si transistor, and each of the first layer and the plurality of second layers may include an OS transistor.

[0017] (6) Another embodiment of the present invention is a memory device including the semiconductor device described in (5) above and a fifth circuit, wherein the fifth circuit is provided in each of a plurality of second layers, and the fifth circuit has a function of outputting a signal that controls an operation of the third circuit.

[0018] One embodiment of the present invention can provide a semiconductor device that can be highly integrated. Alternatively, a semiconductor device that can be manufactured at a reduced cost can be provided. Alternatively, a semiconductor device that can consume less power can be provided. Alternatively, a semiconductor device that can operate at a higher speed can be provided. Alternatively, a semiconductor device that can be downsized can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a memory device including any one or more of the semiconductor devices listed above can be provided.

[0019] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in this specification, drawings, claims, etc., and it is possible to extract other effects from the description in this specification, drawings, claims, etc.

[0020] FIG. 1 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 2 is a schematic diagram illustrating an example of the configuration of a semiconductor device. FIG. 3A is a schematic diagram illustrating an example of the configuration of a semiconductor device. FIG. 3B is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIGS. 4A to 4D are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 5A and 5B are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIG. 6 is a timing chart illustrating an example of the operation of a semiconductor device. FIG. 7 is a timing chart illustrating an example of the operation of a semiconductor device. FIG. 8 is a block diagram illustrating an example of the configuration of a semiconductor device. FIGS. 9A and 9B are schematic diagrams illustrating an example of the configuration of a semiconductor device. FIG. 10 is a schematic diagram illustrating an example of the configuration of a computer. FIG. 11A is a flowchart illustrating an example of the operation of a computer. FIGS. 11B and 11C are schematic diagrams illustrating an example of the operation of a computer. FIG. 12 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 13 is a timing chart illustrating an example of the operation of a semiconductor device. FIG. 14 is a timing chart illustrating an example of the operation of a semiconductor device. FIG. 15 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIGS. 16A and 16B are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIG. 17 is a timing chart illustrating an example of the operation of a semiconductor device. FIG. 18 is a timing chart illustrating an example of the operation of a semiconductor device. FIGS. 19A and 19B are schematic diagrams illustrating an example of the configuration of a memory device. FIGS. 20A and 20B are schematic diagrams illustrating an example of the configuration of a memory device. FIG. 21A is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 21B is a timing chart illustrating an example of the operation of a memory device. FIGS. 22A to 22E are circuit diagrams illustrating an example of the configuration of a memory circuit. FIGS. 23A and 23B are plan layout diagrams illustrating an example of the configuration of a memory device. FIG. 24A is a top view illustrating an example of a semiconductor device. FIGS. 24B to 24D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 25A and 25B are schematic diagrams illustrating an example of a semiconductor device. FIGS. 26A and 26B are diagrams illustrating an example of an electronic component. FIGS. 27A to 27E are schematic diagrams illustrating an example of a memory device. FIGS. 28A to 28H are diagrams illustrating an example of an electronic device.29A and 29B are diagrams showing an example of electronic equipment. FIG. 30 is a diagram showing an example of space equipment. FIG. 31 is a diagram showing an example of a storage system applicable to a data center. FIG. 32 is a cross-sectional view showing an example of a semiconductor device. FIG. 33 is a diagram explaining the characteristics of a transistor used in estimating the operation of a semiconductor chip. FIG. 34 is a diagram explaining the characteristics of a transistor used in estimating the operation of a semiconductor chip. FIG. 35 is a diagram explaining the characteristics of a transistor used in estimating the operation of a semiconductor chip.

[0021] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor, a diode, or a photodiode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, for example, a memory device, a display device, a light-emitting device, a lighting device, or an electronic device may be a semiconductor device and may also include a semiconductor device.

[0022] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are each an object (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, or a layer, etc.).

[0023] As an example of the case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, or a load) that enable the electrical connection between X and Y can be connected between X and Y.

[0024] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, a logic circuit (for example, an inverter, a NAND circuit, or a NOR circuit), a signal conversion circuit (for example, a digital-to-analog conversion circuit, an analog-to-digital conversion circuit, or a gamma correction circuit), a potential level conversion circuit (for example, a power supply circuit (for example, a step-up circuit or a step-down circuit), or a level shifter circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplifier circuit (for example, a circuit that can increase the signal amplitude or current amount, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit), a signal generation circuit, a memory circuit, or a control circuit) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0025] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0026] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer, etc.).

[0027] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0028] Furthermore, in this specification, the term "resistive element" may refer to, for example, a circuit element or wiring having a resistance value higher than 0 Ω. Therefore, in this specification, the term "resistive element" includes, for example, wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, or a coil. Therefore, the term "resistive element" may be replaced with, for example, terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" may be replaced with, for example, terms such as "resistive element." The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value may be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0029] When a wiring is used as a resistor, the resistance value of the resistor may be determined by the length of the wiring. Alternatively, the resistor may use a conductor having a different resistivity from the conductor used as the wiring. Alternatively, when a semiconductor is used as a resistor, the resistance value of the resistor may be determined by doping impurities into the semiconductor.

[0030] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification, a "capacitive element" is not limited to a circuit element including a pair of electrodes and a dielectric between the electrodes. A "capacitive element" also includes, for example, a parasitic capacitance occurring between wirings, or a gate capacitance occurring between one of the source or drain of a transistor and the gate. Furthermore, terms such as "capacitive element," "parasitic capacitance," or "gate capacitance" can be replaced with terms such as "capacitance." Conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with, for example, a "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0031] In this specification and the like, a transistor has three terminals called a gate (also referred to as a gate terminal, a gate region, or a gate electrode), a source (also referred to as a source terminal, a source region, or a source electrode), and a drain (also referred to as a drain terminal, a drain region, or a drain electrode). A transistor also has a region where a channel is formed between the drain and the source (also referred to as a channel formation region). A transistor can pass a current between the source and the drain through the channel formation region. The channel formation region is a region through which a current mainly flows. The gate is a control terminal between the source and the drain that controls the amount of current flowing in the channel formation region. The two terminals that function as a source or a drain are input / output terminals of the transistor.

[0032] Note that one of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type of the transistor (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Furthermore, for example, when the direction of current changes during circuit operation, the function as a source and the function as a drain may be interchanged. For this reason, the terms "source" and "drain" are interchangeable in this specification. Furthermore, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) or "the other of the source or drain" (or second electrode or second terminal) are used.

[0033] Depending on the structure, a transistor may have a back gate in addition to the three terminals described above. In this case, in this specification, one of the gate or the back gate of the transistor may be referred to as a first gate, and the other of the gate or the back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification, each gate may be referred to as, for example, a first gate, a second gate, or a third gate.

[0034] In this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used. A multi-gate transistor has channel formation regions connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, a multi-gate transistor can reduce off-state current and improve the transistor's breakdown voltage (improved reliability). Furthermore, when a multi-gate transistor operates in the saturation region, even if the voltage between the drain and source changes, the current between the drain and source does not change significantly, resulting in a voltage-current characteristic with a flat slope. A transistor with a voltage-current characteristic with a flat slope can realize an ideal current source circuit or an active load with a very high resistance value. As a result, a transistor with a voltage-current characteristic with a flat slope can realize, for example, a differential circuit or a current mirror circuit with good characteristics.

[0035] Furthermore, in this specification, when a single circuit element is illustrated on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a single resistor is illustrated on a circuit diagram, the resistor includes two or more resistors electrically connected in series. For example, when a single capacitor is illustrated on a circuit diagram, the capacitor includes two or more capacitors electrically connected in parallel. For example, when a single transistor is illustrated on a circuit diagram, the transistor includes two or more transistors electrically connected in series, with the gates of the respective transistors electrically connected to each other. Similarly, when a single switch is illustrated on a circuit diagram, the switch includes two or more transistors, with the two or more transistors electrically connected in series or parallel, and with the gates of the respective transistors electrically connected to each other.

[0036] Furthermore, in this specification and the like, a "node" can be rephrased as a "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on, for example, the circuit configuration or the device structure. Furthermore, for example, a "terminal" or "wiring" can be rephrased as a "node."

[0037] Furthermore, in this specification, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative. In other words, a change in the reference potential will change, for example, the potential applied to wiring, the potential applied to a circuit, or the potential output from a circuit.

[0038] Furthermore, in this specification and the like, the terms "high-level potential (also referred to as "high-level potential," "H potential," or "H")" and "low-level potential (also referred to as "low-level potential," "L potential," or "L")" do not refer to any particular potential. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0039] Furthermore, in this specification, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers include electrons, holes, anions, cations, and complex ions. Note that carriers vary depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in, for example, wiring, is the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification and the like, unless otherwise specified regarding the positive or negative sign of a current (or the direction of the current), for example, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, for example, a statement such as "current is input to element A" can be rephrased as "current is output from element A," etc.

[0040] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0041] Furthermore, in this specification, terms indicating arrangement, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to drawings. Furthermore, the positional relationship between components changes as appropriate depending on the orientation in which each component is depicted. Therefore, terms indicating arrangement described in this specification are not limited to these terms and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees. Furthermore, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the left (or right) surface of a conductor" by rotating the orientation of the drawing by 90 degrees.

[0042] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0043] Furthermore, in this specification, terms such as "row" or "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, terms such as "row" or "column" used in this specification are not limited to these terms and can be rephrased appropriately depending on the situation. For example, the expression "row direction" can be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0044] Furthermore, in this specification and the like, for example, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state in which electrode B is formed on insulating layer A. The expression "electrode B overlapping insulating layer A" does not exclude, for example, the state in which electrode B is formed under insulating layer A, or the state in which electrode B is formed on the right (or left) side of insulating layer A.

[0045] Furthermore, in this specification and the like, the terms "adjacent" or "close to" do not limit components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not necessarily mean that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0046] Furthermore, in this specification and the like, terms such as "film" or "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" may be interchangeable with the term "conductive film." For example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, terms such as "film" or "layer" may be interchangeable with other terms depending on the situation without using those terms. For example, the term "conductive layer" or "conductive film" may be interchangeable with the term "conductor." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or "conductive film." For example, the term "insulating layer" or "insulating film" may be interchangeable with the term "insulator." Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or "insulating film."

[0047] Furthermore, in this specification and the like, terms such as "electrode," "wiring," or "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include, for example, cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes, for example, cases where multiple "electrodes," "wirings," or "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal." Furthermore, for example, a "terminal" can be part of a "wiring" or "electrode." Furthermore, for example, terms such as "electrode," "wiring," or "terminal" may be replaced with terms such as "region."

[0048] Furthermore, in this specification and the like, terms such as "wiring," "signal line," or "power line" may be interchangeable depending on the situation. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." The reverse is also true, for example, terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." The reverse is also true, for example, terms such as "signal line" may be changed to the term "power line." The term "potential" applied to wiring may be changed to the term "signal" depending on the situation. The reverse is also true, for example, terms such as "signal" may be changed to the term "potential."

[0049] In addition, in this specification, a "switch" has multiple terminals and has the function of switching (selecting) conduction or non-conduction between the terminals. For example, if a switch has two terminals and both terminals are conductive, the switch is said to be in a "conductive state" or "on state." Also, if both terminals are non-conductive, the switch is said to be in a "non-conductive state" or "off state." Note that switching the switch to either the conductive state or the non-conductive state, or maintaining either the conductive state or the non-conductive state, may be referred to as "controlling the conduction state."

[0050] In other words, a switch is a device that has the function of controlling whether or not a current flows. Alternatively, a switch is a device that has the function of selecting and switching the path through which a current flows. For example, an electrical switch or a mechanical switch can be used as the switch. In other words, the switch is not limited to a specific one as long as it can control a current.

[0051] There are types of switches that are normally in a non-conductive state but can be made conductive by controlling the conductive state, and these switches are sometimes called "contact A." There are also types of switches that are normally in a conductive state but can be made non-conductive by controlling the conductive state, and these switches are sometimes called "contact B."

[0052] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, or diode-connected transistors), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0053] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. Such a switch has an electrode that can be mechanically moved, and the movement of the electrode selects a conductive state or a non-conductive state.

[0054] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0055] In this specification, the term "having the same or approximately the same height" refers to the same height from a reference surface (e.g., a flat surface such as a substrate surface) in a cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process (typically a CMP process) may expose the surface of a single layer or multiple layers. In this case, the surfaces treated by the CMP process have the same height from the reference surface. However, the heights of multiple layers on the treated surface may not be strictly equal depending on the processing equipment, processing method, or material of the treated surface during the CMP process. In this specification, the term "having the same or approximately the same height" is also used. For example, in a case where there are two layers (here, a first layer and a second layer) with different heights relative to a reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less.

[0056] In this specification, "edges that coincide or approximately coincide" refers to the overlapping of at least a portion of the contours between stacked layers when viewed from above. For example, this includes cases in which, in the manufacturing process of a semiconductor device, upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In this specification, this case is also referred to as "edges that coincide or approximately coincide."

[0057] In this specification, for example, when referring to counting values ​​and measurement values, or to objects, methods, and events that can be converted into counting values ​​or measurement values, terms such as "identical," "the same," "equal," or "uniform" (including synonyms thereof) are used, and unless otherwise specified, these terms are intended to include an error of plus or minus 20%.

[0058] In this specification and the like, impurities in a semiconductor refer to, for example, elements other than the main component constituting a semiconductor layer. For example, an element having a concentration of less than 0.1 atomic % is an impurity. When a semiconductor contains impurities, for example, the defect state density of the semiconductor may increase, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main component of the oxide semiconductor. In particular, there are hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. When an impurity is mixed in an oxide semiconductor, for example, oxygen vacancies (V Ｏ When the semiconductor is a silicon layer, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements excluding oxygen and hydrogen.

[0059] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into, for example, oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply as OSs). For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide is used as a material capable of forming a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0060] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0061] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, these configuration examples can be combined as appropriate.

[0062] The embodiments described in this specification will be described with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, those skilled in the art will readily understand that various changes in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments. In the drawings illustrating the embodiments, the same reference numerals may be used in different drawings to designate identical or similarly functional parts in the configuration of the invention, thereby avoiding repetitive description. Furthermore, in the drawings, the same hatching patterns may be used and no particular reference numerals may be used to indicate similar functions. Furthermore, for ease of understanding, the drawings may omit the illustration of some components, for example, in perspective views or top views (also referred to as "plan views"). Furthermore, the drawings may omit the illustration of some hidden lines. Furthermore, the drawings may omit notations such as hatching patterns.

[0063] In addition, in the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to, for example, their size or aspect ratio. Note that the drawings are merely schematic illustrations of ideal examples, and are not limited to, for example, the shapes or values ​​shown in the drawings.

[0064] For example, the drawings and the like relating to this specification may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0065] For example, in the drawings and the like relating to this specification, in the actual manufacturing process, layers or resist masks may be unintentionally thinned due to processes such as etching, but this may not be reflected in the drawings in order to make it easier to understand.

[0066] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0067] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]" may be added to the symbol.

[0068] Embodiment 1 A structural example of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

[0069] Note that a semiconductor device is a device that utilizes semiconductor characteristics, and is a circuit including a semiconductor element (for example, a transistor, a diode, or a photodiode), or a device including such a circuit. The semiconductor device described in this embodiment and the like can be suitably used as, for example, a memory device. Furthermore, for example, the semiconductor device can be suitably used as an electronic computer including the memory device.

[0070] <Structural Example of Semiconductor Device> FIG. 1 is a circuit diagram illustrating a structural example of a semiconductor device 10 according to one embodiment of the present invention.

[0071] The semiconductor device 10 includes a substrate 50 and a layer 20. The substrate 50 may be an insulating substrate or a semiconductor substrate containing various materials. For example, the substrate 50 may be a substrate containing silicon. For example, the substrate 50 may include a transistor containing silicon in a channel formation region (a Si transistor). The layer 20 may include various materials such as a conductor, a semiconductor, or an insulator, and may include various elements such as a capacitor or a transistor. For example, the layer 20 may include a transistor containing an oxide semiconductor in a channel formation region (an OS transistor).

[0072] The layer 20 includes a layer 30 and a layer 40. The layer 40 includes layers 41[1] to 41[m], where m is an integer of 2 or greater.

[0073] The layer 40 includes a plurality of memory cells 42 in each of layers 41[1] to 41[m]. Each of the memory cells 42 is electrically connected to a local bit line LBL. The memory cells 42 have a function of storing data by holding a potential corresponding to the data. Data can be written to or read from the memory cells 42 via the local bit line LBL.

[0074] The memory cell 42 includes one transistor and one capacitor (sometimes referred to as a capacitor) (see FIGS. 3B and 4A ). One of the source and drain of the transistor is electrically connected to one terminal of the capacitor. In the memory cell 42, a transistor with extremely low off-state current is preferably used as the transistor. For example, an OS transistor can be used as the transistor. A memory cell using such an OS transistor can be called DOSRAM (registered trademark). DOSRAM is an abbreviation for Dynamic Oxide Semiconductor RAM (Random Access Memory). By using an OS transistor with extremely low off-state current, DOSRAM can store data for a long period of time. Furthermore, since DOSRAM can be configured with one OS transistor and one capacitor, high-density memory cells can be achieved.

[0075] The OS transistor has a characteristic of extremely low off-state current (current flowing between the source and drain when the transistor is off) because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. The off-state current of an OS transistor per 1 μm of channel width at room temperature is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ In the case of a Si transistor, the off-state current per 1 μm of channel width at room temperature can be 1 fA (1×10 −１５ A) or more and 1 pA (1 × 10 −１２ Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0076] The semiconductor layer of the OS transistor preferably contains at least one of indium and zinc. Furthermore, the semiconductor layer of the OS transistor preferably contains, for example, indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0077] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO") as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used as the semiconductor layer.

[0078] When the semiconductor layer is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include a composition in which In:M:Zn=1:1:1 or thereabouts, a composition in which In:M:Zn=1:1:1.2 or thereabouts, a composition in which In:M:Zn=2:1:3 or thereabouts, a composition in which In:M:Zn=3:1:2 or thereabouts, a composition in which In:M:Zn=4:2:3 or thereabouts, a composition in which In:M:Zn=4:2:4.1 or thereabouts, a composition in which In:M:Zn=5:1:3 or thereabouts, a composition in which In:M:Zn=5:1:6 or thereabouts, a composition in which In:M:Zn=5:1:7 or thereabouts, a composition in which In:M:Zn=5:1:8 or thereabouts, a composition in which In:M:Zn=6:1:6 or thereabouts, and a composition in which In:M:Zn=5:2:5 or thereabouts. Furthermore, the atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include a composition of In:M:Zn=1:3:2 or a composition thereabout, or a composition of In:M:Zn=1:3:4 or a composition thereabout. Note that a composition thereabout includes a range of plus or minus 30% of the desired atomic ratio.

[0079] For example, when describing a composition having an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, this includes a case where, when In is taken as 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. Furthermore, when describing a composition having an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, this includes a case where, when In is taken as 5, Ga is more than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. Furthermore, when describing a composition having an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, this includes a case where, when In is taken as 1, Ga is more than 0.1 and 2 or less, and Zn is more than 0.1 and 2 or less.

[0080] A memory cell using an OS transistor can retain charge accumulated in a capacitor constituting the memory cell for a long period of time because the off-state current of the OS transistor is extremely low. Therefore, the memory cell can store data for a long period of time by storing data based on the level of potential corresponding to the amount of charge stored in the capacitor. In other words, the memory cell can store data once written for a long period of time, thereby reducing the frequency of refreshing data. Therefore, the memory cell can reduce the power consumption of a semiconductor device or a storage device using the memory cell.

[0081] Furthermore, a memory cell using an OS transistor can write or read data by charging or discharging an electric charge, allowing for practically unlimited data write or read operations. Furthermore, a memory cell using an OS transistor has excellent rewrite endurance because it does not involve structural changes at the atomic level, unlike a magnetic memory or a resistance change memory. Furthermore, a memory cell using an OS transistor has excellent stability because it does not exhibit instability due to an increase in electron trap centers, unlike a flash memory, even after repeated writing.

[0082] Furthermore, memory cells using OS transistors can be freely arranged on, for example, a silicon substrate on which Si transistors are provided, and therefore can be easily integrated. Furthermore, memory cells using OS transistors can be manufactured at low cost because they can be manufactured using the same manufacturing equipment as Si transistors.

[0083] An OS transistor can be a four-terminal semiconductor element by including a back gate (back gate electrode) in addition to a gate (gate electrode), a source (source electrode), and a drain (drain electrode). A four-terminal OS transistor can independently control current flowing between the source and the drain depending on potentials applied to the gate or the back gate. Furthermore, OS transistors have better electrical characteristics than Si transistors even under high-temperature conditions. Specifically, OS transistors can perform good switching operation even under high temperatures, such as 125° C. or higher and 150° C. or lower, because of their large on-current / off-current ratio.

[0084] The layer 30 includes a sense circuit 35 , a sense circuit 35_pre, and a switching circuit 37 .

[0085] The sense circuit 35 is electrically connected to a plurality of memory cells 42 included in the layer 40 via local bit lines LBL. The sense circuit 35 is also electrically connected to a switching circuit 37 via global bit lines GBL. When writing data to a memory cell 42, the sense circuit 35 applies a potential corresponding to the data from the global bit line GBL to the local bit line LBL. When reading data from the memory cell 42, the sense circuit 35 amplifies a change in the potential of the local bit line LBL and outputs the amplified potential to the global bit line GBL. The sense circuit 35 can be configured using OS transistors.

[0086] Although not shown, the layer 30 includes a plurality of sense circuits 35. The global bit line GBL is electrically connected to each of the plurality of local bit lines LBL via each of the plurality of sense circuits 35. The semiconductor device 10 has a function of selecting one of the plurality of sense circuits 35 and writing or reading data to or from one memory cell 42 selected from among the plurality of memory cells 42 electrically connected to the selected sense circuit 35.

[0087] Furthermore, the transistors constituting the sense circuits 35 may have threshold voltage variations among the multiple sense circuits 35. In particular, variations in the threshold voltage of transistors that convert slight potential changes in the local bit lines LBL into current significantly affect the operation of the sense circuits 35. Therefore, if such variations affect the operation of the sense circuits 35, the semiconductor device 10 may not correctly read data from the memory cells 42. The sense circuits 35 may have a correction function to reduce the effect of such threshold voltage variations on data reading. This correction function allows the semiconductor device 10 to improve the reliability of read data.

[0088] The sense circuit 35_pre has the same configuration as the sense circuit 35. Therefore, when describing the sense circuit 35_pre, the global bit line GBL should be replaced with the global bit line GBLB, and the local bit line LBL should be replaced with the local bit line LBL_pre, and the description of the sense circuit 35 described above should be appropriately taken into consideration.

[0089] The sense circuit 35, the global bit line GBL, the local bit line LBL, and the plurality of memory cells 42 electrically connected to the local bit line LBL are paired with the sense circuit 35_pre, the global bit line GBLB, the local bit line LBL_pre, and the plurality of memory cells 42 electrically connected to the local bit line LBL_pre.

[0090] The memory cells 42 connected to the local bit line LBL are memory cells into which data is written or read. The memory cells 42 connected to the local bit line LBL_pre are memory cells into which data is not written or read. The local bit line LBL_pre is precharged to a predetermined potential and continues to hold this potential. Note that the memory cells 42 connected to the local bit line LBL_pre may be memory cells into which data is written or read, and the memory cells 42 connected to the local bit line LBL may be memory cells into which data is not written or read. In this case, the local bit line LBL is precharged to a predetermined potential and continues to hold this potential.

[0091] The switching circuit 37 is electrically connected to the sense circuit 35 via the global bit line GBL. The switching circuit 37 is also electrically connected to the sense circuit 35_pre via the global bit line GBLB. The switching circuit 37 is also electrically connected to a drive circuit 51 provided on the substrate 50 via the global bit line SA_GBL and the global bit line SA_GBLB. The switching circuit 37 has a function of establishing a conductive state or a non-conductive state between the global bit line GBL, the global bit line GBLB, the global bit line SA_GBL, and the global bit line SA_GBLB. The switching circuit 37 also has a function of precharging the global bit line GBL and the global bit line GBLB to a predetermined potential.

[0092] The switching circuit 37 includes a transistor M0, a transistor M1, a transistor M2, a transistor M3, and a transistor M4. Note that it is preferable to use a transistor with extremely low off-state current as the transistor included in the switching circuit 37. For example, the transistor included in the switching circuit 37 can be an OS transistor.

[0093] One of the source and drain of the transistor M0 is electrically connected to the global bit line GBL. The other of the source and drain of the transistor M0 is electrically connected to the global bit line GBLB. The transistor M0 has a function of bringing the global bit line GBL and the global bit line GBLB into a conductive state or a non-conductive state in response to a signal SW0.

[0094] One of the source and drain of the transistor M1 is electrically connected to the global bit line GBL. The other of the source and drain of the transistor M1 is electrically connected to the global bit line SA_GBL. The transistor M1 has a function of bringing the global bit line GBL and the global bit line SA_GBL into a conductive state or a non-conductive state in response to a signal SW1.

[0095] One of the source and drain of the transistor M2 is electrically connected to the global bit line GBLB. The other of the source and drain of the transistor M2 is electrically connected to the global bit line SA_GBLB. The transistor M2 has a function of bringing the global bit line GBLB and the global bit line SA_GBLB into a conductive state or a non-conductive state in response to a signal SW2.

[0096] One of the source and drain of the transistor M3 is electrically connected to the global bit line GBL. The other of the source and drain of the transistor M3 is electrically connected to a terminal to which a potential VPRE2 is applied. The transistor M3 has a function of precharging the global bit line GBL to the potential VPRE2 in response to a signal SW3.

[0097] One of the source and drain of the transistor M4 is electrically connected to the global bit line GBLB. The other of the source and drain of the transistor M4 is electrically connected to a terminal to which a potential VPRE2 is applied. The transistor M4 has a function of precharging the global bit line GBLB to the potential VPRE2 in response to a signal SW3.

[0098] The substrate 50 includes a drive circuit 51 .

[0099] The drive circuit 51 is electrically connected to the switching circuit 37 provided in the layer 30 via the global bit line SA_GBL and the global bit line SA_GBLB. When writing data, the drive circuit 51 has a function of applying a potential corresponding to the data to each of the global bit line SA_GBL and the global bit line SA_GBLB. When reading data, the drive circuit 51 has a function of outputting a potential corresponding to the data in accordance with the potential difference between the global bit line SA_GBL and the global bit line SA_GBLB. The drive circuit 51 can be configured using a Si transistor whose channel is formed in the substrate 50.

[0100] Si transistors have a higher operating speed than OS transistors. Furthermore, by electrically connecting the gate of an n-channel Si transistor and the gate of a p-channel Si transistor, a CMOS circuit (e.g., a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be configured. Therefore, by configuring the driver circuit 51 on the substrate 50 with Si transistors, the operating speed can be increased and power consumption in a steady state can be reduced.

[0101] FIG. 2 is a schematic diagram illustrating a configuration example of a semiconductor device 10 according to one embodiment of the present invention.

[0102] As shown in FIG. 2 , the semiconductor device 10 includes a substrate 50 and one or more layers 20 (layers 20[1] to 20[k]). Here, k is an integer of 2 or greater. The substrate 50 can be an insulating substrate or a semiconductor substrate containing various materials. For example, the substrate 50 can be a substrate containing silicon. Each of the layers 20[1] to 20[k] can include various materials, such as a conductor, a semiconductor, or an insulator. Each of the layers 20[1] to 20[k] can include various elements, such as a capacitor or a transistor.

[0103] The schematic diagram shown in FIG. 2 defines the X, Y, and Z directions to explain the arrangement of each layer constituting the semiconductor device 10. The Z direction refers to a direction perpendicular or approximately perpendicular to the surface of the substrate 50. "Approximately perpendicular" refers to a state in which the angle between two elements is 85 degrees or greater and 95 degrees or less. In this embodiment and the like, the Z direction may be referred to as the vertical direction for ease of understanding. The surface of the substrate 50 corresponds to the plane formed by the X direction, which is defined as perpendicular or approximately perpendicular to the Z direction, and the Y direction, which is defined as perpendicular or approximately perpendicular to both the X and Z directions. In this embodiment and the like, the X direction may be referred to as the depth direction and the Y direction may be referred to as the horizontal direction for ease of understanding.

[0104] Each of the layers 20[1] to 20[k] can be stacked in the vertical direction (Z direction) on the substrate 50. Each of the layers 20[1] to 20[k] includes a layer 30 and a layer 40.

[0105] 2 , the layers 41[1] to 41[m] included in the layer 40 can be stacked in the vertical direction. Therefore, the semiconductor device 10 according to one embodiment of the present invention can improve the density (memory density) of the memory cells 42. Furthermore, the layers 41[1] to 41[m] can be manufactured by repeating the same manufacturing process in the vertical direction. Therefore, the semiconductor device 10 according to one embodiment of the present invention can reduce the manufacturing cost of the memory cells 42.

[0106] 2, the layers 30 and 40 (layers 41[1] to 41[m]) can be stacked vertically on the substrate 50. Therefore, the semiconductor device 10 according to one embodiment of the present invention can shorten the length of wiring, such as the local bit line LBL and the global bit line SA_GBL. In other words, the semiconductor device 10 according to one embodiment of the present invention can reduce the parasitic resistance and parasitic capacitance of the wiring by shortening the signal propagation distance between two circuits connected to the wiring. Therefore, the semiconductor device 10 according to one embodiment of the present invention can achieve reduced power consumption and reduced signal delay.

[0107] Furthermore, the semiconductor device 10 according to one aspect of the present invention can operate even if the capacitance of the memory cell 42 is reduced by reducing the parasitic capacitance of the local bit line LBL. This allows the memory cell 42 to occupy a smaller area. This allows the semiconductor device 10 according to one aspect of the present invention to be miniaturized.

[0108] Furthermore, the semiconductor device 10 according to one aspect of the present invention can amplify slight changes in potential of the local bit line LBL by providing the sense circuit 35 in the layer 30. This allows the sense amplifier 55 provided in the substrate 50 to be miniaturized. This allows the semiconductor device 10 according to one aspect of the present invention to be miniaturized.

[0109] In the semiconductor device 10 according to one embodiment of the present invention, OS transistors with extremely low off-state current can be used as the transistors provided in the layer 30 and the layer 40. Therefore, the frequency of refreshing stored data in the memory cell 42 can be reduced. Therefore, the semiconductor device 10 according to one embodiment of the present invention can achieve low power consumption. Furthermore, in the semiconductor device 10 according to one embodiment of the present invention, layers 41[1] to 41[m] in which OS transistors are provided can be stacked vertically. Therefore, each of the layers 41[1] to 41[m] can be repeatedly manufactured using the same manufacturing process. Therefore, the semiconductor device 10 according to one embodiment of the present invention can achieve low manufacturing costs. Furthermore, in the semiconductor device 10 according to one embodiment of the present invention, layers 41[1] to 41[m] in which memory cells 42 are provided can be stacked vertically. Therefore, the memory density of the multiple memory cells 42 can be improved. Therefore, the semiconductor device 10 according to one embodiment of the present invention can be miniaturized. Furthermore, the semiconductor device 10 according to one embodiment of the present invention can use OS transistors whose electrical characteristics fluctuate less than those of Si transistors even in a high-temperature environment. Therefore, the semiconductor device 10 according to one embodiment of the present invention can be a highly reliable semiconductor device.

[0110] FIG. 3A is a schematic diagram of a layer 20 corresponding to any one of layers 20[1] to 20[k] shown in FIG.

[0111] The layer 20 shown in FIG. 3A includes layers 41[1] to 41[m], in which memory cells 42 are provided, arranged in the vertical direction (Z direction) above the layer 30. This configuration allows the distance between the layer 30 and the layers 41[1] to 41[m] to be reduced. This allows the length of the local bit line LBL to be shortened, thereby reducing parasitic capacitance. The layers 41[1] to 41[m] can be fabricated repeatedly in the vertical direction using the same manufacturing process, thereby reducing manufacturing costs.

[0112] FIG. 3B is a diagram showing the circuit symbols of the components in layer 20 shown in FIG. 3A.

[0113] Each of the layers 41[1] to 41[m] includes a plurality of memory cells 42. Each memory cell 42 includes a transistor 43 and a capacitor 44. One of the source or drain of the transistor 43 is electrically connected to one terminal (electrode) of the capacitor 44. The other of the source or drain of the transistor 43 is electrically connected to a local bit line LBL. The gate of the transistor 43 is electrically connected to a word line WL. The other terminal (electrode) of the capacitor 44 is electrically connected to a wiring CSL to which an arbitrary fixed potential is applied. Note that a region where one of the source or drain of the transistor 43 and one terminal of the capacitor 44 are electrically connected may be referred to as a node MND. The transistor 43 has a function of bringing the local bit line LBL and the node MND into a conductive state or a non-conductive state depending on the potential applied to the word line WL.

[0114] The transistor 43 may preferably have an extremely low off-state current. For example, an OS transistor may be used as the transistor 43. The capacitor 44 has a structure in which an insulator is sandwiched between conductors that serve as electrodes. Note that the conductors that form the electrodes may be made of metal or, for example, a semiconductor layer that has been given conductivity. The capacitor 44 may be configured, for example, to be disposed above or below the transistor 43 so as to overlap with the transistor 43, or to use part of the semiconductor layer or electrode that forms the transistor 43 as one electrode of the capacitor 44.

[0115] The memory cell 42 can retain the charge stored in the capacitor 44 for a long period of time by turning off the transistor 43. The memory cell 42 can store binary data by, for example, corresponding the level of the potential of the node MND, which corresponds to "1" or "0," depending on the amount of charge retained in the capacitor 44. When writing data, the memory cell 42 can apply a potential corresponding to the data to the node MND from the local bit line LBL by turning on the transistor 43. When reading data, the memory cell 42 can extract the charge retained in the node MND to the local bit line LBL by turning on the transistor 43.

[0116] Note that when data is read from the memory cell 42, the charge held at the node MND is extracted to the local bit line LBL, causing a change in the potential of the node MND. In other words, when data is read from the memory cell 42, the stored data is destroyed. That is, when data is read from the memory cell 42, a destructive read occurs. Therefore, after data is read from the memory cell 42, the data needs to be written back (refreshed).

[0117] The layer 30 includes a sense circuit 35. The sense circuit 35 includes transistors 31, 32, 33, and 34. One of the source or drain of the transistor 31 is electrically connected to one of the source or drain of the transistor 33 and one of the source or drain of the transistor 34. The other of the source or drain of the transistor 31 is electrically connected to one of the source or drain of the transistor 32. The gate of the transistor 31 is electrically connected to the other of the source or drain of the transistor 33 and a local bit line LBL. The other of the source or drain of the transistor 32 is electrically connected to a wiring SL. The other of the source or drain of the transistor 34 is electrically connected to a global bit line GBL. The transistor 31 has a function of passing a current between its source and drain in accordance with the potential of the local bit line LBL. The transistor 32 has a function of bringing the source and drain into a conductive or non-conductive state in accordance with a signal RE applied to its gate. The transistor 33 has a function of bringing the source and drain into a conductive or non-conductive state in response to a signal WE applied to its gate, and the transistor 34 has a function of bringing the source and drain into a conductive or non-conductive state in response to a signal MUX applied to its gate.

[0118] Transistors with extremely low off-state current are preferably used as the transistors 31 to 34. For example, OS transistors can be used as the transistors 31 to 34.

[0119] The sense circuit 35 changes the potential of the global bit line GBL by causing a current corresponding to the potential of the local bit line LBL to flow from the global bit line GBL to the wiring SL via the transistors 34, 31, and 32. The sense circuit 35 also transfers the potential of the global bit line GBL to the local bit line LBL via the transistors 34 and 33. The sense circuit 35 also changes the potential of the gate of the transistor 31 to a potential corresponding to the threshold voltage of the transistor 31 by discharging charge accumulated in the gate of the transistor 31 to the wiring SL via the transistors 33, 31, and 32. This function enables the sense circuit 35 to make corrections to reduce the influence of the threshold voltage of the transistor 31.

[0120] The sense circuit 35 may include a capacitor. In this case, one terminal of the capacitor may be electrically connected to the local bit line LBL, and the other terminal of the capacitor may be electrically connected to a wiring to which an arbitrary fixed potential is applied.

[0121] By using an OS transistor with extremely low off-state current as the transistor 33, the sense circuit 35 can hold charge accumulated on the local bit line LBL for a long period of time when the transistor 33 is turned off. Therefore, the sense circuit 35 can store binary data by, for example, corresponding a high or low potential depending on the amount of charge held on the local bit line LBL to “1” or “0.” That is, the sense circuit 35 can function as a memory. When writing data to the local bit line LBL, the sense circuit 35 functioning as a memory can apply a potential corresponding to the data to the local bit line LBL from the global bit line GBL by turning on the transistor 33. When reading data stored on the local bit line LBL, the sense circuit 35 functioning as a memory can read the data by applying a potential corresponding to the data to the gate of the transistor 31, causing a current corresponding to the data to flow between the source and drain of the transistor 31.

[0122] Note that when the sense circuit 35 functions as a memory, the charge held in the local bit line LBL does not change when data is read. In other words, when the sense circuit 35 functions as a memory, the stored data is not destroyed when data is read. In other words, when the sense circuit 35 functions as a memory, data is read non-destructively.

[0123] Here, a non-destructive readout memory using OS transistors is called NOSRAM (registered trademark). NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM (Random Access Memory). Therefore, the sense circuit 35 can be considered as a memory that operates like NOSRAM.

[0124] Fig. 4A shows a circuit diagram of the memory cell 42, which corresponds to the circuit diagram of the memory cell 42 shown in Fig. 3B. Fig. 4B shows a circuit block corresponding to the circuit diagram, which corresponds to the circuit block of the memory cell 42 shown in Fig. 1.

[0125] Fig. 4C shows a circuit diagram of the sense circuit 35, which corresponds to the circuit diagram of the sense circuit 35 shown in Fig. 3B. Fig. 4D shows a circuit block corresponding to the circuit diagram, which corresponds to the circuit block of the sense circuit 35 shown in Fig. 1.

[0126] 5A is a circuit diagram showing, by circuit symbols, a drive circuit 51 provided on a substrate 50. The drive circuit 51 includes a switch circuit 52, a precharge circuit 53, a precharge circuit 54, and a sense amplifier 55. The switch circuit 52, the precharge circuit 53, the precharge circuit 54, and the sense amplifier 55 are electrically connected to the global bit line SA_GBL and the global bit line SA_GBLB, respectively. The switch circuit 52 is electrically connected to the bit line BL and the bit line BLB. The drive circuit 51 has a function of controlling writing and reading of data to and from the memory cells 42.

[0127] The switch circuit 52 has a function of establishing a conductive state or a non-conductive state between the wiring pair of the global bit line SA_GBL and the global bit line SA_GBLB and the wiring pair of the bit line BL and the bit line BLB in response to the signal CSEL. Specifically, the switch circuit 52 includes a transistor 52_1 and a transistor 52_2. The transistors 52_1 and 52_2 are each an n-channel transistor. The transistor 52_1 has a function of establishing a conductive state or a non-conductive state between the global bit line SA_GBL and the bit line BL in response to the signal CSEL. The transistor 52_2 has a function of establishing a conductive state or a non-conductive state between the global bit line SA_GBLB and the bit line BLB in response to the signal CSEL.

[0128] The precharge circuit 53 has a function of precharging the global bit lines SA_GBL and SA_GBLB to a potential VPRE in response to a signal EQ. Specifically, the precharge circuit 53 includes transistors 53_1, 53_2, and 53_3. Each of the transistors 53_1, 53_2, and 53_3 is an n-channel transistor. The transistor 53_1 has a function of bringing the global bit lines SA_GBL and SA_GBLB into a conductive state or a non-conductive state in response to the signal EQ. The transistor 53_2 has a function of precharging the global bit line SA_GBL to a potential VPRE in response to the signal EQ. The transistor 53_3 has a function of precharging the global bit line SA_GBLB to a potential VPRE in response to the signal EQ.

[0129] The precharge circuit 54 has a function of precharging the global bit lines SA_GBL and SA_GBLB to a potential VPRE in response to a signal EQB. Specifically, the precharge circuit 54 includes a transistor 54_1, a transistor 54_2, and a transistor 54_3. Each of the transistors 54_1, 54_2, and 54_3 is a p-channel transistor. The transistor 54_1 has a function of turning on or off the global bit lines SA_GBL and SA_GBLB in response to the signal EQB. The transistor 54_2 has a function of precharging the global bit line SA_GBL to a potential VPRE in response to the signal EQB. The transistor 54_3 has a function of precharging the global bit line SA_GBLB to a potential VPRE in response to the signal EQB.

[0130] The sense amplifier 55 has a function of applying a predetermined potential to each of the wiring SAP and the wiring SAN to output a potential corresponding to one of the binary data values ​​to the global bit line SA_GBL and outputting a potential corresponding to the other of the binary data values ​​to the global bit line SA_GBLB. The sense amplifier 55 includes transistors 55_1, 55_2, 55_3, and 55_4. The transistors 55_1 and 55_2 are p-channel transistors. The transistors 55_3 and 55_4 are n-channel transistors. The transistors 55_1 and 55_3 configure an inverter that uses the global bit line SA_GBLB as an input, the global bit line SA_GBL as an output, the wiring SAP as a high-potential power supply line, and the wiring SAN as a low-potential power supply line. The transistor 55_2 and the transistor 55_4 configure an inverter that uses the global bit line SA_GBL as an input, the global bit line SA_GBLB as an output, the wiring SAP as a high-potential power supply line, and the wiring SAN as a low-potential power supply line.

[0131] FIG. 5B shows a circuit block corresponding to the circuit diagram of the drive circuit 51 described in FIG. 5A, and corresponds to the circuit block of the drive circuit 51 shown in FIG.

[0132] <Example of Operation of Semiconductor Device> Next, an example of operation of the semiconductor device 10 will be described with reference to FIGS. 6 and 7. FIG.

[0133] The semiconductor device 10 according to one aspect of the present invention has, as an example of a driving method, read mode 1 and read mode 2. Read mode 1 is a mode in which data stored in the memory cell 42 (the potential held at the node MND) is read by the sense amplifier 55 included in the drive circuit 51 via the sense circuit 35 and the switching circuit 37. Read mode 2 is a mode in which the potential held on the local bit line LBL is read by the sense amplifier 55 included in the drive circuit 51 via the sense circuit 35 and the switching circuit 37. In other words, read mode 2 is a mode in which, when the sense circuit 35 is made to function as a memory, the data stored on the local bit line LBL is read by the sense amplifier 55 included in the drive circuit 51 via the sense circuit 35 and the switching circuit 37.

[0134] In the following description of the operation example, as potentials corresponding to binary data, a potential corresponding to binary data "1" is a high power supply potential VDD (hereinafter may be abbreviated as VDD), and a potential corresponding to binary data "0" is a low power supply potential VSS (hereinafter may be abbreviated as VSS). VDD is a potential higher than VSS by at least a threshold voltage of a transistor. Note that VSS may be, for example, the ground potential GND. In the following description of the operation example, the potential of a signal is assumed to be an H level or an L level. The H level is a potential that, when applied to the gate of an n-channel transistor, turns the transistor conductive, and a potential that, when applied to the gate of a p-channel transistor, turns the transistor non-conductive. The L level is a potential that, when applied to the gate of an n-channel transistor, turns the transistor non-conductive, and a potential that, when applied to the gate of a p-channel transistor, turns the transistor conductive. The H level may be, for example, the same potential as VDD or a potential higher than VDD, and the L level may be, for example, the same potential as VSS or a potential lower than VSS.

[0135] Note that the H level or L level does not need to be the same potential for each of the multiple signals provided to the semiconductor device 10. The H level or L level potential of each of the multiple signals provided to the semiconductor device 10 may differ depending on the threshold voltage of the transistor to which the signal is provided. For example, the H level or L level potential of a signal provided to the gate of a Si transistor provided in the substrate 50 may differ from the H level or L level potential of a signal provided to the gate of an OS transistor provided in the layer 30 or 40. For example, if the threshold voltage of the OS transistor is higher than the threshold voltage of the Si transistor, the H level of the signal provided to the gate of the OS transistor can be higher than the H level of the signal provided to the gate of the Si transistor. For example, in the present embodiment and the like, the H level of each of the signals provided to the word line WL, the signal MUX, the signal WE, the signal RE, the signal SW0, the signal SW1, the signal SW2, and the signal SW3 can be higher than the H level of each of the signals EQ, the signal EQB, and the signal CSEL. In the following description of the operation example, for the sake of simplicity, the potential of all signals will be described as being at H level or L level.

[0136] Hereinafter, examples of operation in read mode 1 and read mode 2 will be described using the timing charts shown in FIGS. 6 and 7, respectively. The timing charts shown in FIGS. 6 and 7 each show the potentials (H level or L level) of the signal applied to the word line WL, the signal MUX, the signal WE, the signal RE, the signal SW0, the signal SW1, the signal SW2, the signal SW3, the signal EQ, the signal EQB, and the signal CSEL at each time of operation. They also show the potentials applied to the wiring SL, the wiring SAP, and the wiring SAN. They also show the changes in the potentials of the node MND of the memory cell 42, the local bit line LBL, the local bit line LBL_pre, the global bit line GBL, the global bit line GBLB, the global bit line SA_GBL, and the global bit line SA_GBLB when reading data "1" (data 1) and when reading data "0" (data 0).

[0137] In this specification, for example, a statement such as "at time T11, the signal becomes H level (or L level)" does not necessarily mean that the potential of the signal becomes constant at H level (or L level) at that instant. For example, even if the potential of the signal gradually changes due to parasitic resistance and parasitic capacitance of the wiring, and there is a slight signal delay until the signal becomes constant at H level (or L level), the statement will be expressed as "at time T11, the signal becomes H level (or L level)." Therefore, for example, the expression "time T11" can be replaced with the expression "approximate time T11" or "substantially time T11." This also applies to times other than time T11. In addition, in the timing chart drawings, the signal delay occurring as the potential of the signal gradually changes and becomes constant at H level (or L level) is indicated by diagonal lines. The signal delay time is, for example, less than 100 nanoseconds, preferably less than 10 nanoseconds, more preferably less than 1 nanosecond, and even more preferably less than 0.1 nanoseconds. Furthermore, the signal delay time may be different for each signal.

[0138] 6 is a timing chart illustrating an example of the operation of the semiconductor device 10 in read mode 1. The period from time T11 to time T13 is a period in which the threshold voltage is corrected. The period from time T13 to time T16 is a period in which data is read. The period from time T16 onwards is a period in which data is written back (refreshed).

[0139] Immediately before time T11, the signals MUX, WE, and RE applied to the word line WL are all set to the L level. The potential of the wiring SL is set to a predetermined potential (e.g., VSS). The signals SW0, SW1, SW2, and SW3 are all set to the L level. The signal EQ is set to the H level, and the signal EQB is set to the L level. The signal CSEL is set to the L level. The potentials of the wiring SAP and the wiring SAN are all set to VDD. The potentials VPRE and VPRE2 are all set to VDD. The potential of the wiring CSL is set to an arbitrary fixed potential (e.g., VSS). At this time, the global bit lines SA_GBL and SA_GBLB are all precharged to VDD. The global bit line GBL and the global bit line GBLB are each in an electrically floating state, and their respective potentials are VDD or VSS. The local bit line LBL and the local bit line LBL_pre are each in an electrically floating state, and are held at VDD or VSS. The node MND of the memory cell 42 is held at VDD (a potential corresponding to data "1") or VSS (a potential corresponding to data "0"). In the description of the operations at times T11 to T16, unless otherwise specified, the potentials of the wirings and signals are assumed to be maintained at the potentials at the immediately preceding times.

[0140] At time T11, signals SW1 and SW2 go high. Furthermore, signals MUX and WE go high. Then, the global bit line GBL and the global bit line GBLB are precharged to VDD. Furthermore, the local bit line LBL and the local bit line LBL_pre are precharged to VDD. Furthermore, the potential of the line SL becomes a predetermined potential between VDD and VSS. This predetermined potential affects the amount of current flowing through the transistor 31 in the operation at time T14, which will be described later. Therefore, the predetermined potential can be determined so that the amount of current becomes an appropriate value.

[0141] At time T12, the signal MUX goes low and the signal RE goes high, causing the potentials of the local bit lines LBL and LBL_pre to drop to "the potential of the line SL plus the threshold voltage of the transistor 31" due to discharge to the line SL via the transistor 31 included in each of the sense circuit 35 and the sense circuit 35_pre.

[0142] At time T13, signals WE and RE go low. This causes local bit line LBL and local bit line LBL_pre to be electrically floating. This causes potentials corresponding to the threshold voltages of transistors 31 included in sense circuit 35 and sense circuit 35_pre to be held on local bit line LBL and local bit line LBL_pre, respectively. This allows the amount of current flowing through transistor 31 in the operation at time T14, described below, to be corrected so that it is not affected by the threshold voltage of transistor 31. By performing such correction, semiconductor device 10 according to an aspect of the present invention can improve the reliability of read data.

[0143] At time T13, signal EQ goes low and signal EQB goes high. This stops precharging global bit lines SA_GBL and GBL, and global bit lines SA_GBLB and GBLB. This causes global bit lines SA_GBL and GBL, and global bit lines SA_GBLB and GBLB, to each enter an electrically floating state.

[0144] Also, at time T13, the signal applied to the word line WL on the side of the memory cell 42 electrically connected to the local bit line LBL goes high. Charge sharing then occurs between the local bit line LBL and the node MND. Therefore, the potential of the local bit line LBL changes according to the data stored in the memory cell 42 (i.e., according to the potential held at the node MND). This causes the potential of the local bit line LBL and the potential of the node MND to become the same potential.

[0145] Specifically, for example, when the data stored in the memory cell 42 is "1" (data 1) (i.e., the potential held at the node MND is VDD), a signal applied to the word line WL goes high, causing the potential of the local bit line LBL to rise and the potential of the node MND to fall. As a result, the potentials of the local bit line LBL and the node MND become the same potential. Alternatively, for example, when the data stored in the memory cell 42 is "0" (data 0) (i.e., the potential held at the node MND is VSS), a signal applied to the word line WL goes high, causing the potential of the local bit line LBL to fall and the potential of the node MND to rise. As a result, the potentials of the local bit line LBL and the node MND become the same potential.

[0146] On the other hand, at time T13, the signal applied to the word line WL on the side of the memory cell 42 electrically connected to the local bit line LBL_pre remains at the L level. That is, charge sharing is not performed on the local bit line LBL_pre. Therefore, the potential of the local bit line LBL does not change.

[0147] Charge sharing changes the potential of node MND. That is, the data stored in memory cell 42 is destroyed. In other words, read mode 1 is a destructive read. Therefore, data is written back in the operation at time T16, which will be described later.

[0148] At time T14, signals MUX and RE go high. Furthermore, the potential of line SL goes to the same potential (e.g., VSS) as the potential immediately before time T11. Then, current flows through transistor 31 of sense circuit 35 and transistor 31 of sense circuit 35_pre, depending on the respective potentials of local bit line LBL and local bit line LBL_pre. This causes the respective potentials of global bit line SA_GBL and global bit line GBL, and global bit line SA_GBLB and global bit line GBLB to gradually decrease. At this time, the difference between the potential of local bit line LBL and the potential of local bit line LBL_pre causes a difference between the amount of current flowing through transistor 31 of sense circuit 35 and the amount of current flowing through transistor 31 of sense circuit 35_pre. This difference in current amount corresponds to the potential of local bit line LBL, which changes due to charge sharing in the operation at time T13 described above. That is, the speed at which the potentials of the global bit lines SA_GBL and GBL drop varies depending on the potential of the local bit line LBL. Therefore, the potential of the local bit line LBL can be converted into a potential difference between the global bit lines SA_GBL and SA_GBLB.

[0149] Specifically, for example, when the data stored in the memory cell 42 is "1" (data 1), the amount of current flowing through the transistor 31 included in the sense circuit 35 is greater than the amount of current flowing through the transistor 31 included in the sense circuit 35_pre. Therefore, the rate at which the potentials of the global bit lines SA_GBL and GBL fall is faster than the rate at which the potentials of the global bit lines SA_GBLB and GBLB fall. As a result, the potential of the global bit line SA_GBL becomes lower than the potential of the global bit line SA_GBLB. Alternatively, for example, when the data stored in the memory cell 42 is "0" (data 0), the amount of current flowing through the transistor 31 included in the sense circuit 35 is smaller than the amount of current flowing through the transistor 31 included in the sense circuit 35_pre. Therefore, the rate at which the potentials of global bit lines SA_GBL and GBL drop is slower than the rate at which the potentials of global bit lines SA_GBLB and GBLB drop, causing the potential of global bit line SA_GBL to become higher than the potential of global bit line SA_GBLB.

[0150] At time T15, signal RE goes low. Furthermore, the potential of line SAN goes to VSS. Then, the sense amplifier 55 operates, amplifying the potential difference between global bit line SA_GBL and global bit line SA_GBLB, which occurred as a result of the operation at time T14 described above. This causes the potentials of global bit line SA_GBL and global bit line SA_GBLB to be determined as either VDD or VSS. In other words, reading of the data stored in memory cell 42 is completed.

[0151] Specifically, for example, when the data stored in the memory cell 42 is "1" (data 1), the potential of the global bit line SA_GBL becomes VSS and the potential of the global bit line SA_GBLB becomes VDD. Alternatively, for example, when the data stored in the memory cell 42 is "0" (data 0), the potential of the global bit line SA_GBL becomes VDD and the potential of the global bit line SA_GBLB becomes VSS.

[0152] At time T16, signal SW0 goes high and signal SW1 goes low. Furthermore, signal WE goes high. Then, an operation to write data back to the memory cell 42 is performed in accordance with the data read from the memory cell 42. That is, the potentials of the global bit line GBL and the local bit line LBL become the same as the potential of the global bit line SA_GBLB established by the operation at time T15. Furthermore, this potential is written back to the memory cell 42.

[0153] Specifically, for example, if the data stored in the memory cell 42 is "1" (data 1), the potential of the global bit line SA_GBLB immediately before time T16 is VDD. Therefore, the potentials of the global bit line GBL and the local bit line LBL become VDD. Furthermore, VDD is written back to the memory cell 42. Alternatively, for example, if the data stored in the memory cell 42 is "0" (data 0), the potential of the global bit line SA_GBLB immediately before time T16 is VSS. Therefore, the potentials of the global bit line GBL and the local bit line LBL become VSS. Furthermore, VSS is written back to the memory cell 42.

[0154] When writing data to the memory cell 42, the semiconductor device 10 may perform the same operation as the time T16 described above. For example, when writing data "1" to the memory cell 42, VDD may be applied to the global bit line SA_GBLB, as at time T16. Alternatively, when writing data "0" to the memory cell 42, VSS may be applied to the global bit line SA_GBLB, as at time T16.

[0155] [Read Mode 2] FIG. 7 is a timing chart illustrating an example of the operation of the semiconductor device 10 in read mode 2. The period from time T21 to time T24 is a period during which data is read. Note that in read mode 2, the data stored in the memory cell 42 is not related to the data read. Furthermore, the potential of the local bit line LBL_pre is also not related to the data read. Therefore, FIG. 7 does not illustrate the potentials of the node MND and the local bit line LBL_pre. Furthermore, the potential of the global bit line GBLB is also not illustrated.

[0156] Immediately before time T21, the signals MUX, WE, and RE applied to the word line WL are all set to the L level. The potential of the wiring SL is set to a predetermined potential (e.g., VSS). The signals SW0, SW1, SW2, and SW3 are all set to the L level. The signal EQ is set to the H level, and the signal EQB is set to the L level. The signal CSEL is set to the L level. The potentials of the wiring SAP and the wiring SAN are each set to (VDD-VSS) / 2. The potential VPRE is set to (VDD-VSS) / 2, and the potential VPRE2 is set to a potential (e.g., VDD) that exceeds (VDD-VSS) / 2 but does not exceed VDD. The potential of the wiring CSL is set to an arbitrary fixed potential (e.g., VSS). At this time, the global bit lines SA_GBL and SA_GBLB are each precharged to (VDD-VSS) / 2. The global bit lines GBL and GBLB are each in an electrically floating state, and their respective potentials are VDD or VSS. The local bit line LBL is also in an electrically floating state, and is held at VDD (a potential corresponding to data "1") or VSS (a potential corresponding to data "0"). In the description of the operations at times T21 to T24, unless otherwise specified, the potentials of the wirings and signals are assumed to be maintained at the potentials at the immediately preceding times.

[0157] At time T21, signal EQ goes low and signal EQB goes high, stopping precharging of global bit lines SA_GBL and SA_GBLB. As a result, global bit lines SA_GBL and SA_GBLB each go into an electrically floating state.

[0158] At time T22, signals SW1 and SW3 go high. This causes global bit line SA_GBL and global bit line GBL to be precharged to a potential between VDD and (VDD-VSS) / 2. That is, the potential of global bit line SA_GBL becomes higher than the potential of global bit line SA_GBLB.

[0159] At time T23, signal SW3 goes low. This stops precharging global bit lines SA_GBL and GBL. Then, signals MUX and RE go high. This causes the potentials of global bit lines SA_GBL and GBL to change according to the potential of local bit line LBL. Therefore, the potential of local bit line LBL can be converted into a potential difference between global bit lines SA_GBL and SA_GBLB.

[0160] Specifically, for example, when the data stored in the sense circuit 35 functioning as a memory is "1" (data 1) (i.e., the potential held on the local bit line LBL is VDD), a current flows through the transistor 31 included in the sense circuit 35, causing the potentials of the global bit line SA_GBL and the global bit line GBL to gradually decrease. As a result, the potential of the global bit line SA_GBL becomes lower than the potential of the global bit line SA_GBLB. Alternatively, for example, when the data stored in the sense circuit 35 functioning as a memory is "0" (data 0) (i.e., the potential held on the local bit line LBL is VSS), the transistor 31 included in the sense circuit 35 becomes non-conductive, thereby maintaining the potentials of the global bit line SA_GBL and the global bit line GBL. As a result, the potential of the global bit line SA_GBL remains higher than the potential of the global bit line SA_GBLB.

[0161] The operation at time T23 does not change the potential of the local bit line LBL. That is, the data stored in the sense circuit 35 functioning as a memory is not destroyed. That is, read mode 2 is a non-destructive read.

[0162] At time T24, signals MUX and RE go low. Furthermore, the potential of line SAN goes to VSS, and the potential of line SAP goes to VDD. Then, the sense amplifier 55 operates, amplifying the potential difference between global bit line SA_GBL and global bit line SA_GBLB that occurred as a result of the operation at time T23 described above. This causes the potentials of global bit line SA_GBL and global bit line SA_GBLB to be fixed at either VDD or VSS. In other words, reading of the data stored in the sense circuit 35, which functions as a memory, is completed.

[0163] Specifically, for example, when the data stored in the sense circuit 35 functioning as a memory is "1" (data 1), the potential of the global bit line SA_GBL becomes VSS and the potential of the global bit line SA_GBLB becomes VDD. Alternatively, for example, when the data stored in the sense circuit 35 functioning as a memory is "0" (data 0), the potential of the global bit line SA_GBL becomes VDD and the potential of the global bit line SA_GBLB becomes VSS.

[0164] When writing data to the sense circuit 35 functioning as a memory, the semiconductor device 10 may, for example, set the signal applied to the word line WL to the L level, similar to the time T16 described above. For example, when writing data "1" to the sense circuit 35 functioning as a memory, the signal applied to the word line WL may be set to the L level and VDD may be applied to the global bit line SA_GBLB, similar to the time T16. Alternatively, when writing data "0" to the sense circuit 35 functioning as a memory, the signal applied to the word line WL may be set to the L level and VSS may be applied to the global bit line SA_GBLB, similar to the time T16.

[0165] Read mode 1 is a mode in which data stored in the memory cell 42 is read. The memory cell 42 occupies a smaller area than the sense circuit 35 functioning as a memory. Furthermore, since the memory cells 42 can be stacked, memory density is high. Read mode 2 is a mode in which data stored in the sense circuit 35 functioning as a memory is read. Read mode 2 does not require a period for correcting the threshold voltage or a period for writing back data, so data can be read faster than read mode 1. Furthermore, the energy required for reading (access energy) is low. The semiconductor device 10 according to one embodiment of the present invention can appropriately use read mode 1 and read mode 2 depending on the situation or purpose. The semiconductor device 10 according to one embodiment of the present invention can appropriately use read mode 1 and read mode 2 depending on the situation or purpose, thereby achieving high-speed data reading and reduced power consumption.

[0166] In the semiconductor device 10 according to one embodiment of the present invention, when reading in read mode 1 is completed, a potential corresponding to the data read from the memory cell 42 is held on the local bit line LBL. That is, the data previously read from the memory cell 42 is stored in the sense circuit 35, which functions as a memory. Therefore, when data needs to be read from the same memory cell 42 again, the data can be read in read mode 2. This allows data to be read faster. Furthermore, the energy required for reading (access energy) can be reduced. Therefore, the semiconductor device 10 can achieve high-speed data reading and reduced power consumption.

[0167] The semiconductor device 10 according to one embodiment of the present invention has the above-described read mode 1 and read mode 2 as driving methods, and thus can be suitably used in, for example, an electronic computer. For example, the memory cells 42 provided in each of the layers 41[1] to 41[m] can be used as a main memory provided in the electronic computer, and the sense circuits 35 provided in the layer 30 can be used as a cache memory provided in the electronic computer. In this case, read mode 1 corresponds to a mode for accessing the main memory, and read mode 2 corresponds to a mode for accessing the cache memory.

[0168] An example in which the semiconductor device 10 according to one embodiment of the present invention is used in a computer will be described in detail later.

[0169] <Configuration Example of Memory Device> A semiconductor device according to one embodiment of the present invention can be suitably used as a memory device. Here, a memory device according to one embodiment of the present invention to which the above-described semiconductor device 10 is applied will be described. Note that in the memory device described below, the above description can be appropriately referred to for the parts to which the semiconductor device 10 is applied, and therefore the same reference numerals may be used in the drawings and the like, and the description may be omitted.

[0170] 8 is a block diagram illustrating a configuration example of a memory device 300 according to one embodiment of the present invention. The memory device 300 using the semiconductor device 10 shown in FIG. 8 includes a memory array 21 and a driver circuit 22. The memory array 21 includes a plurality of sense circuits 35 and a switching circuit 37 provided in a layer 30, and a plurality of memory cells 42 provided in layers 41[1] to 41[m]. The driver circuit 22 is provided on a substrate 50 (not shown).

[0171] 8 includes, as an example, m×n memory cells 42 arranged in a matrix of m rows and n columns, where m and n are integers equal to or greater than 2. The memory array 21 also includes, as an example, n sense circuits 35 arranged for each column.

[0172] In FIG. 8, the memory cell 42 in the first row and first column is indicated as memory cell 42[1,1], and the memory cell 42 in the mth row and nth column is indicated as memory cell 42[m,n]. In the present embodiment and the like, an arbitrary row may be referred to as row i. In the present embodiment and the like, an arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. In the present embodiment and the like, the memory cell 42 in the ith row and jth column is referred to as memory cell 42[i,j]. In the present embodiment and the like, when "i+α" (α is a positive or negative integer) is used, "i+α" is not less than 1 and not more than m. Similarly, when "j+α" is used, "j+α" is not less than 1 and not more than n.

[0173] In addition, in Figure 8, the sense circuit 35 provided in the first column is shown as sense circuit 35[1], the sense circuit 35 provided in the jth column is shown as sense circuit 35[j], and the sense circuit 35 provided in the nth column is shown as sense circuit 35[n].

[0174] The memory array 21 also includes m word lines WL extending in the row direction, m interconnections CSL extending in the row direction, and n local bit lines LBL extending in the column direction. In this embodiment and the like, the first word line WL (first row) is referred to as word line WL[1], and the mth word line WL (mth row) is referred to as word line WL[m]. Similarly, the first interconnection CSL (first row) is referred to as interconnect CSL[1], and the mth interconnection CSL (mth row) is referred to as interconnect CSL[m]. Similarly, the first local bit line LBL (first column) is referred to as local bit line LBL[1], and the nth local bit line LBL (nth column) is referred to as local bit line LBL[n].

[0175] The n memory cells 42 provided in the i-th row are electrically connected to the i-th word line WL (word line WL[i]) and the i-th wiring CSL (wiring CSL[i]). The m memory cells 42 provided in the j-th column are electrically connected to the j-th local bit line LBL (local bit line LBL[j]).

[0176] The sense circuit 35 provided in the jth column (sense circuit 35[j]) is electrically connected to the local bit line LBL in the jth column (local bit line LBL[j]). The switching circuit 37 is electrically connected to the n sense circuits 35 via a global bit line GBL (not shown). The switching circuit 37 is also electrically connected to a drive circuit 51 including a sense amplifier 55, which is included in the drive circuit 22, via a global bit line SA_GBL.

[0177] The drive circuit 22 includes a PSW 62 (power switch), a PSW 63, and a peripheral circuit 71. The peripheral circuit 71 includes a peripheral circuit 81, a control circuit 72, and a voltage generation circuit 73.

[0178] Note that a part of the peripheral circuit 71 may be provided on the layer 30 .

[0179] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Other circuits or signals may also be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside. The signal RDA is an output signal to the outside.

[0180] Signal CLK is a clock signal. Signals BW, CE, and GW are control signals. Signal CE is a chip enable signal. Signal GW is a global write enable signal. Signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data. Signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by control circuit 72.

[0181] The control circuit 72 is a logic circuit having the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode of the memory device 300 (for example, a write operation or a read operation (for example, read mode 1 or read mode 2)). Alternatively, the control circuit 72 generates a control signal for the peripheral circuit 81 so that this operation mode is executed.

[0182] The voltage generating circuit 73 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 73. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 73, and the voltage generating circuit 73 generates a negative voltage.

[0183] The peripheral circuit 81 is a circuit for writing or reading data to or from the memory cells 42. The peripheral circuit 81 is also a circuit for outputting various signals for controlling the sense circuit 35 and the switching circuit 37. The peripheral circuit 81 includes a row decoder 82, a column decoder 84, a row driver 83, a column driver 85, an input circuit 87, an output circuit 88, and a drive circuit 51 including a sense amplifier 55.

[0184] The row decoder 82 and the column decoder 84 have the function of decoding the signal ADDR. The row decoder 82 is a circuit for specifying a row to be accessed. The column decoder 84 is a circuit for specifying a column to be accessed. The row driver 83 has the function of selecting a word line WL specified by the row decoder 82. The column driver 85 has the function of writing data to the memory cells 42, reading data from the memory cells 42, or retaining the read data, for example.

[0185] The input circuit 87 has a function of holding a signal WDA. The data held by the input circuit 87 is output to the column driver 85. The output data of the input circuit 87 is data (data Din) to be written to the memory cell 42. The data (data Dout) read from the memory cell 42 by the column driver 85 is output to the output circuit 88. The output circuit 88 has a function of holding the data Dout. The output circuit 88 also has a function of outputting the data Dout to the outside of the memory device 300. The data output from the output circuit 88 is the signal RDA.

[0186] The PSW 62 has a function of controlling the supply of VDD to the peripheral circuit 71. The PSW 63 has a function of controlling the supply of a potential VHM to the row driver 83. Here, the high power supply potential of the memory device 300 is VDD, and the low power supply potential is the ground potential GND (or may be VSS). The potential VHM is a high power supply potential used to set the word line to an H level and is higher than VDD. The PSW 62 is controlled to an ON or OFF state by a signal PON1. The PSW 63 is controlled to an ON or OFF state by a signal PON2. In FIG. 8 , the number of power domains to which VDD is supplied in the peripheral circuit 71 is one, but multiple power domains may also be used. In this case, the drive circuit 22 may be provided with a power switch for each power domain.

[0187] As in the above description of the semiconductor device 10, the layer 30 and the layers 41[1] to 41[m] may be stacked vertically on the substrate 50.

[0188] FIG. 9A is a perspective view showing, as an example, a memory device 300 in which a layer 30 and five layers (m=5) of layers 41[1] to 41[5] are stacked in the vertical direction on a substrate 50. FIG. 9A illustrates a plurality of memory cells 42 arranged in each of layers 41[1] to 41[5]. It also illustrates a plurality of sense circuits 35 arranged in layer 30. It also illustrates word lines WL and wiring CSL extending in the X direction, and local bit lines LBL extending in the Z direction (the vertical direction on the substrate 50 on which the drive circuit 22 is provided). Note that, for clarity of illustration, the word lines WL and wiring CSL are partially omitted.

[0189] 9B is a schematic diagram showing an example configuration of a sense circuit 35 and a plurality of memory cells 42 electrically connected to one of the plurality of local bit lines LBL shown in FIG. 9A. FIG. 9B also shows a switching circuit 37 and a drive circuit 51 provided in the drive circuit 22. The switching circuit 37 is electrically connected to the sense circuit 35 via a global bit line GBL. The switching circuit 37 is also electrically connected to the drive circuit 51 via a global bit line SA_GBL. Note that the configuration shown in FIG. 9B in which a plurality of memory cells 42 are electrically connected to one local bit line LBL is also referred to as a "memory string."

[0190] The local bit line LBL is provided in contact with the semiconductor layer of the transistor included in the memory cell 42. Alternatively, the local bit line LBL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 42. Alternatively, the local bit line LBL is provided in contact with a conductor that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 42. In other words, the local bit line LBL is a wiring that electrically connects the other of the source or the drain of the transistor included in each of the multiple memory cells 42 provided in the layers 41[1] to 41[5] to the sense circuit 35 in the vertical direction.

[0191] By applying the semiconductor device 10 described above, the memory device 300 according to one embodiment of the present invention can stack a plurality of sense circuits 35, a switching circuit 37, and a plurality of memory cells 42 in a vertical direction above the drive circuit 22 including the sense amplifier 55. This allows the memory device 300 according to one embodiment of the present invention to achieve, for example, improved memory density, reduced manufacturing costs, reduced power consumption, reduced signal delay, and miniaturization.

[0192] Furthermore, by applying the above-described semiconductor device 10, the memory device 300 according to one embodiment of the present invention can be driven in read mode 1 and read mode 2. By having the above-described read mode 1 and read mode 2, the memory device 300 according to one embodiment of the present invention can be suitably used in, for example, a computer.

[0193] <Configuration Example of Electronic Computer> A semiconductor device according to one embodiment of the present invention can be suitably used in an electronic computer. Furthermore, a memory device according to one embodiment of the present invention can be suitably used in an electronic computer. Here, an example in which the above-described semiconductor device 10 is applied to an electronic computer will be described. Note that in the electronic computer described below, the above description can be appropriately taken into consideration for parts to which the semiconductor device 10 is applied, and therefore, the same reference numerals may be used in drawings and the like, and description thereof may be omitted.

[0194] 10 is a schematic diagram showing an electronic computer 90 according to one embodiment of the present invention. The electronic computer 90 includes a processor 91 (CPU) and a main memory 92. The processor 91 includes a core 93, a cache memory 94, and an interface 95 (I / F).

[0195] The processor 91 has a function of accessing the cache memory 94 and storing (also referred to as loading) instructions or data stored in the cache memory 94 into a register (not shown) provided in the core 93 via an interface 95. The processor 91 also has a function of performing a predetermined calculation based on the instructions or data stored in the register. The processor 91 also has a function of accessing the main memory 92 and reading the desired instructions or data stored in the main memory 92 into the cache memory 94 if the instruction or data stored in the register by loading is not the instruction or data desired by the core 93 (also referred to as a cache miss).

[0196] As an example of applying the semiconductor device 10 described above, the electronic computer 90 uses multiple memory cells 42 provided in the semiconductor device 10 as the main memory 92, uses sense circuits 35 functioning as multiple memories provided in the semiconductor device 10 as the cache memory 94, and uses the drive circuit 51 provided in the semiconductor device 10 as the interface 95.

[0197] 10, the core 93 and the interface 95 are provided on the substrate 50, the cache memory 94 is provided on the layer 30, and the main memory 92 is provided on each of the layers 41[1] to 41[m]. Furthermore, the layer 30 on which the cache memory 94 is provided and the layers 41[1] to 41[m] on which the main memory 92 is provided are stacked in the vertical direction on the substrate 50 on which the core 93 and the interface 95 are provided.

[0198] As described above, the configuration of the memory cell 42 can be called DOSRAM. DOSRAM can be used as a main memory, replacing DRAM (Dynamic Random Access Memory), which is generally used as a main memory. Like DRAM, DOSRAM is composed of one transistor and one capacitor. However, by using an OS transistor with extremely low off-state current as the transistor, data can be stored for a long period of time. Therefore, DOSRAM can significantly reduce the refresh cycle compared to DRAM. For example, while the refresh cycle of DRAM is milliseconds or less, the refresh cycle of DOSRAM can be approximately one hour to one year. Furthermore, DOSRAM can be arranged, for example, in multiple layers on a silicon substrate on which a sense amplifier is provided. These features enable DOSRAM to operate faster and consume less access energy (energy consumed when writing or reading data) than DRAM.

[0199] Furthermore, as described above, the sense circuit 35 can be considered a non-oscillating random access memory (NOSRAM) by functioning as a memory. NOSRAM is a non-volatile memory that stores data by retaining charge for a long period of time, taking advantage of the characteristics of OS transistors, which have extremely low off-state current. Furthermore, NOSRAM has the advantage that, in principle, there is no limit to the number of rewrites and that multi-level data can be written. NOSRAM can be used as a cache memory instead of an SRAM (Static Random Access Memory), which is generally used as a cache memory. NOSRAM can be freely arranged, for example, on a layer on a silicon substrate on which a processor core is provided, making integration easy.

[0200] In other words, the electronic computer 90 can be configured such that, on a silicon substrate on which the processor core is provided, a layer on which NOSRAM (sense circuit 35) functioning as cache memory is provided is arranged, and further, multiple layers on which DOSRAM (memory cells 42) functioning as main memory is arranged are arranged.

[0201] <Example of Operation of Electronic Computer> Next, an example of operation of the electronic computer 90 according to one embodiment of the present invention will be described. The electronic computer 90 can be driven by the above-described method for driving the semiconductor device 10.

[0202] FIG. 11A is a flowchart showing an example of the operation of the electronic computer 90. In order to perform a predetermined operation, the electronic computer 90 needs to load a desired instruction or data into a register included in the core 93. The flowchart shown in FIG. 11A shows a method for driving the electronic computer 90 when loading the desired instruction or data into a register included in the core 93. As shown in FIG. 11A, the electronic computer 90 has steps S01, S02, and S03. When loading of the desired instruction or data begins (START), step S01 is first performed.

[0203] In step S01, the cache memory 94 is accessed in access mode 1. FIG. 11B is a diagram schematically illustrating the operation of the electronic computer 90 in access mode 1. That is, the electronic computer 90 loads instructions or data stored in the cache memory 94 into a register provided in the core 93 via the interface 95. Note that access mode 1 corresponds to read mode 2 of the semiconductor device 10 described above (see FIG. 7 as appropriate). That is, the electronic computer 90 reads data stored in the sense circuit 35, which functions as a memory. Next, step S02 is performed.

[0204] In step S02, it is determined whether the instruction or data loaded into the register of the core 93 in step S01 is a cache miss (determination of cache miss). If the determination in step S02 is "YES," i.e., if the instruction or data stored in the register of the core 93 is not the instruction or data desired by the core 93 (cache miss), step S03 is performed. Alternatively, if the determination in step S02 is "NO," i.e., if the instruction or data stored in the register of the core 93 is the instruction or data desired by the core 93 (cache hit), the loading of the instruction or data is completed (END). Thereafter, although not shown, a predetermined operation is performed based on the instruction or data stored in the register.

[0205] In step S03, the main memory 92 is accessed in access mode 2. FIG. 11C is a diagram schematically illustrating the operation of the electronic computer 90 in access mode 2. That is, the electronic computer 90 loads desired instructions or data stored in the main memory 92 into a register included in the core 93 via the cache memory 94 and the interface 95, and completes (ENDs) the loading of the instructions or data. Thereafter, although not shown, a predetermined calculation is performed based on the instructions or data stored in the register. Note that access mode 2 corresponds to read mode 1 of the semiconductor device 10 described above (see FIG. 6 as appropriate). That is, the electronic computer 90 reads data stored in the memory cells 42.

[0206] Note that the electronic computer 90 according to one embodiment of the present invention is not limited to the above-described configuration example. For example, the electronic computer 90 may include a primary cache memory provided on the substrate 50 and a secondary cache memory provided on the layer 30, instead of the cache memory 94. In this case, the electronic computer 90 may use, for example, an SRAM for the primary cache memory and the sense circuit 35 functioning as one of the memories provided in the semiconductor device 10 for the secondary cache memory, and may preferably use the above-described operational example. Furthermore, for example, the electronic computer 90 may include a primary cache memory to a pth-level cache memory (p is an integer greater than or equal to 2) provided on the substrate 50 and a p+1th-level cache memory provided on the layer 30. In this case, the electronic computer may use, for example, an SRAM for each of the primary cache memory to the pth-level cache memory and the sense circuit 35 functioning as one of the memories provided in the semiconductor device 10 for the pth-level cache memory, and may preferably use the above-described operational example. Furthermore, for example, the electronic computer 90 may include a storage class memory in addition to the above-described configuration. In this case, the electronic computer 90 may use, for example, the multiple memory cells 42 included in the semiconductor device 10 as the storage class memory, and may preferably use the above-described example of operation.

[0207] By applying the configuration of the semiconductor device 10 and the driving method of the semiconductor device 10 described above, the electronic computer 90 according to one embodiment of the present invention can achieve, for example, improved memory density, reduced manufacturing costs, reduced power consumption, reduced signal delay, and miniaturization.

[0208] Note that a semiconductor device according to one embodiment of the present invention is not limited to the semiconductor device 10 described above. A memory device according to one embodiment of the present invention is not limited to the memory device 300 described above. A computer according to one embodiment of the present invention is not limited to the computer 90 described above. At least part of the configuration examples, operation examples, and corresponding drawings described in this embodiment can be combined as appropriate with other configuration examples, operation examples, other drawings, other embodiments or other examples described in this specification, etc.

[0209] (Embodiment 2) In this embodiment, a semiconductor device 10A according to one aspect of the present invention will be described. The semiconductor device 10A is a modified example of the semiconductor device 10 described in the above-mentioned embodiment 1. Therefore, in order to reduce repetition of the description, differences between the semiconductor device 10A and the semiconductor device 10 will be mainly described. Note that the description of the semiconductor device 10 described above can be taken into consideration as appropriate.

[0210] <Structural Example of Semiconductor Device> FIG. 12 is a circuit diagram illustrating a structural example of a semiconductor device 10A of one embodiment of the present invention.

[0211] The semiconductor device 10A differs from the semiconductor device 10 in that it includes a switching circuit 37A instead of the switching circuit 37. The switching circuit 37A differs from the switching circuit 37 in that it includes capacitors C1 and C2 instead of the transistors M3 and M4.

[0212] The switching circuit 37A is electrically connected to the sense circuit 35 via the global bit line GBL. The switching circuit 37A is also electrically connected to the sense circuit 35_pre via the global bit line GBLB. The switching circuit 37A is also electrically connected to a drive circuit 51 provided on the substrate 50 via the global bit line SA_GBL and the global bit line SA_GBLB. The switching circuit 37A has a function of establishing a conductive state or a non-conductive state between the global bit line GBL, the global bit line GBLB, the global bit line SA_GBL, and the global bit line SA_GBLB. The switching circuit 37A also has a function of changing the potentials of the global bit line GBL and the global bit line GBLB.

[0213] The switching circuit 37A includes a transistor M0, a transistor M1, a transistor M2, a capacitor C1, and a capacitor C2. Note that the transistors included in the switching circuit 37A are preferably transistors with extremely low off-state current. For example, the transistors included in the switching circuit 37A can be OS transistors.

[0214] One of the source and drain of the transistor M0 is electrically connected to the global bit line GBL. The other of the source and drain of the transistor M0 is electrically connected to the global bit line GBLB. The transistor M0 has a function of bringing the global bit line GBL and the global bit line GBLB into a conductive state or a non-conductive state in response to a signal SW0.

[0215] One of the source and drain of the transistor M1 is electrically connected to the global bit line GBL. The other of the source and drain of the transistor M1 is electrically connected to the global bit line SA_GBL. The transistor M1 has a function of bringing the global bit line GBL and the global bit line SA_GBL into a conductive state or a non-conductive state in response to a signal SW1.

[0216] One of the source and drain of the transistor M2 is electrically connected to the global bit line GBLB. The other of the source and drain of the transistor M2 is electrically connected to the global bit line SA_GBLB. The transistor M2 has a function of bringing the global bit line GBLB and the global bit line SA_GBLB into a conductive state or a non-conductive state in response to a signal SW2.

[0217] One terminal of the capacitor C1 is electrically connected to the global bit line GBL, and the other terminal of the capacitor C1 is electrically connected to a terminal to which a signal BOOT1 is applied. The capacitor C1 has a function of changing the potential of the global bit line GBL in response to the signal BOOT1.

[0218] One terminal of the capacitor C2 is electrically connected to the global bit line GBLB, and the other terminal of the capacitor C2 is electrically connected to a terminal to which a signal BOOT2 is applied. The capacitor C2 has a function of changing the potential of the global bit line GBLB in response to the signal BOOT2.

[0219] <Operation Example of Semiconductor Device> Next, an operation example of the semiconductor device 10A will be described with reference to FIGS. 13 and 14. FIG.

[0220] The semiconductor device 10A according to one embodiment of the present invention has, as with the semiconductor device 10 described above, a read mode 1 and a read mode 2 as examples of driving methods.

[0221] 13 and 14, examples of operation in read mode 1 and read mode 2 will be described below. The timing charts shown in Figures 13 and 14 differ from the timing charts shown in Figures 6 and 7 in that they show the potentials (H level or L level) of signals BOOT1 and BOOT2 instead of signal SW3.

[0222] [Read Mode 1] FIG. 13 is a timing chart illustrating an example of the operation of the semiconductor device 10A in read mode 1.

[0223] Immediately before time T11 and at each of times T11 to T13, signals BOOT1 and BOOT2 are at L level. Signals other than signals BOOT1 and BOOT2 are the same as those in the timing chart shown in Figure 6. Therefore, the description of read mode 1 of semiconductor device 10A can be appropriately taken into consideration, and therefore a description thereof will be omitted.

[0224] [Read Mode 2] FIG. 14 is a timing chart illustrating an example of the operation of the semiconductor device 10A in read mode 2. The period from time T21 to time T24 is the period during which data is read. Note that in read mode 2, the data stored in the memory cell 42 is not related to the data read. Furthermore, the potential of the local bit line LBL_pre is also not related to the data read. Therefore, FIG. 14 does not illustrate the potentials of the node MND and the local bit line LBL_pre. Furthermore, the potential of the global bit line GBLB is also not illustrated.

[0225] Immediately before time T21, the signals MUX, WE, and RE applied to the word line WL are all set to the L level. The potential of the wiring SL is set to a predetermined potential (for example, VSS). The signal SW0 is set to the L level, and the signals SW1 and SW2 are each set to the H level. The signals BOOT1 and BOOT2 are each set to the L level. The signal EQ is set to the H level, and the signal EQB is set to the L level. The signal CSEL is set to the L level. The potentials of the wiring SAP and the wiring SAN are each set to (VDD-VSS) / 2. The potential VPRE is set to (VDD-VSS) / 2. The potential of the wiring CSL is set to an arbitrary fixed potential (for example, VSS). At this time, the global bit lines SA_GBL and GBL, and the global bit lines SA_GBLB and GBLB are precharged to (VDD-VSS) / 2, respectively. The local bit line LBL is in an electrically floating state, and is held at VDD (a potential corresponding to data "1") or VSS (a potential corresponding to data "0"). In the description of the operations at times T21 to T24, unless otherwise specified, the potentials of the wirings and signals are assumed to be maintained at the potentials at the immediately preceding times.

[0226] At time T21, signal EQ goes low and signal EQB goes high. This stops precharging global bit lines SA_GBL and GBL, and global bit lines SA_GBLB and GBLB. Therefore, global bit lines SA_GBL and GBL, and global bit lines SA_GBLB and GBLB, respectively, are electrically floating.

[0227] At time T22, signal BOOT1 goes high. This causes the potentials of global bit line SA_GBL and global bit line GBL to rise due to capacitive coupling via capacitor C1. That is, the potential of global bit line SA_GBL becomes higher than the potential of global bit line SA_GBLB.

[0228] At time T23, the signals MUX and RE go high. Then, the potentials of the global bit lines SA_GBL and GBL change according to the potential of the local bit line LBL. Therefore, the potential of the local bit line LBL can be converted into a potential difference between the global bit lines SA_GBL and SA_GBLB.

[0229] At time T24, signals MUX and RE go low. Furthermore, the potential of line SAN goes to VSS, and the potential of line SAP goes to VDD. Then, the sense amplifier 55 operates, amplifying the potential difference between global bit line SA_GBL and global bit line SA_GBLB that occurred as a result of the operation at time T23 described above. This causes the potentials of global bit line SA_GBL and global bit line SA_GBLB to be fixed at either VDD or VSS. In other words, reading of the data stored in the sense circuit 35, which functions as a memory, is completed.

[0230] The semiconductor device 10A has a configuration in which the transistors M3 and M4 in the semiconductor device 10 are replaced with capacitors C1 and C2. This allows the semiconductor device 10A to improve area efficiency. Furthermore, at time T22, the semiconductor device 10A changes the potentials of the global bit lines SA_GBL and GBL by capacitive coupling rather than precharging. Therefore, the semiconductor device 10A does not need to generate the potential VPRE2 in the semiconductor device 10. This allows for reduced power consumption and miniaturization of circuits (e.g., voltage generation circuits) that supply potential to the semiconductor device 10A.

[0231] The semiconductor device according to one embodiment of the present invention is not limited to the above-described semiconductor device 10A. At least part of the configuration examples and operation examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples, operation examples, other drawings, other embodiments or other examples described in this specification.

[0232] Embodiment 3 In this embodiment, a semiconductor device 10B according to one aspect of the present invention will be described. The semiconductor device 10B is a modified example of the semiconductor device 10 described in the above-described embodiment 1. Therefore, in order to reduce repetition of the description, differences between the semiconductor device 10B and the semiconductor device 10 will be mainly described. Note that the description of the semiconductor device 10 described above can be referred to as appropriate.

[0233] <Structural Example of Semiconductor Device> FIG. 15 is a circuit diagram illustrating a structural example of a semiconductor device 10B of one embodiment of the present invention.

[0234] The semiconductor device 10B differs from the semiconductor device 10 in that it includes a switching circuit 37B instead of the switching circuit 37. The switching circuit 37B differs from the switching circuit 37 in that it does not include the transistors M3 and M4. The semiconductor device 10B also differs from the semiconductor device 10 in that it includes a driving circuit 51B instead of the driving circuit 51.

[0235] 16A is a circuit diagram showing, by circuit symbols, a drive circuit 51B provided on a substrate 50. In addition to the configuration of the drive circuit 51 described above, the drive circuit 51B includes a precharge circuit 56. The precharge circuit 56 is electrically connected to the global bit lines SA_GBL and SA_GBLB. In addition to the functions of the drive circuit 51 described above, the drive circuit 51B has the function of precharging each of the global bit lines SA_GBL and SA_GBLB to a predetermined potential.

[0236] The precharge circuit 56 has a function of precharging the global bit line SA_GBL to a potential VPRE3 in response to a signal SW5, and a function of precharging the global bit line SA_GBLB to a potential VPRE3 in response to a signal SW6.

[0237] Specifically, the precharge circuit 56 includes a transistor M5 and a transistor M6. Each of the transistors M5 and M6 is a p-channel transistor.

[0238] One of the source and drain of the transistor M5 is electrically connected to the global bit line SA_GBL. The other of the source and drain of the transistor M5 is electrically connected to a terminal to which a potential VPRE3 is applied. The transistor M5 has a function of precharging the global bit line SA_GBL to the potential VPRE3 in response to a signal SW5.

[0239] One of the source and drain of the transistor M6 is electrically connected to the global bit line SA_GBLB. The other of the source and drain of the transistor M6 is electrically connected to a terminal to which a potential VPRE3 is applied. The transistor M6 has a function of precharging the global bit line SA_GBLB to the potential VPRE3 in response to a signal SW6.

[0240] FIG. 16B shows a circuit block corresponding to the circuit diagram of the drive circuit 51B described in FIG. 16A, and corresponds to the circuit block of the drive circuit 51B shown in FIG.

[0241] <Operation Example of Semiconductor Device> Next, an operation example of the semiconductor device 10B will be described with reference to FIGS. 17 and 18. FIG.

[0242] The semiconductor device 10B according to one embodiment of the present invention has, as with the semiconductor device 10 described above, a read mode 1 and a read mode 2 as examples of driving methods.

[0243] 17 and 18, examples of operation in read mode 1 and read mode 2 will be described below. The timing charts shown in Figures 17 and 18 differ from the timing charts shown in Figures 6 and 7 in that they show the potentials (H level or L level) of signals SW5 and SW6 instead of signal SW3.

[0244] [Read Mode 1] FIG. 17 is a timing chart illustrating an example of the operation of the semiconductor device 10B in read mode 1.

[0245] Immediately before time T11 and at each of times T11 to T13, signals SW5 and SW6 are at H level. Furthermore, signals other than signals SW5 and SW6 are the same as those in the timing chart shown in Figure 6. Therefore, the description of read mode 1 of semiconductor device 10B can be appropriately taken into consideration, and therefore a description thereof will be omitted.

[0246] [Read Mode 2] FIG. 18 is a timing chart illustrating an example of the operation of the semiconductor device 10B in read mode 2. The period from time T21 to time T24 is the period during which data is read. Note that in read mode 2, the data stored in the memory cell 42 is not related to the data read. Furthermore, the potential of the local bit line LBL_pre is also not related to the data read. Therefore, FIG. 18 does not illustrate the potentials of the node MND and the local bit line LBL_pre. Furthermore, the potential of the global bit line GBLB is also not illustrated.

[0247] Immediately before time T21, the signals MUX, WE, and RE applied to the word line WL are all set to the L level. The potential of the wiring SL is set to a predetermined potential (e.g., VSS). The signals SW0, SW1, and SW2 are all set to the L level. The signals SW5 and SW6 are all set to the H level. The signal EQ is set to the H level, and the signal EQB is set to the L level. The signal CSEL is set to the L level. The potentials of the wiring SAP and the wiring SAN are each set to (VDD-VSS) / 2. The potential VPRE is set to (VDD-VSS) / 2, and the potential VPRE3 is set to a potential (e.g., VDD) that is greater than (VDD-VSS) / 2 but does not exceed VDD. The potential of the wiring CSL is set to an arbitrary fixed potential (for example, VSS). At this time, the global bit line SA_GBL and the global bit line SA_GBLB are each precharged to (VDD-VSS) / 2. The global bit line GBL and the global bit line GBLB are each in an electrically floating state, and their respective potentials are VDD or VSS. The local bit line LBL is also in an electrically floating state, and is held at VDD (a potential corresponding to data "1") or VSS (a potential corresponding to data "0"). In the description of the operations at each of times T21 to T24, unless otherwise specified, the potential of each wiring and each signal is assumed to be maintained at the potential at the immediately preceding time.

[0248] At time T21, signal EQ goes low and signal EQB goes high, stopping precharging of global bit lines SA_GBL and SA_GBLB. As a result, global bit lines SA_GBL and SA_GBLB each go into an electrically floating state.

[0249] At time T22, signal SW1 goes high. Signal SW5 goes low. This causes global bit line SA_GBL and global bit line GBL to be precharged to a potential between VDD and (VDD-VSS) / 2. This means that the potential of global bit line SA_GBL becomes higher than the potential of global bit line SA_GBLB.

[0250] At time T23, signal SW5 goes high. This stops precharging global bit lines SA_GBL and GBL. Then, signals MUX and RE go high. This causes the potentials of global bit lines SA_GBL and GBL to change according to the potential of local bit line LBL. Therefore, the potential of local bit line LBL can be converted into a potential difference between global bit lines SA_GBL and SA_GBLB.

[0251] At time T24, signals MUX and RE go low. Furthermore, the potential of line SAN goes to VSS, and the potential of line SAP goes to VDD. Then, the sense amplifier 55 operates, amplifying the potential difference between global bit line SA_GBL and global bit line SA_GBLB that occurred as a result of the operation at time T23 described above. This causes the potentials of global bit line SA_GBL and global bit line SA_GBLB to be fixed at either VDD or VSS. In other words, reading of the data stored in the sense circuit 35, which functions as a memory, is completed.

[0252] The semiconductor device 10B can be said to have a configuration in which the transistors M3 and M4, which are OS transistors and provided in the layer 30 of the semiconductor device 10, are replaced with transistors M5 and M6, which are Si transistors and provided in the substrate 50. This enables the semiconductor device 10B to achieve improved area efficiency.

[0253] The semiconductor device according to one embodiment of the present invention is not limited to the above-described semiconductor device 10B. At least part of the configuration examples and operation examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples, operation examples, other drawings, other embodiments or other examples described in this specification.

[0254] Embodiment 4 In this embodiment, a memory device according to one embodiment of the present invention will be described. The memory device described in this embodiment can suitably use at least a part of the semiconductor device 10, the semiconductor device 10A, the semiconductor device 10B, or the memory device 300 described in any of Embodiments 1 to 3. Therefore, the above description can be referred to as appropriate.

[0255] <Configuration Example A of Memory Device> FIGS. 19A and 19B are schematic diagrams illustrating a configuration example of a memory device 370A of one embodiment of the present invention.

[0256] 19A, the X, Y, and Z directions are defined to explain the arrangement of the elements constituting the memory device 370A. The X, Y, and Z directions are perpendicular or approximately perpendicular to each other. Furthermore, to make the arrangement of the elements constituting the memory device 370A easier to understand, the elements are shown separated from each other.

[0257] The memory device 370A can include one or more memory array units 371. Note that, as an example, Fig. 19A shows a state in which four memory array units 371 are arranged in the X direction within the memory device 370A.

[0258] The memory array unit 371 can include one or more memory units 372. Note that, as an example, Fig. 19A shows a state in which a plurality of memory units 372 are arranged in the Y direction within the memory array unit 371.

[0259] The memory array unit 371 can be preferably provided with the above-described memory device 300 (see FIG. 9A ). In this case, the memory unit 372 can be preferably provided with at least a part of the above-described semiconductor device 10 (see FIG. 1 ), semiconductor device 10A (see FIG. 12 ), or semiconductor device 10B (see FIG. 15 ).

[0260] That is, by applying the semiconductor device 10 shown in FIGS. 1 to 5 , for example, the memory unit 372 can include a sense amplifier 55 provided on the substrate 50, a sense circuit 35 provided on a layer 30 stacked in the Z direction on the substrate 50, and memory cells 42 provided in each of a plurality of layers (layers 41[1] to 41[m] (m is an integer of 2 or more)) stacked in the Z direction on the layer 30. That is, in the memory unit 372, a plurality of memory cells 42 are arranged in a matrix in the X and Y directions for each of the layers 41[1] to 41[m] stacked in the Z direction. Note that FIG. 19A shows, as an example, four layers (layers 41[1] to 41[4]) in which memory cells 42 are provided.

[0261] The memory unit 372 may or may not have a switching circuit 37 in the layer 30. If the memory unit 372 does not have a switching circuit 37, for example, in the semiconductor device 10 shown in FIG. 1 , the global bit line SA_GBL and the global bit line GBL are short-circuited, and the global bit line SA_GBLB and the global bit line GBLB are short-circuited.

[0262] Furthermore, there are cases where the memory unit 372 does not need to be provided with the sense circuit 35. When the sense circuit 35 is not provided, the memory unit 372 has a configuration in which, for example, in the semiconductor device 10 shown in FIG. 1 , the global bit line GBL and the local bit line LBL are short-circuited, and the global bit line GBLB and the local bit line LBL_pre are short-circuited.

[0263] 19A , the memory device 370A includes a word line driver unit 373, a column driver unit 374, a sense amplifier driver unit 375, a sense circuit driver unit 376, a data sense amplifier unit 377, and a memory controller unit 378 arranged around a memory array unit 371. Note that, as an example, Figure 19A shows a state in which four word line driver units 373, four sense amplifier driver units 375, four sense circuit driver units 376, and four data sense amplifier units 377 are arranged for each of the four memory array units 371. Note that, for example, one word line driver unit 373, one sense amplifier driver unit 375, one sense circuit driver unit 376, and one data sense amplifier unit 377 may be arranged for each of the four memory array units 371.

[0264] Each of the word line driver section 373, column driver section 374, sense amplifier driver section 375, sense circuit driver section 376, data sense amplifier section 377, and memory controller section 378 can be provided on the substrate 50 and can be constructed using Si transistors whose channels are formed in the substrate 50.

[0265] The word line driver unit 373 has a function of selecting one of the layers 41[1] to 41[m] stacked in the Z direction and selecting one of the plurality of memory cells 42 arranged in the X direction, and applying a signal to the word line WL corresponding to the selected memory cell 42. The signal applied to the word line WL controls the operation of writing or reading data to or from the memory cell 42.

[0266] In FIG. 19A , dashed arrows indicate the word line driver unit 373 applying signals to word lines WL corresponding to the memory cells 42 provided in each of the layers 41[1] to 41[4]. In FIG. 19B , solid arrows indicate the word lines WL corresponding to the memory cells 42 provided in each of the layers 41[1] to 41[4], each labeled with a corresponding word line WL[1] to WL[4]. That is, the word line driver unit 373 can select one of the layers 41[1] to 41[4] and apply a signal to one of the corresponding word lines WL[1] to WL[4]. For example, to select layer 41[1], a signal can be applied to the corresponding word line WL[1]. Similarly, to select layer 41[4], a signal can be applied to the corresponding word line WL[4].

[0267] The column driver unit 374 has a function of selecting one of the plurality of semiconductor devices 10 arranged in the Y direction. For example, the column driver unit 374 can output the signal CSEL in the semiconductor device 10 described above. In other words, the column driver unit 374 can select the corresponding semiconductor device 10 by providing the signal CSEL to one of the plurality of semiconductor devices 10 arranged in the Y direction.

[0268] The sense amplifier driver unit 375 has a function of controlling the operation of the sense amplifier 55. For example, the sense amplifier driver unit 375 can output the signals EQ and EQB in the semiconductor device 10 described above. The sense amplifier driver unit 375 can also control the potentials applied to the wiring SAP and the wiring SAN.

[0269] The sense circuit driver unit 376 has a function of controlling the operation of the sense circuit 35. For example, the sense circuit driver unit 376 can output the signal MUX, the signal WE, and the signal RE in the semiconductor device 10 described above. The sense circuit driver unit 376 can also control the potential applied to the wiring SL.

[0270] The data sense amplifier section 377 has a function of writing or reading data to or from the memory cell 42 selected by the word line driver section 373 and the column driver section 374 .

[0271] The memory controller unit 378 has the function of controlling the operations of the word line driver unit 373 , column driver unit 374 , sense amplifier driver unit 375 , sense circuit driver unit 376 , data sense amplifier unit 377 , and memory controller unit 378 .

[0272] 20A and 20B are schematic diagrams illustrating a configuration example of a memory device 370B according to one embodiment of the present invention. The memory device 370B is a variation of the memory device 370A described above. Therefore, to avoid repetition, differences between the memory device 370B and the memory device 370A will be mainly described. Note that the description of the memory device 370A described above can be referred to as appropriate.

[0273] In addition to the configuration of the memory device 370A described above, the memory device 370B is provided with layer selection driver units 373L[1] to 373L[m] on layers 41[1] to 41[m], respectively. The layer selection driver units 373L[1] to 373L[m] are arranged so as to overlap in the Z direction on the word line driver unit 373. Note that Figures 20A and 20B show, as an example, a state in which the layer selection driver units 373L[1] to 373L[4] are provided on layers 41[1] to 41[4], respectively.

[0274] The word line driver unit 373 has the function of selecting one of the layers 41[1] to 41[m] stacked in the Z direction using the layer selection driver unit 373L[1] to layer selection driver unit 373L[m], and selecting one of the multiple memory cells 42 arranged in the X direction, and applying a signal to the word line WL corresponding to the selected memory cell 42.

[0275] That is, a signal for selecting one of the plurality of memory cells 42 arranged in the X direction is output from the word line driver unit 373 and input to each of the layer selection driver units 373L[1] to 373L[m]. The signal is also output from one of the layer selection driver units 373L[1] to 373L[m].

[0276] 20A, the word line driver unit 373 provides signals to the layer select driver units 373L[1] to 373L[4] provided in the layers 41[1] to 41[4], respectively, as indicated by solid arrows and labeled with the word lines WLin. Also, in FIG. 20B, the layer select driver units 373L[1] to 373L[4] provide signals to the word lines WL corresponding to the memory cells 42 provided in the layers 41[1] to 41[4], respectively, as indicated by solid arrows and labeled with the word lines WLout[1] to WLout[4]. In other words, the word line driver unit 373 can provide a signal to one of the corresponding word lines WLout[1] to WLout[4] via one of the layer selection driver units 373L[1] to 373L[4] provided in each of layers 41[1] to 41[4].

[0277] 21A is a circuit diagram illustrating an example of the configuration of the layer selection driver 373Lbuf. Each of the layer selection driver units 373L[1] to 373L[m] includes one or more layer selection drivers 373Lbuf.

[0278] The layer selection driver 373Lbuf includes a transistor ML1, a transistor ML2, a transistor ML3, and a capacitor CL1. Each of the transistors ML1 to ML3 is an OS transistor.

[0279] The gate of the transistor ML2 is electrically connected to one of the source or drain of the transistor ML1 and one terminal of the capacitor CL1. The one of the source or drain of the transistor ML2 is electrically connected to one of the source or drain of the transistor ML3, the other terminal of the capacitor CL1, and the word line WLout. The other of the source or drain of the transistor ML2 is electrically connected to the word line WLin. The gate of the transistor ML1 is electrically connected to a wiring to which a potential VLD is applied. The other of the source or drain of the transistor ML1 is electrically connected to a wiring to which a signal LSEL is applied. The gate of the transistor ML3 is electrically connected to a wiring to which a signal LSELB is applied. The other of the source or drain of the transistor ML3 is electrically connected to a wiring to which a potential VLS is applied. Note that a region where the gate of the transistor ML2, one of the source or drain of the transistor ML1, and one terminal of the capacitor CL1 are electrically connected is sometimes referred to as a node BL1.

[0280] The configuration of the layer selection driver 373Lbuf is not limited to the example configuration shown in FIG. 21A . For example, the other terminal of the capacitor CL1 may be electrically connected to the other of the source or drain of the transistor ML2. Alternatively, for example, the capacitor CL1 may not be provided. In that case, the parasitic capacitance between the gate of the transistor ML2 and either the source or the drain can function as the capacitor CL1.

[0281] The layer selection driver 373Lbuf has a function of outputting either the signal applied to the word line WLin or the potential VLS to the word line WLout in response to the signals LSEL and LSELB.

[0282] FIG. 21B is a timing chart illustrating an example of the operation of the layer selection driver 373Lbuf.

[0283] 21B shows the potentials (H level or L level) of the signals LSEL and LSELB and the signal applied to the word line WLin at each time point of operation, as well as the potential changes of the node B1 and the word line WLout.

[0284] In the following description of the operation example, it is assumed that the potential VLD is the same as the H level of the signals LSEL and LSELB, and that the potential VLS is the same as the L level of the signals LSEL and LSELB.

[0285] Immediately before time TL1, signal LSEL is set to L level and signal LSELB is set to H level. At this time, transistor ML1 is conductive, so the potential of node BL1 is L level. Therefore, transistor ML2 is non-conductive and transistor ML3 is conductive. Therefore, whether the signal applied to word line WLin is H level or L level, the potential of word line WLout is L level (potential VLS).

[0286] At time TL1, signal LSEL goes high and signal LSELB goes low. At this time, the potential of node BL1 rises from high (potential VLD) to a potential obtained by subtracting the threshold voltage of transistor ML1, and transistor ML1 goes non-conductive. This causes transistor ML2 to go conductive and transistor ML3 to go non-conductive. Therefore, the potential of word line WLout goes low (the signal applied to word line WLin at time TL1).

[0287] At time TL2, the signal applied to word line WLin goes high. This causes current to flow from word line WLin to word line WLout via transistor ML2, raising the potential of word line WLout. At this time, because transistor ML1 is non-conductive, the potential of node BL1 also rises due to capacitive coupling by capacitor CL1. This maintains the potential difference between the gate and source of transistor ML2, i.e., transistor ML2 remains conductive. This causes the potential of word line WLout to go high (the signal applied to word line WLin at time TL2).

[0288] In this way, the layer selection driver 373Lbuf forms a bootstrap circuit in which the capacitance CL1 is provided between the gate and source of the transistor ML2, so that when the signal applied to the word line WLin becomes high, the transistor ML2 remains conductive, and therefore a high level signal can be output to the word line WLout. The capacitance CL1 is sometimes called a "bootstrap capacitance."

[0289] The memory device 370B can select one of the layer selection driver units 373L[1] to 373L[m] by controlling the signals LSEL and LSELB given to the layer selection driver 373Lbuf provided in each of the layer selection driver units 373L[1] to 373L[m], and output the signal given to the word line WLin to the word line WLout.

[0290] For example, by setting the signals LSEL and LSELB given to the layer selection driver 373Lbuf provided in the layer selection driver unit 373L[1] to H level and L level, respectively, and setting the signals LSEL and LSELB given to the layer selection drivers 373Lbuf provided in the layer selection driver units 373L[2] to 373L[m] to L level and H level, respectively, the signal given to the word line WLin from the word line driver unit 373 is output to the word line WLout[1] via the layer selection driver 373Lbuf provided in the layer selection driver unit 373L[1].

[0291] The storage device 370B has advantages over the storage device 370A, for example, in the points described below.

[0292] In the memory device 370A, m word lines must be provided from the substrate 50 to each of the layers 41[1] to 41[m], whereas in the memory device 370B, only one word line must be provided from the substrate 50 to each of the layers 41[1] to 41[m]. Furthermore, in the memory device 370A, m buffers must be provided on the substrate 50 to provide signals to each of the m word lines. In the memory device 370B, however, a buffer must be provided in each of the layer selection driver units 373L[1] to 373L[m] provided in each of the layers 41[1] to 41[m]. For example, in the layer selection driver 373Lbuf provided in each of the layer selection driver units 373L[1] to 373L[m], the transistors ML2 and ML3 may function as buffers.

[0293] Therefore, the memory device 370B can suppress an increase in the area of ​​the word line driver unit 373 that occurs when the number of layers 41[1] to 41[m] in which the memory cells 42 are provided increases. That is, the memory device 370B can increase the number of layers 41[1] to 41[m] in which the memory cells 42 are provided without increasing the area overhead. In other words, the memory device 370B can improve the density of the memory cells 42 (memory density) without increasing the area overhead.

[0294] <Configuration Examples of Memory Cells> A memory device according to one embodiment of the present invention can include memory cells with various configurations.

[0295] 22A to 22E illustrate examples of circuit configurations that can be used as a memory cell 42, which can be used in a memory device of one embodiment of the present invention.

[0296] The memory cell 42a shown in FIG. 22A includes a transistor Ma and a capacitor Ca. One of the source and drain of the transistor Ma is electrically connected to one terminal of the capacitor Ca. The other of the source and drain of the transistor Ma is electrically connected to a bit line BL. The gate of the transistor Ma is electrically connected to a word line WL. The other terminal of the capacitor Ca is electrically connected to a wiring CSL. The transistor Ma is an OS transistor. OS transistors have extremely low off-state current. Therefore, by turning off the transistor Ma, charge corresponding to data can be held in the charge holding node FN. Therefore, the refresh rate of data corresponding to the charge held in the charge holding node FN can be reduced.

[0297] The memory cell 42b shown in Figure 22B is a modified example of the memory cell 42a shown in Figure 22A. The difference from the transistor Ma in Figure 22A is that the transistor Ma has a back gate, and the back gate and gate are electrically connected to each other, allowing the potential of the word line WL to be applied from both. This configuration increases the amount of current flowing between the source and drain when the transistor Ma is turned on.

[0298] The memory cell 42c shown in Figure 22C is a modified version of the memory cell 42a shown in Figure 22A. The difference from the transistor Ma in Figure 22A is that the transistor Ma has a back gate, and by electrically connecting the back gate to the back gate line BGL, a potential different from that applied to the gate is applied to the back gate. This configuration allows the threshold voltage of the transistor Ma to be controlled, thereby changing the amount of current flowing between the source and drain of the transistor Ma.

[0299] The memory cell 42d shown in FIG. 22D includes a transistor Ma, a transistor Mb, and a capacitor Ca. One of the source and drain of the transistor Ma is electrically connected to the gate of the transistor Mb and one terminal of the capacitor Ca. The other of the source and drain of the transistor Ma is electrically connected to a write bit line WBL. The gate of the transistor Ma is electrically connected to a write word line WWL. The other terminal of the capacitor Ca is electrically connected to a read word line RWL. One of the source and drain of the transistor Mb is electrically connected to a read bit line RBL. The other of the source and drain of the transistor Mb is electrically connected to a wiring SL. Although an n-channel transistor is illustrated as the transistor Mb, a p-channel transistor may also be used. By turning off the transistor Ma, charge corresponding to data can be held in the charge holding node FN. The transistor Mb is an OS transistor. Note that the transistor Mb may also be a Si transistor. The transistor Ma may have the same configuration as the transistor Ma shown in FIG. 22B or FIG. 22C.

[0300] The memory cell 42e shown in FIG. 22E includes a transistor Ma, a transistor Mb, a transistor Mc, and a capacitor Ca. One of the source or drain of the transistor Ma is electrically connected to the gate of the transistor Mb and one terminal of the capacitor Ca. The other of the source or drain of the transistor Ma is electrically connected to a write bit line WBL. The gate of the transistor Ma is electrically connected to a write word line WWL. The other terminal of the capacitor Ca is electrically connected to a wiring CSL. One of the source or drain of the transistor Mb is electrically connected to one of the source or drain of the transistor Mc. The other of the source or drain of the transistor Mb is electrically connected to a wiring SL. The gate of the transistor Mc is electrically connected to a read word line RWL. The other of the source or drain of the transistor Mc is electrically connected to a read bit line RBL. Although an n-channel transistor is illustrated as the transistor Mc, it may be a p-channel transistor. By turning off the transistor Ma, charge corresponding to data can be held in the charge holding node FN. The transistors Mb and Mc are each an OS transistor. Note that at least one of the transistors Mb and Mc may be a Si transistor. Note that the transistor Ma may have the same structure as the transistor Ma shown in FIG. 22B or 22C described above.

[0301] The memory cell configuration shown in FIGS. 22A to 22C is called DOSRAM (registered trademark). DOSRAM is an abbreviation for Dynamic Oxide Semiconductor RAM (Random Access Memory). A configuration using DOSRAM electrically connects one of the source or drain of an OS transistor to one terminal of a capacitor, so that when the OS transistor is turned off, the charge accumulated in one terminal of the capacitor can be retained. A configuration using DOSRAM is particularly effective when the amount of data to be stored increases. For example, DOSRAM can suppress an increase in circuit area compared to when the memory cell of a storage circuit is configured using SRAM (Static RAM). The memory cell configuration shown in FIGS. 22A to 22C is particularly effective in suppressing an increase in circuit area.

[0302] The memory cell configurations shown in FIGS. 22D and 22E are called NOSRAM (registered trademark). NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. A configuration using NOSRAM can retain charge accumulated in the gate of a read transistor when the write OS transistor is turned off by electrically connecting one of the source and drain of the write OS transistor to the gate of the read transistor. A configuration using NOSRAM may also be used as a nonvolatile memory. For example, NOSRAM can continue to store data even in a power gating state by turning off the write OS transistor.

[0303] Note that the circuit configurations illustrated in FIGS. 22A to 22E are merely examples, and any configuration can be used as long as it can realize one embodiment of the present invention.

[0304] <Layout Example> FIGS. 23A and 23B are planar layout diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention.

[0305] 23A , as an example, a module 381 is arranged in a 4 mm square chip 380. The module 381 may include, for example, a memory device 370A or a memory device 370B. An interface for exchanging signals between the module 381 and the outside of the chip 380 is arranged around the module 381. The interface is, for example, an Inter-Integrated Circuit (I2C) or a Low Voltage Differential Signaling (LVDS).

[0306] In the planar layout diagram shown in FIG. 23B , as an example of a module 381 including a memory device 370A or 370B, regions 382, ​​383, 384, 385, and 386 are arranged within the module 381. Region 382 is arranged with a memory array section 371 including, for example, memory cells 42, sense circuits 35, and sense amplifiers 55. Region 383 is arranged with, for example, a word line driver section 373, a sense amplifier driver section 375, and a sense circuit driver section 376. Furthermore, in the memory device 370B, region 383 is also arranged with a layer selection driver 373Lbuf. Region 384 is arranged with a column driver section 374. Region 385 is arranged with a data sense amplifier section 377. Region 386 is arranged with a memory controller section 378.

[0307] The memory device 370A or the memory device 370B can have a plurality of memory cells 42 stacked and arranged in the region 382. Therefore, the memory device 370A or the memory device 370B can improve the density of the memory cells 42 (memory density).

[0308] The storage device according to one embodiment of the present invention is not limited to the storage device 370A and the storage device 370B. At least part of the configuration examples and operation examples described in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples, operation examples, other drawings, other embodiments or other examples described in this specification.

[0309] Embodiment 5 In this embodiment, an example of a semiconductor device according to one embodiment of the present invention will be described with reference to FIG 24. The semiconductor device according to one embodiment of the present invention includes a transistor and a capacitor.

[0310] Note that the semiconductor device described in this embodiment can be suitably used for the memory cell 42 described in Embodiment 1. That is, the transistor and capacitor included in the semiconductor device correspond to the transistor 43 and capacitor 44 included in the memory cell 42, respectively.

[0311] The structure of a semiconductor device having a transistor and a capacitor will be described with reference to FIG. 24 . FIGS. 24A to 24D are top views and cross-sectional views of a semiconductor device having a transistor 200a, a transistor 200b, a capacitor 100a, and a capacitor 100b. FIG. 24A is a top view of the semiconductor device. FIGS. 24B to 24D are cross-sectional views of the semiconductor device. FIG. 24B is a cross-sectional view of a portion indicated by dashed dotted lines A1-A2 in FIG. 24A and is also a cross-sectional view of the transistor 200a, the transistor 200b, the capacitor 100a, and the capacitor 100b in the channel length direction. FIG. 24C is a cross-sectional view of a portion indicated by dashed dotted lines A3-A4 in FIG. 24A and is also a cross-sectional view of the transistor 200a in the channel width direction. FIG. 24D is a cross-sectional view of a portion indicated by dashed dotted lines A5-A6 in FIG. 24A and is also a cross-sectional view of the capacitor 100a in the channel width direction. It should be noted that some elements have been omitted from the top view of FIG. 24A for clarity.

[0312] 24A is parallel to the channel length direction of the transistor 200a and the channel length direction of the transistor 200b, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X direction and the Y direction. The X direction, Y direction, and Z direction shown in FIG. 24A are also shown in FIGS. 24B to 24D.

[0313] A semiconductor device of one embodiment of the present invention includes an insulator 214 over a substrate (not shown), a transistor 200a, a transistor 200b, a capacitor 100a, and a capacitor 100b over the insulator 214, an insulator 280 over an insulator 275 provided in the transistor 200a and the transistor 200b, an insulator 282 over the insulator 280, an insulator 285 over the capacitor 100a, the capacitor 100b, and the insulator 282, and a conductor 240 (the conductor 240a and the conductor 240b). The insulator 214, the insulator 280, the insulator 282, and the insulator 285 function as interlayer films. As shown in FIG. 24B , the transistor 200a, the transistor 200b, the capacitor 100a, and the capacitor 100b are at least partially embedded in the insulator 280.

[0314] Here, the transistor 200a and the transistor 200b each include an oxide 230 that functions as a semiconductor layer, a conductor 260 that functions as a first gate (also referred to as a top gate) electrode, a conductor 205 that functions as a second gate (also referred to as a back gate) electrode, a conductor 242b that functions as one of a source electrode and a drain electrode, and a conductor 242a that functions as the other of the source electrode and the drain electrode. The transistors 200a and 200b also include an insulator 253 and an insulator 254 that function as a first gate insulator. The transistors 200a and 200b also include an insulator 222 and an insulator 224 that function as a second gate insulator. The gate insulator may also be referred to as a gate insulating layer or a gate insulating film.

[0315] Note that the insulators 282 and 222 may each have a function of capturing or fixing hydrogen, for example, so that hydrogen contained in the insulators 280, 224, 253, and 254, for example, can be captured or fixed in the insulators 282 and 222.

[0316] Since transistors 200a and 200b have the same configuration, when describing matters common to transistors 200a and 200b, the symbols added to the reference numerals may be omitted and the transistors may be described as transistor 200.

[0317] The first gate electrode and the first gate insulating film are disposed in an opening 258 formed in the insulator 280 and the insulator 275. That is, the conductor 260, the insulator 254, and the insulator 253 are disposed in the opening 258.

[0318] Each of the capacitors 100a and 100b has a conductor 156 that functions as a lower electrode, an insulator 153 that functions as a dielectric, and a conductor 160 that functions as an upper electrode. That is, each of the capacitors 100a and 100b constitutes an MIM (Metal-Insulator-Metal) capacitor.

[0319] Since capacitors 100a and 100b have the same configuration, when describing matters common to capacitors 100a and 100b below, the symbols added to the reference numerals may be omitted and the capacitors may be described as capacitor 100.

[0320] The upper electrode, the dielectric, and a portion of the lower electrode of capacitor 100 are disposed within opening 158 formed in insulator 282, insulator 280, and insulator 275. That is, conductor 160, insulator 153, and conductor 156 are disposed within opening 158.

[0321] The semiconductor device of one embodiment of the present invention also includes a conductor 240 (conductor 240a and conductor 240b) which functions as a plug (also referred to as a connection electrode) by being electrically connected to the transistor 200. The conductor 240 is disposed in an opening 206 formed in the insulator 280, for example. The conductor 240 has a region in contact with part of the top surface and part of the side surface of the conductor 242a.

[0322] Furthermore, the semiconductor device of one embodiment of the present invention includes an insulator 210 and a conductor 209 between a substrate (not shown) and an insulator 214. The conductor 209 is disposed so as to be embedded in the insulator 210. The conductor 209 has a region in contact with the conductor 240.

[0323] Furthermore, the semiconductor device of one embodiment of the present invention may include an insulator 212 between the insulator 210 and the conductor 209 and between the insulator 214 and the conductor 209 .

[0324] The semiconductor device including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device. In this case, the conductor 240 may be electrically connected to a sense amplifier and function as a bit line. Here, as shown in FIG. 24A , the capacitor 100 is provided so that at least a portion thereof overlaps with the conductor 242b of the transistor 200. Therefore, in the semiconductor device according to this embodiment, the capacitor 100 can be provided without significantly increasing the occupied area in a plan view, thereby enabling miniaturization or high integration.

[0325] The semiconductor device described in this embodiment can be suitably used for the semiconductor device 10 or the memory device 300 described in Embodiment 1. That is, the transistor 200, the capacitor 100, and the conductor 240 included in the semiconductor device correspond to the transistor 43, the capacitor 44, and the local bit line LBL, respectively. The sense amplifier electrically connected to the conductor 240 corresponds to the sense circuit 35.

[0326] The semiconductor device described in this embodiment has a line-symmetrical configuration with the dashed-dotted line A7-A8 in FIG. 24A as the axis of symmetry. That is, the transistor 200b can be said to be arranged in a line-symmetrical position with respect to the transistor 200a with the conductor 240 as the axis of symmetry. The capacitor 100b can be said to be arranged in a line-symmetrical position with respect to the capacitor 100a with the conductor 240 as the axis of symmetry. Here, in the semiconductor device described in this embodiment, the other of the source electrode or the drain electrode of the transistor 200a and the other of the source electrode or the drain electrode of the transistor 200b also serve as the conductor 242a. The transistors 200a and 200b also serve as the conductor 240 that functions as a plug. Thus, the semiconductor device described in this embodiment enables miniaturization or high integration by configuring the connections between the two transistors, the two capacitors, and the plug as described above.

[0327] [Transistor 200] As shown in Figures 24A to 24C, the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductors 205a and 205b) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and a conductor 242a (conductor 242a1 and conductor 242a2) on the oxide 230b. conductor 242a (conductor 242a2) and conductor 242b (conductor 242b1 and conductor 242b2), insulator 253 on oxide 230b, insulator 254 on insulator 253, conductor 260 (conductor 260a and conductor 260b) located on insulator 254 and overlapping with part of oxide 230b, and insulator 275 arranged on insulator 222, insulator 224, oxide 230a, oxide 230b, conductor 242a, and conductor 242b.

[0328] In this specification and the like, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. Furthermore, the conductor 242a and the conductor 242b may be collectively referred to as the conductor 242.

[0329] An opening 258 reaching the oxide 230b is provided in the insulator 280 and the insulator 275. That is, the opening 258 can be said to have a region overlapping with the oxide 230b. Furthermore, the insulator 275 can be said to have an opening overlapping with the opening of the insulator 280. That is, the opening 258 includes the opening of the insulator 280 and the opening of the insulator 275. Furthermore, the insulator 253, the insulator 254, and the conductor 260 are disposed in the opening 258. That is, the conductor 260 has a region overlapping with the oxide 230b with the insulators 253 and 254 interposed therebetween. Furthermore, the conductor 260, the insulator 253, and the insulator 254 are provided between the conductor 242a and the conductor 242b in the channel length direction of the transistor 200. The insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. As shown in Fig. 24C, the top surface of the insulator 222 is exposed in the region of the opening 258 that does not overlap with the oxide 230.

[0330] Note that it is preferable to use a material with a high ability to capture or fix hydrogen, such as aluminum oxide, as the insulator 253, and a material with a high hydrogen barrier property, such as silicon nitride, as the insulator 254. This can prevent impurities, such as water or hydrogen, from diffusing into the oxide 230.

[0331] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the oxide 230a. By having the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0332] Note that although the transistor 200 has a structure in which the oxide 230 has two stacked layers of the oxide 230a and the oxide 230b, one embodiment of the present invention is not limited to this. For example, the oxide 230 may have a single layer of the oxide 230b. Alternatively, the oxide 230 may have a stacked structure of three or more layers. Alternatively, each of the oxide 230a and the oxide 230b may have a stacked structure.

[0333] An example of such a stacked structure is a three-layer stacked structure in which a first layer is a semiconductor layer having an atomic ratio of metal elements of In:Ga:Zn = 1:1:1, a second layer is a semiconductor layer having an atomic ratio of metal elements of In:Zn = 4:1, and a third layer is a semiconductor layer having an atomic ratio of metal elements of In:Ga:Zn = 1:1:1. It is preferable that the band gaps of the first and third semiconductor layers be larger than the band gap of the second semiconductor layer. This configuration allows the second semiconductor layer to be the main current path, resulting in a so-called buried channel structure.

[0334] The conductor 260 functions as a first gate electrode, and the conductor 205 functions as a second gate electrode. The insulators 253 and 254 function as first gate insulators, and the insulators 222 and 224 function as second gate insulators. The conductor 242b functions as one of a source electrode and a drain electrode, and the conductor 242a functions as the other of the source electrode and the drain electrode. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0335] 24A , 24B, and 24D , the capacitor 100 includes a conductor 156, an insulator 153, and a conductor 160 (conductors 160 a and 160 b). The conductor 156 functions as one of a pair of electrodes (also referred to as a lower electrode) of the capacitor 100, the conductor 160 functions as the other of the pair of electrodes (also referred to as an upper electrode) of the capacitor 100, and the insulator 153 functions as a dielectric of the capacitor 100.

[0336] At least a portion of the conductor 156, the insulator 153, the conductor 160a, and the conductor 160b are disposed in the openings 158 formed in the insulators 275, 280, and 282. The conductor 156 is disposed over the conductor 242b, the insulator 153 is disposed over the conductor 156, the conductor 160a is disposed over the insulator 153, and the conductor 160b is disposed over the conductor 160a.

[0337] The conductor 156 is disposed along the opening 158 formed in the insulators 275, 280, and 282. It is preferable that a portion of the upper surface of the conductor 156 is higher than the upper surface of the insulator 282. The lower surface of the conductor 156 is in contact with the upper surface of the conductor 242b. The conductor 156 is preferably formed using a film formation method with good coating properties, such as an ALD method or a CVD method. The conductor 156 may be formed using a conductor that can be used for the conductor 205, the conductor 260, or the conductor 242. For example, the contact resistance between the conductor 156 and the conductor 242b can be reduced by using the same conductive material as the conductor 242b for the conductor 156. For example, the conductor 156 may be formed using titanium nitride or tantalum nitride formed using an ALD method.

[0338] The insulator 153 is disposed so as to cover the conductor 156 and a portion of the insulator 282. A high-dielectric-constant (high-k) material (a material with a high relative dielectric constant) is preferably used for the insulator 153. The insulator 153 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0339] The high-dielectric-constant insulator may be, for example, an oxide, oxynitride, oxynitride, or nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be contained in the oxide, oxynitride, oxynitride, or nitride. The high-dielectric-constant insulator may also be formed by stacking insulating layers made of the above materials.

[0340] Furthermore, examples of high-dielectric-constant insulators that can be used include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxynitrides containing hafnium and zirconium. By using such high-dielectric-constant materials, it is possible to thicken insulator 153 to a degree that can suppress leakage current and to ensure a sufficient capacitance of capacitor 100.

[0341] It is also preferable to use a laminated insulating layer made of the above materials, and it is preferable to use a laminated structure of a high-dielectric-constant material and a material with a higher dielectric strength than the high-dielectric-constant material. For example, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used as the insulator 153. Alternatively, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used. Alternatively, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used. By using a laminated insulator with a relatively high dielectric strength, such as aluminum oxide, as the insulator 153, the dielectric strength can be improved and electrostatic breakdown of the capacitor 100 can be suppressed.

[0342] The conductor 160 is arranged to fill the opening 158 formed in the insulators 275, 280, and 282. The conductor 160 is preferably formed by, for example, an ALD method or a CVD method. The conductor 160 may be formed using a conductor that can be used for the conductor 205 or the conductor 260. For example, titanium nitride formed by an ALD method can be used as the conductor 160a, and tungsten formed by a CVD method can be used as the conductor 160b. Note that if the adhesion of tungsten to the insulator 153 is sufficiently high, a single layer of tungsten formed by a CVD method may be used as the conductor 160.

[0343] The opening 158 is provided to reach the conductor 242b. That is, it can be said that the opening 158 has a region overlapping with the conductor 242b. The conductor 242b is one of the source electrode and the drain electrode of the transistor 200, and can electrically connect the transistor 200 and the capacitor 100 by being in contact with the bottom surface of the conductor 156 provided in the opening 158.

[0344] In plan view, it is preferable that the distance between the opening 158 and the oxide 230 is short. By using such a structure, it is possible to reduce the area occupied by a memory cell having the capacitor 100 and the transistor 200. Note that in plan view, the shape of the opening 158 may be a rectangle, a polygonal shape other than a rectangle, a polygonal shape with curved corners, or a circular shape including an ellipse.

[0345] 24B and 24D , conductor 156 is provided in contact with the bottom surface and inner wall of opening 158. Thus, conductor 156 is in contact with the side surfaces of insulators 275, 280, and 282, the side surface of conductor 242b1, the side surface and top surface of conductor 242b2, and the top surface of insulator 222. Also, insulator 153 is provided in contact with the top surface of conductor 156, conductor 160a is provided in contact with the top surface of insulator 153, and conductor 160b is provided in contact with the top surface of conductor 160a.

[0346] 24B and 24D , capacitor 100 can be formed in which conductor 156 and conductor 160 are disposed opposite each other at the bottom and side surfaces of opening 158, with insulator 153 sandwiched between them. Therefore, by increasing the depth of opening 158 (which can also be referred to as the film thickness of insulator 280), the capacitance of capacitor 100 can be increased. Increasing the capacitance per unit area of ​​capacitor 100 in this way can stabilize the read operation of the memory device.

[0347] 24B , a portion of conductor 156, a portion of insulator 153, and a portion of conductor 160 are exposed from opening 158. In other words, a portion of conductor 156, a portion of insulator 153, and a portion of conductor 160 are formed above the upper surface of conductor 260 or above the upper surface of insulator 282.

[0348] A portion of conductor 156 and a portion of insulator 153 contact the upper surface of insulator 282. In other words, the side edge of conductor 156 is covered by insulator 153. Furthermore, conductor 160 preferably has an area that overlaps with insulator 282 via insulator 153. Here, as shown in FIG. 24B , the side edge of conductor 160 and the side edge of insulator 153 roughly coincide with each other. With this configuration, conductor 160 and conductor 156 can be separated by insulator 153, thereby preventing short-circuiting between conductor 160 and conductor 156.

[0349] Furthermore, the portion of the conductor 160 above the insulator 282 may be routed to form a wiring. For example, as shown in FIG. 24C , the conductor 160 can be provided extending in the channel width direction of the transistor 200. This allows the conductor 160 to function as a wiring when a plurality of transistors 200 and capacitors 100 are provided. In this case, the insulator 153 can also be provided extending along with the conductor 160.

[0350] Fig. 32 is a cross-sectional view illustrating another configuration example of the transistor 200a and the capacitor 100a included in the semiconductor device illustrated in Fig. 24B. Here, differences between the semiconductor device illustrated in Fig. 32 and the semiconductor device illustrated in Fig. 24B will be mainly described.

[0351] The semiconductor device shown in Figure 32 differs from the semiconductor device shown in Figure 24B in that the side ends of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a1, and the conductor 242a2 are formed so as to be approximately aligned.

[0352] In addition to the semiconductor device shown in FIG. 24B, the semiconductor device shown in FIG. 32 has an insulator 271a, an insulator 271b, an insulator 255, an insulator 241, an insulator 221, an insulator 283, and an insulator 284.

[0353] 32 , the insulator 271a is provided between the conductor 242a2 and the insulator 275. The insulator 271b is provided between the conductor 242b2 and the insulator 275. Here, the insulators 271a and 271b may function as an etching stopper to protect the conductors 242a2 and 242b2 when the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a1, the conductor 242a2, the insulator 271a, and the insulator 271b are processed collectively.

[0354] 32 , insulator 255 is provided in opening 258 between insulator 253 and conductor 242a2, conductor 242b2, insulator 271a, insulator 271b, insulator 275, and insulator 280, and in contact with a portion of the top surface of conductor 242a1 and a portion of the top surface of conductor 242b1. In other words, insulator 255 can be said to be formed in a sidewall shape in contact with the side wall of opening 258. Here, insulator 255 preferably functions as a protective film that prevents conductors 242a2 and 242b2 from being excessively oxidized when heat treatment is performed in an oxygen-containing atmosphere after conductors 242a1 and 242b1 are separated.

[0355] 32 , the insulator 221 is provided in contact with the lower surface of the insulator 222. The insulator 283 is provided in contact with the upper surface of the insulator 282. The insulator 221 preferably has a function of suppressing diffusion of impurities such as water or hydrogen from an interlayer insulating film disposed below the insulator 221 to the transistor 200 a. The insulator 283 preferably has a function of suppressing diffusion of impurities such as water or hydrogen from an interlayer insulating film disposed above the insulator 283 to the transistor 200 a.

[0356] 32 , an insulator 284 is provided between the insulators 283 and 285. The insulator 284 has a function of changing the capacitance of the capacitor 100a depending on its thickness. That is, in the capacitor 100a, for example, by increasing the depth of the opening 158 (for example, by increasing the thickness of the insulator 284), the capacitance of the capacitor 100a can be increased.

[0357] 32, an insulator 241 is provided in contact with the side surface of the conductor 240. Specifically, the insulator 241 is formed in contact with the inner wall of the opening (corresponding to the opening 206 shown in FIG. 24B) of the insulators 216, 221, 222, 275, 280, 282, 283, 284, and 285. The insulator 241 is also formed to protrude into the opening. The insulator 241 is also formed on the side surfaces of the insulator 224, the oxide 230, and the conductor 242a. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. In other words, the conductor 240 is formed so as to fill the interior of the opening via the insulator 241.

[0358] The uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the upper surface of the conductor 242a. This configuration allows the conductor 240 to contact at least a portion of the side end of the conductor 242a. Note that the insulator 241 formed below the conductor 242a preferably has a region that contacts the side surface of the oxide 230. This configuration can prevent impurities such as water or hydrogen contained in the insulator 280 from entering the oxide 230 through the conductor 240. Note that the insulator 241 may have a stacked structure of two or more layers.

[0359] Note that the semiconductor device of one embodiment of the present invention can have a structure in which the structure of the semiconductor device illustrated in FIG. 24B and the structure of the semiconductor device illustrated in FIG. 32 are combined as appropriate.

[0360] At least part of the structures, methods, and the like described in this embodiment can be implemented in appropriate combination with other embodiment modes or other examples described in this specification and the like.

[0361] 25A and 25B show an example of a chip 1200 on which a semiconductor device of the present invention is mounted. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0362] As shown in FIG. 25A, the chip 1200 includes, for example, a CPU 1211, a GPU 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, and one or more network circuits 1216.

[0363] Chip 1200 is provided with bumps (not shown), and as shown in Fig. 25B, is connected to a first surface of package substrate 1201 via the bumps. Package substrate 1201 is also provided with a plurality of bumps 1202 on the back side of the first surface, and is connected to motherboard 1203 via the plurality of bumps 1202.

[0364] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. For example, the DOSRAM described in the above embodiment and the like can be used as the DRAM 1221. This allows the DRAM 1221 to achieve low power consumption, high speed, and large capacity.

[0365] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The memory can be the DOSRAM described above. The GPU 1212 is suitable for parallel calculation of multiple pieces of data and can perform image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate operation circuit using the oxide semiconductor of the present invention, the image processing or multiply-and-accumulate operation can be performed with low power consumption.

[0366] Furthermore, since the CPU 1211 and the GPU 1212 are provided on the same chip, the chip can shorten the wiring between the CPU 1211 and the GPU 1212. Therefore, the chip can quickly transfer data from the CPU 1211 to the GPU 1212, transfer data between the memories of the CPU 1211 and the GPU 1212, and transfer the calculation results from the GPU 1212 to the CPU 1211 after calculations in the GPU 1212.

[0367] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0368] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0369] The interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, or a controller. The controller may include a mouse, a keyboard, or a game controller. Such an interface may be, for example, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI®).

[0370] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0371] The above-described multiple circuits (systems) can be formed in the chip 1200 using the same manufacturing process. Therefore, even if the number of required circuits increases, there is no need to increase the manufacturing process for the chip 1200. Therefore, the chip 1200 can be manufactured at low cost.

[0372] The package substrate 1201 on which the chip 1200 having the GPU 1212 is provided, the motherboard 1203 on which the DRAM 1221 and the flash memory 1222 are provided, can be collectively called a GPU module 1204.

[0373] The GPU module 1204 includes a chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, the GPU module 1204 is suitable for use in smartphones, tablet devices, laptop PCs, or portable electronic devices such as handheld (portable) game consoles. Furthermore, the GPU module 1204 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), or deep belief networks (DBNs) using a multiply-and-accumulate circuit using the GPU 1212. Therefore, the chip 1200 can be used as an AI chip. The GPU module 1204 can also be used as an AI system module.

[0374] At least part of the structures, methods, and the like described in this embodiment can be implemented in appropriate combination with other embodiment modes or other examples described in this specification and the like.

[0375] This embodiment describes an example of an electronic component and an electronic device incorporating, for example, a memory device described in the above embodiment, etc. By using the memory device described in the above embodiment, etc. in the following electronic component and electronic device, the electronic component and electronic device can achieve low power consumption and high speed.

[0376] <Electronic Component> First, an example of an electronic component incorporating the memory device 720 will be described with reference to FIGS. 26A and 26B.

[0377] FIG. 26A is a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 26A has a memory device 720 inside a mold 711. In FIG. 26A, some parts are omitted in order to show the interior of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713. The electrode pads 713 are electrically connected to the memory device 720 by wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0378] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722 .

[0379] The memory circuit layer 722 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 721 and the memory circuit layer 722 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 721 and the memory circuit layer 722 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration makes it possible to increase the operation speed of the interface between the processor and the memory.

[0380] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0381] It is also preferable that the memory cell arrays included in the memory circuit layer 722 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time. Also, the access latency is the time from access to the start of data exchange. Note that when Si transistors are used in the memory circuit layer 722, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0382] That is, OS transistors have an excellent effect of enabling a wider memory bandwidth than Si transistors.

[0383] The memory device 720 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0384] 26B is a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 720 provided on the interposer 731.

[0385] In the electronic component 730, for example, the storage device 720 can be used as a high bandwidth memory (HBM), and the semiconductor device 735 can be used as an integrated circuit (semiconductor device) such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0386] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The interposer 731 may be, for example, a silicon interposer, a resin interposer, etc.

[0387] The interposer 731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits with different terminal pitches via each of the plurality of wirings. The plurality of wirings are provided in a single layer or in multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer 731 is sometimes referred to as a "rewiring substrate" or "intermediate substrate." The interposer 731 may also be provided with through electrodes, which may be used to electrically connect the integrated circuits to the package substrate 732. When a silicon interposer is used for the interposer 731, TSVs may also be used as the through electrodes.

[0388] It is preferable to use a silicon interposer as the interposer 731. A silicon interposer does not require an active element, and therefore can be manufactured at lower cost than an integrated circuit. Furthermore, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0389] To achieve a wide memory bandwidth, an HBM needs to connect many wires. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0390] Furthermore, for example, SiP or MCM using a silicon interposer is less likely to suffer from a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer for a 2.5D package (2.5-dimensional packaging) in which multiple integrated circuits are arranged side by side on an interposer.

[0391] On the other hand, for example, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0392] The substrate on which the electronic component 730 is mounted may be provided with a heat sink (heat sink) overlapping the electronic component 730. When a heat sink is provided, it is preferable that the height of the integrated circuit provided on the interposer 731 is the same. For example, it is preferable that the height of the electronic component 730 described in this embodiment is the same as that of the memory device 720 and the semiconductor device 735.

[0393] In order to mount the electronic component 730 on another substrate, the package substrate 732 may have electrodes 733 on its bottom. FIG. 26B shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, the electronic component 730 can be mounted using a ball grid array (BGA) method. The electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, the electronic component 730 can be mounted using a pin grid array (PGA) method.

[0394] The electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA or PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0395] Note that the memory device of one embodiment of the present invention can be applied to electronic components to reduce power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or integration of memory devices, the use of the memory device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the memory device of one embodiment of the present invention consumes low power and is therefore effective as a countermeasure against global warming.

[0396] As described above, the structures or methods described in this embodiment can be used in appropriate combination with other structures or methods described in this embodiment, or structures or methods described in other embodiments or other examples.

[0397] (Embodiment 8) In this embodiment, an application example of a storage device using the storage device described in the above embodiments and the like will be described. The storage device described in the above embodiments and the like can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). By using the storage device described in the above embodiments and the like as a storage device for the electronic device, the electronic device can achieve low power consumption and high speed. Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. The storage device described in the above embodiments and the like can be applied to various removable storage devices such as a memory card (e.g., an SD card), a USB memory, or an SSD (solid state drive). FIGS. 27A to 27E are diagrams schematically illustrating several configuration examples of removable storage devices. For example, the storage device described in the above embodiments and the like can be processed into a packaged memory chip and used in various storage devices or removable memories.

[0398] 27A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. For example, the memory chip 1105 can incorporate the storage device described in the above embodiments.

[0399] FIG. 27B is a schematic diagram of the external appearance of an SD card. FIG. 27C is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a board 1113. The board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the board 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the board 1113 opposite the side on which the controller chip 1115 is attached. The SD card 1110 may also have a wireless chip with wireless communication capabilities provided on the board 1113. This allows the SD card 1110 to read or write data from the memory chip 1114 through wireless communication between the host device and the SD card 1110. For example, the memory chip 1114 can incorporate the storage device described in the above embodiments.

[0400] FIG. 27D is a schematic diagram of the external appearance of an SSD. FIG. 27E is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the board 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. The capacity of the SSD 1150 can be increased by providing a memory chip 1154 on the back side of the board 1153 opposite the side on which the controller chip 1156 is attached. For example, the memory chip 1154 can incorporate the storage device described in the above embodiments.

[0401] At least part of the structures, methods, and the like described in this embodiment can be implemented in appropriate combination with other embodiment modes or other examples described in this specification and the like.

[0402] (Embodiment 9) A memory device according to one embodiment of the present invention can be used in, for example, a processor such as a CPU or a GPU, or a chip. By using a processor such as a CPU or a GPU, or a chip using a memory device according to one embodiment of the present invention in an electronic device, the electronic device can achieve low power consumption and high speed. Figures 28A to 28H show specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip using the memory device.

[0403] <Electronic Devices and Systems> A GPU or chip according to one embodiment of the present invention can be installed in various electronic devices. Examples of electronic devices include electronic devices with relatively large screens, such as television devices, desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines. Other examples include digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by incorporating a GPU or chip according to one embodiment of the present invention into an electronic device, the electronic device can be equipped with artificial intelligence.

[0404] An electronic device according to one embodiment of the present invention may include an antenna. The electronic device can display, for example, video or information on a display portion by receiving a signal through the antenna. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0405] An electronic device according to one embodiment of the present invention may have a sensor (e.g., a sensor having the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light, etc.).

[0406] An electronic device according to one embodiment of the present invention can have various functions. For example, the electronic device can have a function of displaying various information (e.g., still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. FIGS. 28A to 28H show examples of electronic devices.

[0407] 28A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0408] The information terminal 5100 may include, for example, a power button, an operation button, a speaker, a microphone, a camera, a light source, and a control device. The control device may include, for example, one or more selected from a CPU, a GPU, and a storage device. The use of the storage device of one embodiment of the present invention in the control device is preferable because power consumption can be reduced.

[0409] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters or figures input by a user to a touch panel included in the display portion 5102 and displays the characters or figures on the display portion 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0410] 28B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0411] The notebook information terminal 5200 may include, for example, a pointing device, an external connection port, and a control device. The control device may include, for example, one or more selected from a CPU, a GPU, and a storage device. The use of the storage device of one embodiment of the present invention in the control device is preferable because power consumption can be reduced.

[0412] The notebook information terminal 5200 can execute applications using artificial intelligence by applying a chip according to one embodiment of the present invention, similar to the information terminal 5100 described above. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, a user of the notebook information terminal 5200 can develop new artificial intelligence.

[0413] 28A and 28B, a smartphone and a notebook type information terminal are illustrated as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be applied. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0414] [Gaming Machine] FIG. 28C illustrates a portable game machine 5300, which is an example of a game machine. The portable game machine 5300 includes, for example, a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connecting portion 5305, and operation keys 5306. The housings 5302 and 5303 can be detached from the housing 5301. By attaching the connecting portion 5305 of the housing 5301 to another housing (not shown), the portable game machine 5300 can output the video displayed on the display portion 5304 to another video device (not shown). In this case, the housings 5302 and 5303 can each function as an operation portion. This allows multiple players to play a game simultaneously on the portable game machine 5300. For example, the chips described in the above embodiments can be incorporated into the substrates of the housings 5301, 5302, and 5303.

[0415] 28D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wired connection.

[0416] For example, a game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, the game machine can reduce heat generation from a circuit due to low power consumption, and therefore, the influence of heat generation on the circuit itself, peripheral circuits, or modules can be reduced.

[0417] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can be realized as a portable game console having artificial intelligence.

[0418] In a game console, the expression of the progress of the game, the behavior of creatures appearing in the game, or phenomena occurring in the game is originally determined by the program of the game, but the application of artificial intelligence in the portable game console 5300 makes it possible to express things that are not limited to the game program. The portable game console 5300 makes it possible to express things such as changing the behavior of characters appearing in the game depending on, for example, the content of a question asked by the player, the progress of the game, or the time of day.

[0419] Furthermore, when playing a game that requires multiple players, the portable game console 5300 can create anthropomorphic game players using artificial intelligence, so that the game can be played by one player by making the opponent a game player using artificial intelligence.

[0420] 28C and 28D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (e.g., game arcades or amusement parks), and pitching machines for batting practice installed in sports facilities.

[0421] [Mainframe Computer] The GPU or chip according to one aspect of the present invention can be applied to a mainframe computer.

[0422] Fig. 28E is a diagram showing a supercomputer 5500, which is an example of a large computer. Fig. 28F is a diagram showing a rack-mounted calculator 5502 included in the supercomputer 5500.

[0423] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504. The board 5504 can be equipped with a GPU or a chip described in the above embodiment and the like.

[0424] The supercomputer 5500 is a large-scale computer mainly used for scientific and technological calculations. The supercomputer 5500 requires high-speed processing of a huge number of calculations, resulting in high power consumption and large heat generation from the chip. By applying a GPU or chip according to one embodiment of the present invention, the supercomputer 5500 can be realized as a low-power supercomputer. Furthermore, the low power consumption of the supercomputer 5500 can reduce heat generation from circuits, thereby reducing the impact of heat generation on the circuits themselves, peripheral circuits, or modules.

[0425] The supercomputer 5500 can also function as a parallel computer. By using the supercomputer 5500 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference in artificial intelligence, for example.

[0426] 28E and 28F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied include a computer that provides services (a server) or a large general-purpose computer (a mainframe).

[0427] Fig. 29A is a perspective view illustrating a specific example configuration of a computer 5502. In Fig. 29A, the computer 5502 has a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals (not shown). A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0428] PC card 5621 shown in FIG. 29B is an example of a processing board including, for example, a CPU, a GPU, and a storage device. PC card 5621 includes board 5622. Board 5622 also includes connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that FIG. 29B illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but for these semiconductor devices, the following description of semiconductor devices 5626, 5627, and 5628 may be referred to.

[0429] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe (Peripheral Component Interconnect Express).

[0430] Each of connection terminals 5623, 5624, and 5625 can be, for example, an interface for supplying power or inputting signals to PC card 5621. Furthermore, each of connection terminals 5623, 5624, and 5625 can be, for example, an interface for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include Universal Serial Bus (USB), Serial ATA (SATA), and Small Computer System Interface (SCSI). When video signals are output from connection terminals 5623, 5624, and 5625, examples of standards for each of connection terminals 5623, 5624, and 5625 include High-Definition Multimedia Interface (HDMI), a registered trademark.

[0431] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0432] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 described above can be used as the semiconductor device 5627.

[0433] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 described above can be used as the semiconductor device 5628.

[0434] [Mobile Body] The GPU or chip according to one embodiment of the present invention can be applied to a mobile body such as an automobile and the area around the driver's seat of the automobile.

[0435] Fig. 28G is a diagram showing the area around the windshield in the interior of an automobile, which is an example of a moving body, illustrating display panels 5701, 5702, and 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0436] The display panels 5701 to 5703 can provide various information by displaying, for example, a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, or air conditioning settings. Furthermore, the display items or layouts displayed on the display panels can be changed as needed to suit the user's preferences. Therefore, the display panels can have improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0437] The display panel 5704 can complement a view blocked by a pillar (blind spot) by displaying an image from an imaging device (not shown) installed in the vehicle. That is, the display panel 5704 can complement a blind spot and improve safety by displaying an image from an imaging device installed outside the vehicle. Furthermore, the display panel 5704 can display an image that complements an invisible part, allowing a driver to check for safety more naturally and without feeling uncomfortable. The display panel 5704 can also be used as a lighting device.

[0438] The GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence and can therefore be used, for example, in an autonomous driving system for automobiles. The chip can also be used, for example, in a system that provides road guidance or hazard prediction. The display panels 5701 to 5704 may be configured to display information such as road guidance or hazard prediction.

[0439] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. Other examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). By applying a chip according to one embodiment of the present invention to these moving objects, a system using artificial intelligence can be provided.

[0440] 28H shows an example of an electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 has, for example, a housing 5801, a refrigerator door 5802, and a freezer door 5803.

[0441] By applying the chip of one embodiment of the present invention, the electric refrigerator-freezer 5800 can be realized as an electric refrigerator-freezer 5800 having artificial intelligence. By using artificial intelligence, the electric refrigerator-freezer 5800 can have, for example, a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 or the expiration dates of the ingredients, a function of automatically adjusting the temperature according to the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0442] Although an electric refrigerator-freezer has been described as an example of an electrical appliance, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment.

[0443] Note that the storage device of one embodiment of the present invention can be applied to any one or more of electronic devices, information terminals, game consoles, large-scale computers, mobile objects, and electrical appliances to reduce power consumption. Therefore, while energy demand is expected to increase with the performance or integration of storage devices, the use of the storage device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the memory device of one embodiment of the present invention consumes low power and is therefore effective as a countermeasure against global warming.

[0444] For example, the electronic devices, functions of the electronic devices, application examples of artificial intelligence, or effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0445] At least part of the structures, methods, and the like described in this embodiment can be implemented in appropriate combination with other embodiment modes or other examples described in this specification and the like.

[0446] Embodiment 10 A semiconductor device of one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. In this embodiment, a specific example of application of the semiconductor device of one embodiment of the present invention to space equipment will be described with reference to FIG. 30 .

[0447] Fig. 30 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig. 30 also shows a planet 6804 in outer space. Although outer space refers to an altitude of 100 km or higher, the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0448] 30 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0449] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0450] The solar panel 6802 generates the power necessary for the operation of the satellite 6800 when irradiated with sunlight. However, for example, in a situation where the solar panel 6802 is not irradiated with sunlight or where the amount of sunlight irradiating the solar panel 6802 is small, the solar panel 6802 generates less power. Therefore, the satellite 6800 may not generate the power necessary for its operation. In order to operate the satellite 6800 even in a situation where the power generated by the solar panel 6802 is small, the satellite 6800 may be provided with a secondary battery 6805. Note that the solar panel 6802 may be called a solar cell module.

[0451] The satellite 6800 can generate a signal. The signal is transmitted via the antenna 6803. Furthermore, for example, a receiver installed on the ground or another satellite can receive the signal. For example, the receiver can measure the position of the receiver by receiving the signal transmitted by the satellite 6800. As described above, the satellite 6800 can constitute a satellite positioning system.

[0452] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor, which is one embodiment of the present invention. The OS transistor exhibits less change in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0453] That is, an OS transistor has an excellent effect of being more radiation resistant than a Si transistor.

[0454] The artificial satellite 6800 may also be configured to include a sensor. For example, the artificial satellite 6800 may be configured to include a visible light sensor, thereby enabling it to have the function of detecting sunlight reflected from an object on the ground. The artificial satellite 6800 may also be configured to include a thermal infrared sensor, thereby enabling it to have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 may function as, for example, an earth observation satellite.

[0455] Note that by applying the semiconductor device of one embodiment of the present invention to space equipment, power consumption can be reduced. Therefore, while energy demand is expected to increase with the improvement in performance or integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention consumes low power and is therefore effective as a countermeasure against global warming.

[0456] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0457] At least part of the structures, methods, and the like described in this embodiment can be implemented in appropriate combination with other embodiment modes or other examples described in this specification and the like.

[0458] In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) will be described. Note that the description of the OS transistor will be briefly compared with a transistor including silicon in a channel formation region (also referred to as a Si transistor).

[0459] [OS Transistor] An OS transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 １８ cm −３Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３ less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３ That is all. Note that in order to reduce the carrier concentration in an oxide semiconductor, the density of defect states in the oxide semiconductor may be reduced by reducing the impurity concentration in the oxide semiconductor. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0460] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Furthermore, charges trapped in the trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0461] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0462] Furthermore, when impurities or oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and reliability may be reduced. ＯH) in the channel formation region, generating electrons that serve as carriers. Ｏ When H is formed, the donor concentration in the channel formation region may increase. As a result, the threshold voltage of an OS transistor may vary as the donor concentration in the channel formation region increases. Therefore, if an OS transistor has oxygen vacancies in the channel formation region of an oxide semiconductor, the OS transistor is likely to have normally-on characteristics (a drain current flows when the gate voltage is 0 V). Therefore, in the channel formation region of an oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0463] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0464] Furthermore, as the size of Si transistors is reduced, a short channel effect (also referred to as SCE) occurs. This makes it difficult to reduce the size of Si transistors. One of the reasons for the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0465] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is kept constant in the subthreshold region.

[0466] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0467] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0468] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are each an n-type region. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or＋ / n − / n ＋ It can also be regarded as an accumulation type non-junction transistor structure.

[0469] The above structure enables an OS transistor to have good electrical characteristics even when miniaturized or highly integrated. For example, an OS transistor can have good electrical characteristics even when the gate length is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less and 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be suitably used as a transistor with a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in a direction in which carriers move inside a channel formation region during transistor operation and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.

[0470] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0471] As described above, an OS transistor has excellent advantages over a Si transistor in that it has a smaller off-state current and can be manufactured as a transistor with a short channel length.

[0472] The configuration, structure, method, or the like described in this embodiment can be used in appropriate combination with the configuration, structure, method, or the like described in other embodiment modes or other examples.

[0473] In this embodiment, a data center (also referred to as a DC) in which the semiconductor device described in the above embodiment can be used will be described. A data center using the semiconductor device of one embodiment of the present invention is effective in achieving high performance, such as low power consumption.

[0474] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. Data centers are required to perform long-term data management, such as ensuring data immutability. Long-term data management requires, for example, the installation of storage and servers for storing huge amounts of data, the provision of a stable power source for data retention, or the provision of cooling equipment required for data retention. Therefore, for example, the size of the data center building needs to be increased.

[0475] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, for example, it is possible to reduce the size of the storage system, the size of the power supply for storing data, and the size of the cooling equipment. Therefore, it is possible to reduce the space required for the data center.

[0476] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and peripheral modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0477] Fig. 31 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 31 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0478] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0479] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to write or read data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to write or read data.

[0480] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0481] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing the cache memory can be reduced and the power consumption of the cache memory can be reduced.Furthermore, by using a stacked memory cell array, the cache memory can be miniaturized.

[0482] Note that the application of the semiconductor device of one embodiment of the present invention to a data center can reduce power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention consumes low power and is therefore effective as a countermeasure against global warming.

[0483] The configuration, structure, method, or the like described in this embodiment can be used in appropriate combination with the configuration, structure, method, or the like described in other embodiment modes or other examples.

[0484] In this example, the results of estimating the write time, read time, memory density, and retention time of a memory device according to one embodiment of the present invention will be described.

[0485] 3B , 19A, and 19B, the memory device for which the write time, read time, memory density, and retention time were estimated had a memory array in which four layers (corresponding to layers 41[1] to 41[4]) in which memory cells (corresponding to memory cells 42) formed with OS transistors were stacked on a layer (corresponding to layer 30) in which a read circuit (corresponding to sense circuit 35) formed with OS transistors was provided. Furthermore, for example, drive circuits such as a driver, a sense amplifier, and a controller (corresponding to sense amplifier 55, for example) were provided on a substrate (corresponding to substrate 50) including Si transistors.

[0486] The storage device estimated in this example has a configuration in which DOSRAM memory cells are stacked, and may be called 3D DOSRAM.

[0487] Table 1 shows the results of estimating the write time, read time, memory density, and retention time of the 3D DOSRAM (hereinafter sometimes simply referred to as DOSRAM) configured as described above and a DRAM configured with Si transistors.

[0488]

[0489] As shown in Table 1, in the estimation of DOSRAM, the design rule for OS transistors was set to 30 nm, and in the estimation of DRAM, the design rule for Si transistors was set to 14 nm.

[0490] Table 1 also shows the results of estimation for three different DOSRAM configurations (condition A, condition B, and condition C).

[0491] In condition A, the DOSRAM memory cell has a configuration as shown in FIG. 24B, and the semiconductor layer (corresponding to oxide 230) of the OS transistor (corresponding to transistor 200) is a semiconductor layer in which the atomic ratio of metal elements is In:Ga:Zn=1:1:1.

[0492] In condition B, the memory cell of the DOSRAM has the configuration shown in FIG. 32, and the semiconductor layer of the OS transistor has an atomic ratio of metal elements of In:Ga:Zn=1:1:1.

[0493] In condition C, the DOSRAM memory cell has a configuration as shown in FIG. 24B , and the semiconductor layer of the OS transistor has a three-layer stacked structure in which a first semiconductor layer has an atomic ratio of metal elements of In:Ga:Zn=1:1:1, a second semiconductor layer has an atomic ratio of metal elements of In:Zn=4:1, and a third semiconductor layer has an atomic ratio of metal elements of In:Ga:Zn=1:1:1.

[0494] In the estimation of the DOSRAM shown in Table 1, the design values ​​of the channel length and channel width of the OS transistor were set to 30 nm and 30 nm, respectively, and the cell capacitance (corresponding to a capacitance of 100) was set to 1.5 fF.

[0495] 33 , 34 , and 35 show the Id-Vg characteristics of the OS transistor used for the estimation under conditions A, B, and C, respectively. Each of these figures shows the drain current Id (current flowing between the source and drain) when the gate voltage Vg (voltage between the source and gate) ranges from −1 V to 4 V under an environment of 27° C., with the drain voltage Vd (voltage between the source and drain) being 1.2 V and the backgate voltage Vb (voltage between the source and backgate) being 0 V. The Id-Vg characteristics (measurement) shown by the solid line are the Id-Vg characteristics of an actually fabricated OS transistor, and the Id-Vg characteristics (simulation) shown by the dashed line are the Id-Vg characteristics of the OS transistor used for the estimation. Note that FIG. 35 only shows the Id-Vg characteristics (simulation) shown by the dashed line.

[0496] Note that the on-state current Ion of the OS transistor (in this example, this is the drain current Id per 1 μm of channel width when the gate voltage Vg is 3.3 V in the Id-Vg characteristics (Measurement) shown by the solid line) was 272.6 μA / μm under condition A shown in FIG. 33 and 297.8 μA / μm under condition B shown in FIG. 34 .

[0497] As shown in Table 1, the estimated write times for DOSRAM were 7 ns, 6 ns, and 3 ns under conditions A, B, and C, respectively, which were shorter than the estimated 20 ns write time for DRAM under all conditions. The estimated read times for DOSRAM were 48 ns, 24 ns, and 16 ns under conditions A, B, and C, respectively, which was shorter than the estimated 20 ns read time for DRAM under condition C. In other words, it was found that DOSRAM may be able to achieve higher performance than DRAM in terms of write and read times, depending on the conditions.

[0498] In addition, in the density item where the memory density was estimated, the memory density of DOSRAM was estimated to be 77 cells / μm per layer. ２For example, by stacking five layers of memory cells, the estimated memory density of DRAM is 383 cells / μm ２ In other words, it was found that DOSRAM has the potential to surpass DRAM in performance in terms of memory density by increasing the number of layers.

[0499] In addition, in the data retention section, which estimates the data retention time, it was estimated that DOSRAM requires refreshing at least once every 6.4 seconds, while DRAM requires refreshing all memory cells once every 64 ms. As a result, it was found that the power required for refreshing DOSRAM could be reduced to 1 / 100 of the power required for refreshing DRAM.

[0500] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification and the like.

[0501] 10: semiconductor device, 20: layer, 30: layer, 40: layer, 41: layer, 50: substrate, 35: sense circuit, 35_pre: sense circuit, 37: switching circuit, 42: memory cell, 51: drive circuit, LBL: local bit line, LBL_pre: local bit line, GBL: global bit line, GBLB: global bit line, SA_GBL: global bit line, SA_GBLB: global bit line, BL: bit line, BLB: bit line, M0: transistor, M1: transistor, M2: transistor, M3: transistor, M4: transistor, SW0: signal line signal, SW1: signal, SW2: signal, SW3: signal, VPRE2: potential, MUX: signal, WE: signal, RE: signal, SL: wiring, WL: word line, CSL: wiring, EQ: signal, EQB: signal, CSEL: signal, VPRE: potential, SAP: wiring, SAN: wiring, 31: transistor, 32: transistor, 33: transistor, 34: transistor, 43: transistor, 44: capacitance, MND: node, 52: switch circuit, 53: precharge circuit, 54: precharge circuit, 55: sense amplifier, 52_1: transistor, 52_2: transistor, 5 3_1: transistor, 53_2: transistor, 53_3: transistor, 54_1: transistor, 54_2: transistor, 54_3: transistor, 55_1: transistor, 55_2: transistor, 55_3: transistor, 55_4: transistor, T11: time, T12: time, T13: time, T14: time, T15: time, T16: time, T21: time, T22: time, T23: time, T24: time, 300: storage device, 21: memory array, 22: drive circuit, 62: PSW, 63: PSW, 71: peripheral circuit, 72: control circuit Path, 73: Voltage generation circuit, 81: Peripheral circuit, 82: Row decoder, 83: Row driver, 84: Column decoder, 85: Column driver, 87: Input circuit, 88: Output circuit, BW: Signal, CE: Signal, GW: Signal, CLK: Signal, WAKE: Signal, ADDR: Signal, WDA: Signal, RDA: Signal, PON1: Signal, PON2: Signal, VDD: Potential, VHM: Potential, GND: Ground potential, Din: Data, Dout: Data, 90: Electronic computer, 91: Processor, 92: Main memory, 93: Core, 94: Cache memory, 95: Interface, S01: Step,S02: step, S03: step, 10A: semiconductor device, 37A: switching circuit, C1: capacitance, C2: capacitance, BOOT1: signal, BOOT2: signal, 10B: semiconductor device, 37B: switching circuit, 51B: drive circuit, 56: precharge circuit, M5: transistor, M6: transistor, SW5: signal, SW6: signal, VPRE3: potential, 370A: storage device, 371: memory array unit, 372: memory unit, 373: word line driver unit, 374: column driver section, 375: sense amplifier driver section, 376: sense circuit driver section, 377: data sense amplifier section, 378: memory controller section, 370B: memory device, 373L: layer selection driver section, 373Lbuf: layer selection driver, ML1: transistor, ML2: transistor, ML3: transistor, CL1: capacitance, BL1: node, LSEL: signal, LSELB: signal, VLD: potential, VLS: potential, WL in: word line, WLout: word line, TL1: time, TL2: time, 42a: memory cell, 42b: memory cell, 42c: memory cell, 42d: memory cell, 42e: memory cell, Ma: transistor, Mb: transistor, Mc: transistor, Ca: capacitance, FN: node, BGL: back gate line, WWL: word line, RWL: word line, WBL: bit line, RBL: bit line, 380: chip, 381: module, 382 : region, 383: region, 384: region, 385: region, 386: region, 735: semiconductor device, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 1104: substrate, 1113: substrate, 1153: substrate, 5504: substrate, 200: transistor, 200a: transistor, 200b: transistor, 100: capacitance, 100a: capacitance, 100b: capacitance, 1200: chip, 720: storage device, 7003md: storage device,

Claims

1. It comprises a first circuit, a second circuit, a third circuit, a fourth circuit, a fifth circuit, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring. The first circuit is electrically connected to the second circuit via the first wiring, The first circuit is electrically connected to the fourth circuit via the third and fourth wiring, respectively. The second circuit is electrically connected to the third circuit via the fifth wiring, The first circuit has the function of making the first wiring, the second wiring, the third wiring, and the fourth wiring each conduct or not conduct, The third circuit has the function of holding the potential corresponding to the first data, The second circuit has the function of supplying a potential corresponding to the first data from the first wiring to the fifth wiring, the function of holding the potential corresponding to the second data, and the function of amplifying the change in the potential of the fifth wiring and outputting it to the first wiring. The fourth circuit has the function of outputting a potential corresponding to the first data or the second data according to the potential difference between the third wiring and the fourth wiring. The fourth circuit is provided on the circuit board, The first circuit and the second circuit are provided on the first layer arranged on the substrate, The third circuit is provided on each of the plurality of second layers arranged on the substrate, The fifth circuit is provided in each of the plurality of second layers, The fifth circuit has the function of outputting a signal to control the operation of the third circuit. Semiconductor equipment.

2. In claim 1, The first circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor has the function of making the connection between the first wiring and the second wiring conductive or non-conductive. The second transistor has the function of making the connection between the first wiring and the third wiring conductive or non-conductive. The third transistor has the function of making the connection between the second wiring and the fourth wiring conductive or non-conductive. The fourth transistor has the function of pre-charging the first wiring, The fifth transistor has the function of pre-charging the second wiring. Semiconductor equipment.

3. In claim 1, The first circuit comprises a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor has the function of making the connection between the first wiring and the second wiring conductive or non-conductive. The second transistor has the function of making the connection between the first wiring and the third wiring conductive or non-conductive. The third transistor has the function of making the connection between the second wiring and the fourth wiring conductive or non-conductive. The first capacitance has the function of changing the potential of the first wiring, The second capacitance has the function of changing the potential of the second wiring. Semiconductor equipment.

4. In claim 1, The first circuit comprises a first transistor, a second transistor, and a third transistor. The first transistor has the function of making the connection between the first wiring and the second wiring conductive or non-conductive. The second transistor has the function of making the connection between the first wiring and the third wiring conductive or non-conductive. The third transistor has the function of making the connection between the second wiring and the fourth wiring conductive or non-conductive. The fourth circuit comprises a sixth transistor and a seventh transistor, The sixth transistor has the function of pre-charging the third wiring, The seventh transistor has the function of pre-charging the fourth wiring. Semiconductor equipment.

5. In any one of claims 1 to 4, The aforementioned substrate includes a Si transistor, Each of the first layer and the plurality of second layers includes an OS transistor. Semiconductor equipment.