Semiconductor device

Abstract

A semiconductor device according to the present invention comprises an insulating layer, a conductive layer, a heat dissipation layer, a semiconductor element and a bonding layer. The conductive layer has a main surface which faces a direction that is opposite to the direction that faces the insulating layer in a first direction; and the conductive layer is bonded to the insulating layer. The heat dissipation layer is positioned on the opposite side of the conductive layer with respect to the insulating layer, and is bonded to the insulating layer. The semiconductor element is bonded to the main surface. The bonding layer bonds the main surface and the semiconductor element to each other. The conductive layer is provided with a recess that is recessed from the main surface. When viewed in the first direction, the bonding layer has a first part that is positioned between the semiconductor element and the recess; and the first part covers the main surface.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses an example of a semiconductor device (power module) in which multiple semiconductor elements are bonded to a conductor layer. The multiple semiconductor elements are bonded to the conductor layer via a solder layer. In this way, the multiple semiconductor elements are mounted on the conductor layer.

[0003] In the semiconductor device disclosed in Patent Document 1, when multiple semiconductor elements are bonded to a conductor layer, the positions of the multiple semiconductor elements relative to the conductor layer may become misaligned due to the spreading of the solder layer. If the misalignment of the multiple semiconductor elements becomes large, problems may occur, such as requiring a longer time for conductive bonding of wires or the like to each of the multiple semiconductor elements. Therefore, it is desirable to improve the accuracy of the bonding positions of the semiconductor elements relative to the conductor layer.

[0004] JP 2016-162773 A

[0005] An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can further improve the accuracy of the bonding position of a semiconductor element to a conductive layer.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes an insulating layer, a conductive layer having a main surface facing away from the side facing the insulating layer in a first direction and bonded to the insulating layer, a heat dissipation layer located on the opposite side of the insulating layer from the conductive layer and bonded to the insulating layer, a semiconductor element bonded to the main surface, and a bonding layer bonding the main surface to the semiconductor element. The conductive layer has a recess recessed from the main surface. When viewed in the first direction, the bonding layer has a first portion located between the semiconductor element and the recess, and the first portion covers the main surface.

[0007] According to the above configuration, in the semiconductor device, it is possible to further improve the accuracy of the bonding position of the semiconductor element to the conductive layer.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a plan view corresponding to FIG. 2, seen through a sealing resin. FIG. 4 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 5 is a front view of the semiconductor device shown in FIG. 1. FIG. 6 is a right side view of the semiconductor device shown in FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. FIG. 9 is a partially enlarged view of FIG. 3, showing a plurality of first elements and their vicinity. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 9. FIG. 11 is a partially enlarged view of FIG. 10. FIG. 12 is a partially enlarged view of FIG. 3, showing a plurality of second elements and their vicinity. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is a partially enlarged plan view of a semiconductor device according to a first modification of the first embodiment of the present disclosure, corresponding to FIG. 9. FIG. 15 is a partially enlarged plan view of a semiconductor device according to a second modified example of the first embodiment of the present disclosure, corresponding to FIG. 9 . FIG. 16 is a partially enlarged plan view of a semiconductor device according to a third modified example of the first embodiment of the present disclosure, corresponding to FIG. 9 . FIG. 17 is a partially enlarged cross-sectional view of a semiconductor device according to a fourth modified example of the first embodiment of the present disclosure, corresponding to FIG. 11 . FIG. 18 is a perspective view of a semiconductor device according to the second embodiment of the present disclosure. FIG. 19 is a plan view of the semiconductor device shown in FIG. 18 . FIG. 20 is a plan view of the semiconductor device shown in FIG. 18 , seen through the sealing resin. FIG. 21 is a front view of the semiconductor device shown in FIG. 18 . FIG. 22 is a right side view of the semiconductor device shown in FIG. 18 . FIG. 23 is a left side view of the semiconductor device shown in FIG. 18 . FIG. 24 is a bottom view of the semiconductor device shown in FIG. 18 . FIG. 25 is a partially enlarged view of FIG. 20 . FIG. 26 is a partially enlarged view of FIG. 20 . FIG. 27 is a cross-sectional view taken along line XXVII-XXVII of FIG. 20 . Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII in Fig. 20. Fig. 29 is a cross-sectional view taken along line XXIX-XXIX in Fig. 20. Fig. 30 is a cross-sectional view taken along line XXX-XXX in Fig. 20. Fig. 31 is a partially enlarged view of Fig. 25, showing one of the plurality of first elements and its vicinity. Fig. 32 is a cross-sectional view taken along line XXXII-XXXII in Fig. 31.Fig. 33 is a partially enlarged view of Fig. 25, showing one of the second elements and its vicinity, and Fig. 34 is a cross-sectional view taken along line XXXIV-XXXIV in Fig. 33.

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0011] First Embodiment: A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 13. The semiconductor device A10 includes an insulating layer 11, multiple conductive layers 12, a heat dissipation layer 13, multiple input terminals 21, multiple output terminals 22, multiple semiconductor elements 31, a bonding layer 39, multiple first wires 41, multiple second wires 42, and a sealing resin 50. The semiconductor device A10 also includes multiple control terminals 23, dummy terminals 29, multiple ICs 33, multiple diodes 34, multiple third wires 43, multiple fourth wires 44, multiple fifth wires 45, and multiple sixth wires 46. For ease of understanding, FIG. 3 shows the sealing resin 50 in a perspective view. The transparent sealing resin 50 is indicated by an imaginary line (double-dashed line) in FIG. 3. In FIG. 3, lines VII-VII and VIII-VIII are indicated by dashed lines, respectively.

[0012] In the description of the semiconductor device A10, for convenience, the normal direction to a main surface 121 of a conductive layer 12 (described later) will be referred to as the "first direction z." One direction perpendicular to the first direction z will be referred to as the "second direction x." The direction perpendicular to the first direction z and the second direction x will be referred to as the "third direction y."

[0013] The semiconductor device A10 converts DC power input to a plurality of input terminals 21 into AC power using a plurality of semiconductor elements 31. The converted AC power is output from a plurality of output terminals 22 as three phases (U phase, V phase, and W phase) with different phases. Furthermore, in the semiconductor device A10, a plurality of ICs 33 drive the plurality of semiconductor elements 31. Therefore, the semiconductor device A10 is an IPM (Intelligent Power Module). The semiconductor device A10 is used, for example, in a power supply circuit for driving a three-phase AC motor.

[0014] 3, 7, and 8, the insulating layer 11 supports a plurality of conductive layers 12. The insulating layer 11 is made of ceramics containing, for example, aluminum nitride (AlN). The insulating layer 11 has a rectangular shape with its longer side aligned in the second direction x.

[0015] 7 and 8 , the plurality of conductive layers 12 are bonded to the insulating layer 11. The composition of the plurality of conductive layers 12 includes copper (Cu). When viewed in the first direction z, the plurality of conductive layers 12 are surrounded by the outer edge of the insulating layer 11. The dimension of each of the plurality of conductive layers 12 in the first direction z is larger than the dimension of the insulating layer 11 in the first direction z.

[0016] 7, each of the plurality of conductive layers 12 has a main surface 121. The main surface 121 faces the side opposite to the side facing the insulating layer 11 in the first direction z. As shown in Fig. 3, the plurality of conductive layers 12 includes a first conductive layer 12A and a plurality of second conductive layers 12B. The plurality of second conductive layers 12B are located on one side of the first conductive layer 12A in the second direction x.

[0017] 7 and 8 , the heat dissipation layer 13 is located on the opposite side of the insulating layer 11 from the plurality of conductive layers 12. The heat dissipation layer 13 is bonded to the insulating layer 11. The heat dissipation layer 13 contains copper. When viewed in the first direction z, the heat dissipation layer 13 is surrounded by the outer edge of the insulating layer 11. The dimension of the heat dissipation layer 13 in the first direction z is larger than the dimension of the insulating layer 11 in the first direction z.

[0018] In the semiconductor device A10, the insulating layer 11, the plurality of conductive layers 12, and the heat dissipation layer 13 are obtained from a DBC (Direct Bonded Copper) substrate by etching copper foil that forms part of the DBC substrate.

[0019] 3 and 7 , each of the plurality of semiconductor elements 31 is bonded to a main surface 121 of one of the plurality of conductive layers 12. The plurality of semiconductor elements 31 includes a plurality of first elements 31A and a plurality of second elements 31B. The plurality of first elements 31A are bonded to a main surface 121 of a first conductive layer 12A of the plurality of conductive layers 12. The plurality of second elements 31B are individually bonded to a respective main surface 121 of a plurality of second conductive layers 12B of the plurality of conductive layers 12.

[0020] The semiconductor elements 31 are, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, the semiconductor elements 31 may be switching elements such as insulated gate bipolar transistors (IGBTs) or diodes. In the description of the semiconductor device A10, the semiconductor elements 31 are n-channel MOSFETs with a vertical structure. The semiconductor elements 31 include a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC). As shown in FIG. 9 , the semiconductor elements 31 have a first electrode 311, a second electrode 312, and a gate electrode 313.

[0021] 9 , the first electrode 311 faces one of the main surfaces 121 of the plurality of conductive layers 12. A current corresponding to the power before being converted by the semiconductor element 31 flows through the first electrode 311. In other words, the first electrode 311 corresponds to the drain electrode of the semiconductor element 31.

[0022] 9 , the second electrode 312 is located on the opposite side of the first electrode 311 in the first direction z. A current corresponding to the power converted by the semiconductor element 31 flows through the second electrode 312. That is, the second electrode 312 corresponds to the source electrode of the semiconductor element 31. The second electrode 312 includes a plurality of metal plating layers. The second electrode 312 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer. Alternatively, the second electrode 312 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer.

[0023] 9 , the gate electrode 313 is provided on the same side as the second electrode 312 in the first direction z, and is positioned away from the second electrode 312. A gate voltage for driving the semiconductor element 31 is applied to the gate electrode 313. As shown in FIG. 10 , the area of ​​the gate electrode 313 is smaller than the area of ​​the second electrode 312 when viewed in the first direction z.

[0024] 7 and 8 , the bonding layer 39 bonds the main surface 121 of any one of the plurality of conductive layers 12 to any one of the plurality of semiconductor elements 31. The first electrode 311 of each of the plurality of first elements 31A is conductively bonded to the main surface 121 of the first conductive layer 12A via the bonding layer 39. The first electrode 311 of each of the plurality of second elements 31B is individually conductively bonded to the main surface 121 of each of the plurality of second conductive layers 12B via the bonding layer 39. The bonding layer 39 is solder.

[0025] 3, at least one recess 19 is provided in each of the plurality of conductive layers 12. The recess 19 is recessed from one of the main surfaces 121 of the plurality of conductive layers 12. The first conductive layer 12A is provided with a plurality of recesses 19. When viewed in the first direction z, the plurality of recesses 19 provided in the first conductive layer 12A individually surround the plurality of first elements 31A. The plurality of second conductive layers 12B are provided with a recess 19 located around one of the plurality of second elements 31B.

[0026] 9 and 12 , when viewed in the first direction z, the bonding layer 39 has a first portion 391 located between any one of the plurality of semiconductor elements 31 and the recess 19. As shown in FIGS. 10 and 13 , the first portion 391 covers the main surface 121 of any one of the plurality of conductive layers 12.

[0027] 10 and 13 , each of the plurality of conductive layers 12 has an inner circumferential surface 122. The inner circumferential surface 122 is connected to the main surface 121 of one of the plurality of conductive layers 12 and defines a recess 19. As shown in FIG. 11 , a first portion 391 of the bonding layer 39 is in contact with a boundary 121A between the inner circumferential surface 122 and the main surface 121. An end face 391A of the first portion 391 is inclined with respect to the main surface 121. The end face 391A is inclined with respect to the main surface 121 because, when each of the plurality of semiconductor elements 31 is bonded to one of the plurality of conductive layers 12, surface tension acts on the molten bonding layer 39 at the boundary 121A.

[0028] As shown in FIG. 11 , the inner circumferential surface 122 has a first circumferential surface 122A, a second circumferential surface 122B, and a third circumferential surface 122C. The first circumferential surface 122A and the second circumferential surface 122B face each other in a direction perpendicular to the first direction z. Of these, the first circumferential surface 122A is located closest to one of the multiple semiconductor elements 31. The first circumferential surface 122A and the second circumferential surface 122B approach each other in the first direction z as they move from the main surface 121 of one of the multiple conductive layers 12 toward the insulating layer 11. Each of the first circumferential surface 122A and the second circumferential surface 122B curves inward toward one of the multiple conductive layers 12. The third circumferential surface 122C is connected to the first circumferential surface 122A and the second circumferential surface 122B. The third circumferential surface 122C faces the same side as the main surface 121 in the first direction z.

[0029] 10 and 13 , in the semiconductor device A10, the first conductive layer 12A has a plurality of pedestals 123. The plurality of pedestals 123 are individually surrounded by a plurality of recesses 19 provided in the first conductive layer 12A. Each of the plurality of pedestals 123 includes a main surface 121 of the first conductive layer 12A. The first electrode 311 of each of the plurality of first elements 31A is individually conductively bonded to the main surface 121 of each of the plurality of pedestals 123 via a bonding layer 39. The cross-sectional area of ​​each of the plurality of pedestals 123 in the first direction z increases from the main surface 121 of the first conductive layer 12A toward the insulating layer 11.

[0030] 12 , in the semiconductor device A10, the recesses 19 provided in each of the multiple second conductive layers 12B extend in a direction intersecting the periphery 314 of one of the multiple second elements 31B as viewed in the first direction z. The recesses 19 include a first recess 19A, a second recess 19B, a third recess 19C, and a fourth recess 19D. The first recess 19A, the second recess 19B, the third recess 19C, and the fourth recess 19D are separated from one another. The first recess 19A and the second recess 19B are located on opposite sides of the second element 31B in the second direction x. The third recess 19C and the fourth recess 19D are located on opposite sides of the second element 31B in the third direction y. Each of the first recess 19A, the second recess 19B, the third recess 19C, and the fourth recess 19D includes two separated portions.

[0031] The input terminals 21, the output terminals 22, the control terminals 23, and the dummy terminals 29 are formed from the same lead frame. The lead frame is made of a material containing copper (Cu) or a copper alloy. Therefore, the input terminals 21, the output terminals 22, the control terminals 23, and the dummy terminals 29 all contain copper.

[0032] 3 , the multiple input terminals 21 include a first input terminal 21A and multiple second input terminals 21B. The multiple second input terminals 21B are located on the opposite side of the multiple output terminals 22 from the first input terminal 21A. Each of the multiple input terminals 21 has an external connection portion 211 and an internal connection portion 212. The external connection portion 211 is exposed to the outside from the sealing resin 50. The internal connection portion 212 is connected to the external connection portion 211 and is covered by the sealing resin 50.

[0033] 8, the internal connection portion 212 of the first input terminal 21A is conductively joined to the main surface 121 of the first conductive layer 12A via the joining layer 39. The first input terminal 21A corresponds to a P terminal (positive electrode) to which DC power to be converted is input.

[0034] The second input terminals 21B are spaced apart from the insulating layer 11. The second input terminals 21B are supported by the sealing resin 50. As shown in Fig. 3 , the second input terminals 21B are spaced apart from the conductive layers 12 when viewed in the first direction z. The second input terminals 21B correspond to N terminals (negative electrodes) to which DC power to be converted is input.

[0035] 3 , the plurality of output terminals 22 are located between the first input terminal 21A and the plurality of second input terminals 21B in the second direction x. The plurality of output terminals 22 include a first output terminal 22A, a second output terminal 22B, and a third output terminal 22C. Each of the output terminals 22 has an external connection portion 221 and an internal connection portion 222. The external connection portion 221 is exposed to the outside from the sealing resin 50. The internal connection portion 222 is connected to the external connection portion 221 and is covered by the sealing resin 50.

[0036] The internal connection portions 222 of the plurality of output terminals 22 are individually conductively bonded to the main surfaces 121 of the plurality of second conductive layers 12B via bonding layers 39. The plurality of output terminals 22 output three-phase AC power converted by the plurality of semiconductor elements 31.

[0037] 3, the multiple first wires 41 are individually conductively bonded to the second electrodes 312 of the multiple first elements 31A and to the internal connection portions 222 of the multiple output terminals 22. As a result, the second electrodes 312 of the multiple first elements 31A are individually conductively connected to the multiple second conductive layers 12B. Furthermore, the first electrodes 311 of the multiple second elements 31B are also conductively connected to the second electrodes 312 of any of the multiple first elements 31A. The composition of the multiple first wires 41 includes aluminum (Al). Alternatively, the composition of the multiple first wires 41 may include copper.

[0038] 3, the second wires 42 are individually conductively bonded to the second electrodes 312 of the second elements 31B and to the second input terminals 21B. As a result, the second electrodes 312 of the second elements 31B are individually conductively connected to the second input terminals 21B. The second wires 42 include aluminum. Alternatively, the second wires 42 may include copper.

[0039] In the semiconductor device A10, a plurality of upper arm circuits are formed by the first conductive layer 12A, a plurality of first elements 31A, and a plurality of first wires 41. In addition, a plurality of lower arm circuits are formed by the plurality of second conductive layers 12B, a plurality of second elements 31B, a plurality of second wires 42, and a plurality of second input terminals 21B. Therefore, the voltage applied to the gate electrode 313 of each of the plurality of first elements 31A differs from the voltage applied to the gate electrode 313 of each of the plurality of second elements 31B. Furthermore, since the semiconductor device A10 includes a plurality of second input terminals 21B, the grounds of the plurality of lower arm circuits are individually set in the semiconductor device A10.

[0040] 3, the plurality of control terminals 23 are located on the opposite side of the plurality of input terminals 21 and the plurality of output terminals 22 with respect to the plurality of conductive layers 12 in the third direction y. Similar to the plurality of second input terminals 21B, the plurality of control terminals 23 are located away from the insulating layer 11 and are supported by the sealing resin 50. As shown in FIGS. 2 and 4, a portion of each of the plurality of control terminals 23 is exposed to the outside from the sealing resin 50.

[0041] 3 , the plurality of control terminals 23 include a pad portion 231, a plurality of power supply portions 232, a plurality of first control portions 233, a plurality of second control portions 234, and a dummy portion 235. The pad portion 231 is mounted with a plurality of ICs 33. Furthermore, the pad portion 231 serves as the ground for the plurality of ICs 33. The plurality of ICs 33 are located on the opposite side of the plurality of conductive layers 12 from the plurality of input terminals 21 and the plurality of output terminals 22 in the third direction y.

[0042] 3 , the multiple ICs 33 include a first IC 33A and a second IC 33B that are spaced apart from each other in the second direction x. A power supply that serves as a basis for gate voltages for driving the multiple first elements 31A is input to the multiple power supply units 232. Electrical signals related to control of the first IC 33A are input / output to the multiple first control units 233. Electrical signals related to control of the second IC 33B are input / output to the multiple second control units 234. The dummy unit 235 is not electrically connected to the multiple ICs 33.

[0043] 8, the first IC 33A is bonded to the pad portion 231 via a bonding layer 39. As shown in Fig. 3, the first IC 33A is located closer to the first conductive layer 12A than the second IC 33B. The first IC 33A applies a gate voltage to the gate electrodes 313 of the multiple first elements 31A.

[0044] Similar to the first IC 33A, the second IC 33B is bonded to the pad portion 231 via the bonding layer 39. As shown in Fig. 3, the second IC 33B is located closer to the second conductive layers 12B than the first IC 33A. The second IC 33B applies a gate voltage to the gate electrodes 313 of the second elements 31B.

[0045] 8, the plurality of diodes 34 are individually conductively bonded to the plurality of power supply units 232 via bonding layers 39. The plurality of diodes 34 prevent a reverse bias from being applied to the plurality of power supply units 232 when the plurality of first elements 31A are driven.

[0046] 3, the plurality of third wires 43 are conductively bonded to the first IC 33A and the second electrode 312 and gate electrode 313 of each of the plurality of first elements 31A. This allows a gate voltage to be applied from the first IC 33A to the gate electrodes 313 of the plurality of first elements 31A. At the same time, the first IC 33A sets the ground for this gate voltage. The composition of the plurality of third wires 43 includes, for example, gold.

[0047] 3, the plurality of fourth wires 44 are conductively bonded to the second IC 33B and the gate electrodes 313 of the plurality of second elements 31B. This allows a gate voltage to be applied from the second IC 33B to the gate electrodes 313 of the plurality of second elements 31B. The composition of the plurality of fourth wires 44 includes, for example, gold.

[0048] 3, the plurality of fifth wires 45 are conductively joined to the first IC 33A, the pad portion 231, the plurality of power supply portions 232, the plurality of diodes 34, and the plurality of first control portions 233. As a result, the pad portion 231, the plurality of power supply portions 232, the plurality of diodes 34, and the plurality of first control portions 233 are electrically connected to the first IC 33A. The composition of the plurality of fifth wires 45 includes, for example, gold.

[0049] 3, the sixth wires 46 are connected to the second IC 33B, the pad 231, and the second control units 234. This provides electrical continuity between the pad 231 and the second control units 234 and the second IC 33B. The sixth wires 46 may contain, for example, gold.

[0050] 3, the dummy terminal 29 is spaced apart from the insulating layer 11 when viewed in the first direction z. The dummy terminal 29 is located on the opposite side of the first input terminal 21A from the plurality of output terminals 22 in the second direction x. As shown in FIGS. 2, 4, and 6, a portion of the dummy terminal 29 is exposed to the outside from the sealing resin 50.

[0051] As shown in FIGS. 7 and 8 , the sealing resin 50 covers the plurality of conductive layers 12, the plurality of semiconductor elements 31, the plurality of ICs 33, the internal connection portions 212 of the plurality of input terminals 21, and the internal connection portions 222 of the plurality of output terminals 22. The sealing resin 50 also covers a portion of each of the plurality of control terminals 23 and a portion of the dummy terminals 29. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, black epoxy resin. As shown in FIGS. 10 and 13 , a portion of the sealing resin 50 fills the recesses 19 provided in each of the plurality of conductive layers 12. The sealing resin 50 has a top surface 51, a bottom surface 52, a pair of first side surfaces 53, a pair of second side surfaces 54, and a pair of recesses 55.

[0052] 7 and 8, the top surface 51 faces the same side as the main surfaces 121 of the plurality of conductive layers 12 in the first direction z. As shown in Fig. 7 and 8, the bottom surface 52 faces the opposite side from the main surfaces 121 in the first direction z. Therefore, the top surface 51 and the bottom surface 52 face opposite sides to each other in the first direction z. As shown in Fig. 4, the heat dissipation layer 13 is exposed to the outside from the bottom surface 52.

[0053] 2, 4, and 5, the pair of first side surfaces 53 are spaced apart from each other in the second direction x. The pair of first side surfaces 53 are connected to the top surface 51 and the bottom surface 52.

[0054] 2 , 4 , and 6 , the pair of second side surfaces 54 are spaced apart from each other in the third direction y. The pair of second side surfaces 54 are connected to the top surface 51 and the bottom surface 52. From one of the pair of second side surfaces 54, the external connection portions 211 of the multiple input terminals 21, the external connection portions 221 of the multiple output terminals 22, and portions of the dummy terminals 29 are exposed to the outside. From the other of the pair of second side surfaces 54, portions of the multiple control terminals 23 are exposed to the outside.

[0055] 2, 4, and 6, the pair of recesses 55 are recessed in the second direction x from the pair of first side surfaces 53. In the first direction z, the pair of recesses 55 extend from the top surface 51 to the bottom surface 52. The pair of recesses 55 ensure a longer creepage distance of the sealing resin 50 from the external connection portion 211 of any one of the plurality of input terminals 21 to any one of the plurality of control terminals 23. In addition, a longer creepage distance of the sealing resin 50 from any one of the plurality of second input terminals 21B to any one of the plurality of control terminals 23 is also ensured. This is advantageous in terms of improving the dielectric strength voltage of the semiconductor device A10.

[0056] First Modification of First Embodiment: Next, a semiconductor device A11, which is a first modification of the semiconductor device A10, will be described with reference to Fig. 14. The position in Fig. 14 corresponds to the position in Fig. 9.

[0057] 14 , in the semiconductor device A11, each of the multiple recesses 19 provided in the first conductive layer 12A extends along the periphery 314 of one of the multiple first elements 31A as viewed in the first direction z. Each of the multiple recesses 19 includes a first recess 19A, a second recess 19B, a third recess 19C, and a fourth recess 19D. The first recess 19A and the second recess 19B are located on opposite sides of the first element 31A in the second direction x. The third recess 19C and the fourth recess 19D are located on opposite sides of the first element 31A in the third direction y. In this modification, each of the first recess 19A, the second recess 19B, the third recess 19C, and the fourth recess 19D is a single recess. Alternatively, each of the first recess 19A, the second recess 19B, the third recess 19C and the fourth recess 19D may include two separate portions as shown in FIG.

[0058] Second Modification of First Embodiment Next, a semiconductor device A12, which is a second modification of the semiconductor device A10, will be described with reference to Fig. 15. The position in Fig. 15 corresponds to the position in Fig. 9.

[0059] 15 , in the semiconductor device A12, each of the multiple recesses 19 provided in the first conductive layer 12A extends along the periphery 314 of one of the multiple first elements 31A when viewed in the first direction z. Each of the multiple recesses 19 includes a first recess 19A, a second recess 19B, a third recess 19C, and a fourth recess 19D. Each of the first recess 19A, the second recess 19B, the third recess 19C, and the fourth recess 19D is located closest to one of the four corners of the first element 31A.

[0060] 15 , as viewed in the first direction z, the periphery 314 of the first element 31A has a first periphery 314A and a second periphery 314B. The second periphery 314B extends in a different direction from the first periphery 314A and is connected to the first periphery 314A. The first recess 19A, the second recess 19B, the third recess 19C, and the fourth recess 19D each have a first groove 191 and a second groove 192. The first groove 191 extends along the first periphery 314A. The second groove 192 extends along the second periphery 314B and is connected to the first groove 191. As viewed in the first direction z, the first groove 191 intersects with an extension line EL2 of the second periphery 314B. When viewed in the first direction z, the second groove 192 intersects with an extension line EL1 of the first periphery 314A.

[0061] Third Modification of First Embodiment Next, a semiconductor device A13, which is a third modification of the semiconductor device A10, will be described with reference to Fig. 16. The position in Fig. 16 corresponds to the position in Fig. 9.

[0062] 16 , in the semiconductor device A13, each of the multiple recesses 19 provided in the first conductive layer 12A extends in a direction intersecting the periphery 314 of one of the multiple first elements 31A when viewed in the first direction z. The multiple recesses 19 include a first recess 19A, a second recess 19B, a third recess 19C, and a fourth recess 19D. The first recess 19A and the second recess 19B are located on opposite sides of each other with respect to the first element 31A. The third recess 19C and the fourth recess 19D are located on opposite sides of each other with respect to the first element 31A. Each of the first recess 19A, the second recess 19B, the third recess 19C, and the fourth recess 19D is located closest to one of the four corners of the first element 31A.

[0063] Fourth Modification of First Embodiment: Next, a semiconductor device A14, which is a fourth modification of the semiconductor device A10, will be described with reference to Fig. 17. The position in Fig. 17 corresponds to the position in Fig. 11.

[0064] 17, in the semiconductor device A14, the first peripheral surface 122A and the second peripheral surface 122B are connected to each other on the inner peripheral surface 122 of any one of the plurality of conductive layers 12 that define the recess 19. Therefore, in the semiconductor device A14, the inner peripheral surface 122 does not include a third peripheral surface 122C.

[0065] Next, the effects of the semiconductor device A10 will be described.

[0066] The semiconductor device A10 includes a conductive layer 12 bonded to an insulating layer 11, a semiconductor element 31 bonded to a main surface 121 of the conductive layer 12, and a bonding layer 39 bonding the main surface 121 to the semiconductor element 31. The conductive layer 12 has a recess 19 recessed from the main surface 121. When viewed in the first direction z, the bonding layer 39 has a first portion 391 located between the semiconductor element 31 and the recess 19. The first portion 391 covers the main surface 121. With this configuration, when the semiconductor element 31 is bonded to the main surface 121 via the bonding layer 39, surface tension acts on the molten bonding layer 39 at a boundary 121A between the main surface 121 and the recess 19, as shown in FIG. 11 . This suppresses the spreading of the bonding layer 39, thereby suppressing movement of the semiconductor element 31 due to the spreading of the bonding layer 39. Therefore, according to this configuration, in the semiconductor device A10, it is possible to further improve the accuracy of the bonding position of the semiconductor element 31 to the conductive layer 12.

[0067] The above-described effect can also be obtained by providing a slit in the conductive layer 12 that penetrates the conductive layer 12 in the first direction z near the bonding position of the semiconductor element 31. However, the semiconductor device A10 employs a recess 19 instead of a slit. This reduces the volumetric reduction of the conductive layer 12, thereby suppressing a decrease in the thermal conductivity of the conductive layer 12 in the direction perpendicular to the first direction z.

[0068] The conductive layer 12 has an inner circumferential surface 122 that is connected to the main surface 121 and defines the recess 19. The inner circumferential surface 122 has a first circumferential surface 122A and a second circumferential surface 122B that face each other in a direction perpendicular to the first direction z. The first circumferential surface 122A and the second circumferential surface 122B approach each other as they move from the main surface 121 toward the insulating layer 11. This configuration allows the size of the recess 19 to be set as small as possible, thereby further minimizing the reduction in volume of the conductive layer 12.

[0069] As viewed in the first direction z, the recess 19 surrounds the semiconductor element 31. With this configuration, when the semiconductor element 31 is bonded to the main surface 121 of the conductive layer 12 via the bonding layer 39, movement of the semiconductor element 31 in a direction perpendicular to the first direction z is suppressed, and rotation of the semiconductor element 31 about the first direction z is also suppressed.

[0070] In the above case, the conductive layer 12 has a pedestal portion 123 surrounded by the recess 19. The cross-sectional area of ​​the pedestal portion 123 in the first direction z increases from the main surface 121 of the conductive layer 12 toward the insulating layer 11. This configuration makes it easier for heat conducted from the semiconductor element 31 to the pedestal portion 123 to be conducted over a wider area. This improves the heat dissipation properties of the conductive layer 12.

[0071] As viewed in the first direction z, the periphery 314 of the semiconductor element 31 has a first periphery 314A and a second periphery 314B that extends in a direction different from the first periphery 314A and is connected to the first periphery 314A. The recess 19 has a first groove 191 that extends along the first periphery 314A and a second groove 192 that extends along the second periphery 314B and is connected to the first groove 191. As viewed in the first direction z, the first groove 191 intersects with an extension line EL2 of the second periphery 314B, and the second groove 192 intersects with an extension line EL1 of the first periphery 314A (see FIG. 15 ). With this configuration, when the semiconductor element 31 is bonded to the main surface 121 of the conductive layer 12 via the bonding layer 39, bidirectional rotation of the semiconductor element 31 around the first direction z can be suppressed.

[0072] The recess 19 includes a first recess 19A and a second recess 19B separated from the first recess 19A. The first recess 19A and the second recess 19B are located on opposite sides of the semiconductor element 31. Even with this configuration, when the semiconductor element 31 is bonded to the main surface 121 of the conductive layer 12 via the bonding layer 39, the spreading of the bonding layer 39 can be suppressed.

[0073] The semiconductor device A10 further includes a sealing resin 50 that covers the semiconductor element 31. A portion of the sealing resin 50 fills the recess 19. This configuration allows the sealing resin 50 to have an anchoring effect on the conductive layer 12. This makes it possible to suppress peeling at the interface between the main surface 121 of the conductive layer 12 and the sealing resin 50.

[0074] The sealing resin 50 has a bottom surface 52 facing the opposite side to the main surface 121 of the conductive layer 12 in the first direction z. The heat dissipation layer 13 is exposed from the bottom surface 52. This configuration can improve the heat dissipation performance of the semiconductor device A10.

[0075] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 18 to 34. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, the sealing resin 50 is omitted from Figures 20, 25, and 26. In Figure 20, lines XXVII-XXVII and XXVIII-XXVIII are indicated by dashed lines, respectively.

[0076] The semiconductor device A20 includes an insulating layer 11, multiple conductive layers 12, a heat dissipation layer 13, multiple input terminals 21, output terminals 22, multiple semiconductor elements 31, and a sealing resin 50. The semiconductor device A20 further includes multiple gate wirings 14, multiple detection wirings 15, multiple gate terminals 24, multiple detection terminals 25, and a case 70. The semiconductor device A20 is a power module. The semiconductor device A20 is used in inverters for electrical appliances, hybrid vehicles, and the like. As shown in FIGS. 18 and 19 , the semiconductor device A20 has a rectangular (or substantially rectangular) shape when viewed in the first direction z. The second direction x corresponds to the longitudinal direction of the semiconductor device A20.

[0077] As shown in Figures 27 and 28, the insulating layer 11 is bonded to the heat dissipation member 75 via the heat dissipation layer 13. As shown in Figure 24, a portion of the heat dissipation member 75 is exposed to the outside of the semiconductor device A20. The heat dissipation member 75 is, for example, a flat metal plate. The metal plate contains copper. The surface of the heat dissipation member 75 may be nickel-plated. The dimension of the heat dissipation member 75 in the first direction z is larger than the dimension of the heat dissipation layer 13 in the first direction z.

[0078] 20 , the multiple conductive layers 12 include a first conductive layer 12A, a second conductive layer 12B, and a third conductive layer 12C. Each of the first conductive layer 12A, the second conductive layer 12B, and the third conductive layer 12C extends in the second direction x. The second conductive layer 12B is located on one side of the first conductive layer 12A in the third direction y. The third conductive layer 12C is located on the opposite side of the first conductive layer 12A in the third direction y with respect to the second conductive layer 12B.

[0079] 25 and 26 , each of the first conductive layer 12A and the second conductive layer 12B has a plurality of recesses 19. As viewed in the first direction z, each of the plurality of recesses 19 provided in the first conductive layer 12A surrounds a plurality of first elements 31A. As viewed in the first direction z, each of the plurality of recesses 19 provided in the second conductive layer 12B surrounds a plurality of second elements 31B.

[0080] As shown in FIG. 20 , the multiple gate wirings 14 are joined to the insulating layer 11 so as to be on the same side as the multiple conductive layers 12 in the first direction z. The multiple gate wirings 14 include a first gate wiring 141 and a second gate wiring 142. The first gate wiring 141 is located on the opposite side of the second conductive layer 12B in the third direction y, with the first conductive layer 12A sandwiched therebetween. The first gate wiring 141 extends in the second direction x. The first gate wiring 141 includes two portions spaced apart from each other in the third direction y. One ends of the two portions of the first gate wiring 141 located closest to the multiple input terminals 21 are connected to each other. The second gate wiring 142 is located on the opposite side of the second conductive layer 12B in the third direction y, with the third conductive layer 12C sandwiched therebetween. The second gate wiring 142 extends in the second direction x. The second gate wiring 142 includes two portions spaced apart from each other in the third direction y. The two portions of the second gate wiring 142 located closest to the output terminal 22 are connected to each other at one end.

[0081] As shown in FIG. 20 , the multiple detection wirings 15 are joined to the insulating layer 11 so as to be on the same side as the multiple conductive layers 12 in the first direction z. The multiple detection wirings 15 include a first detection wiring 161 and a second detection wiring 162. The first detection wiring 161 is located adjacent to the first gate wiring 141 in the third direction y. The first detection wiring 161 extends in the second direction x. The first detection wiring 161 includes two portions that are spaced apart from each other in the third direction y. One ends of the two portions of the first detection wiring 161 that are located closest to the output terminal 22 are connected to each other. The second detection wiring 162 is located adjacent to the second gate wiring 142 in the third direction y. The second detection wiring 162 extends in the second direction x. The second detection wiring 162 includes two portions that are spaced apart from each other in the third direction y. One ends of the two portions of the second detection wiring 162 located closest to the plurality of input terminals 21 are connected to each other.

[0082] 25 , the semiconductor device A20 further includes a pair of pads 16. The pair of pads 16 are bonded to the insulating layer 11 so as to be on the same side as the plurality of conductive layers 12 in the first direction z. The pair of pads 16 are adjacent to each other in the second direction x. The pair of pads 16 are located at corners of the insulating layer 11. The pair of pads 16 are close to the first conductive layer 12A.

[0083] 19 and 20 , the input terminals 21 are part of external connection terminals provided on the semiconductor device A20. The input terminals 21 are connected to a DC power supply arranged outside the semiconductor device A20. The input terminals 21 are supported by a case 70. The input terminals 21 are made of a metal plate. The metal plate includes, for example, copper.

[0084] As shown in FIG. 25 , the multiple input terminals 21 include a first input terminal 21A and a second input terminal 21B. The first input terminal 21A is a positive electrode (P terminal). The first input terminal 21A is joined to a joint 124 of the first conductive layer 12A. This provides electrical continuity between the first input terminal 21A and the first conductive layer 12A. The second input terminal 21B is a negative electrode (N terminal). The second input terminal 21B is joined to a joint 124 of the third conductive layer 12C. This provides electrical continuity between the second input terminal 21B and the third conductive layer 12C. The first input terminal 21A and the second input terminal 21B are adjacent to each other in the third direction y.

[0085] As shown in FIGS. 25 and 29, each of the first input terminal 21A and the second input terminal 21B has an external connection portion 211, an internal connection portion 212, and an intermediate portion 213.

[0086] The external connection portion 211 is exposed from the semiconductor device A20 and has a flat plate shape perpendicular to the first direction z. A DC power cable or the like is joined to the external connection portion 211. The external connection portion 211 is supported by the case 70. The external connection portion 211 is provided with a connection hole 211A that penetrates in the first direction z. A fastening member such as a bolt is inserted into the connection hole 211A. The surface of the external connection portion 211 may be nickel (Ni) plated.

[0087] The internal connection portion 212 of the first input terminal 21A is conductively bonded to the joint portion 124 of the first conductive layer 12A. The internal connection portion 212 of the second input terminal 21B is conductively bonded to the joint portion 124 of the third conductive layer 12C. The internal connection portion 212 has a plurality of teeth arranged along the third direction y. The plurality of teeth are bent in the first direction z. Therefore, the plurality of teeth have a hook shape when viewed in the third direction y. The plurality of teeth are conductively bonded to the joint portion 124 of either the first conductive layer 12A or the third conductive layer 12C by ultrasonic vibration.

[0088] The intermediate portion 213 interconnects the external connection portion 211 and the internal connection portion 212. The cross section of the intermediate portion 213 in the second direction x is L-shaped. The intermediate portion 213 has a base portion 213A and an upright portion 213B. The base portion 213A extends along the second direction x and the third direction y. One end of the base portion 213A in the second direction x is connected to the internal connection portion 212. The upright portion 213B stands up from the base portion 213A in the first direction z. One end of the upright portion 213B in the first direction z is connected to the external connection portion 211.

[0089] 19 and 20 , the output terminal 22 is part of the external connection terminals provided on the semiconductor device A20. The output terminal 22 is connected to a power supply target (such as a motor) arranged outside the semiconductor device A20. The output terminal 22 is supported by the case 70 and is located on the opposite side of the insulating layer 11 from the multiple input terminals 21 in the second direction x. The output terminal 22 is made of a metal plate. The metal plate may include, for example, copper.

[0090] In the semiconductor device A20, the output terminal 22 is separated into two, a first output terminal 22A and a second output terminal 22B. Alternatively, the output terminal 22 may be a single member in which the first output terminal 22A and the second output terminal 22B are integrated. The first output terminal 22A and the second output terminal 22B are conductively joined to the joint 124 of the second conductive layer 12B. This allows the output terminal 22 to be electrically connected to the second conductive layer 12B. The first output terminal 22A and the second output terminal 22B are adjacent to each other in the third direction y.

[0091] As shown in FIGS. 26 and 30, each of the first output terminal 22A and the second output terminal 22B has an external connection portion 221, an internal connection portion 222, and an intermediate portion 223.

[0092] The external connection portion 221 is exposed from the semiconductor device A20 and has a flat plate shape perpendicular to the first direction z. A cable or the like that is electrically connected to a power supply target is joined to the external connection portion 221. The external connection portion 221 is supported by the case 70. The external connection portion 221 is provided with a connection hole 221A that penetrates in the first direction z. A fastening member such as a bolt is inserted into the connection hole 221A. The surface of the external connection portion 221 may be nickel plated.

[0093] The internal connection portion 222 is conductively bonded to the bonding portion 124 of the second conductive layer 12B. The internal connection portion 222 has a plurality of teeth arranged along the third direction y. The plurality of teeth are bent in the first direction z. Therefore, the plurality of teeth have a hook shape when viewed in the third direction y. The plurality of teeth are conductively bonded to the bonding portion 124 of the second conductive layer 12B by ultrasonic vibration.

[0094] The intermediate portion 223 interconnects the external connection portion 221 and the internal connection portion 222. The cross section of the intermediate portion 223 in the second direction x is L-shaped. The intermediate portion 223 has a base portion 223A and an upright portion 223B. The base portion 223A extends along the second direction x and the third direction y. One end of the base portion 223A in the second direction x is connected to the internal connection portion 222. The upright portion 223B stands up from the base portion 223A in the first direction z. One end of the upright portion 223B in the first direction z is connected to the external connection portion 221.

[0095] The semiconductor device A20 converts DC power input to a plurality of input terminals 21 into AC power using a plurality of semiconductor elements 31. The converted AC power is output from an output terminal 22. The AC power is supplied to a power supply target such as a motor.

[0096] As shown in FIGS. 19 to 21 , the multiple gate terminals 24 are part of external connection terminals provided on the semiconductor device A20. The multiple gate terminals 24 are electrically connected to the multiple gate wirings 14. The multiple gate terminals 24 are connected to an external drive circuit (such as a gate driver) for the semiconductor device A20. The multiple gate terminals 24 are supported by a case 70. The multiple gate terminals 24 are made of metal rods. The metal rods may contain, for example, copper. Note that the surfaces of the multiple gate terminals 24 may be plated with tin (Sn) or nickel and tin. As shown in FIG. 28 , the multiple gate terminals 24 have an L-shaped cross section in the second direction x. A portion of each of the multiple gate terminals 24 protrudes from the case 70 in the first direction z toward the main surfaces 121 of the multiple conductive layers 12.

[0097] The multiple gate terminals 24 include a first gate terminal 24A and a second gate terminal 24B. As shown in Fig. 26 , the first gate terminal 24A is adjacent to the first gate wiring 141 in the third direction y. As shown in Fig. 25 , the second gate terminal 24B is located on the opposite side of the insulating layer 11 from the first gate terminal 24A in the third direction y. The second gate terminal 24B is adjacent to the second gate wiring 142.

[0098] As shown in FIGS. 19 to 21 , the multiple detection terminals 25 are part of external connection terminals provided on the semiconductor device A20. The multiple detection terminals 25 are electrically connected to the multiple detection wirings 15. The multiple detection terminals 25 are connected to a control circuit of the semiconductor device A20 arranged externally. The multiple detection terminals 25 are supported by a case 70. The multiple detection terminals 25 are made of metal rods. The metal rods may contain, for example, copper. Note that the surfaces of the multiple detection terminals 25 may be tin-plated or nickel-plated and tin-plated. As shown in FIG. 28 , the multiple detection terminals 25 have an L-shaped cross section in the second direction x. A portion of each of the multiple detection terminals 25 protrudes from the case 70 in the first direction z toward the main surfaces 121 of the multiple conductive layers 12.

[0099] The plurality of detection terminals 25 include a first detection terminal 25A and a second detection terminal 25B. As shown in Fig. 26 , the first detection terminal 25A is located adjacent to the first gate terminal 24A in the second direction x. As shown in Fig. 25 , the second detection terminal 25B is located adjacent to the second gate terminal 24B in the second direction x.

[0100] As shown in FIGS. 19 to 21 and 26 , the semiconductor device A20 further includes an input current detection terminal 26. The input current detection terminal 26 is part of the external connection terminals provided on the semiconductor device A20. The input current detection terminal 26 is connected to an externally disposed control circuit for the semiconductor device A20. The input current detection terminal 26 is supported by the case 70. The input current detection terminal 26 is made of a metal rod. The metal rod may contain, for example, copper. Note that the surface of the input current detection terminal 26 may be tin-plated or nickel-plated and tin-plated. The shape of the input current detection terminal 26 is the same as that of the multiple gate terminals 24 shown in FIG. 28 . Like the multiple gate terminals 24 shown in FIG. 28 , a portion of the input current detection terminal 26 protrudes from the case 70 in the first direction z toward the main surfaces 121 of the multiple conductive layers 12. In the third direction y, the position of the input current detection terminal 26 is the same as that of the first gate terminal 24A. The input current detection terminal 26 is spaced apart from the first gate terminal 24A in the second direction x toward the side where the output terminal 22 is located.

[0101] 26 , the semiconductor device A20 further includes an input current detection wire 64. The input current detection wire 64 is conductively bonded to the input current detection terminal 26 and the first conductive layer 12A. This allows the input current detection terminal 26 to be electrically connected to the first conductive layer 12A. The input current detection wire 64 is made of, for example, aluminum.

[0102] As shown in FIGS. 19 to 21 and 25 , the semiconductor device A20 further includes a pair of thermistor terminals 27. The pair of thermistor terminals 27 are part of external connection terminals provided on the semiconductor device A20. The pair of thermistor terminals 27 are connected to an externally disposed control circuit for the semiconductor device A20. The pair of thermistor terminals 27 are supported by a case 70. The pair of thermistor terminals 27 are formed from metal rods. The metal rods may contain, for example, copper. Note that the surfaces of the pair of thermistor terminals 27 may be tin-plated or nickel-plated and tin-plated. The shape of the pair of thermistor terminals 27 is the same as that of the multiple gate terminals 24 shown in FIG. 28 . Like the multiple gate terminals 24 shown in FIG. 28 , portions of the pair of thermistor terminals 27 protrude from the case 70 in the first direction z toward the main surfaces 121 of the multiple conductive layers 12. In the third direction y, the position of the pair of thermistor terminals 27 is the same as that of the first gate terminal 24A. The pair of thermistor terminals 27 are spaced apart in the second direction x from the first gate terminal 24A toward the side where the plurality of input terminals 21 are located. The pair of thermistor terminals 27 are adjacent to each other in the second direction x.

[0103] 25 , the semiconductor device A20 further includes a pair of thermistor wires 65. The pair of thermistor wires 65 are individually conductively bonded to the pair of thermistor terminals 27 and the pair of pads 16. As a result, the pair of input current detection terminals 26 are electrically connected to the pair of pads 16. The pair of thermistor wires 65 is made of, for example, aluminum.

[0104] As shown in FIGS. 20 and 25 , the semiconductor device A20 further includes a thermistor 35. The thermistor 35 is conductively connected to a pair of pads 16. In the semiconductor device A20, the thermistor 35 is an NTC (Negative Temperature Coefficient) thermistor. NTC thermistors have the characteristic of gradually decreasing resistance as temperature increases. The thermistor 35 is used as a temperature detection sensor for the semiconductor device A20. The thermistor 35 is electrically connected to a pair of thermistor terminals 27 via the pair of pads 16 and a pair of thermistor wires 65.

[0105] As shown in FIGS. 25 and 26 , the semiconductor device A20 further includes a plurality of conductive members 61, a plurality of first gate wires 621, and a plurality of first detection wires 631. These are individually conductively bonded to the plurality of semiconductor elements 31. The plurality of conductive members 61 are metal clips. The composition of the plurality of conductive members 61 includes copper. Alternatively, each of the plurality of conductive members 61 may be composed of a plurality of wires. The plurality of first gate wires 621 and the plurality of first detection wires 631 are made of, for example, aluminum.

[0106] 31 and 33 , the plurality of conductive members 61 have a first bonding portion 611 and a second bonding portion 612. The first bonding portion 611 is conductively bonded to a second electrode 312 of one of the plurality of semiconductor elements 31 via a bonding layer 39. The bonding layer 39 is, for example, solder. The second bonding portion 612 is conductively bonded to one of the second conductive layer 12B and the third conductive layer 12C of the plurality of conductive layers 12 via the bonding layer 39.

[0107] As shown in FIGS. 25 and 26 , the plurality of conductive members 61 include a plurality of first conductive members 61A and a plurality of second conductive members 61B. As shown in FIG. 31 , the plurality of first conductive members 61A are individually conductively bonded to the second electrodes 312 of the plurality of first elements 31A and the second conductive layer 12B. As a result, the second electrodes 312 of the plurality of first elements 31A are electrically connected to the second conductive layer 12B. Therefore, the second electrodes 312 of the plurality of first elements 31A are electrically connected to the output terminal 22. As shown in FIG. 33 , the plurality of second conductive members 61B are individually conductively bonded to the second electrodes 312 of the plurality of second elements 31B and the third conductive layer 12C. As a result, the second electrodes 312 of the plurality of semiconductor elements 31B are electrically connected to the third conductive layer 12C. Therefore, the second electrodes 312 of the plurality of second elements 31B are electrically connected to the second input terminal 21B.

[0108] 31 , the multiple first gate wires 621 and multiple first detection wires 631 that are individually conductively bonded to the multiple first elements 31A will be described. The multiple first gate wires 621 are individually conductively bonded to the gate electrodes 313 of the multiple first elements 31A and the first gate wiring 141. The multiple first detection wires 631 are individually conductively bonded to the second electrodes 312 of the multiple first elements 31A and the first detection wiring 161.

[0109] 33 , the multiple first gate wires 621 and multiple first detection wires 631 that are individually conductively bonded to the multiple second elements 31B will be described. The multiple first gate wires 621 are individually conductively bonded to the gate electrodes 313 of the multiple second elements 31B and the second gate wiring 142. The multiple first detection wires 631 are individually conductively bonded to the second electrodes 312 of the multiple second elements 31B and the second detection wiring 162.

[0110] 25 and 26 , the semiconductor device A20 further includes a pair of second gate wires 622. The pair of second gate wires 622 are individually conductively bonded to the plurality of gate terminals 24 and the plurality of gate wirings 14. The plurality of second gate wires 622 are made of, for example, aluminum.

[0111] 26 , one second gate wire 622 is conductively joined to the first gate terminal 24A and the first gate wiring 141. As a result, the first gate terminal 24A is electrically connected to the gate electrodes 313 of the plurality of first elements 31A. As shown in FIG. 25 , the other second gate wire 622 is conductively joined to the second gate terminal 24B and the second gate wiring 142. As a result, the second gate terminal 24B is electrically connected to the gate electrodes 313 of the plurality of second elements 31B.

[0112] 25 and 26 , the semiconductor device A20 further includes a pair of second detection wires 632. The pair of second detection wires 632 are joined to the plurality of detection terminals 25 and the plurality of detection wirings 15. The plurality of second detection wires 632 are made of, for example, aluminum.

[0113] 26 , one second detection wire 632 is conductively joined to the first detection terminal 25A and the first detection wiring 161. As a result, the first detection terminal 25A is electrically connected to the second electrodes 312 of the plurality of first elements 31A. As shown in FIG. 25 , the other second detection wire 632 is conductively joined to the second detection terminal 25B and the second detection wiring 162. As a result, the second detection terminal 25B is electrically connected to the second electrodes 312 of the plurality of second elements 31B.

[0114] As shown in FIGS. 27 and 28 , the case 70 supports a heat dissipation member 75. The case 70 houses an insulating layer 11, a plurality of conductive layers 12, a heat dissipation layer 13, a plurality of semiconductor elements 31, and a sealing resin 50. The case 70 has electrical insulation properties. The case 70 is made of a material containing a heat-resistant resin such as PPS (polyphenylene sulfide). The case 70 has a pair of first side walls 711, a pair of second side walls 712, a plurality of mounting portions 72, an input terminal block 73, and an output terminal block 74.

[0115] 19 and 20 , the pair of first side walls 711 are spaced apart from each other in the second direction x. The pair of first side walls 711 are arranged along both the third direction y and the first direction z, and one end of each of the pair of first side walls 711 in the first direction z is in contact with the heat dissipation member 75.

[0116] As shown in FIGS. 19 and 20 , the pair of second side walls 712 are spaced apart from each other in the third direction y. The pair of second side walls 712 are arranged along both the second direction x and the first direction z, and one end in the first direction z is in contact with the heat dissipation member 75. Both ends of the pair of second side walls 712 in the second direction x are connected to the pair of first side walls 711. The first gate terminal 24A, the first detection terminal 25A, the input current detection terminal 26, and a pair of thermistor terminals 27 are arranged inside one of the second side walls 712. The second gate terminal 24B and the second detection terminal 25B are arranged inside the other second side wall 712. As shown in FIGS. 25 and 26 , the ends of these terminals that are close to the insulating layer 11 in the first direction z are supported by the pair of second side walls 712.

[0117] 19 , 25 , and 26 , the mounting portions 72 are portions provided at the four corners of the case 70 when viewed in the first direction z. A heat dissipation member 75 is in contact with the undersides of the mounting portions 72. Each of the mounting portions 72 has a mounting hole 721 that penetrates in the first direction z. The semiconductor device A20 can be attached to the heat sink by inserting fastening members such as bolts into the mounting holes 721.

[0118] As shown in FIGS. 19 , 22 , and 25 , the input terminal block 73 protrudes outward in the second direction x from one of the first side walls 711. A plurality of input terminals 21 are supported on the input terminal block 73. The input terminal block 73 includes a first terminal block 731 and a second terminal block 732. The first terminal block 731 and the second terminal block 732 are spaced apart from each other in the third direction y. The first terminal block 731 supports the first input terminal 21A. The external connection portion 211 of the first input terminal 21A is exposed from the first terminal block 731. The second terminal block 732 supports the second input terminal 21B. The external connection portion 211 of the second input terminal 21B is exposed from the second terminal block 732. A plurality of grooves 733 extending in the second direction x are formed between the first terminal block 731 and the second terminal block 732. As shown in FIGS. 27 and 29 , a pair of nuts 734 and a pair of intermediate members 735 are disposed inside the first terminal block 731 and the second terminal block 732. The pair of intermediate members 735 are located on the side of the pair of nuts 734 where the insulating layer 11 is located in the first direction z, and are in contact with the pair of nuts 734. One intermediate member 735 supports the external connection portion 211 and the intermediate portion 213 of the first input terminal 21A. The other intermediate member 735 supports the external connection portion 211 and the intermediate portion 213 of the second input terminal 21B. A portion of each of the pair of intermediate members 735 is exposed from the input terminal block 73. The pair of nuts 734 correspond to a pair of connection holes 211A provided in the first input terminal 21A and the second input terminal 21B. Fastening members, such as bolts, inserted into the pair of connection holes 211A are fitted into the pair of nuts 734.

[0119] As shown in FIGS. 19 , 23 , and 26 , the output terminal block 74 protrudes outward in the second direction x from the other first side wall 711. The output terminal block 74 supports the output terminal 22. The output terminal block 74 includes a first terminal block 741 and a second terminal block 742. The first terminal block 741 and the second terminal block 742 are spaced apart from each other in the third direction y. The first terminal block 741 supports the first output terminal 22A of the output terminal 22. The external connection portion 221 of the first output terminal 22A is exposed from the first terminal block 741. The second terminal block 742 supports the second output terminal 22B of the output terminal 22. The external connection portion 221 of the second output terminal 22B is exposed from the second terminal block 742. A plurality of grooves 743 extending in the second direction x are formed between the first terminal block 741 and the second terminal block 742. As shown in FIGS. 27 and 30 , a pair of nuts 744 and a pair of intermediate members 745 are disposed inside the first terminal block 741 and the second terminal block 742. The pair of intermediate members 745 are located on the side of the pair of nuts 744 where the insulating layer 11 is located in the first direction z and are in contact with the pair of nuts 744. One intermediate member 745 supports the external connection portion 221 and the intermediate portion 223 of the first output terminal 22A. The other intermediate member 745 supports the external connection portion 221 and the intermediate portion 223 of the second output terminal 22B. A portion of each of the pair of intermediate members 745 is exposed from the output terminal block 74. The pair of nuts 744 correspond to a pair of connection holes 221A provided in the first output terminal 22A and the second output terminal 22B. Fastening members such as bolts inserted into the pair of connection holes 221A are fitted into the pair of nuts 744.

[0120] As shown in Figures 27 and 28, the sealing resin 50 covers the multiple semiconductor elements 31 housed in the case 70. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is, for example, silicone gel. Alternatively, the sealing resin 50 may be an epoxy-based resin. A portion of the sealing resin 50 fills the recesses 19 provided in the first conductive layer 12A and the second conductive layer 12B of the multiple conductive layers 12.

[0121] Next, the effects of the semiconductor device A20 will be described.

[0122] The semiconductor device A20 includes a conductive layer 12 bonded to an insulating layer 11, a semiconductor element 31 bonded to a main surface 121 of the conductive layer 12, and a bonding layer 39 bonding the main surface 121 to the semiconductor element 31. The conductive layer 12 has a recess 19 recessed from the main surface 121. When viewed in the first direction z, the bonding layer 39 has a first portion 391 located between the semiconductor element 31 and the recess 19. The first portion 391 covers the main surface 121. Therefore, with this configuration, the semiconductor device A20 can also further improve the bonding position accuracy of the semiconductor element 31 relative to the conductive layer 12. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0123] The semiconductor device A20 further includes a first input terminal 21A electrically connected to a plurality of first elements 31A and a second input terminal 21B electrically connected to a plurality of second elements 31B. The first input terminal 21A and the second input terminal 21B are adjacent to each other. As a result, when a voltage is applied to the first input terminal 21A and the second input terminal 21B, mutual inductance occurs between the first input terminal 21A and the second input terminal 21B. This reduces the parasitic inductance of the semiconductor device A20.

[0124] The semiconductor device A20 further includes a heat dissipation member 75 located on the opposite side of the insulating layer 11 with respect to the heat dissipation layer 13. The heat dissipation layer 13 is bonded to the heat dissipation member 75. The dimension of the heat dissipation member 75 in the first direction z is larger than the dimension of the heat dissipation layer 13 in the first direction z. This configuration can further improve the heat dissipation performance of the semiconductor device A20.

[0125] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0126] The present disclosure includes embodiments described in the following supplementary notes. Supplementary note 1. A semiconductor device comprising: an insulating layer; a conductive layer having a main surface facing opposite to a side facing the insulating layer in a first direction and bonded to the insulating layer; a heat dissipation layer located on the opposite side of the insulating layer from the conductive layer and bonded to the insulating layer; a semiconductor element bonded to the main surface; and a bonding layer bonding the main surface to the semiconductor element, wherein the conductive layer has a recess recessed from the main surface, and the bonding layer has a first portion located between the semiconductor element and the recess as viewed in the first direction, and the first portion covers the main surface. Supplementary note 2. The semiconductor device described in Supplementary note 1, wherein the conductive layer has an inner circumferential surface that is connected to the main surface and defines the recess, and the first portion is in contact with the boundary between the inner circumferential surface and the main surface. Supplementary note 3. The semiconductor device according to Supplementary Note 2, wherein the inner circumferential surface has a first circumferential surface and a second circumferential surface that face each other in a direction perpendicular to the first direction, and the first circumferential surface and the second circumferential surface approach each other as they move from the main surface to the insulating layer. Supplementary Note 4. The semiconductor device according to Supplementary Note 3, wherein the inner circumferential surface has a third circumferential surface that connects to the first circumferential surface and the second circumferential surface, and the third circumferential surface faces the same side as the main surface in the first direction. Supplementary Note 5. The semiconductor device according to Supplementary Note 3 or 4, wherein each of the first circumferential surface and the second circumferential surface is curved inwardly of the conductive layer. Supplementary Note 6. The semiconductor device according to any of Supplements 2 to 5, wherein the recess extends in a direction intersecting the periphery of the semiconductor element when viewed in the first direction. Supplementary Note 7. The semiconductor device according to any of Supplements 2 to 5, wherein the recess extends along the periphery of the semiconductor element when viewed in the first direction. Supplementary Note 8. The semiconductor device according to any one of Supplementary Notes 2 to 5, wherein the recess surrounds the semiconductor element as viewed in the first direction.Supplementary Note 9: The semiconductor device according to Supplementary Note 8, wherein the conductive layer has a pedestal surrounded by the recess, and a cross-sectional area of ​​the pedestal in the first direction increases from the main surface toward the insulating layer.Supplementary Note 10. The semiconductor device according to Supplementary Note 6 or 7, wherein the recess includes a first recess and a second recess separated from the first recess, and the first recess and the second recess are located on opposite sides of the semiconductor element. Supplementary Note 11. The semiconductor device according to Supplementary Note 10, wherein each of the first recess and the second recess is located closest to one of four corners of the semiconductor element. Supplementary Note 12. The semiconductor device according to Supplementary Note 7 or 8, wherein, when viewed in the first direction, the periphery of the semiconductor element has a first edge and a second edge extending in a direction different from the first edge and connected to the first edge, the recess has a first groove extending along the first edge and a second groove extending along the second edge and connected to the first groove, and when viewed in the first direction, the first groove intersects with an extension of the second edge and the second groove intersects with an extension of the first edge. Supplementary Note 13. The semiconductor device according to any one of Supplementary Notes 2 to 12, wherein the semiconductor element has a first electrode facing the main surface and a second electrode located on the opposite side of the first electrode in the first direction, and the first electrode is conductively bonded to the main surface via the bonding layer. Supplementary Note 14. The semiconductor device according to Supplementary Note 13, further comprising a terminal conductive to the second electrode, and the terminal is spaced from the conductive layer as viewed in the first direction. Supplementary Note 15. The semiconductor device according to any one of Supplementary Notes 2 to 14, further comprising a sealing resin covering the semiconductor element, a portion of the sealing resin filling the recess. Supplementary Note 16. The semiconductor device according to Supplementary Note 15, wherein the sealing resin has a bottom surface facing opposite to the main surface in the first direction, and the heat dissipation layer is exposed from the bottom surface. Supplementary Note 17. The semiconductor device according to Supplementary Note 15 or 16, further comprising an IC conductive to the semiconductor element, and the IC is covered by the sealing resin.

[0127] A10, A20: semiconductor device 11: insulating layer 12: conductive layer 12A: first conductive layer 12B: second conductive layer 12C: third conductive layer 121: main surface 121A: boundary 122: inner circumferential surface 122A: first circumferential surface 122B: second circumferential surface 122C: third circumferential surface 123: base portion 124: bonding portion 13: heat dissipation layer 14: gate wiring 141: first gate wiring 142: second gate wiring 15: detection wiring 151: first detection wiring 152: second detection wiring 16: pad 19: recess 19A: first recess 19B: second recess 19C: third recess 19D: fourth recess 191: first groove 192: second groove 21: input terminal 21A: first input terminal 21B: Second input terminal 211: External connection portion 211A: Connection hole 212: Internal connection portion 213: Intermediate portion 213A: Base portion 213B: Standing portion 22: Output terminal 22A: First output terminal 22B: Second output terminal 22C: Third output terminal 221: External connection portion 221A: Connection hole 222: Internal connection portion 223: Intermediate portion 223A: Base portion 223B: Standing portion 23: Control terminal 231: Pad portion 232: Power supply portion 233: First control portion 234: Second control portion 235: Dummy portion 24: Gate terminal 24A: First gate terminal 24B: Second gate terminal 25: Detection terminal 25A: First detection terminal 25B: Second detection terminal 26: Input current detection terminal 27: Thermistor terminal 29: Dummy terminal 31: Semiconductor element 31A: First element 31B: Second element 311: First electrode 312: Second electrode 313: Gate electrode 314: Edge 314A: First edge 314B: Second edge 33: IC 33A: First IC 33B: Second IC 34: Diode 35: Thermistor 39: Bonding layer 391: First part 391A: End face 41: First wire 42: Second wire 43: Third wire 44: Fourth wire 45: Fifth wire 46: Sixth wire 50: Sealing resin 51: Top surface 52: Bottom surface 53: First side surface 54: Second side surface 55: Depression 61: Conductive member 61A: First conductive member61B: Second conductive member 611: First joint 612: Second joint 621: First gate wire 622: Second gate wire 631: First detection wire 632: Second detection wire 64: Input current detection wire 65: Thermistor wire 70: Case 711: First side wall 712: Second side wall 72: Mounting base 721: Mounting hole 73: Input terminal block 731: First terminal block 732: Second terminal block 733: Groove 734: Nut 735: Intermediate member 74: Output terminal block 741: First terminal block 742: Second terminal block 744: Groove 745: Nut 745: Intermediate member 75: Heat dissipation member z: First direction x: Second direction y: Third direction

Claims

1. An insulating layer; a conductive layer having a main surface facing a side opposite to a side facing the insulating layer in a first direction and joined to the insulating layer; a heat dissipation layer located on the opposite side of the insulating layer from the conductive layer and joined to the insulating layer; a semiconductor element bonded to the main surface; a bonding layer that bonds the main surface and the semiconductor element, the conductive layer is provided with a recess recessed from the main surface, When viewed in the first direction, the bonding layer has a first portion located between the semiconductor element and the recessed portion, The first portion covers the main surface.

2. the conductive layer has an inner circumferential surface that is connected to the main surface and defines the recess; The semiconductor device according to claim 1 , wherein the first portion is in contact with a boundary between the inner circumferential surface and the main surface.

3. The inner circumferential surface has a first circumferential surface and a second circumferential surface opposed to each other in a direction perpendicular to the first direction, The semiconductor device according to claim 2 , wherein the first peripheral surface and the second peripheral surface approach each other from the main surface toward the insulating layer.

4. the inner circumferential surface has a third circumferential surface connected to the first circumferential surface and the second circumferential surface, The semiconductor device according to claim 3 , wherein the third circumferential surface faces the same side as the main surface in the first direction.

5. The semiconductor device according to claim 3 , wherein each of the first peripheral surface and the second peripheral surface is curved inwardly of the conductive layer.

6. The semiconductor device according to claim 2 , wherein the recess extends in a direction intersecting a periphery of the semiconductor element when viewed in the first direction.

7. The semiconductor device according to claim 2 , wherein the recess extends along a periphery of the semiconductor element when viewed in the first direction.

8. The semiconductor device according to claim 2 , wherein the recess surrounds the semiconductor element when viewed in the first direction.

9. the conductive layer has a base portion surrounded by the recess, The semiconductor device according to claim 8 , wherein a cross-sectional area of ​​said pedestal portion in said first direction increases from said main surface toward said insulating layer.

10. The recess includes a first recess and a second recess separated from the first recess, The semiconductor device according to claim 6 , wherein the first recess and the second recess are located on opposite sides of the semiconductor element.

11. The semiconductor device according to claim 10 , wherein each of the first recess and the second recess is located closest to any one of four corners of the semiconductor element.

12. When viewed in the first direction, a periphery of the semiconductor element has a first edge and a second edge that extends in a direction different from the first edge and is connected to the first edge; The recess has a first groove extending along the first edge and a second groove extending along the second edge and connected to the first groove, The semiconductor device according to claim 7 , wherein, when viewed in the first direction, the first groove intersects with an extension line of the second edge, and the second groove intersects with an extension line of the first edge.

13. the semiconductor element has a first electrode facing the main surface and a second electrode located on an opposite side to the first electrode in the first direction; The semiconductor device according to claim 2 , wherein the first electrode is conductively bonded to the main surface via the bonding layer.

14. A terminal electrically connected to the second electrode is further provided. The semiconductor device according to claim 13 , wherein the terminal is spaced apart from the conductive layer when viewed in the first direction.

15. Further comprising a sealing resin for covering the semiconductor element, 13. The semiconductor device according to claim 2, wherein a portion of said sealing resin fills said recess.

16. the sealing resin has a bottom surface facing a side opposite to the main surface in the first direction, The semiconductor device according to claim 15 , wherein the heat dissipation layer is exposed from the bottom surface.

17. Further comprising an IC that is electrically connected to the semiconductor element, The semiconductor device according to claim 15 , wherein the IC is covered with the sealing resin.