Semiconductor device

Abstract

This semiconductor device comprises: a first substrate having a first main surface; a first main surface conductive part disposed on the first main surface; a second substrate having a second main surface; a second main surface conductive part disposed on the second main surface; a switching element disposed on the first main surface and conductively connected to the first main surface conductive part; a driving device that is disposed on the second main surface and conductively connected to the second main surface conductive part, and that drives the switching element; and a sealing resin that covers at least part of the first substrate and the second substrate, and the entirety of the switching element and the driving device.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] One of the various semiconductor devices is called an IPM (Intelligent Power Module). This semiconductor device includes multiple semiconductor chips, multiple electrodes, a heat dissipation layer, and a sealing resin (see Patent Document 1). The semiconductor chip is disposed on a die pad of one of the electrodes. The multiple electrodes form a conductive path that connects the semiconductor chip to the outside.

[0003] Japanese Patent Application Laid-Open No. 2020-98938

[0004] Semiconductor chips include LSI chips such as control ICs. LSI chips have input and output of multiple types of control signals. As the number of control signals increases, the number of conductive paths to the LSI chip must also increase. However, if these conductive paths are configured using multiple electrodes as in the past, it may become difficult to further increase the integration density of semiconductor devices.

[0005] An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that enables even higher integration.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a first substrate having a first main surface and a first back surface facing opposite each other in a thickness direction, a first main surface conductive portion having conductivity arranged on the first main surface, a second substrate having a second main surface facing the same side as the first main surface in the thickness direction and a second back surface facing the same side as the first back surface, a second main surface conductive portion having conductivity arranged on the second main surface, a switching element arranged on the first main surface and conductively connected to the first main surface conductive portion, a drive device arranged on the second main surface and conductively connected to the second main surface conductive portion and which drives the switching element, and a sealing resin that covers at least a portion of the first substrate and the second substrate, and the entirety of the switching element and the drive device.

[0007] According to the above configuration, a semiconductor device can be further highly integrated.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing the semiconductor device of FIG. 1. FIG. 3 is a plan view showing the semiconductor device of FIG. 1, seen through the sealing resin. FIG. 4 is a bottom view showing the semiconductor device of FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V of FIG. 3. FIG. 6 is a partially enlarged view of FIG. 5. FIG. 7 is a plan view showing each wiring substrate of the semiconductor device of FIG. 1. FIG. 8 is a flowchart showing one step of an example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 9 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure. FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 12 is a partially enlarged plan view showing a semiconductor device according to a fifth embodiment of the present disclosure, seen through the sealing resin.

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed from a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B."

[0012] 1 to 7 show an example of a semiconductor device according to the present disclosure. The semiconductor device A1 of this embodiment includes a plurality of leads 1, a wiring substrate 2, a wiring substrate 3, a plurality of semiconductor chips 4, a plurality of driving devices 5, a plurality of passive elements 6, a plurality of wires 7, and a sealing resin 8. In this embodiment, the semiconductor device A1 is an IPM (Intelligent Power Module). The semiconductor device A1 is used, for example, in applications such as air conditioners and motor control devices.

[0013] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a plan view showing the semiconductor device A1. FIG. 3 is a plan view showing the semiconductor device A1, seen through the sealing resin 8. In FIG. 3, the outline of the sealing resin 8 is shown by an imaginary line (two-dot chain line). FIG. 4 is a bottom view showing the semiconductor device A1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 3. FIG. 6 is a partially enlarged view of FIG. 5. FIG. 7 is a plan view showing the wiring substrate 2 and the wiring substrate 3.

[0014] For convenience of explanation, the thickness direction of the wiring substrate 2 is referred to as thickness direction z, the direction along one side of the wiring substrate 2 perpendicular to thickness direction z (the up-down direction in FIGS. 2 to 4) is referred to as first direction y, and the direction perpendicular to thickness direction z and first direction y (the left-right direction in FIGS. 2 to 4) is referred to as second direction x. Note that the shape and dimensions of the semiconductor device A1 are not limited.

[0015] The wiring board 2 is mounted with a plurality of semiconductor chips 4 and a plurality of passive elements 6 (shunt resistors 6a, described later), and is arranged at the center of the semiconductor device A1 in the second direction x and toward the first side y1 in the first direction y. As described later, the plurality of semiconductor chips 4 are power transistors, and the wiring board 2 is a power section substrate on which a power circuit is arranged. The wiring board 2 includes a base material 21, a main surface conductive portion 22, and a back surface conductive portion 23.

[0016] The substrate 21 is plate-shaped and has a rectangular shape that is long in the second direction x when viewed in the thickness direction z (i.e., in a plan view). The thickness dimension of the substrate 21 (dimension in the thickness direction z) is, for example, approximately 0.1 mm to 1.0 mm. Note that the dimensions of the substrate 21 are not limited. The substrate 21 is made of an insulating material. The constituent material of the substrate 21 is, for example, ceramics with excellent thermal conductivity, and in this embodiment, contains aluminum nitride (AlN). Note that the constituent material of the substrate 21 is not limited to this.

[0017] The substrate 21 has a main surface 211 and a back surface 212. The main surface 211 and the back surface 212 are surfaces facing opposite each other in the thickness direction z and are both flat surfaces perpendicular to the thickness direction z. The main surface 211 is a surface facing a first side z1 in the thickness direction z. A main surface conductive portion 22 is arranged on the main surface 211, and a plurality of semiconductor chips 4, a plurality of passive elements 6, and a plurality of leads 1 are mounted on the main surface 211. The back surface 212 is a surface facing a second side z2 in the thickness direction z. A back surface conductive portion 23 is arranged on the back surface 212. The main surface 211 and the back surface 212 are both rectangular in shape. The shape of the substrate 21 is not limited.

[0018] The main surface conductive portion 22 is disposed on the main surface 211 of the substrate 21. The main surface conductive portion 22 is made of a conductive material. The constituent material of the main surface conductive portion 22 is not particularly limited, and may be, for example, copper (Cu), silver (Ag), gold (Au), or an alloy containing these. In this embodiment, the case where the main surface conductive portion 22 is made of copper (Cu) will be described. The thickness dimension (dimension in the thickness direction z) T1 (see FIG. 6 ) of the main surface conductive portion 22 is a thickness that can maintain the heat dissipation effect of the heat generated by the semiconductor chip 4, and is, for example, 0.2 mm or more. In this embodiment, the thickness dimension T1 is approximately 0.25 mm. However, the thickness dimension T1 is not limited.

[0019] The shape of the main surface conductive portion 22 is not particularly limited. In this embodiment, the main surface conductive portion 22 includes a plurality of pads 221 and a plurality of wirings 222, as shown in FIG. 7 , for example. Each pad 221 is, for example, rectangular, and is conductively joined to the semiconductor chip 4, the passive element 6, the lead 1 (lead 11 described later), or the wire 7 (wires 71 and 72 described later). The shape of the pad 221 is not limited. The pads 221 are arranged spaced apart from each other. Each of the plurality of wirings 222 is connected to one of the pads 221 and serves as a conductive path for electrically connecting the two. The shape of each wiring 222 is not limited.

[0020] The back surface conductive portion 23 is disposed on the back surface 212 of the substrate 21. The back surface conductive portion 23 is made of a conductive material. The material of the back surface conductive portion 23 is not particularly limited and may be, for example, copper (Cu), silver (Ag), gold (Au), or an alloy containing these. In this embodiment, the material of the back surface conductive portion 23 is copper (Cu), similar to the main surface conductive portion 22. The thickness dimension (dimension in the thickness direction z) of the back surface conductive portion 23 is a thickness that can maintain the heat dissipation effect of the heat generated by the semiconductor chip 4, and is, for example, 0.2 mm or more. In this embodiment, the thickness dimension of the back surface conductive portion 23 is, similar to the thickness dimension T1, approximately 0.25 mm, but is not limited to this. In this embodiment, the back surface conductive portion 23 covers the entire back surface 212. The shape of the back surface conductive portion 23 is not limited. As shown in FIG. 4 , the back surface conductive portion 23 is exposed from the sealing resin 8.

[0021] In this embodiment, the wiring board 2 is formed from a so-called DBC (Direct Bonded Copper) board. The DBC board is a board in which copper foil is bonded to both sides of a ceramic plate. The wiring board 2 is formed by patterning the copper foil on one side of the DBC board by etching. The patterned copper foil on one side becomes the main surface conductive portion 22, and the copper foil on the other side becomes the back surface conductive portion 23. The method for forming the wiring board 2 is not limited. Regardless of the method used, a copper layer of 0.2 mm or more must be formed. As described above, the main surface conductive portion 22 and the back surface conductive portion 23 may be made of a metal other than copper, and layers of that metal are formed on both sides of the ceramic plate.

[0022] The wiring board 3 has a plurality of driving devices 5 and a plurality of passive elements 6 mounted thereon, and is disposed at the center of the semiconductor device A1 in the second direction x, toward the second side y2 in the first direction y. The wiring board 2 and the wiring board 3 are disposed side by side in the first direction y, and the wiring board 3 is located on the second side y2 in the first direction y relative to the wiring board 2. The wiring board 3 is a control unit board on which a control circuit for controlling the power circuit disposed on the wiring board 2 is disposed. The wiring board 3 includes a base material 31, a main surface conductive portion 32, and a back surface conductive portion 33.

[0023] The substrate 31 is plate-shaped, and its shape when viewed in the thickness direction z is a rectangle elongated in the second direction x. The thickness dimension of the substrate 31 (dimension in the thickness direction z) is, for example, approximately 0.1 mm to 1.0 mm, which is similar to that of the substrate 21. Note that the dimensions of the substrate 31 are not limited. The substrate 31 is made of an insulating material. The constituent material of the substrate 31 is, for example, ceramics, and in this embodiment, contains alumina (Al2O3). The substrate 31 does not require as much thermal conductivity as the substrate 21. In this embodiment, the constituent material of the substrate 21 is aluminum nitride ceramic, and has higher thermal conductivity than the substrate 31, which is made of alumina ceramic. Note that the constituent material of the substrate 31 is not limited to this. For example, the constituent material of the substrate 21 and the constituent material of the substrate 31 may be the same.

[0024] The substrate 31 has a main surface 311 and a back surface 312. The main surface 311 and the back surface 312 are surfaces facing opposite each other in the thickness direction z and are both flat surfaces perpendicular to the thickness direction z. The main surface 311 is a surface facing a first side z1 in the thickness direction z. A main surface conductive portion 32 is arranged on the main surface 311, and a plurality of driving devices 5, a plurality of passive elements 6, and a plurality of leads 1 are mounted on the main surface 311. The back surface 312 is a surface facing a second side z2 in the thickness direction z. A back surface conductive portion 33 is arranged on the back surface 312. The main surface 311 and the back surface 312 are both rectangular in shape. The shape of the substrate 31 is not limited.

[0025] The principal surface conductive portion 32 is disposed on the principal surface 311 of the substrate 31. The principal surface conductive portion 32 is made of a conductive material. The constituent material of the principal surface conductive portion 32 is not particularly limited, and may be, for example, copper (Cu), silver (Ag), gold (Au), or an alloy containing these. In this embodiment, the case where the principal surface conductive portion 32 is made of copper (Cu) will be described. The thickness dimension (dimension in the thickness direction z) T2 (see FIG. 6 ) of the principal surface conductive portion 32 is smaller than the thickness dimension T1 and is a thickness that allows for finer processing by etching than the principal surface conductive portion 22. In this embodiment, the thickness dimension T2 is, for example, approximately 0.1 mm. The thickness dimension T2 is not limited.

[0026] The shape of the principal surface conductive portion 32 is not particularly limited. In this embodiment, the principal surface conductive portion 32 includes a plurality of pads 321 and a plurality of wirings 322, as shown in FIG. 7 . Each pad 321 is, for example, rectangular, and is conductively bonded to a driving device 5, a passive element 6, a lead 1 (lead 15 described later), or a wire 7 (wires 73 and 74 described later). The shape of the pads 321 is not limited. The pads 321 are spaced apart from one another. Each of the plurality of wirings 322 is connected to another pad 321 and provides a conductive path between the two. The shape of the wirings 322 is not limited. A conductive plate-like member may be placed on the pad 321 to which the wire 7 is bonded in order to protect the pad 321 and the substrate 31 from impacts caused by wire bonding.

[0027] The back surface conductive portion 33 is disposed on the back surface 312 of the base material 31. The back surface conductive portion 33 is made of a conductive material. The constituent material of the back surface conductive portion 33 is not particularly limited, and may be, for example, copper (Cu), silver (Ag), gold (Au), or an alloy containing these. In this embodiment, the constituent material of the back surface conductive portion 33 is copper (Cu), similar to the constituent material of the main surface conductive portion 32. The thickness dimension (dimension in the thickness direction z) of the back surface conductive portion 33 is approximately the same as the thickness dimension T2, for example, approximately 0.1 mm. Note that the thickness dimension of the back surface conductive portion 33 is not limited to this. In this embodiment, the back surface conductive portion 33 covers the entire back surface 312. Note that the shape of the back surface conductive portion 33 is not limited. As shown in FIG. 4 , the back surface conductive portion 33 is exposed from the sealing resin 8. Note that the wiring substrate 3 does not necessarily have to include the back surface conductive portion 33. In this case, the rear surface 312 of the base material 31 may be exposed from the sealing resin 8, or the entire wiring board 3 may be covered with the sealing resin 8 (the wiring board 3 may not be exposed from the sealing resin 8).

[0028] In this embodiment, the wiring board 3 is formed from a so-called DBC substrate. The DBC substrate is a substrate in which copper foil is bonded to both sides of a ceramic plate. The copper foil of the DBC substrate is thinner than the copper foil of the DBC substrate used to form the wiring board 2. Like the wiring board 2, the wiring board 3 is formed by patterning the copper foil on one side of the DBC substrate by etching. The patterned copper foil on one side becomes the main surface conductive portion 32, and the copper foil on the other side becomes the back surface conductive portion 33. The method for forming the wiring board 3 is not limited. For example, the wiring board 3 may be formed from a so-called DPC (Direct Plated Copper) substrate in which copper plating is formed on both sides of a ceramic plate. Because the copper layer of a DPC substrate is thinner than that of a DBC substrate, more detailed processing is possible for the main surface conductive portion 32. Alternatively, the wiring board 3 may be formed by applying copper paste to both sides of a ceramic plate and firing the applied paste. As described above, the constituent material of the main surface conductive portion 32 and the back surface conductive portion 33 may be a metal other than copper, and layers of the metal are formed on both sides of the ceramic plate.

[0029] The multiple leads 1 are configured to contain a metal. The metal configuring the leads 1 is not particularly limited, and may be, for example, copper (Cu), aluminum, iron (Fe), oxygen-free copper, or an alloy thereof (for example, a Cu—Sn alloy, a Cu—Zr alloy, a Cu—Fe alloy, etc.). The multiple leads 1 may also be plated with nickel (Ni). The multiple leads 1 may be formed, for example, by pressing a mold against a metal plate, or by patterning a metal plate by etching. The method for forming the multiple leads 1 is not particularly limited. The thickness of each lead 1 is not particularly limited, and may be, for example, about 0.4 mm to 0.8 mm. The leads 1 are spaced apart from each other.

[0030] In this embodiment, the plurality of leads 1 each include a plurality of leads 11, 12, 15, and 16. The leads 11 and 12 form a conductive path to the semiconductor chip 4. The leads 15 and 16 form a conductive path to the driving device 5 or the passive element 6.

[0031] The multiple leads 11 are each arranged on the substrate 21, and in this embodiment, are arranged on the main surface 211 toward the first side y1 in the first direction y. Each lead 11 is joined to a pad 221 of the main surface conductive portion 22 via a conductive bonding material 76. The conductive bonding material 76 may be any material that can conductively bond the leads 11 to the pads 221, and may be, for example, silver paste, copper paste, or solder. The conductive bonding material 76 is not limited. Each lead 11 is electrically connected to the semiconductor chip 4 via the main surface conductive portion 22 and the wire 71. In this embodiment, the multiple leads 1 include three leads 11. The number and arrangement of the leads 11 are not limited.

[0032] There is no particular limitation on the configuration of the lead 11. In this embodiment, the lead 11 will be described by dividing it into a joint portion 111, a protruding portion 112, an inclined connection portion 113, and a parallel connection portion 114, as shown in FIG.

[0033] The joint portion 111 has a main surface 111a and a back surface 111b. The main surface 111a and the back surface 111b are surfaces facing opposite each other in the thickness direction z and are both flat surfaces perpendicular to the thickness direction z. The main surface 111a faces a first side z1 in the thickness direction z. The back surface 111b faces a second side z2 in the thickness direction z. The back surface 111b is bonded to a pad 221 of the main surface conductive portion 22 by a conductive bonding material 76. The inclined connection portion 113 and the parallel connection portion 114 are covered with a sealing resin 8. The inclined connection portion 113 is connected to the joint portion 111 and the parallel connection portion 114 and is inclined with respect to the joint portion 111 and the parallel connection portion 114. The parallel connection portion 114 is connected to the inclined connection portion 113 and the protruding portion 112 and is parallel to the joint portion 111. The protruding portion 112 is connected to an end of the parallel connection portion 114 and is a portion of the lead 11 that protrudes from the sealing resin 8. The protruding portion 112 protrudes on the opposite side (y1 side) from the bonding portion 111 in the first direction y. The protruding portion 112 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 112 is bent in the thickness direction z toward the side toward which the main surface 111a of the bonding portion 111 faces.

[0034] In this embodiment, the multiple leads 12 are not arranged on the substrate 21, but are arranged on a first side y1 in the first direction y of the substrate 21. Each lead 12 does not include portions corresponding to the joint portion 111 and the inclined connection portion 113 of the lead 11, and is configured only to include portions corresponding to the protruding portion 112 and the parallel connection portion 114. A wire 72 is conductively joined to the portion corresponding to the parallel connection portion 114. Each lead 12 is electrically connected to the semiconductor chip 4 or the passive element 6 via the wire 72 and the main surface conductive portion 22. In this embodiment, the multiple leads 1 include six leads 12. Note that the configuration, number, and arrangement of the leads 12 are not limited to this.

[0035] The multiple leads 15 are each arranged on the substrate 31, and in this embodiment, are arranged on the main surface 311 toward the second side y2 in the first direction y. Each lead 15 is joined to a pad 321 of the main surface conductive portion 32 via a conductive bonding material 76. Each lead 15 is electrically connected to the driving device 5 or the passive element 6 via the main surface conductive portion 22. In this embodiment, the multiple leads 1 include 18 leads 15. The number and arrangement of the leads 15 are not limited.

[0036] There are no particular limitations on the configuration of the lead 15. In this embodiment, the lead 15 will be described by dividing it into a joint portion 151, a protruding portion 152, an inclined connection portion 153, and a parallel connection portion 154, as shown in FIG.

[0037] The joint portion 151 has a main surface 151a and a back surface 151b. The main surface 151a and the back surface 151b are surfaces facing opposite each other in the thickness direction z and are both flat surfaces perpendicular to the thickness direction z. The main surface 151a faces a first side z1 in the thickness direction z. The back surface 151b faces a second side z2 in the thickness direction z. The back surface 151b is joined to the pad 321 of the main surface conductive portion 32 by a conductive bonding material 76. The inclined connection portion 153 and the parallel connection portion 154 are covered with a sealing resin 8. The inclined connection portion 153 is connected to the joint portion 151 and the parallel connection portion 154 and is inclined with respect to the joint portion 151 and the parallel connection portion 154. The parallel connection portion 154 is connected to the inclined connection portion 153 and the protruding portion 152 and is parallel to the joint portion 151. The protruding portion 152 is connected to an end of the parallel connection portion 154 and is a portion of the lead 15 that protrudes from the sealing resin 8. The protruding portion 152 protrudes on the opposite side (y2 side) from the joint portion 151 in the first direction y. The protruding portion 152 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 152 is bent in the thickness direction z toward the side toward which the main surface 151 a of the joint portion 151 faces.

[0038] In this embodiment, the multiple leads 16 are not arranged on the substrate 31, but are arranged on the first side x1 or the second side x2 of the substrate 31 in the second direction x. Each lead 16 has a configuration similar to that of the lead 15. At the portion corresponding to the joint portion 151, instead of being joined to the pad 321 of the main surface conductive portion 32, a wire 74 is electrically connected thereto. Each lead 16 is electrically connected to the driving device 5 and the passive element 6 via the wire 74 and the main surface conductive portion 32. In this embodiment, the multiple leads 16 include four leads 16. Note that the configuration, number, and arrangement of the leads 16 are not limited to this.

[0039] The multiple semiconductor chips 4 are switching elements and power transistors that control power. The semiconductor chips 4 are made of a semiconductor material primarily made of SiC (silicon carbide). The semiconductor material is not limited to SiC and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. The semiconductor chips 4 are, for example, MOSFETs (metal-oxide-semiconductor field-effect transistors). Note that the semiconductor chips 4 are not limited to MOSFETs and may be IGBTs (insulated gate bipolar transistors), or the like. In this embodiment, the semiconductor device A1 includes four semiconductor chips 4, but this is merely an example, and the number of semiconductor chips 4 is not limited.

[0040] Each semiconductor chip 4 has a rectangular plate shape when viewed in the thickness direction z, and includes a main surface 41, a back surface 42, a source electrode 43, a gate electrode 44, and a drain electrode 45. The main surface 41 and the back surface 42 face opposite each other in the thickness direction z. The main surface 41 faces a first side z1 in the thickness direction z. The back surface 42 faces a second side z2 in the thickness direction z. As shown in FIG. 3 , the source electrode 43 and the gate electrode 44 are arranged on the main surface 41. The drain electrode 45 is arranged on the back surface 42. The shapes and arrangements of the source electrode 43, the gate electrode 44, and the drain electrode 45 are not limited.

[0041] As shown in FIGS. 3 and 5 , each semiconductor chip 4 is mounted on the wiring substrate 2. Each semiconductor chip 4 is disposed on the main surface 211 of the base material 21. In this embodiment, the four semiconductor chips 4 are disposed side by side in the second direction x, closer to the second side y2 in the first direction y of the main surface 211. The position of each driver 5 is not limited. As shown in FIG. 5 , each semiconductor chip 4 is bonded to a pad 221 of the main surface conductive portion 22 with a conductive bonding material 76, with the element back surface 42 facing the main surface 211. As a result, the drain electrode 45 of each semiconductor chip 4 is electrically connected to the pad 221 via the conductive bonding material 76. Furthermore, as shown in FIG. 3 , the source electrode 43 of each semiconductor chip 4 is electrically connected to the adjacent pad 221 via a wire 71. The semiconductor device A1 includes two bridge circuits each formed by two semiconductor chips 4.

[0042] As shown in FIG. 3, the source electrode 43 and the gate electrode 44 of the semiconductor chip 4 are electrically connected to the driving device 5 via the wire 73 and the main surface conductive portion 32 of the wiring substrate 3, respectively.

[0043] Each of the multiple driving devices 5 is a so-called gate driver that outputs a driving signal to drive the corresponding semiconductor chip 4. In this embodiment, the driving devices 5 are insulated gate drivers in which a low-voltage side to which a signal is input is insulated from a high-voltage side to which a driving signal is output. Note that the driving devices 5 are not limited to insulated gate drivers. The semiconductor device A1 includes four driving devices 5, matching the number of semiconductor chips 4.

[0044] As shown in FIGS. 3 and 5 , each driver 5 is mounted on the wiring substrate 3. Each driver 5 is disposed on the main surface 311 of the base material 31. In this embodiment, the four drivers 5 are disposed at the center (or approximately the center) of the main surface 311 in the first direction y, aligned in the second direction x. The position of each driver 5 is not limited. In this embodiment, the driver 5 is a small outline package (SOP) type package. The driver 5 includes a plurality of terminals extending from both sides in the first direction y. These terminals are electrically connected to pads 321 on the main surface conductive portion 32 by conductive bonding material 76. The package type of the driver 5 is not limited to the SOP type, and may be other types such as a quad flat package (QFP) type or a small outline J-lead package (SOJ) type. The size, shape, and number of terminals of the driver 5 are not limited. Instead of the driver 5, a driver chip may be directly disposed on the wiring substrate 3. The driving device 5 outputs a driving signal to the gate electrode 44 of the corresponding semiconductor chip 4 via the main surface conductive portion 32 and the wire 73. The driving device 5 also receives the potential of the source electrode 43 of the corresponding semiconductor chip 4 via the main surface conductive portion 32 and the wire 73.

[0045] 3 and 5, a plurality of passive elements 6 are mounted on the wiring board 2 or the wiring board 3. Each passive element 6 is disposed on the main surface 211 of the substrate 21 or the main surface 311 of the substrate 31, and is conductively connected to a pad 221 of the main surface conductive portion 22 or a pad 321 of the main surface conductive portion 32. The passive elements 6 are, for example, resistors, capacitors, coils, diodes, etc. The passive elements 6 include two shunt resistors 6a and a thermistor 6b.

[0046] The two shunt resistors 6a are mounted on the wiring board 2 and arranged on the main surface 211 of the base material 21. Each shunt resistor 6a straddles two pads 221 of the main surface conductive portion 22 and is conductively joined to each pad 221. An output current of a bridge circuit formed by two semiconductor chips 4 flows through each shunt resistor 6a, and a potential difference between both terminals is output.

[0047] The thermistor 6b is mounted on the wiring board 3 and disposed on the main surface 311 of the base material 31. The thermistor 6b straddles two pads 321 of the main surface conductive portion 32 and is conductively joined to each of the pads 321. Each of the pads 321 to which the thermistor 6b is joined is electrically connected to the lead 15 via the pad 321 that is conductively connected by wiring 322. When a predetermined current is passed through the thermistor 6b, the thermistor 6b outputs a voltage signal corresponding to the temperature of the wiring board 3.

[0048] The other passive elements 6 are mounted on the wiring board 3 and arranged on the main surface 311 of the base material 31. Each passive element 6 is electrically connected to a pad 321 of the main surface conductive portion 32, and is electrically connected to the driving device 5 via the wiring 322 and the pad 321. Note that the type, arrangement position, and number of each passive element 6 are not limited.

[0049] The plurality of wires 7 each include a plurality of wires 71, 72, 73, and 74. The plurality of wires 71 are electrically connected to the source electrode 43 of the semiconductor chip 4 and the pad 221. In this embodiment, each semiconductor chip 4 and the pad 221 are connected by two wires 71, but the number of wires 71 connecting each semiconductor chip 4 and the pad 221 is not limited. The wires 71 are made of, for example, aluminum (Al) or copper (Cu). The material and diameter of the wires 71 are not limited. The plurality of wires 72 are electrically connected to the pads 221 of the main surface conductive portion 22 and the leads 12. The number of wires 72 connecting the pads 221 and the leads 12 is not limited. The wires 72 are made of, for example, aluminum (Al) or copper (Cu). The material and diameter of the wires 72 are not limited.

[0050] A plurality of wires 73 are electrically connected to the source electrodes 43 or gate electrodes 44 of the semiconductor chips 4 and the pads 321 of the main surface conductive portion 32 of the wiring substrate 3. In this embodiment, each semiconductor chip 4 is connected to each pad 321 by a single wire 73, but the number of wires 73 connecting each semiconductor chip 4 to each pad 321 is not limited. The wires 73 are made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). The material and diameter of the wires 73 are not limited. A plurality of wires 74 are electrically connected to the pads 321 of the main surface conductive portion 32 of the wiring substrate 3 and the leads 16. In this embodiment, each pad 321 is connected to each lead 16 by a single wire 74, but the number of wires 74 connecting each pad 321 to each lead 16 is not limited. The wires 74 are made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). The material and diameter of the wire 74 are not limited.

[0051] The sealing resin 8 covers at least the semiconductor chips 4, the driving devices 5, the passive elements 6, the wires 7, a portion of each of the leads 1, and a portion of each of the wiring boards 2 and 3. The material of the sealing resin 8 is not particularly limited, and an insulating material such as epoxy resin or silicone gel may be used as appropriate.

[0052] The sealing resin 8 has a resin main surface 81, a resin back surface 82, and four resin side surfaces 83. The resin main surface 81 and the resin back surface 82 are surfaces facing opposite each other in the thickness direction z and are both flat surfaces perpendicular to the thickness direction z. The resin main surface 81 faces a first side z1 in the thickness direction z. The resin back surface 82 faces a second side z2 in the thickness direction z. Each resin side surface 83 is connected to the resin main surface 81 and the resin back surface 82, respectively, and faces the second direction x or the first direction y. As shown in FIG. 4 , the back surface conductive portion 23 of the wiring board 2 and the back surface conductive portion 33 of the wiring board 3 are exposed from the resin back surface 82 of the sealing resin 8. Furthermore, the leads 11 and the leads 12 each protrude from the resin side surface 83 facing the first side y1 in the first direction y of the sealing resin 8. The leads 15 and the leads 16 each protrude from a resin side surface 83 of the sealing resin 8 facing the second side y2 in the first direction y.

[0053] Next, an example of a method for manufacturing the semiconductor device A1 will be described below with reference to Fig. 8. Note that the manufacturing method described below is one means for realizing the semiconductor device A1, and is not limited to this.

[0054] As shown in FIG. 8, the manufacturing method of this example includes a substrate forming step (step S1), a lead frame joining step (step S2), a semiconductor chip mounting step (step S3), a drive device mounting step (step S4), a wire connecting step (step S5), a resin forming step (step S6), and a frame cutting step (step S7).

[0055] In the substrate formation process (step S1), two types of DBC substrates are first prepared. One DBC substrate is a substrate in which copper foil with a thickness of T1 is bonded to both sides of an aluminum nitride ceramic plate. The other DBC substrate is a substrate in which copper foil with a thickness of T2 is bonded to both sides of an alumina ceramic plate. Next, the copper foil on one side of each DBC substrate is patterned by etching. This converts the aluminum nitride DBC substrate into wiring substrate 2. The patterned copper foil on one side becomes main surface conductive portion 22, and the copper foil on the other side becomes back surface conductive portion 23. The alumina DBC substrate becomes wiring substrate 3. The patterned copper foil on one side becomes main surface conductive portion 32, and the copper foil on the other side becomes back surface conductive portion 33.

[0056] In the lead frame bonding process (step S2), first, the wiring board 2 and the wiring board 3 are arranged side by side in the first direction y. Next, a conductive bonding paste is applied to the predetermined pads 221 of the main surface conductive portion 22 and the predetermined pads 321 of the main surface conductive portion 32. The conductive bonding paste may be, for example, silver paste, copper paste, or solder. Next, a lead frame is prepared. The lead frame includes multiple leads 1 and further has a frame to which the multiple leads 1 are connected. Note that the shape of the lead frame is not limited in any way. Next, the multiple leads 11 are each placed against the predetermined pads 221 via the conductive bonding paste. Also, the multiple leads 15 are each placed against the predetermined pads 321 via the conductive bonding paste. Next, the conductive bonding paste is heated and then cooled to form a conductive bonding material 76. As a result, each lead 11 is bonded to the predetermined pad 221 via the conductive bonding material 76, and each lead 15 is bonded to the pad 321 via the conductive bonding material 76.

[0057] In the semiconductor chip mounting process (step S3), first, a conductive adhesive paste is placed at a predetermined position on a predetermined pad 221 of the main surface conductive portion 22 of the wiring substrate 2. Next, each semiconductor chip 4 is attached to the conductive adhesive paste. Next, the conductive adhesive paste is heated and then cooled to form a conductive adhesive material 76. This bonds the semiconductor chip 4 to the pad 221 via the conductive adhesive material 76. Furthermore, by a similar process, the shunt resistor 6a is bonded to the pad 221 via the conductive adhesive material 76.

[0058] In the driver mounting process (step S4), first, a conductive adhesive paste is placed on predetermined pads 321 on the main surface conductive portion 32 of the wiring board 3. Next, each terminal of each driver 5 is attached to the conductive adhesive paste. Next, the conductive adhesive paste is heated and then cooled to form a conductive adhesive material 76. This bonds the driver 5 to the pad 321 via the conductive adhesive material 76. Furthermore, by a similar process, the thermistor 6b and other passive elements 6 are bonded to the pad 321 via the conductive adhesive material 76.

[0059] In the wire connection process (step S5), first, a plurality of wires 71 and 72 are connected. In this example, wire materials made of aluminum (Al) are connected in sequence, for example, by wedge bonding. This results in a plurality of wires 71. Next, a plurality of wires 73 and 74 are connected. In this example, wire materials made of gold (Au) are connected in sequence, for example, by capillary bonding. This results in a plurality of wires 72.

[0060] In the resin forming step (step S6), for example, a mold is used to enclose a portion of the lead frame, the wiring substrates 2 and 3, and the respective semiconductor chips 4, the drive devices 5, the passive elements 6, and the wires 7. Next, a liquid resin material is poured into the space defined by the mold. Next, the resin material is cured to obtain the sealing resin 8.

[0061] In the frame cutting process (step S7), the lead frame is cut at appropriate locations of the portions exposed from the sealing resin 8. This separates the leads 1 from one another. Thereafter, the leads 1 are subjected to processes such as bending as necessary, thereby obtaining the semiconductor device A1 described above.

[0062] Next, the effects of the semiconductor device A1 will be described.

[0063] According to this embodiment, the wiring board 3 includes a main surface conductive portion 32 disposed on the main surface 311 of the base material 31. The main surface conductive portion 32 has a pad 321 electrically connected to the driving device 5. This allows the conductive path to the driving device 5 to be formed by the main surface conductive portion 32 disposed on the main surface 311 of the base material 31. Therefore, compared to when the conductive path is formed by, for example, a metal lead, it is possible to achieve a thinner and denser conductive path.

[0064] According to this embodiment, the semiconductor device A1 includes a wiring substrate 2 in addition to the wiring board 3. The wiring substrate 2 includes a main surface conductive portion 22 disposed on the main surface 211 of the substrate 21. The main surface conductive portion 22 has pads 221 to which the semiconductor chip 4 is bonded. The thickness T1 of the main surface conductive portion 22 is larger than the thickness T2 of the main surface conductive portion 32, and is a thickness that can maintain the heat dissipation effect of the heat generated by the semiconductor chip 4. On the other hand, the thickness T2 is smaller than the thickness T1, and is a thickness that allows for finer processing by etching. When a common main surface conductive portion is disposed on the main surface of a common substrate, a thicker main surface conductive portion makes fine processing difficult, while a thinner main surface conductive portion does not provide sufficient heat dissipation effect. Because the semiconductor device A1 includes the wiring substrate 2 and the wiring substrate 3, it is possible to achieve both heat dissipation from the semiconductor chip 4 and thin and denser conduction paths to the drive device 5.

[0065] Furthermore, in this embodiment, the wiring board 2 is formed by patterning the copper foil on one surface of the DBC board by etching. Therefore, the manufacturing process can be simplified compared to when the main surface conductive portion 22 and the back surface conductive portion 23 are separately formed on the base material 21. The same applies to the wiring board 3.

[0066] Furthermore, in this embodiment, the base material 21 of the wiring board 2 is an aluminum nitride ceramic plate. Furthermore, the base material 31 of the wiring board 3 is an alumina ceramic plate. Therefore, the base material 21 has higher thermal conductivity than the base material 31. This allows the wiring board 2 to appropriately dissipate the heat generated by the semiconductor chip 4. Furthermore, the material cost of the wiring board 3, which does not require as much heat dissipation as the wiring board 2, can be reduced.

[0067] Furthermore, according to this embodiment, the rear surface conductive portion 33 of the wiring substrate 2 is exposed from the resin rear surface 82. This allows the heat transferred from the semiconductor chip 4 to the wiring substrate 2 to be more efficiently dissipated to the outside.

[0068] Furthermore, according to this embodiment, the semiconductor device A1 includes a thermistor 6b mounted on the wiring board 3. Therefore, the semiconductor device A1 can detect the temperature of the wiring board 3.

[0069] Furthermore, according to this embodiment, the multiple leads 11 are bonded to the pads 221 of the main surface conductive portion 22 via the conductive bonding material 76. This allows the multiple leads 11 to be firmly fixed to the wiring board 2. This also allows for low resistance between the multiple leads 11 and the main surface conductive portion 22. Furthermore, the multiple leads 15 are bonded to the pads 321 of the main surface conductive portion 32 via the conductive bonding material 76. This allows the multiple leads 15 to be firmly fixed to the wiring board 3. This also allows for low resistance between the multiple leads 15 and the main surface conductive portion 32.

[0070] In this embodiment, the base material 31 is described as being made of ceramic, but the present invention is not limited to this. The base material 31 does not require as much thermal conductivity as the base material 21, and therefore may be a substrate containing a synthetic resin such as glass epoxy resin. In other words, the wiring board 3 may be a so-called PCB (Printed Circuit Board) board. The base material 31 may also be a multilayer board in which multiple base materials are stacked.

[0071] 9 to 12 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are denoted by the same reference numerals as those in the above embodiment.

[0072] Second Embodiment: Figure 9 is a diagram for explaining a semiconductor device A2 according to a second embodiment of the present disclosure. Figure 9 is a cross-sectional view showing the semiconductor device A2, and is a diagram corresponding to Figure 5. The semiconductor device A2 according to the second embodiment differs from the first embodiment in that the entire wiring substrate 3 is covered with a sealing resin 8. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment.

[0073] In this embodiment, the wiring board 3 does not have a back surface conductive portion 33. The wiring board 3 according to this embodiment is formed by patterning, by etching, the copper foil of a DBC substrate, in which copper foil is bonded to only one side of a ceramic plate. Furthermore, the wiring board 3 is not exposed from the resin back surface 82, and is entirely covered with the sealing resin 8. Unlike the wiring board 2 on which the semiconductor chip 4 is mounted, the wiring board 3 does not require much heat dissipation. Therefore, it does not pose much of a problem if the wiring board 3 is not exposed from the resin back surface 82 and heat dissipation is suppressed.

[0074] In this embodiment, the semiconductor device A2 also includes the wiring substrate 2 and the wiring substrate 3, which allows for both the dissipation of heat generated by the semiconductor chip 4 and the thinning and high-density of the conductive path to the drive device 5. Furthermore, the semiconductor device A2 has a configuration in common with the semiconductor device A1, thereby achieving the same effects as the semiconductor device A1. Furthermore, the semiconductor device A2 does not include the back surface conductive portion 33 on the wiring substrate 3, which allows for reduction in material costs.

[0075] In the present embodiment, the case where the wiring board 3 is not exposed from the resin rear surface 82 has been described, but this is not limiting. The wiring board 3 may have the rear surface 312 of the base material 31 exposed from the resin rear surface 82.

[0076] Third Embodiment: Figure 10 is a diagram illustrating a semiconductor device A3 according to a third embodiment of the present disclosure. Figure 10 is a cross-sectional view showing the semiconductor device A3, and is a diagram corresponding to Figure 5. The semiconductor device A3 according to the third embodiment differs from the first embodiment in that passive elements 6 are also arranged on the back surface 312 of the base material 31 of the wiring board 3. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first and second embodiments described above may be combined in any desired manner.

[0077] In this embodiment, the wiring board 3 has passive elements 6 arranged not only on the main surface 311 but also on the back surface 312. The type, number, and arrangement position of the passive elements 6 arranged on the back surface 312 are not limited. In the wiring board 3, the back surface conductive portion 33 includes pads 331 and wiring 332. The pads 331 and wiring 332 are formed by patterning the copper foil on the other surface of the DBC substrate by etching. The shape of the back surface conductive portion 33 is not limited. The passive elements 6 are conductively joined to the pads 331 via conductive bonding material 76. Also, in this embodiment, as in the second embodiment, the wiring board 3 is not exposed from the resin back surface 82 and is entirely covered with the sealing resin 8. The passive elements 6 arranged on the back surface 312 are also covered with the sealing resin 8. The electronic components arranged on the back surface 312 are not limited to the passive elements 6; for example, a driving device 5 may be arranged on the back surface 312.

[0078] In this embodiment, the semiconductor device A3 also includes the wiring substrate 2 and the wiring substrate 3, so that it is possible to dissipate heat generated by the semiconductor chip 4 while simultaneously achieving thinner and denser conductive paths to the drive device 5. Furthermore, by adopting a configuration common to the semiconductor device A1, the semiconductor device A3 achieves the same effects as the semiconductor device A1. Furthermore, the semiconductor device A3 can mount more passive elements 6 because the passive elements 6 can be disposed on both sides of the wiring substrate 3. Furthermore, even if the passive elements 6 mounted on the wiring substrate 3 remain the same, disposing the passive elements 6 on both sides can reduce the size of the wiring substrate 3 as viewed in the thickness direction z. This allows the semiconductor device A3 to be miniaturized.

[0079] Fourth Embodiment: Figure 11 is a diagram illustrating a semiconductor device A4 according to a fourth embodiment of the present disclosure. Figure 11 is a cross-sectional view showing the semiconductor device A4, and is a diagram corresponding to Figure 5. The semiconductor device A4 according to the fourth embodiment differs from the first embodiment in the method of arranging the wiring substrate 2 and the wiring substrate 3. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first to third embodiments described above may be combined in any desired manner.

[0080] In this embodiment, the dimension of the wiring board 2 in the first direction y is larger than that of the semiconductor device A1. The wiring board 3 is disposed on a first side z1 in the thickness direction z of the wiring board 2, closer to a second side y2 in the first direction y of the wiring board 2. The entire wiring board 3 overlaps the wiring board 2 when viewed in the thickness direction z. The wiring board 3 does not include a back surface conductive portion 33, and the back surface 312 of the base material 31 is joined to the main surface 211 of the base material 21 of the wiring board 2.

[0081] In this embodiment, the semiconductor device A4 also includes the wiring substrate 2 and the wiring substrate 3, so that it is possible to dissipate heat generated by the semiconductor chip 4 while simultaneously achieving thinner and denser conductive paths to the drive device 5. Furthermore, by adopting a configuration common to the semiconductor device A1, the semiconductor device A4 achieves the same effects as the semiconductor device A1. Furthermore, since the dimension of the wiring substrate 2 in the first direction y is large in the semiconductor device A4, the area of ​​the back surface conductive portion 23 exposed from the resin back surface 82 is also large. This allows the semiconductor device A4 to more efficiently dissipate heat transferred from the semiconductor chip 4 to the wiring substrate 2 to the outside.

[0082] Fifth Embodiment: FIG. 12 is a diagram illustrating a semiconductor device A5 according to a fifth embodiment of the present disclosure. FIG. 12 is a partially enlarged plan view showing the semiconductor device A5, and is an enlarged view of a portion of the diagram corresponding to FIG. 3. Note that the sealing resin 8 is omitted in FIG. 12. The semiconductor device A5 according to the fifth embodiment differs from the first embodiment in that a thermistor is also mounted on the wiring substrate 2. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first to fourth embodiments described above may be combined in any desired manner.

[0083] In this embodiment, the semiconductor device A5 further includes a thermistor 6c. The thermistor 6c is mounted on the wiring substrate 2 and disposed on the main surface 211 of the base material 21. In this embodiment, the main surface conductive portion 22 of the wiring substrate 2 includes two pads 221a. The two pads 221a are disposed side by side in the x direction, spaced apart from each other, at the center of the main surface 211 of the base material 21 in the second direction x and at the end of the second side y2 in the first direction y. The thermistor 6c straddles the two pads 221a and is conductively bonded to each of the pads 221a. In this embodiment, the semiconductor device A5 further includes two wires 75. The wires 75 are made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). The material and diameter of the wires 75 are not limited. Each wire 75 is conductively bonded to a pad 221a and a pad 321 of the main surface conductive portion 32. The pads 321 to which the wires 75 are bonded are electrically connected to the leads 15 via the pads 321 electrically connected by wiring 322. The layout of the main surface conductive portion 32 is not shown. A predetermined current is passed through the thermistor 6c, and the thermistor 6c outputs a voltage signal corresponding to the temperature of the wiring board 2.

[0084] In this embodiment, the semiconductor device A5 also includes the wiring substrate 2 and the wiring substrate 3, which allows for both the dissipation of heat generated by the semiconductor chip 4 and the thinning and high-density conduction paths to the drive device 5. The semiconductor device A5 also has the same configuration as the semiconductor device A1, thereby achieving the same effects as the semiconductor device A1. Furthermore, the semiconductor device A5 includes the thermistor 6c, which allows it to detect the temperature of the wiring substrate 2.

[0085] In this embodiment, the semiconductor device A5 is described as having only one thermistor 6c for detecting the temperature of the wiring substrate 2, but this is not limiting. The semiconductor device A5 may have, for example, four thermistors 6c, each disposed adjacent to a semiconductor chip 4. In this case, each thermistor 6c can detect the temperature of the adjacent semiconductor chip 4.

[0086] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. The present disclosure includes the embodiments described in the following appendices.

[0087] Supplementary Note 1. A semiconductor device (A1) comprising: a first substrate (21) having a first main surface (211) and a first back surface (212) facing opposite each other in a thickness direction (z); a conductive first main surface conductive portion (22) arranged on the first main surface; a second substrate (31) having a second main surface (311) facing the same side as the first main surface in the thickness direction and a second back surface (312) facing the same side as the first back surface; a conductive second main surface conductive portion (32) arranged on the second main surface; a switching element (4) arranged on the first main surface and conductively connected to the first main surface conductive portion; a drive device (5) arranged on the second main surface and conductively connected to the second main surface conductive portion, and driving the switching element; and a sealing resin (8) covering at least a portion of the first substrate and the second substrate, and the entirety of the switching element and the drive device. (FIG. 6) The semiconductor device according to Supplementary Note 1, wherein a first dimension (T1) in the thickness direction of the first main surface conductive portion is larger than a second dimension (T2) in the thickness direction of the second main surface conductive portion. Supplementary Note 3. The semiconductor device according to Supplementary Note 1 or 2, wherein the first base material has higher thermal conductivity than the second base material. Supplementary Note 4. The semiconductor device according to any of Supplements 1 to 3, wherein the first base material contains aluminum nitride. Supplementary Note 5. The semiconductor device according to any of Supplements 1 to 4, wherein the second base material contains alumina. Supplementary Note 6. The semiconductor device according to any of Supplements 1 to 4, wherein the second base material contains synthetic resin. Supplementary Note 7. The semiconductor device according to any of Supplements 1 to 6, wherein the second base material is disposed in a first direction (y) perpendicular to the thickness direction with respect to the first base material. Supplementary Note 8. The semiconductor device according to Supplementary Note 7, further comprising a second back surface conductive portion (33) having conductivity disposed on the second back surface, wherein the second back surface conductive portion is exposed from the sealing resin. Supplementary Note 9. (Third embodiment, FIG. 10) The semiconductor device according to appendix 7, further comprising a back surface electronic component (6) arranged on the second back surface, the back surface electronic component being covered with the sealing resin.Supplementary Note 10. (Fourth embodiment, FIG. 11) The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the second base material is disposed in the thickness direction relative to the first base material. Supplementary Note 11. The semiconductor device according to any one of Supplementary Notes 1 to 10, further comprising a first back surface conductive portion (23) having conductivity disposed on the first back surface, wherein the first back surface conductive portion is exposed from the sealing resin. Supplementary Note 12. The semiconductor device according to any one of Supplementary Notes 1 to 11, wherein the drive device is an insulated gate driver. Supplementary Note 13. (Fifth embodiment, FIG. 12) The semiconductor device according to any one of Supplementary Notes 1 to 12, further comprising a first temperature detection portion (6c) disposed on the first main surface. Supplementary Note 14. The semiconductor device according to any one of Supplementary Notes 1 to 13, further comprising a second temperature detection portion (6b) disposed on the second main surface.

[0088] A1, A2, A3, A4, A5: semiconductor device 1, 11, 12, 15, 16: lead 111: bonding portion 111a: main surface 111b: back surface 112: protruding portion 113: inclined connection portion 114: parallel connection portion 151: bonding portion 151a: main surface 151b: back surface 152: protruding portion 153: inclined connection portion 154: parallel connection portion 2: wiring substrate 21: base material 211: main surface 212: back surface 22: main surface conductive portion 221, 221a: pad 222: wiring 23: back surface conductive portion 3: wiring substrate 31: base material 311: main surface 312: back surface 32: main surface conductive portion 321: pad 322: wiring 33: back surface conductive portion 331: pad 332: wiring 4: semiconductor chip 41: Element main surface 42: Element back surface 43: Source electrode 44: Gate electrode 45: Drain electrode 5: Driver 6: Passive element 6a: Shunt resistor 6b, 6c: Thermistor 7, 71 to 75: Wire 76: Conductive bonding material 8: Sealing resin 81: Resin main surface 82: Resin back surface 83: Resin side surface

Claims

1. a first base material having a first main surface and a first back surface facing in opposite directions in a thickness direction; a first main surface conductive portion having conductivity and disposed on the first main surface; a second base material having a second main surface facing the same side as the first main surface in the thickness direction and a second back surface facing the same side as the first back surface; a second main surface conductive portion having conductivity and disposed on the second main surface; a switching element disposed on the first main surface and conductively connected to the first main surface conductive portion; a driving device disposed on the second main surface, conductively connected to the second main surface conductive portion, and configured to drive the switching element; a sealing resin that covers at least a portion of the first base material and the second base material, and the entirety of the switching element and the drive device; The semiconductor device comprises:

2. The semiconductor device according to claim 1 , wherein a first dimension in the thickness direction of said first main surface conductive portion is larger than a second dimension in the thickness direction of said second main surface conductive portion.

3. The semiconductor device according to claim 1 , wherein the first base material has a higher thermal conductivity than the second base material.

4. The semiconductor device according to claim 1 , wherein the first base material comprises aluminum nitride.

5. The semiconductor device according to claim 1 , wherein the second base material comprises alumina.

6. The semiconductor device according to claim 1 , wherein the second base material includes a synthetic resin.

7. The semiconductor device according to claim 1 , wherein the second base material is disposed in a first direction perpendicular to the thickness direction of the first base material.

8. a second back surface conductive portion having conductivity and disposed on the second back surface; The semiconductor device according to claim 7 , wherein the second back surface conductive portion is exposed from the sealing resin.

9. Further comprising a backside electronic component disposed on the second backside surface, The semiconductor device according to claim 7 , wherein the back surface electronic components are covered with the sealing resin.

10. The semiconductor device according to claim 1 , wherein the second base material is disposed in the thickness direction relative to the first base material.

11. a first back surface conductive portion having conductivity and disposed on the first back surface; The semiconductor device according to claim 1 , wherein the first back surface conductive portion is exposed from the sealing resin.

12. 7. The semiconductor device according to claim 1, wherein the driving device is an insulated gate driver.

13. 7. The semiconductor device according to claim 1, further comprising a first temperature detector disposed on said first main surface.

14. 7. The semiconductor device according to claim 1, further comprising a second temperature detector disposed on said second main surface.