Semiconductor device

Abstract

A semiconductor device according to the present invention comprises: a plurality of transistors which are electrically connected in parallel with each other, and each of which comprises a first pad; and a conductive member. The first pad is a source pad or an emitter pad; and the first pad has a first connection region, and a second connection region and a third connection region, between which the first connection region is sandwiched. This semiconductor device comprises: a first connection member which connects the first connection region and the conductive member to each other; a second connection member which connects the second connection regions of two transistors among the plurality of transistors; and a third connection member which connects the third connection regions of the two transistors among the plurality of transistors.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2022-101718 filed on June 24, 2022, and incorporates by reference all of the contents of the aforementioned Japanese application.

[0003] One known semiconductor device is a power module in which multiple transistors are connected in parallel to ensure current capacity. Patent documents 1, 2, and 3 have also been proposed, in which main electrodes, such as source electrodes, of multiple transistors are connected to each other to suppress oscillation of the potential of the gate electrodes of the transistors.

[0004] Japanese Patent Publication No. 2016-184667 Japanese Patent Publication No. 2010-178615 Japanese Patent Publication No. 2013-012560

[0005] The semiconductor device of the present disclosure has a plurality of transistors electrically connected in parallel to each other and including a first pad, and a conductive member, the first pad being a source pad or an emitter pad, the first pad having a first connection region, a second connection region and a third connection region sandwiching the first connection region, a first connection member connecting the first connection region and the conductive member, a second connection member connecting the second connection regions of two of the plurality of transistors, and a third connection member connecting the third connection regions of the two of the plurality of transistors.

[0006] FIG. 1 is a top view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 3 is a schematic diagram showing the configuration of a transistor. FIG. 4 is a top view showing a semiconductor device according to a second embodiment. FIG. 5 is a top view showing a semiconductor device according to a third embodiment. FIG. 6 is a top view showing a semiconductor device according to a fourth embodiment. FIG. 7 is a top view showing a semiconductor device according to a fifth embodiment. FIG. 8 is a top view showing a semiconductor device according to a sixth embodiment. FIG. 9 is a cross-sectional view showing a semiconductor device according to the sixth embodiment. FIG. 10 is a diagram showing a method of using the semiconductor device according to the sixth embodiment.

[0007] [Problem to be Solved by the Present Disclosure] Conventional semiconductor devices are unable to sufficiently suppress oscillation, making it difficult to stabilize parallel operation between multiple transistors.

[0008] An object of the present disclosure is to provide a semiconductor device that can improve the stability of parallel operation among a plurality of transistors.

[0009] [Advantages of the Present Disclosure] According to the present disclosure, it is possible to improve the stability of parallel operation among a plurality of transistors.

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0011] [1] A semiconductor device according to one aspect of the present disclosure includes a plurality of transistors electrically connected in parallel to each other and including a first pad, and a conductive member, the first pad being a source pad or an emitter pad, the first pad having a first connection region, and a second connection region and a third connection region sandwiching the first connection region, a first connection member connecting the first connection region and the conductive member, a second connection member connecting the second connection regions of two of the plurality of transistors, and a third connection member connecting the third connection regions of the two of the plurality of transistors.

[0012] In each transistor, a current reaching the first connection region flows to the first connection member, a current reaching the second connection region flows to the first connection member via the first connection region, and a current reaching the third connection region flows to the first connection member via the first connection region. That is, a current reaching a first pad flows to the first connection member via the first connection region sandwiched between the second and third connection regions. Furthermore, the second connection regions of two transistors are connected by the second connection member, and the third connection regions are connected by the third connection member. Without the second connection member or the third connection member, potential differences between the second connection regions or the third connection regions of two transistors are likely to occur. When potential differences between the second connection regions or the third connection regions occur, oscillations can occur due to potential differences between the first pads. In contrast, the provision of the second connection member and the third connection member reduces the potential differences between the first pads, thereby suppressing oscillations. This improves the stability of parallel operation among multiple transistors.

[0013] [2] In [1], the second connection region may have a first internal connection region and a second internal connection region spaced apart from the first internal connection region, and may have a fourth connection member connecting the first internal connection region and the second internal connection region. In this case, it is easy to suppress a potential difference within each second connection region.

[0014] [3] In [2], the second connection member and the fourth connection member may be integral. In this case, the second connection member and the fourth connection member can be continuously formed by stitch bonding, reducing the frequency of bonding wire breakage and suppressing damage to transistors due to breakage.

[0015] [4] In [2] or [3], the first pad may have a gap between the first internal connection region and the second internal connection region, in which case a gate wiring can be disposed between the first internal connection region and the second internal connection region.

[0016] [5] In any one of [1] to [4], an insulating substrate may be provided, and the plurality of transistors may be mounted on the insulating substrate. In this case, the plurality of transistors may be easily arranged close to each other.

[0017] [6] In any one of [1] to [4], a plurality of insulating substrates may be provided, some of the plurality of transistors may be mounted on each insulating substrate, and the second connection regions of the two transistors mounted on different insulating substrates may be connected to each other by the second connection member, and the third connection regions of the two transistors may be connected to each other by the third connection member. In this case, heat transfer between the transistors mounted on different insulating substrates may be suppressed.

[0018] [7] In any one of [1] to [6], the cross-sectional areas of the second connection member and the third connection member perpendicular to the longitudinal direction may be equal to the cross-sectional area of ​​the first connection member perpendicular to the longitudinal direction, making it easier to form the first connection region, the second connection member, and the third connection member.

[0019] [8] In any one of [1] to [6], the transistor may have a gate pad and a fifth connection member connected to the gate pad, and the cross-sectional areas of the second connection member and the third connection member perpendicular to the longitudinal direction may be equal to the cross-sectional area of ​​the fifth connection member perpendicular to the longitudinal direction. In this case, the second connection member, the third connection member, and the fifth connection member may be easily formed.

[0020] [9] In any one of [1] to [8], a diode may be electrically connected in parallel to the plurality of transistors. In this case, the diode can be used as a free wheel diode.

[0021]

[10] In [9], the diode may be a silicon carbide diode, which makes it easier to achieve a high breakdown voltage for the diode.

[0022]

[11] In any one of [1] to

[10] , the transistor may be a silicon carbide transistor. In this case, it is easy to realize a high breakdown voltage for the transistor.

[0023]

[12] In any one of [1] to

[11] , the first connection region, the second connection region, and the third connection region may be spaced apart from one another when viewed from a direction perpendicular to a surface of the transistor on which the first pad is provided. In this case, it is easy to reduce the potential difference between the first pads and to suppress oscillation.

[0024]

[13] A semiconductor device according to another aspect of the present disclosure includes a transistor including a first pad, a sealing material that seals the transistor, a first terminal connected to the first pad and extending from the sealing material in a first direction, and a second terminal connected to the first pad and extending from the sealing material in a second direction different from the first direction, wherein the first pad is a source pad or an emitter pad.

[0025] When multiple semiconductor devices are used with the transistors electrically connected in parallel, connecting the second terminals together reduces the potential difference between the first pads and suppresses oscillation, thereby improving the stability of parallel operation among the multiple transistors.

[0026]

[14] In

[13] , a first wire may be provided connecting the first pad and the first terminal, and a second wire may be provided connecting the first pad and the second terminal. In this case, the first pad and the first terminal can be easily connected, and the first pad and the second terminal can be easily connected.

[0027]

[15] In the configuration

[13] or

[14] , a third terminal may be connected to the first pad and extend from the sealing material in a direction opposite to the second terminal. In this case, by arranging a plurality of semiconductor devices linearly and connecting the second terminal and the third terminal, the potential difference between the first pads can be reduced.

[0028]

[16] In

[15] , a third wire may be provided to connect the first pad and the third terminal. In this case, the first pad and the third terminal can be easily connected.

[0029]

[17] In any one of

[13] to

[16] , the transistor may be a silicon carbide transistor. In this case, it is easy to realize a high breakdown voltage for the transistor.

[0030] [Details of Embodiments of the Present Disclosure] Embodiments of the present disclosure will be described in detail below, but the present disclosure is not limited thereto. Note that, in this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant description. In this specification and drawings, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. The plane including the X1-X2 direction and the Y1-Y2 direction is defined as the XY plane, the plane including the Y1-Y2 direction and the Z1-Z2 direction is defined as the YZ plane, and the plane including the Z1-Z2 direction and the X1-X2 direction is defined as the ZX plane. For convenience, the Z1 direction is defined as the upward direction, and the Z2 direction is defined as the downward direction. Furthermore, in this disclosure, a planar view refers to viewing an object from the Z1 side.

[0031] First Embodiment First, the first embodiment will be described. Fig. 1 is a top view showing a semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. Fig. 2 corresponds to a cross-sectional view taken along line II-II in Fig. 1.

[0032] 1 and 2 , the semiconductor device 1 according to the first embodiment has a heat sink 121, a housing 122, a source terminal 101, a drain terminal 102, a gate terminal 103, and a sense source terminal 104. The semiconductor device 1 further has a first conductive layer 11, a second conductive layer 12, a third conductive layer 13, a fourth conductive layer 14, and an insulating substrate 123. The semiconductor device 1 further has a plurality of transistors 200. The number of transistors 200 is not limited, and is four in one example.

[0033] The transistor 200 is a field-effect transistor and includes a silicon carbide substrate 210, a gate pad 231, a source pad 232, and a drain electrode 233. The gate pad 231 and the source pad 232 are provided on the upper surface (surface on the Z1 side) of the transistor 200, and the drain electrode 233 is provided on the lower surface (surface on the Z2 side) of the transistor 200. The source pad 232 includes a first connection region 241, a second connection region 242, and a third connection region 243. The first connection region 241 is located on the Y2 side of the second connection region 242, and the third connection region 243 is located on the Y2 side of the first connection region 241. Therefore, the second connection region 242 and the third connection region 243 sandwich the first connection region 241 therebetween. The source pad 232 is an example of a first pad.

[0034] The heat sink 121 is, for example, a rectangular plate-like body with a uniform thickness in a plan view. The material of the heat sink 121 is a metal with high thermal conductivity, such as copper (Cu), a copper alloy, or aluminum (Al). The heat sink 121 is fixed to a cooler or the like using a thermal interface material (TIM) or the like.

[0035] The housing 122 is formed, for example, in a frame shape in a plan view, and the outer shape of the housing 122 is the same as the outer shape of the heat sink 121. The housing 122 is made of an insulating material such as resin. The housing 122 has a pair of side walls 191 and 192 facing each other and a pair of end walls 193 and 194 connecting both ends of the side walls 191 and 192. The side walls 191 and 192 are arranged parallel to the ZX plane, and the end walls 193 and 194 are arranged parallel to the YZ plane. The side wall 191 is arranged on the Y1 side of the side wall 192, and the end wall 193 is arranged on the X1 side of the end wall 194.

[0036] A gate terminal 103 and a sense source terminal 104 are disposed on the upper surface (surface on the Z1 side) of the side wall portion 191. The gate terminal 103 and the sense source terminal 104 are each made of a metal plate.

[0037] A source terminal 101 and a drain terminal 102 are arranged on the upper surface (surface on the Z1 side) of the end wall portion 193. For example, the drain terminal 102 is arranged on the Y1 side of the source terminal 101. The source terminal 101 and the drain terminal 102 are each made of a metal plate.

[0038] An insulating substrate 123 is disposed inside the housing 122 on the Z1 side of the heat sink 121. The first conductive layer 11, the second conductive layer 12, the third conductive layer 13, and the fourth conductive layer 14 are provided on the Z1 side surface of the insulating substrate 123. A fifth conductive layer 15 is provided on the Z2 side surface of the insulating substrate 123. The fifth conductive layer 15 is bonded to the heat sink 121 by a second bonding material 132. The insulating substrate 123 is made of a material such as silicon nitride (SiN), aluminum oxide (Al ２ O ３ ) or aluminum nitride (AlN). The material of the first conductive layer 11, the second conductive layer 12, the third conductive layer 13, the fourth conductive layer 14, and the fifth conductive layer 15 is, for example, copper. The material of the second bonding material 132 is, for example, a solder such as a lead-free solder containing tin (Sn). The first conductive layer 11 is an example of a conductive member.

[0039] The source terminal 101 is connected to the first conductive layer 11, and the drain terminal 102 is connected to the second conductive layer 12. The gate terminal 103 is connected to the third conductive layer 13, and the sense source terminal 104 is connected to the fourth conductive layer 14.

[0040] The semiconductor device 1 further includes a first bonding wire 161 , a second bonding wire 162 , a third bonding wire 163 , a fourth bonding wire 164 , and a fifth bonding wire 165 .

[0041] The transistors 200 are provided on the second conductive layer 12. The transistors 200 are lined up along the X1-X2 direction. A first connection region 241 of a source pad 232 of each transistor 200 is connected to the first conductive layer 11 by a plurality of first bonding wires 161. A drain electrode 233 of each transistor 200 is bonded to the second conductive layer 12 by a first bonding material 131. The material of the first bonding material 131 is, for example, a solder such as a lead-free solder containing tin (Sn). A gate pad 231 of each transistor 200 is connected to the third conductive layer 13 by a fourth bonding wire 164. The source pad 232 of each transistor 200 is also connected to the fourth conductive layer 14 by a fifth bonding wire 165. Between transistors 200 adjacent to each other in the X1-X2 direction, the second connection regions 242 are connected to each other by the second bonding wire 162, and the third connection regions 243 are connected to each other by the third bonding wire 163. The first bonding wire 161 is an example of a first connecting member, the second bonding wire 162 is an example of a second connecting member, the third bonding wire 163 is an example of a third connecting member, and the fourth bonding wire 164 is an example of a fifth connecting member.

[0042] Here, a description will be given of the current path in the transistor 200. FIG.

[0043] As shown in FIG. 3 , the transistor 200 mainly includes a silicon carbide substrate 210 , a gate pad 231 , a source pad 232 , and a drain electrode 233 .

[0044] The silicon carbide substrate 210 includes a silicon carbide single crystal substrate 211 and a silicon carbide epitaxial layer 212 on the silicon carbide single crystal substrate 211. The silicon carbide substrate 210 has a main surface 210A and a main surface 210B opposite to the main surface 210A. The silicon carbide epitaxial layer 212 forms the main surface 210A, and the silicon carbide single crystal substrate 211 forms the main surface 210B. Although not shown, a plurality of transistor cells are provided in the silicon carbide epitaxial layer 212. A gate pad 231 and a source pad 232 are provided on the main surface 210A, and a drain electrode 233 is provided on the main surface 210B.

[0045] In each transistor cell, a current I flows from the drain electrode 233 toward the source pad 232. Furthermore, within the source pad 232, the current I flows toward the first connection region 241 to which the first bonding wire 161 is connected. Then, the current I flows through the first connection region 241 to the first bonding wire 161. The current I that reaches the first connection region 241 flows directly to the first bonding wire 161. Furthermore, the current I that reaches the second connection region 242 flows to the first bonding wire 161 via the first connection region 241, and the current I that reaches the third connection region 243 flows to the first bonding wire 161 via the first connection region 241. The length and electrical resistance of the current path between the transistor cell close to the first connection region 241 and the first bonding wire 161 differ from those of the current path between the transistor cell far from the first connection region 241 and the first bonding wire 161. Therefore, without the second bonding wire 162 or the third bonding wire 163, a difference in potential between the second connection regions 242 or the third connection regions 243 between two transistors 200 is likely to occur. If a difference in potential between the second connection regions 242 or the third connection regions 243 occurs, a potential difference occurs between the source pads 232, and this potential difference can cause oscillation. In contrast, in this embodiment, the provision of the second bonding wire 162 and the third bonding wire 163 reduces the potential difference between the source pads 232 and suppresses oscillation. This improves the stability of parallel operation between multiple transistors 200.

[0046] Furthermore, since the plurality of transistors 200 are mounted on the insulating substrate 123, it is easy to arrange the plurality of transistors 200 in close proximity to one another.

[0047] Since transistor 200 is a silicon carbide transistor including silicon carbide substrate 210, a high breakdown voltage can be easily achieved.

[0048] The cross-sectional area perpendicular to the longitudinal direction of second bonding wire 162 and third bonding wire 163 is not limited, but may be equal to the cross-sectional area perpendicular to the longitudinal direction of first bonding wire 161. In this case, first bonding wire 161, second bonding wire 162, and third bonding wire 163 can be formed without replacing the wires. Therefore, first bonding wire 161, second bonding wire 162, and third bonding wire 163 can be easily formed.

[0049] Furthermore, the cross-sectional area perpendicular to the longitudinal direction of second bonding wire 162 and third bonding wire 163 may be equal to the cross-sectional area perpendicular to the longitudinal direction of fourth bonding wire 164. In this case, fourth bonding wire 164, second bonding wire 162, and third bonding wire 163 can be formed without replacing the wires. Therefore, fourth bonding wire 164, second bonding wire 162, and third bonding wire 163 can be easily formed.

[0050] Second Embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the transistor and in that bonding wires are further included. Figure 4 is a top view showing a semiconductor device according to the second embodiment.

[0051] 4 , the semiconductor device 2 according to the second embodiment has a transistor 300 instead of the transistor 200. The transistor 300 has a gate pad 231, a source pad 332, a drain electrode 233, and a gate wiring (gate runner) 234. The gate pad 231, the gate wiring 334, and the source pad 332 are provided on the upper surface (surface on the Z1 side) of the semiconductor device 1, and the drain electrode 233 is provided on the lower surface (surface on the Z2 side) of the semiconductor device 1.

[0052] The source pad 332 has a first connection region 341, a second connection region 342, and a third connection region 343. The first connection region 341 is on the Y2 side of the second connection region 342, and the third connection region 343 is on the Y2 side of the first connection region 341. Therefore, the second connection region 342 and the third connection region 343 sandwich the first connection region 341 therebetween.

[0053] The source pad 332 has a source pad 332A and a source pad 332B. The source pads 332A and 332B are spaced apart from each other in the X1-X2 direction. The source pad 332A is on the X1 side of the source pad 332B. A first connection region 341, a second connection region 342, and a third connection region 343 span the source pads 332A and 332B. The second connection region 342 has a first internal connection region 351 in the source pad 332A and a second internal connection region 352 in the source pad 332B. The second internal connection region 352 is spaced apart from the first internal connection region 351. The source pad 332 has a gap 353 between the first internal connection region 351 and the second internal connection region 352. The first internal connection region 351 is on the X1 side of the second internal connection region 352. The source pad 332 is an example of a first pad.

[0054] The gate wiring 334 is provided between the source pad 332A and the source pad 332B, and extends in the Y1-Y2 direction. The gate wiring 334 is connected to the gate pad 231. The gate wiring 334 is provided in the gap 353.

[0055] The other configurations of the transistor 300 are the same as those of the transistor 200 .

[0056] The semiconductor device 2 further includes a sixth bonding wire 166. Within the transistor 200, the first internal connection region 351 and the second internal connection region 352 are connected by the sixth bonding wire 166. The sixth bonding wire 166 is an example of a fourth connecting member.

[0057] Other configurations of the second embodiment are the same as those of the first embodiment.

[0058] The second embodiment also provides the same effects as the first embodiment. Furthermore, since the first internal connection region 351 and the second internal connection region 352 are connected by the sixth bonding wire 166, it is easy to suppress the potential difference within the second connection region 342. Furthermore, since there is a gap 353 between the first internal connection region 351 and the second internal connection region 352, it is possible to arrange the gate wiring 334 between the first internal connection region 351 and the second internal connection region 352.

[0059] The second bonding wire 162 and the sixth bonding wire 166 may be integrated. For example, the second bonding wire 162 and the sixth bonding wire 166 may be formed by stitch bonding. In this case, the frequency of cutting the bonding wires when forming the second bonding wire 162 and the sixth bonding wire 166 can be reduced, and damage to the transistor 300 that may be caused by the cutting can be suppressed.

[0060] Third Embodiment Next, a third embodiment will be described. The third embodiment differs from the second embodiment mainly in the configuration of the transistors. Fig. 5 is a top view showing a semiconductor device according to the third embodiment.

[0061] 5 , the semiconductor device 3 according to the third embodiment has a transistor 400 instead of the transistor 300. The transistor 400 has a gate pad 231, a source pad 432, a drain electrode 233, and a gate wiring (gate runner) 434. The gate pad 231, the gate wiring 434, and the source pad 432 are provided on the upper surface (surface on the Z1 side) of the semiconductor device 1, and the drain electrode 233 is provided on the lower surface (surface on the Z2 side) of the semiconductor device 1.

[0062] The source pad 432 has a first connection region 441, a second connection region 442, and a third connection region 443. The first connection region 441 is on the Y2 side of the second connection region 442, and the third connection region 443 is on the Y2 side of the first connection region 441. Therefore, the second connection region 442 and the third connection region 443 sandwich the first connection region 441 therebetween.

[0063] The source pad 432 includes a source pad 432A, a source pad 432B, and a conductive region 432C. The source pads 432A and 432B are spaced apart in the X1-X2 direction. The source pad 432A is located on the X1 side of the source pad 432B. The first connection region 441, the second connection region 442, and the third connection region 443 span the source pads 332A and 332B. The conductive region 432C is connected to the corner of the source pad 432A on the X2 and Y2 sides and the corner of the source pad 432B on the X1 and Y2 sides, and electrically connects the source pads 432A and 432B to each other. The conductive region 432C is included in the third connection region 443. The second connection region 442 includes a first internal connection region 451 in the source pad 432A and a second internal connection region 452 in the source pad 432B. The second internal connection region 452 is spaced apart from the first internal connection region 451. The source pad 432 has a gap 453 between the first internal connection region 451 and the second internal connection region 452. The first internal connection region 451 is on the X1 side of the second internal connection region 452. The source pad 432 is an example of a first pad.

[0064] The gate wiring 434 is provided between the source pad 432A and the source pad 432B, and extends in the Y1-Y2 direction. The gate wiring 434 is connected to the gate pad 231. The Y2-side end of the gate wiring 434 is near the conductive region 432C, but is separated from the conductive region 432C. The gate wiring 434 is provided in the gap 453.

[0065] Other configurations of the transistor 400 are the same as those of the transistor 300. Other configurations of the third embodiment are the same as those of the second embodiment.

[0066] The third embodiment also provides the same effects as the first embodiment. Furthermore, since the first internal connection region 451 and the second internal connection region 452 are connected by the sixth bonding wire 166, it is easy to suppress the potential difference within the second connection region 442. Furthermore, since there is a gap 453 between the first internal connection region 451 and the second internal connection region 452, the gate wiring 434 can be disposed between the first internal connection region 451 and the second internal connection region 452.

[0067] Fourth Embodiment Next, a fourth embodiment will be described. The fourth embodiment differs from the first embodiment mainly in that a diode is provided. Fig. 6 is a top view showing a semiconductor device according to the fourth embodiment.

[0068] 6 , the semiconductor device 4 according to the fourth embodiment includes a plurality of diodes 500 in addition to a plurality of transistors 200. The number of diodes 500 is not limited, and is four in one example. The semiconductor device 4 further includes a seventh bonding wire 167.

[0069] The diode 500 is a Schottky barrier diode and includes an anode pad 532 and a cathode electrode (not shown). The anode pad 532 is provided on the upper surface (surface on the Z1 side) of the diode 500, and the cathode electrode is provided on the lower surface (surface on the Z2 side) of the diode 500.

[0070] The diodes 500 are provided on the second conductive layer 12. The diodes 500 are lined up along the X1-X2 direction. The diodes 500 are on the X1 side of the transistor 200. The anode pads 532 of the diodes 500 are connected to the first conductive layer 11 by a plurality of seventh bonding wires 167. The cathode electrodes of the diodes 500 are bonded to the second conductive layer 12 by a third bonding material (not shown). The material of the third bonding material is, for example, a solder such as a lead-free solder containing tin (Sn).

[0071] Other configurations of the fourth embodiment are the same as those of the first embodiment.

[0072] The fourth embodiment also provides the same effects as the first embodiment. Furthermore, the diode 500 can be used as a freewheeling diode. If the diode 500 is a silicon carbide diode including a silicon carbide substrate, a high breakdown voltage can be easily achieved.

[0073] Fifth Embodiment Next, a fifth embodiment will be described. The fifth embodiment differs from the first embodiment mainly in the configuration of the insulating substrate. Fig. 7 is a top view showing a semiconductor device according to the fifth embodiment.

[0074] As shown in FIG. 7, the semiconductor device 5 according to the fifth embodiment has insulating substrates 623 and 624 instead of the insulating substrate 123 .

[0075] Inside the housing 122, insulating substrates 623 and 624 are arranged on the Z1 side of the heat sink 121. The insulating substrate 623 is on the X1 side of the insulating substrate 624. A first conductive layer 11, a second conductive layer 12, a third conductive layer 13, and a fourth conductive layer 14 are provided on the Z1 side surface of the insulating substrate 623 and the Z1 side surface of the insulating substrate 624. A fifth conductive layer 15 is provided on the Z2 side surface of the insulating substrate 623 and the Z2 side surface of the insulating substrate 624. The insulating substrates 623 and 624 are made of materials such as silicon nitride (SiN), aluminum oxide (Al ２ O ３ ) or aluminum nitride (AlN).

[0076] Four transistors 200 are provided on the second conductive layer 12 on the insulating substrate 623, and the other four transistors 200 are provided on the second conductive layer 12 on the insulating substrate 624. The transistors 200 are lined up along the X1-X2 direction.

[0077] The semiconductor device 5 further has an eighth bonding wire 168, a ninth bonding wire 169, a tenth bonding wire 170, and an eleventh bonding wire 171. The first conductive layer 11 on the insulating substrate 623 and the first conductive layer 11 on the insulating substrate 624 are connected by a plurality of eighth bonding wires 168. The second conductive layer 12 on the insulating substrate 623 and the second conductive layer 12 on the insulating substrate 624 are connected by a plurality of ninth bonding wires 169. The third conductive layer 13 on the insulating substrate 623 and the third conductive layer 13 on the insulating substrate 624 are connected by a tenth bonding wire 170. The fourth conductive layer 14 on the insulating substrate 623 and the fourth conductive layer 14 on the insulating substrate 624 are connected by an eleventh bonding wire 171.

[0078] The source terminal 101 is connected to a first conductive layer 11 on the insulating substrate 623, and the drain terminal 102 is connected to a second conductive layer 12 on the insulating substrate 623. The gate terminal 103 is connected to a third conductive layer 13 on the insulating substrate 624, and the sense source terminal 104 is connected to a fourth conductive layer 14 on the insulating substrate 624.

[0079] Other configurations of the fifth embodiment are the same as those of the first embodiment.

[0080] The fifth embodiment also provides the same effects as the first embodiment. In addition, heat transfer between the transistor 200 mounted on the insulating substrate 623 and the transistor 200 mounted on the insulating substrate 624 is suppressed.

[0081] In the present disclosure, the second and third connection members are not limited to bonding wires, but may be copper clips or ribbons, etc.

[0082] Sixth Embodiment Next, a sixth embodiment will be described. Fig. 8 is a top view showing a semiconductor device according to the sixth embodiment. Fig. 9 is a cross-sectional view showing the semiconductor device according to the sixth embodiment. Fig. 9 corresponds to a cross-sectional view taken along line IX-IX in Fig. 8.

[0083] 8 and 9, the semiconductor device 6 according to the sixth embodiment includes a transistor 710, a sealing material 720, a first source terminal 731, a second source terminal 732, a third source terminal 733, a gate terminal 740, a drain terminal 750, and a die pad 760. In Fig. 8, the sealing material 720 is seen through.

[0084] The semiconductor device 6 further has a first bonding wire 781, a second bonding wire 782, a third bonding wire 783, and a fourth bonding wire 784. The first bonding wire 781, the second bonding wire 782, the third bonding wire 783, and the fourth bonding wire 784 are, for example, aluminum (Al) wires.

[0085] The transistor 710 is a field-effect transistor and includes a silicon carbide substrate 711, a gate pad 771, a source pad 772, and a drain electrode 773. The gate pad 771 and the source pad 772 are provided on the upper surface (surface on the Z1 side) of the transistor 710, and the drain electrode 773 is provided on the lower surface (surface on the Z2 side) of the transistor 710. The source pad 772 is an example of a first pad.

[0086] The drain terminal 750 is formed integrally with the die pad 760 and extends from the die pad 760 to the Y2 side. The first source terminal 731 is on the X1 side of the drain terminal 750 and extends parallel to the drain terminal 750. The gate terminal 740 is on the X2 side of the drain terminal 750 and extends parallel to the drain terminal 750. The second source terminal 732 is on the X1 side of the die pad 760 and away from the die pad 760, extending along the X1-X2 direction. The third source terminal 733 is on the X2 side of the die pad 760 and away from the die pad 760, extending along the X1-X2 direction.

[0087] The transistor 710 is provided on a die pad 760. A drain electrode 773 of the transistor 710 is bonded to the die pad 760 by a bonding material 790. The material of the bonding material 790 is, for example, a solder such as a lead-free solder containing tin (Sn). A source pad 772 of the transistor 710 is connected to a first source terminal 731 by a plurality of first bonding wires 781. The source pad 772 of the transistor 710 is also connected to a second source terminal 732 by a second bonding wire 782. The source pad 772 of the transistor 710 is also connected to a third source terminal 733 by a third bonding wire 783. A gate pad 771 of the transistor 710 is connected to a gate terminal 740 by a fourth bonding wire 784. The first source terminal 731 is an example of a first terminal, the second source terminal 732 is an example of a second terminal, and the third source terminal 733 is an example of a third terminal. Moreover, the first bonding wire 781 is an example of a first wire, the second bonding wire 782 is an example of a second wire, and the third bonding wire 783 is an example of a third wire.

[0088] The encapsulant 720 encapsulates the transistor 710. The encapsulant 720 also encapsulates a first bonding wire 781, a second bonding wire 782, a third bonding wire 783, and a fourth bonding wire 784. The encapsulant 720 also encapsulates a connection portion of the first source terminal 731 with the first bonding wire 781, a connection portion of the second source terminal 732 with the second bonding wire 782, and a connection portion of the third source terminal 733 with the third bonding wire 783. The encapsulant 720 also encapsulates a connection portion of the gate terminal 740 with the fourth bonding wire 784.

[0089] The first source terminal 731, the gate terminal 740, and the drain terminal 750 extend from the sealing material 720 to the Y2 side. The second source terminal 732 extends from the sealing material 720 to the X1 side. The third source terminal 733 extends from the sealing material 720 to the X2 side. The direction in which the first source terminal 731, the gate terminal 740, and the drain terminal 750 extend is an example of a first direction. The direction in which the second source terminal 732 extends is an example of a second direction.

[0090] Here, a method of using the semiconductor device 6 according to the sixth embodiment will be described below. Figure 10 is a diagram showing a method of using the semiconductor device 6 according to the sixth embodiment.

[0091] 10 , a plurality of semiconductor devices 6 are used. The plurality of semiconductor devices 6 are connected in parallel to one another. Furthermore, the second source terminal 732 and the third source terminal 733 are connected between two of the plurality of semiconductor devices 6. For example, the second source terminal 732 and the third source terminal 733 are connected to one another by welding, soldering, or screwing.

[0092] In this way, even when discrete semiconductor devices 6 are used, it is possible to suppress variations in the potential of the source pad 772 among a plurality of semiconductor devices 6, thereby suppressing oscillation, thereby improving the stability of parallel operation among a plurality of transistors 710.

[0093] Furthermore, by using the first bonding wire 781, the second bonding wire 782, and the third bonding wire 783, the source pad 772 can be easily connected to the first source terminal 731, the second source terminal 732, and the third source terminal 733.

[0094] When the transistor 710 is a silicon carbide transistor including the silicon carbide substrate 711, a high breakdown voltage can be easily achieved.

[0095] The transistors 200, 300, 400, and 710 do not necessarily have to be field-effect transistors, but may be, for example, insulated gate bipolar transistors (IGBTs). In this case, the emitter pad is used as the first pad. The IGBT may be a silicon carbide IGBT.

[0096] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0097] 1, 2, 3, 4, 5, 6: Semiconductor device 11: First conductive layer (conductive member) 12: Second conductive layer 13: Third conductive layer 14: Fourth conductive layer 15: Fifth conductive layer 101: Source terminal 102: Drain terminal 103: Gate terminal 104: Sense source terminal 121: Heat sink 122: Housing 123, 623, 624: Insulating substrate 131: First bonding material 132: Second bonding material 161: First bonding wire (first connecting member) 162: Second bonding wire (second connecting member) 163: Third bonding wire (third connecting member) 164: Fourth bonding wire (fifth connecting member) 165: Fifth bonding wire 166: Sixth bonding wire (fourth connecting member) 167: Seventh bonding wire 168: Eighth bonding wire 169: ninth bonding wire 170: tenth bonding wire 171: eleventh bonding wire 191, 192: side wall portion 193, 194: end wall portion 200, 300, 400: transistor 210: silicon carbide substrate 210A: main surface 210B: main surface 211: silicon carbide single crystal substrate 212: silicon carbide epitaxial layer 231: gate pad 232, 332, 332A, 332B, 432, 432A, 432B: source pad (first pad) 233: drain electrode 234, 334, 434: gate wiring 241, 341, 441: first connection region 242, 342, 442: second connection region 243, 343, 443: third connection region 351, 451: First internal connection region 352, 452: Second internal connection region 353, 453: Gap 432C: Conduction region 500: Diode 532: Anode pad 710: Transistor 711: Silicon carbide substrate 720: Sealing material 731: First source terminal 732: Second source terminal 733: Third source terminal 740: Gate terminal 750: Drain terminal 760: Die pad 771: Gate pad 772: Source pad (first pad) 773: Drain electrode 781: First bonding wire (first wire) 782: Second bonding wire (second wire) 783: Third bonding wire (third wire) 784: Fourth bonding wire 790: Bonding material I: Current

Claims

1. a plurality of transistors electrically connected in parallel with each other and including a first pad; A conductive member; having the first pad is a source pad or an emitter pad; The first pad is A first connection region; a second connection region and a third connection region sandwiching the first connection region therebetween; having a first connection member that connects the first connection region and the conductive member; a second connection member that connects the second connection regions of two of the plurality of transistors; a third connection member that connects the third connection regions of the two transistors among the plurality of transistors; A semiconductor device having the above structure.

2. The second connection region is A first interconnect region; a second interconnect region spaced from the first interconnect region; having 2. The semiconductor device according to claim 1, further comprising a fourth connection member connecting said first internal connection region and said second internal connection region.

3. The semiconductor device according to claim 2 , wherein the second connection member and the fourth connection member are integral with each other.

4. 4. The semiconductor device according to claim 2, wherein the first pad has a gap between the first internal connection region and the second internal connection region.

5. An insulating substrate is provided.

4. The semiconductor device according to claim 1, wherein the plurality of transistors are mounted on the insulating substrate.

6. A plurality of insulating substrates are provided. A part of the plurality of transistors is mounted on each of the insulating substrates; 4. A semiconductor device according to claim 1, wherein the second connection regions are connected to each other by the second connection member, and the third connection regions are connected to each other by the third connection member between the two transistors mounted on different insulating substrates.

7. 4 . The semiconductor device according to claim 1 , wherein a cross-sectional area perpendicular to a longitudinal direction of the second connection member and the third connection member is equal to a cross-sectional area perpendicular to the longitudinal direction of the first connection member.

8. the transistor has a gate pad; a fifth connection member connected to the gate pad; 4 . The semiconductor device according to claim 1 , wherein cross-sectional areas of the second connection member and the third connection member perpendicular to the longitudinal direction are equal to a cross-sectional area of ​​the fifth connection member perpendicular to the longitudinal direction.

9. 4. The semiconductor device according to claim 1, further comprising a diode electrically connected in parallel to the plurality of transistors.

10. The semiconductor device according to claim 9 , wherein the diode is a silicon carbide diode.

11. The semiconductor device according to claim 1 , wherein the transistor is a silicon carbide transistor.

12. 4. The semiconductor device according to claim 1, wherein the first connection region, the second connection region, and the third connection region are spaced apart from each other when viewed in a direction perpendicular to a surface on which the first pad of the transistor is provided.

13. a transistor including a first pad; a sealing material for sealing the transistor; a first terminal connected to the first pad and extending from the sealing material in a first direction; a second terminal connected to the first pad and extending from the sealing material in a second direction different from the first direction; having The first pad is a source pad or an emitter pad.

14. a first wire connecting the first pad and the first terminal; a second wire connecting the first pad and the second terminal; The semiconductor device according to claim 13 , comprising:

15. 15. The semiconductor device according to claim 13, further comprising a third terminal connected to the first pad and extending from the sealing material in a direction opposite to the second terminal.

16. The semiconductor device according to claim 15 , further comprising a third wire connecting the first pad and the third terminal.

17. 15. The semiconductor device according to claim 13, wherein the transistor is a silicon carbide transistor.

18. A first transistor and a second transistor electrically connected in parallel to each other and including a first pad; A conductive member; a first connection member that connects a first connection region of a first pad of the first transistor and the conductive member; another first connection member that connects a first connection region of a first pad of the second transistor and the conductive member; a second connection member that connects a second connection region of the first pad of the first transistor and a second connection region of the first pad of the second transistor; a third connection member that connects a third connection region of the first pad of the first transistor and a third connection region of the first pad of the second transistor; having the first pad is a source pad or an emitter pad; the first connection region of the first pad of the first transistor is between the second connection region of the first pad of the first transistor and the third connection region of the first pad of the first transistor; A semiconductor device, wherein the first connection region of the first pad of the second transistor is located between the second connection region of the first pad of the second transistor and the third connection region of the first pad of the second transistor.