Linear power source device and power source system

Abstract

A linear power source device (1) comprises: a first mirror transistor (M2) that is configured to be able to generate a first mirror current (Im2) of current flowing in an output transistor; a second mirror transistor (M3) that is configured to be able to generate a second mirror current (Im3) of the current that is flowing in the output transistor; a source terminal (Tsr) that is configured to be able to externally output the first mirror current; a sink terminal (Tsk) that is separate from the source terminal and that is configured so as to enable input of a third mirror current; and a comparison unit (CM) that is configured so as to compare the third mirror current and the second mirror current, and, on the basis of the result of the comparison, draw a current from a second node (N2) to which a first feedback resistor and a second feedback resistor are connected, or inject a current into the second node.

Description

Linear Power Supplies and Power Systems

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to linear power supplies and power systems.

[0002] Conventionally, linear power supply devices (linear regulators) capable of generating a desired output voltage from an input voltage have been installed in a variety of applications (such as in-vehicle equipment, industrial equipment, office equipment, digital home appliances, and portable devices).

[0003] Some linear power supplies use two linear power supplies, each with an output terminal connected to a common load, and output voltages from the output terminals of the two linear power supplies (see, for example, Patent Document 1). In other words, these linear power supplies are connected in parallel to the common load. Such linear power supplies are used to dissipate heat by distributing the load current across the output terminals, or to increase the load current based on the output current from each output terminal.

[0004] Japanese Patent Application Laid-Open No. 2020-4214

[0005] However, when linear power supply units are connected in parallel as described above, variations in the linear power supply units may cause differences in the output voltages from their respective output terminals. In this case, the linear power supply unit with the lower output voltage may not output any output current, and the load current may be supplied only by the output current of the linear power supply unit with the higher output voltage. This may render the parallel connection of linear power supply units meaningless.

[0006] In view of the above circumstances, an object of the present disclosure is to provide a linear power supply device that can effectively perform parallel operation in parallel connection applications regardless of variations in the linear power supply devices.

[0007] a first error amplifier configured to receive a feedback voltage generated at a first node where the second feedback resistor and the third feedback resistor are connected and a reference voltage, and to drive a control terminal of the output transistor; an output terminal connected to the second main electrode; a first mirror transistor configured to generate a first mirror current of a current flowing through the output transistor; a second mirror transistor configured to generate a second mirror current of a current flowing through the output transistor; a source terminal configured to output the first mirror current to the outside; a sink terminal configured to receive a third mirror current and separate from the source terminal; and a comparison unit configured to compare the third mirror current with the second mirror current, and to draw current from or inject current into a second node where the first feedback resistor and the second feedback resistor are connected based on a comparison result.

[0008] The linear power supply according to the present disclosure enables effective parallel operation in parallel connection applications regardless of variations in the linear power supply.

[0009] FIG. 1 is a diagram showing the configuration of a power supply system according to a comparative example. FIG. 2 is a diagram showing the configuration of a linear power supply device according to an embodiment of the present disclosure. FIG. 3 is a diagram showing the configuration of a power supply system according to an embodiment of the present disclosure. FIG. 4 is a diagram showing the flow of current in a power supply system according to an embodiment of the present disclosure. FIG. 5 is a diagram showing example waveforms of output current and output voltage. FIG. 6 is a diagram showing the configuration of a power supply system according to a modified example. FIG. 7 is a diagram showing the configuration of a linear power supply device according to a modified example.

[0010] <1. Comparative Example> Before describing the new embodiment of the linear power supply device, a comparative example for comparison therewith will be described.

[0011] 1 is a diagram showing the configuration of a power supply system 50 according to a comparative example. The power supply system 50 includes a linear power supply 10A, a linear power supply 10B, and resistors Ra and Rb. The power supply system 50 supplies a load current Iout to a load RL using the two linear power supplies 10A and 10B.

[0012] Linear power supply units 10A and 10B are linear regulators that step down an input voltage Vin to generate desired output voltages VoA and VoB, respectively. Linear power supply units 10A and 10B are integrated circuits (ICs) with the same configuration, and corresponding components are shown with the same reference numerals followed by the letter "A" or "B." The configuration of linear power supply unit 10A will be described below as a representative example.

[0013] As shown in FIG. 1, the linear power supply device 10A is an IC that includes an output transistor M10A, resistors R11A and R12A, and an error amplifier AP10A, all of which are integrated on a single chip.

[0014] The source of the output transistor M10A, which is configured as a PMOS transistor (P-channel MOSFET (metal-oxide-semiconductor field-effect transistor)), is connected to the input terminal of the input voltage Vin. The drain of the output transistor M10A and a first terminal of a resistor R11A are commonly connected to an output terminal ToA for outputting an output voltage VoA. The second terminal of the resistor R11A is connected to a first terminal of a resistor R12A. The second terminal of the resistor R12A is connected to the ground terminal. The non-inverting input terminal (+) of the error amplifier AP10A is connected to a connection node (= application terminal of a feedback voltage VfbA) where the resistors R11A and R12A are connected. The inverting input terminal (-) of the error amplifier AP10A is connected to an application terminal of a reference voltage VrefA. The output terminal of the error amplifier AP10A is connected to the gate of the output transistor M10A.

[0015] The error amplifier AP10A controls the gate of the output transistor M10A so that a feedback voltage VfbA (=VoA×{R12A / (R11A+R12A)}) corresponding to the output voltage VoA matches a predetermined reference voltage VrefA. That is, the on-resistance value of the output transistor M10A is continuously controlled so that the output voltage VoA matches its target value (=VrefA×{(R11A+R12A) / R12A}).

[0016] Similarly, in the linear power supply device 10B, the on-resistance value of the output transistor M10B is continuously controlled so that the output voltage VoB coincides with its target value.

[0017] The output terminal ToA is connected to a first end of a resistor Ra provided external to the linear power supplies 10A and 10B. The output terminal ToB is connected to a first end of a resistor Rb provided external to the linear power supplies 10A and 10B. The second ends of the resistors Ra and Rb are commonly connected to a load RL. Therefore, the linear power supplies 10A and 10B are connected in parallel to the common load RL.

[0018] Although the standard values ​​(Typ values) of the output voltages VoA and VoB of the linear power supply units 10A and 10B are set to be the same, the output voltages may vary from the standard values ​​due to variations in the linear power supply units. For example, the output voltage may vary by ±2% from the standard value of 5V. Such variations are caused by, for example, variations in the reference voltage, feedback voltage, or threshold voltage of the output transistor, as well as variations in the input offset voltage of the error amplifier.

[0019] In the case of a configuration in which the output terminals ToA and ToB are directly connected, if, for example, output voltage VoA is higher than VoB due to variations, output transistor M10B on the linear power supply 10B side will be kept off, output current IoutB will not be output from output terminal ToB, and load current Iout will be supplied only by output current IoutA output from output terminal ToA of linear power supply 10A. As a result, the output current will be concentrated in one of the linear power supply devices.

[0020] In contrast, in the configuration of this comparative example shown in FIG. 1 , for example, when the output voltage VoA is higher than VoB, as the load current Iout gradually increases from 0 A, the output voltage VoA is dropped by the resistor Ra, and the output voltage Vo generated at the node connected to the second ends of the resistors Ra and Rb gradually drops. Then, when the output voltage Vo reaches the output voltage VoB, the output transistor M10B on the linear power supply 10B side starts operating, and output of the output current IoutB begins from the output terminal ToB. In other words, parallel operation is initiated in which the load current Iout is supplied by both the output currents IoutA and IoutB. The resistors Ra and Rb may be set to resistance values ​​such that the voltage drop across the resistors is equal to or greater than the voltage difference between the maximum and minimum values ​​due to output voltage variations.

[0021] As described above, the configuration of this comparative example allows parallel operation even when two linear power supply units are connected in parallel and there is variation in the output voltage. However, this comparative example has problems such as loss and heat generation due to resistors Ra and Rb, and uneven output currents IoutA and IoutB. Furthermore, when the load current Iout changes, the output voltage Vo changes due to the voltage drop across resistors Ra and Rb, which causes problems with the regulator's function.

[0022] 2. Configuration of Linear Power Supply Device Various embodiments that can solve the above problems will be described below. Figure 2 is a diagram showing the configuration of a linear power supply device 1 according to an embodiment of the present disclosure. The linear power supply device 1 is a linear regulator that steps down an input voltage Vin to generate a desired output voltage Vo.

[0023] 2, the linear power supply 1 is an IC that includes an output transistor M1, mirror transistors M2 and M3, NMOS transistors (N-channel MOSFETs) NM1 and NM2, feedback resistors R1, R2, and R3, an error amplifier AP1, and a voltage protection element MP, all of which are integrated on a single chip. The linear power supply 1 also has external terminals, such as an output terminal To, a source terminal Tsr, and a sink terminal Tsk, for establishing electrical connections with the outside.

[0024] The source of the output transistor M1, which is configured as a PMOS transistor, is connected to the terminal to which the input voltage Vin is applied. The drain of the output transistor M1 is connected to the first terminal of the feedback resistor R1. The second terminal of the feedback resistor R1 is connected to the first terminal of the feedback resistor R2. The second terminal of the feedback resistor R2 is connected to the first terminal of the feedback resistor R3. The second terminal of the feedback resistor R3 is connected to the ground terminal.

[0025] The non-inverting input terminal (+) of the error amplifier AP1 is connected to the connection node (= the terminal to which the feedback voltage Vfb is applied) where the feedback resistors R2 and R3 are connected. The inverting input terminal (-) of the error amplifier AP1 is connected to the terminal to which the reference voltage Vref is applied. The output terminal of the error amplifier AP1 is connected to the gate of the output transistor M1.

[0026] The source of the mirror transistor M2, which is configured as a PMOS transistor, is connected to the application terminal of the input voltage Vin. The drain of the mirror transistor M2 is connected to the drain of the voltage protection element MP, which is configured as an NMOS transistor. The source of the voltage protection element MP is connected to the source terminal Tsr. A predetermined bias voltage Vbs is applied to the gate of the voltage protection element MP. The gate of the mirror transistor M2 is connected to the output terminal of the error amplifier AP1.

[0027] A mirror current Im2 of the current flowing through the output transistor M1 flows through the mirror transistor M2. The mirror current Im2 is, for example, several hundredths or several thousandths of the current flowing through the output transistor M1. The mirror current Im2 flows through the voltage protection element MP and is output to the outside via the source terminal Tsr.

[0028] The current mirror circuit CM has an NMOS transistor NM1 on the input side and an NMOS transistor NM2 on the output side. The drain and gate of the NMOS transistor NM1 are shorted. The drain of the NMOS transistor NM1 is connected to the sink terminal Tsk. The gate of the NMOS transistor NM1 is connected to the gate of the NMOS transistor NM2. The sources of the NMOS transistor NM1 and the NMOS transistor NM2 are commonly connected to the ground terminal.

[0029] The source of the mirror transistor M3 configured as a PMOS transistor is connected to the application terminal of the input voltage Vin, the drain of the mirror transistor M3 is connected to the drain of the NMOS transistor NM2, and the gate of the mirror transistor M3 is connected to the output terminal of the error amplifier AP1.

[0030] A mirror current Im3 of the current flowing through the output transistor M1 flows through the mirror transistor M3. The mirror current Im3 is, for example, several hundredths or several thousandths of the current flowing through the output transistor M1. The mirror current Im3 flows into the node N1 at which the mirror transistor M3 and the NMOS transistor NM2 are connected.

[0031] The current Icm mirrored and output by the current mirror circuit CM is compared with the mirror current Im3 at node N1. If the current Icm is greater than the mirror current Im3, current is extracted from node N2, where feedback resistors R1 and R2 are connected, toward node N1. On the other hand, if the current Icm is smaller than the mirror current Im3, current is injected into node N2. The feedback voltage Vfb is adjusted in response to the extraction / injection of current into node N2, thereby controlling the output voltage Vo.

[0032] 3 is a diagram showing the configuration of a power supply system 5 configured using a linear power supply 1 according to an embodiment of the present disclosure. The power supply system 5 includes a linear power supply 1A and a linear power supply 1B. The power supply system 5 supplies a load current Iout to a load RL using the two linear power supplies 1A and 1B.

[0033] Linear power supply 1A and linear power supply 1B are linear power supply 1 (power supply IC) with the same configuration as described in FIG. 2, and in FIG. 3, corresponding components are shown with the same reference numerals followed by "A" or "B."

[0034] An output terminal ToA of the linear power supply 1A and an output terminal ToB of the linear power supply 1B are commonly connected to a load RL, that is, the linear power supplies 1A and 1B are connected in parallel to the common load RL.

[0035] The source terminal TsrA of the linear power supply 1A and the sink terminal TskB of the linear power supply 1B are connected for transmitting and receiving the mirror current. The source terminal TsrA and the sink terminal TskB are connected via a resistor R10. The resistor R10 receives the voltage difference between the source of the voltage protection element MPA and the drain of the NMOS transistor NM1B and limits the current. The voltage protection element MPA allows the NMOS transistor NM1B to be configured as a low-voltage element.

[0036] The source terminal TsrB of the linear power supply 1B is connected to the sink terminal TskA of the linear power supply 1A for transmitting and receiving the mirror current. The source terminal TsrB and sink terminal TskA are connected via a resistor R20. The resistor R20 receives the voltage difference between the source of the voltage protection element MPB and the drain of the NMOS transistor NM1A and limits the current. The voltage protection element MPB allows the NMOS transistor NM1A to be configured as a low-voltage element.

[0037] Next, the operation of power supply system 5 will be described with reference to Figures 4 and 5. Figure 5 is a waveform diagram showing an example of the operation of power supply system 5 at startup. Here, due to variations in linear power supply devices 1, it is assumed that the output voltage VoA of linear power supply device 1A when used alone is higher than the output voltage VoB of linear power supply device 1B when used alone (VoA and VoB shown in Figure 5).

[0038] 5, even if the load current Iout starts to flow from 0 A, the output current IoutB is not initially output from the output terminal ToB of the linear power supply 1B, and the load current Iout is supplied only by the output current IoutA output from the output terminal ToA of the linear power supply 1A. The sum of the output current IoutA and the output current IoutB is the load current Iout.

[0039] 4, in linear power supply device 1A, mirror current Im2A is output from source terminal TsrA by mirror transistor M2A to the outside. Meanwhile, in linear power supply device 1B, mirror current Im2A flows from the outside into NMOS transistor NM1B via sink terminal TskB.

[0040] The mirror current Im2A flowing through the input-side NMOS transistor NM1B is mirrored by the current mirror circuit CMB to become the current IcmB flowing through the output-side NMOS transistor NM2B. Here, since the mirror current Im3B by the mirror transistor M3B does not flow, the differential current In2B is drawn from node N2B to node N1B. Therefore, the feedback voltage VfbB is adjusted, and the output voltage VoB increases.

[0041] On the other hand, in linear power supply 1B, mirror current Im2B does not flow through mirror transistor M2B, so the current flowing through sink terminal TskA in linear power supply 1A is zero. Because mirror current Im3A flows through mirror transistor M3A, differential current In2A is injected from node N1A to node N2B. Therefore, feedback voltage VfbA is adjusted, and output voltage VoA decreases. The decrease in output voltage VoA appears as a decrease in output voltage Vo of power supply system 5 (Vo in FIG. 5 ).

[0042] As the load current Iout increases, and the output current IoutA and therefore the mirror current Im3A increase, the differential current In2A increases and the output voltage VoA decreases. When the output voltage VoA reaches VoB, the output current IoutB begins to be output from the output terminal ToB of the linear power supply 1B (timing t1 in FIG. 5). In other words, parallel operation of the linear power supplies 1A and 1B begins.

[0043] When the output current IoutB starts to flow, the mirror current Im3B also starts to flow, and the differential current In2B is extracted or injected depending on the magnitude relationship between the current IcmB and the mirror current Im3B. Therefore, the feedback voltage VfbB is adjusted, and the output current IoutB is controlled to approach IoutA. Meanwhile, when the output current IoutB starts to flow, the mirror current Im2B also starts to flow. Therefore, the mirror current Im2B flows from the source terminal TsrB to the sink terminal TskA and is mirrored by the current mirror CMA to become the current IcmA. Depending on the magnitude relationship between the current IcmA and the mirror current Im3A, the differential current In2A is extracted or injected. Therefore, the feedback voltage VfbA is adjusted, and the output current IoutA is controlled to approach IoutB.

[0044] This allows parallel operation even when there is a variation in output voltage between the linear power supply units 1A and 1B, making the output currents closer to equal. It also makes it possible to suppress changes in output voltage in response to changes in load current. Furthermore, there is no need for resistors to drop the voltage, as in the comparative example mentioned above, making it possible to suppress loss and heat generation. Furthermore, these effects can be achieved with linear power supply units of the same model number.

[0045] 6 is a diagram showing another example of the configuration of a power supply system 5 according to an embodiment of the present disclosure. In the embodiment shown in Fig. 3 described above, two linear power supplies 1 are connected in parallel to the load RL, but as shown in Fig. 6, three linear power supplies 1 (1A, 1B, 1C) may be connected in parallel to the load RL.

[0046] 6, the source terminal TsrA of linear power supply 1A is connected to the sink terminal TskB of linear power supply 1B, the source terminal TsrB of linear power supply 1B is connected to the sink terminal TskC of linear power supply 1C, and the source terminal TsrC of linear power supply 1C is connected to the sink terminal TskA of linear power supply 1A. This configuration enables the three linear power supply 1 to operate in parallel, and the output currents IoutA, IoutB, and IoutC of each can be made nearly equal.

[0047] Similarly to the above, the power supply system 5 can be configured by connecting four or more linear power supply devices 1 in parallel to the load RL.

[0048] 7 is a diagram showing the configuration of a linear power supply 1 according to a modified example. The configuration shown in Fig. 7 differs from the configuration shown in Fig. 2 in that a circuit including an error amplifier AP2 is used as a comparison unit for comparing mirror currents instead of the current mirror circuit CM.

[0049] The linear power supply 1 shown in FIG. 7 has an error amplifier AP2 and sense resistors Rs1 and Rs2. The sink terminal Tsk is connected to a first terminal of the sense resistor Rs1. The second terminal of the sense resistor Rs1 is connected to the ground terminal. The drain of the mirror transistor M3A is connected to a first terminal of the sense resistor Rs2. The second terminal of the sense resistor Rs2 is connected to the ground terminal. The inverting input terminal (-) of the error amplifier AP2 is connected to the first terminal of the sense resistor Rs1. The non-inverting input terminal (+) of the error amplifier AP2 is connected to the first terminal of the sense resistor Rs2. The output terminal of the error amplifier AP2 is connected to a node N2.

[0050] A mirror current Im2 flowing from the outside via the sink terminal Tsk is converted to a voltage Vs1 by the sense resistor Rs1. Meanwhile, a mirror current Im3 flowing through the mirror transistor M3 is converted to a voltage Vs2 by the sense resistor Rs2. The error amplifier AP2 extracts and injects a current In2 into the node N2 based on the difference between the input voltages Vs1 and Vs2. This embodiment allows for more accurate control of the output current Iout.

[0051] <6. Others> In addition to the above embodiments, various technical features of the present disclosure can be modified in various ways without departing from the spirit of the technical creation. In other words, the above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention should not be limited to the above embodiments, but should be understood to include all modifications that fall within the meaning and scope of the claims. Furthermore, the above embodiments may be implemented in appropriate combinations as long as there are no contradictions.

[0052] <7. Supplementary Note> As described above, a linear power supply device (1) according to one aspect of the present disclosure includes: an output transistor (M1) having a first main electrode configured to be connectable to an application terminal of an input voltage (Vin), and a second main electrode configured to be connectable to the first feedback resistor of a first feedback resistor (R1), a second feedback resistor (R2), and a third feedback resistor (R3) connected in series; a first error amplifier (AP1) configured to receive a feedback voltage (Vfb) generated at a first node connecting the second feedback resistor and the third feedback resistor, and a reference voltage (Vref), and to drive a control terminal of the output transistor; an output terminal (To) connected to the second main electrode; a first mirror transistor (M2) configured to be able to generate a first mirror current (Im2) of a current flowing in the output transistor; a second mirror transistor (M3) configured to be able to generate a second mirror current (Im3) of a current flowing in the output transistor; and a source terminal (Tsr) configured to be able to output the first mirror current to the outside. The first configuration includes a sink terminal (Tsk) configured to be able to input a third mirror current and separate from the source terminal, and a comparison unit (CM) configured to compare the third mirror current with the second mirror current and, based on the comparison result, draw current from a second node (N2) to which the first feedback resistor and the second feedback resistor are connected, or inject current into the second node (N2) (first configuration).

[0053] In addition, the first configuration may be configured to include a voltage protection element (MP) connected between the first mirror transistor (M2) and the source terminal (Tsr) (second configuration).

[0054] In the second configuration, the voltage protection element (MP) may be configured by an NMOS transistor having a gate to which a bias voltage (Vbs) can be applied (third configuration).

[0055] In any one of the first to third configurations, the comparison section may have a current mirror circuit (CM) that mirrors the third mirror current and outputs the mirrored current (fourth configuration).

[0056] Furthermore, in any of the first to third configurations, the comparison unit may be configured to have: a first sense resistor (Rs1) that performs current / voltage conversion of the third mirror current to a first voltage (Vs1); a second sense resistor (Rs2) that performs current / voltage conversion of the second mirror current to a second voltage (Vs2); and a second error amplifier (AP2) that draws out current from the second node or injects current into the second node based on the difference between the first voltage and the second voltage (fifth configuration).

[0057] Furthermore, a power supply system (5) according to one aspect of the present disclosure includes a plurality of linear power supply devices (1) having any of the above configurations, wherein the output terminal (To) of each of the plurality of linear power supply devices can be commonly connected to a load (RL), and the source terminal (Tsr) and the sink terminal (Tsk) of each of the plurality of linear power supply devices are sequentially connected between different linear power supply devices (sixth configuration).

[0058] In the sixth configuration, the source terminal (Tsr) and the sink terminal (Tsk) may be connected via resistors (R10, R20) (seventh configuration).

[0059] The present disclosure can be used in power supply systems installed in various devices.

[0060] 1 Linear power supply 1A, 1B, 1C Linear power supply 5 Power supply system 10A, 10B Linear power supply 50 Power supply system AP1 Error amplifier AP10A, AP10B Error amplifier AP2 Error amplifier CM Current mirror circuit M1 Output transistor M10A, M10B Output transistor M2, M3 Mirror transistor MP Withstand voltage protection element NM1 NMOS transistor NM2 NMOS transistor R1, R2, R3 Feedback resistor R10 Resistor R11A, R12A Resistor R11B, R12B Resistor R20 Resistor RL Load Ra, Rb Resistor Rs1, Rs2 Sense resistor ToA, ToB Output terminal To Output terminal Tsk Sink terminal Tsr Source terminal

Claims

1. an output transistor having a first main electrode configured to be connectable to an application terminal of an input voltage, and a second main electrode configured to be connectable to the first feedback resistor of a first feedback resistor, a second feedback resistor, and a third feedback resistor that are connected in series; a first error amplifier configured to receive a feedback voltage generated at a first node to which the second feedback resistor and the third feedback resistor are connected and a reference voltage and to drive a control end of the output transistor; an output terminal connected to the second main electrode; a first mirror transistor configured to generate a first mirror current of a current flowing through the output transistor; a second mirror transistor configured to generate a second mirror current of the current flowing through the output transistor; a source terminal configured to be able to output the first mirror current to an outside; a sink terminal configured to receive a third mirror current and separate from the source terminal; a comparison unit configured to compare the third mirror current with the second mirror current and, based on a comparison result, to draw a current from a second node to which the first feedback resistor and the second feedback resistor are connected or to inject a current into the second node; 1. A linear power supply comprising:

2. 2. A linear power supply as claimed in claim 1, further comprising a voltage protection element connected between said first mirror transistor and said source terminal.

3. 3. The linear power supply according to claim 2, wherein the voltage protection element is constituted by an NMOS transistor having a gate to which a bias voltage can be applied.

4. 4. The linear power supply device according to claim 1, wherein the comparison section includes a current mirror circuit that mirrors the third mirror current and outputs the mirrored third mirror current.

5. The comparison unit is a first sense resistor for current / voltage conversion of the third mirror current to a first voltage; a second sense resistor for current / voltage conversion of the second mirror current to a second voltage; a second error amplifier that sinks or injects a current from or to the second node based on a difference between the first voltage and the second voltage; 4. A linear power supply as claimed in claim 1, further comprising:

6. A linear power supply device according to any one of claims 1 to 3, the output terminals of each of the plurality of linear power supplies are commonly connectable to a load; A power supply system, wherein the source terminals and the sink terminals of the plurality of linear power supply devices are sequentially connected between different linear power supply devices.

7. The power supply system according to claim 6 , wherein the source terminal and the sink terminal are connected via a resistor.