Interleaving buck converter with low output ripple and automatic current sharing and control method thereof

Abstract

The invention discloses a low-output-ripple automatic-current-sharing interleaving buck converter and a control method thereof.The converter comprises a main power circuit and an auxiliary compensation circuit, and the main power circuit adopts two interleaving main branches to achieve voltage conversion and energy transmission; automatic current sharing of the circuit is realized through the integrated network switch module and PWM signal control; the auxiliary compensation circuit adopts a current mirror image compensation principle, and adjusts the magnitude of the compensation current by comparing the difference between the output current of the main power circuit and the reference current, so as to effectively suppress the output current ripple; the control method comprises the steps of output voltage monitoring, PI adjustment, duty ratio modulation and a complementary control mechanism, current ripple phase offset is ensured, and the system stability and efficiency are improved. Compared with the prior art, the method has the advantages that the complexity of a control system is reduced, the working efficiency is improved, the current ripples are effectively eliminated, and the method has relatively high practical value and popularization prospect.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a low-output-ripple, automatic-current-sharing interleaved-parallel buck converter and a control method thereof. Background Art

[0002] In recent years, with the continuous development of DC / DC converter technology, higher requirements have been placed on the performance of buck converters. As a common DC step-down converter, buck converters are widely used in power electronic systems. However, in specific application scenarios, such as the renewable energy field, buck converters need to meet requirements such as low ripple and fast response to ensure system stability and efficiency.

[0003] Traditional interleaved parallel technology has significant advantages in the field of buck converters, such as good output ripple suppression, fast dynamic response, high power density, and low device stress. These advantages make interleaved parallel technology an important means to improve buck converter performance. However, traditional interleaved parallel technology has inherent defects in multi-phase current sharing control. Specifically, in order to achieve balanced distribution of multi-phase current, it is usually necessary to introduce complex current sharing control strategies, which not only increases the difficulty of system design but also increases costs.

[0004] Therefore, in the context of pursuing high-performance buck converters, it is particularly important to design a buck converter with low output ripple and automatic current sharing characteristics. This converter not only needs to perform well in output current ripple suppression, but also needs to have automatic current sharing function to reduce the complexity of the control system and save costs. Summary of the Invention

[0005] In view of the deficiencies in the prior art, the present invention provides an interleaved parallel buck converter with low output ripple and automatic current sharing and a control method thereof, which can achieve automatic current sharing and low output ripple, has high working efficiency, and saves control circuit costs.

[0006] To achieve the above object, the technical solution provided by the present invention is:

[0007] A low output ripple, automatic current-sharing interleaved parallel buck converter includes a main power circuit and an auxiliary compensation circuit, and is characterized by:

[0008] The main power circuit is composed of a first main branch and a second main branch connected in parallel, and is used to convert the input voltage into the required output voltage and transmit current;

[0009] The auxiliary compensation circuit adopts the current mirror compensation principle to construct a closed-loop control system to suppress the output current ripple;

[0010] The main power circuit and the auxiliary compensation circuit are connected in parallel. The parallel main power circuit and the auxiliary compensation circuit work together to not only improve the voltage conversion efficiency and energy transmission capability of the converter, but also significantly enhance the stability and reliability of the system.

[0011] To optimize the above technical solutions, specific measures taken also include:

[0012] The first main branch and the second main branch are controlled and modulated by staggered PWM with a phase difference of 180° to achieve staggered parallel connection, and the two-phase inductor current ripple peaks of the first main branch and the second main branch are complementary and superimposed on the time axis.

[0013] When the inductor current of one phase is in the rising stage, the inductor current of the other phase is in the falling stage, and the two cancel each other out, thereby reducing the total ripple of the output current.

[0014] The first main branch and the second main branch integrate a network switch module composed of two switch tubes and a non-polar capacitor.

[0015] Furthermore, the network switch module realizes dynamic conduction state switching through PWM signal control, so that the converter can automatically share the current.

[0016] The first main branch is composed of a first switch tube S1 and a first anti-parallel diode S1a connected in parallel, a first inductor L1 connected between the output end of the first switch tube S1 and the non-polar capacitor C1 and the load, a first synchronous freewheeling switch tube S3 connected between the first inductor L1 and the load, and a non-polar capacitor C1 connected in parallel across the load, together forming a standard buck topology structure for reducing the input voltage to the required output.

[0017] The second switch tube S2 and the second anti-parallel diode S2a are connected in parallel, the second inductor L2 is connected between the output end of the second switch tube S2 and the non-polar capacitor C1 and the load, the second synchronous freewheeling switch tube S4 is connected between the second inductor L2 and the load, and shares the non-polar capacitor C1 with the first main branch, forming a symmetrical structure with the first main branch to achieve voltage conversion and energy transmission.

[0018] The auxiliary compensation circuit includes a third switch tube S5, a third inductor LS and a DC blocking capacitor CS connected in series in sequence; further, the auxiliary compensation circuit also includes a third synchronous freewheeling switch tube S6, and the third synchronous freewheeling switch tube S6 is arranged between the third switch tube S5 and the first synchronous freewheeling switch tube S3 and the second synchronous freewheeling switch tube S4 connected in parallel with each other.

[0019] Furthermore, the auxiliary compensation circuit drives the switch tube of the network switch module by comparing the difference between the output current of the main power circuit and the reference current, and adjusts the size of the compensation current with a specific duty cycle to achieve active compensation of the ripple amplitude.

[0020] Furthermore, a multivariable state space description is established through the switching mode analysis method. Its state vector is composed of the continuous state quantities of the system. This modeling method strictly follows the principle of energy conservation and accurately characterizes the dynamic response characteristics of the converter near the steady-state operating point through the state continuity constraint equation during the topology switching process. Through mathematical modeling, we can finally obtain:

[0021]

[0022] Among them, including the first main branch duty cycle D1, the second main branch duty cycle D2, the capacitor parameter Co, the capacitor voltage iCo, R is the resistance of the entire circuit, L is the inductance of the entire circuit, N is the number of phases of the converter, the first inductor current iL1, the second inductor current iL2, is defined as the Laplace transform constant of the inductor current, The definition of is the Laplace transform constant of the output filter capacitor voltage, The definition of is the Laplace transform constant of the input voltage and the Laplace transform constant of the output voltage, is defined as the Laplace transform constant of the output voltage, is defined as the Laplace transform constant of the input voltage, The definition of is the change of input voltage over time, The definition of is the time differential of the first branch input voltage, The definition of is the change of the current of the second inductor L2 over time, The definition of is the change of the current of the first inductor L1 over time, The definition of is the time differential of the second branch input voltage, The definition of is the change of output voltage over time, The definition of is the change of the voltage of capacitor C0 over time, The definition of is the change of the current of capacitor C0 over time, RL1, RL2, RL are the parasitic resistances of the first inductor L1, the second inductor L2, and the third inductor Ls respectively, and s is the Laplace transform constant of the entire circuit;

[0023] After performing Laplace transform on the above formula, the complex frequency domain model is obtained:

[0024]

[0025] From the above, we can get the transfer function G of the converter Vd (s) is:

[0026]

[0027] Furthermore, the transfer function G Vd The dynamic response characteristics of the converter near the steady-state operating point can be accurately characterized. Based on the dynamic response characteristics of the converter, the parameters of the PI regulator and other control mechanisms can be adjusted and optimized to improve the response speed and regulation accuracy of the system. At the same time, the optimized control method can reduce the switching tube loss and conduction loss of the converter, thereby improving the overall efficiency of the system.

[0028] A control method for an interleaved parallel buck converter with low output ripple and automatic current sharing comprises the following steps:

[0029] Step S1, first continuously monitor the output voltage Vout at the load end of the interleaved parallel buck converter; compare and analyze the monitored output voltage Vout with a preset reference value Vref; through the comparison and analysis, generate an error vector, the error vector reflecting the difference between the current output voltage and the expected output voltage;

[0030] In step S2, the generated error vector is sent to the PI regulator for processing. The PI regulator is a linear controller. The PI regulator forms a control deviation based on a preset reference value and the actual output voltage value, and forms a control quantity through a linear combination of the proportion and integral of the control deviation to control the controlled object. The PI regulator performs steady-state accuracy compensation on the error vector through proportional and integral operations. The adjusted control quantity is input to the limiting module, which imposes upper and lower limit constraints on the output value. When the output value exceeds the upper limit, the output is limited to the upper limit value; when the output value is lower than the lower limit, the output is limited to the lower limit value; when the output value is between the upper and lower limits, the original output is maintained.

[0031] Step S3: After the amplitude is adjusted, the control variable is duty cycle modulated with a sawtooth carrier wave having the same amplitude-frequency characteristics as the first and second main branches and strictly opposite phases. The purpose of this step is to convert the continuous control signal into a discrete switching signal to drive the power switch tube.

[0032] The first anti-parallel diode S1a and the second anti-parallel diode S2a use the same-phase drive pulse as the first switch S1 and the second switch S2. The driving logic of the first synchronous freewheeling switch S3 and the second synchronous freewheeling switch S4 forms a complementary relationship with the first switch S1 and the second switch S2. That is, the first synchronous freewheeling switch S3 and the second synchronous freewheeling switch S4 are 180° out of phase with the first switch S1 and the second switch S2. This complementary relationship ensures that the current can flow continuously when the power switch is switched, avoiding current interruption and voltage spikes.

[0033] In step S4, the staggered parallel structure of the topology is used. When the current ripple of the main power circuit is in the negative change phase, the third switch tube S5 is turned on and the third synchronous freewheeling switch tube S6 is locked. When the current ripple enters the positive change phase, the third synchronous freewheeling switch tube S6 is turned on and the third switch tube S5 is locked. The current amplitudes in the two phases are the same, and the phase complementarity realizes the phase cancellation effect of the current ripple of the main power circuit and the auxiliary compensation circuit.

[0034] The main power circuit architecture of this converter can be viewed as an improvement on the traditional two-phase interleaved parallel buck topology. By adding a non-polar capacitor C1, a first anti-parallel diode S1a, and a second anti-parallel diode S2a, and controlling the network switch module using a PWM signal, automatic current sharing in the main power circuit is achieved. This innovation effectively eliminates the circulating current problem in the traditional parallel structure, reduces the complexity of the control system, and improves the operating efficiency of the converter.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] The present invention naturally achieves current balancing in each parallel branch without adopting additional current balancing control, thereby reducing the complexity of the control system and reducing costs; by optimizing the circuit design, the present invention reduces the switching frequency, thereby improving the overall working efficiency; through the design of the auxiliary compensation circuit, the present invention effectively eliminates current ripple, realizes low output ripple, and realizes the functions of automatic current balancing. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a circuit topology diagram of the present invention.

[0038] Figure 2 It is the equivalent circuit diagram of the present invention.

[0039] Figure 3 This is the overall control block diagram of the main power circuit of the present invention.

[0040] Figure 4 This is the control block diagram of the auxiliary compensation circuit of the present invention.

[0041] Figure 5 This is the overall waveform diagram of the main power branch inductor currents iL1 and iL2 of the present invention.

[0042] Figure 6 This is an amplified waveform diagram of the main power branch inductor currents iL1 and iL2 of the present invention.

[0043] Figure 7 It is the composite current ia of the main power circuit of the present invention.

[0044] Figure 8 This is the waveform diagram of the current ib of the auxiliary compensation circuit of the present invention.

[0045] Figure 9 This is the waveform diagram of the total output current io of the present invention.

[0046] Figure 10 This is a comparison diagram of the output current sharing characteristics of the present invention. DETAILED DESCRIPTION

[0047] The above contents of the present invention are further described in detail below in the form of specific implementation methods, but this should not be understood as the scope of the above subject matter of the present invention being limited to the following embodiments. All technologies implemented based on the above contents of the present invention belong to the scope of the present invention.

[0048] The present invention provides a low-output-ripple, automatic-current-sharing interleaved-parallel buck converter and a control method thereof.

[0049] In some instances, such as Figure 1 and Figure 2 As shown, the main power circuit includes a first switch S1, a second switch S2, a third switch S5, a first antiparallel diode S1a, a second antiparallel diode S2a, a first synchronous freewheeling switch S3, a second synchronous freewheeling switch S4, a third synchronous freewheeling switch S6, a first inductor L1, a second inductor L2, a third inductor LS, a non-polar capacitor C1, a DC blocking capacitor CS, and a load capacitor Co. This circuit adopts a dual-main-branch architecture, wherein the first main branch comprises the first switch S1, the first antiparallel diode S1a, the first synchronous freewheeling switch S3, the first inductor L1, and the non-polar capacitor C1, forming a standard buck topology. The second main branch comprises the first main branch comprising the second switch S2, the second antiparallel diode S2a, the second synchronous freewheeling switch S4, the second inductor L2, and the non-polar capacitor C1, forming a symmetrical structure. The auxiliary compensation circuit comprises the third switch S5, the third synchronous freewheeling switch S6, the third inductor LS, and the DC blocking capacitor CS.

[0050] The first switch tube S1, the second switch tube S2 and the third switch tube S5 are used to control the on and off of the current to realize the switching function of the circuit; the first switch tube S1 and the second switch tube S2 respectively control the on and off of the two main branches, while the third switch tube S5 controls the on and off of the auxiliary branch; the first synchronous freewheeling switch tube S3, the second synchronous freewheeling switch tube S4 and the third synchronous freewheeling switch tube S6 provide a freewheeling path when the corresponding main switch tube or auxiliary switch tube is disconnected to maintain the continuous flow of current; the first inductor L1, the second inductor L2 and the third inductor LS are used to store magnetic field energy and pass the inductor The output current is smoothed by current changes to reduce ripple; the first inductor L1 and the second inductor L2 are located in the two main branches respectively, while the third inductor LS is located in the auxiliary compensation circuit; the non-polar capacitor C1 is used to filter and smooth the output voltage to reduce output voltage fluctuations; the non-polar capacitor C1 is shared by both main branches; the DC blocking capacitor CS is used to isolate the DC component to prevent DC current from passing through the third inductor LS; the DC blocking capacitor CS plays a role in high-frequency ripple compensation in the auxiliary compensation circuit; the load capacitor Co is used to further filter and smooth the output voltage to ensure that the load receives a stable DC voltage.

[0051] When the first switch S1 is on, current flows from the input power supply through the first switch S1, through the first inductor L1, and then to the load and non-polar capacitor C1, powering the load and charging the non-polar capacitor C1. When the first switch S1 is off, the current is not immediately interrupted. Instead, it continues to flow through the first anti-parallel diode S1a or the first synchronous freewheeling switch S3, maintaining the current flow. At this time, the first inductor L1 releases the previously stored energy and continues to supply power to the load.

[0052] The current flow process of the second main branch is similar to that of the first main branch, but uses the second switch tube S2, the second inductor L2 and the same non-polar capacitor C1; when the second switch tube S2 is turned on, the current flows from the input power supply through the second switch tube S2, through the second inductor L2, and then flows to the load and the non-polar capacitor C1; when the second switch tube S2 is turned off, the current flows through the second anti-parallel diode S2a or the second synchronous freewheeling switch tube S4, and the second inductor L2 releases the stored energy.

[0053] The auxiliary compensation circuit consists of a third switch S5, a third synchronous freewheeling switch S6, a third inductor LS, and a DC-blocking capacitor CS. When the third switch S5 is on, current flows from the input power supply through the third switch S5, through the third inductor LS, and then to the DC-blocking capacitor CS. During this time, the DC-blocking capacitor CS charges and stores energy. When the third switch S5 is off, the current continues to flow through the third synchronous freewheeling switch S6, maintaining the current flow in the third inductor LS. The third inductor LS releases energy, and the DC-blocking capacitor CS smoothes the high-frequency ripple in the output voltage.

[0054] like Figure 3 The main circuit control block diagram shown provides a control system workflow for a specific implementation:

[0055] First, the input reference signals Vref and Vout are fed into an adder, which calculates the difference between the two signals, known as the error vector. This error vector is then fed into a PI controller, which, based on the magnitude and rate of change of the error signal, generates a control signal using proportional and integral control strategies. This control signal aims to reduce the error and bring the system output closer to the desired reference signal. The control signal output by the PI controller then passes through a gain block K, which amplifies or reduces the control signal to suit the specific system requirements. Adjusting the gain of gain block K controls the sensitivity and stability of the system response. The output signal from the gain block passes through a filter, which removes high-frequency noise from the signal, making it smoother and more stable. The filtered signal is then fed into two adders, ultimately generating two control signals, Y1 and Y2. By adjusting the magnitude and rate of change of these control signals, the system's behavior can be precisely regulated, ensuring stable operation according to the reference signal Vref.

[0056] In some examples, a multivariable state space description is further established through the switching mode analysis method. Its state vector is composed of the system's continuous state quantities. This modeling method strictly follows the principle of energy conservation and accurately characterizes the dynamic response characteristics of the converter near the steady-state operating point through the state continuity constraint equation during the topology switching process. Through mathematical modeling, the following can be finally obtained:

[0057]

[0058] Among them, including the first main branch duty cycle D1, the second main branch duty cycle D2, the capacitor parameter Co, the capacitor voltage iCo, R is the resistance of the entire circuit, L is the inductance of the entire circuit, N is the number of phases of the converter, the first inductor current iL1, the second inductor current iL2, is defined as the Laplace transform constant of the inductor current, The definition of is the Laplace transform constant of the output filter capacitor voltage, The definition of is the Laplace transform constant of the input voltage and the Laplace transform constant of the output voltage, is defined as the Laplace transform constant of the output voltage, is defined as the Laplace transform constant of the input voltage, The definition of is the change of input voltage over time, The definition of is the time differential of the first branch input voltage, The definition of is the change of the current of the second inductor L2 over time, The definition of is the change of the current of the first inductor L1 over time, The definition of is the time differential of the second branch input voltage, The definition of is the change of output voltage over time, The definition of is the change of the voltage of capacitor C0 over time, The definition of is the change of the current of capacitor C0 over time, RL1, RL2, RL are the parasitic resistances of the first inductor L1, the second inductor L2, and the third inductor Ls respectively, and s is the Laplace transform constant of the entire circuit.

[0059] After performing Laplace transform on the above formula, the complex frequency domain model is obtained:

[0060]

[0061] From the above, we can get the transfer function G of the converter Vd (s) is:

[0062]

[0063] Transfer function G Vd The dynamic response characteristics of the converter near the steady-state operating point can be accurately characterized. Based on the dynamic response characteristics of the converter, the parameters of the PI regulator and other control mechanisms can be adjusted and optimized to improve the response speed and regulation accuracy of the system; at the same time, the optimized control method can reduce the switching loss and conduction loss of the converter, thereby improving the overall efficiency of the system.

[0064] In some examples, the buck converter is controlled as follows:

[0065] Step S1, first continuously monitor the output voltage Vout at the load end of the interleaved parallel buck converter; compare and analyze the monitored output voltage Vout with a preset reference value Vref; through the comparison and analysis, generate an error vector, the error vector reflecting the difference between the current output voltage and the expected output voltage;

[0066] In step S2, the generated error vector is sent to the PI regulator for processing. The PI regulator is a linear controller. The PI regulator forms a control deviation based on a preset reference value and the actual output voltage value, and forms a control quantity through a linear combination of the proportion and integral of the control deviation to control the controlled object. The PI regulator performs steady-state accuracy compensation on the error vector through proportional and integral operations. The adjusted control quantity is input to the limiting module, which imposes upper and lower limit constraints on the output value. When the output value exceeds the upper limit, the output is limited to the upper limit value; when the output value is lower than the lower limit, the output is limited to the lower limit value; when the output value is between the upper and lower limits, the original output is maintained.

[0067] Step S3: After the amplitude is adjusted, the control variable is duty cycle modulated with a sawtooth carrier wave having the same amplitude-frequency characteristics as the first and second main branches and strictly opposite phases. The purpose of this step is to convert the continuous control signal into a discrete switching signal to drive the power switch tube.

[0068] The first anti-parallel diode S1a and the second anti-parallel diode S2a use the same-phase drive pulse as the first switch S1 and the second switch S2. The driving logic of the first synchronous freewheeling switch S3 and the second synchronous freewheeling switch S4 forms a complementary relationship with the first switch S1 and the second switch S2. That is, the first synchronous freewheeling switch S3 and the second synchronous freewheeling switch S4 are 180° out of phase with the first switch S1 and the second switch S2. This complementary relationship ensures that the current can flow continuously when the power switch is switched, avoiding current interruption and voltage spikes.

[0069] In step S4, the staggered parallel structure of the topology is used. When the current ripple of the main power circuit is in the negative change phase, the third switch tube S5 is turned on and the third synchronous freewheeling switch tube S6 is locked. When the current ripple enters the positive change phase, the third synchronous freewheeling switch tube S6 is turned on and the third switch tube S5 is locked. The current amplitudes in the two phases are the same, and the phase complementarity realizes the phase cancellation effect of the current ripple of the main power circuit and the auxiliary compensation circuit.

[0070] The main power circuit architecture of this converter can be viewed as an improvement on the traditional two-phase interleaved parallel buck topology. By adding a non-polar capacitor C1, a first anti-parallel diode S1a, and a second anti-parallel diode S2a, and controlling the network switch module using a PWM signal, automatic current sharing in the main power circuit is achieved. This innovation effectively eliminates the circulating current problem in the traditional parallel structure, reduces the complexity of the control system, and improves the operating efficiency of the converter.

[0071] Figure 4This is the control block diagram of the auxiliary compensation circuit. When the duty cycle is greater than 0 and less than 0.5, when the first switch tube S1 and the second switch tube S2 are in the single-tube conduction state, the current ripple of the main power branch presents a positive slope characteristic, triggering the phase compensation mechanism of the auxiliary compensation circuit's third synchronous freewheeling switch tube S6 to turn on and the third switch tube S5 to lock, forming a negative slope compensation current; when the main power devices are fully turned off, the main power branch enters the negative slope dynamic response stage. At this time, the compensation branch switches to the third switch tube S5 to turn on and the third synchronous freewheeling switch tube S6 to lock, generating a positive slope compensation current to achieve ripple amplitude offset. When the duty cycle is greater than 0.5 and less than 1, the main power device is fully turned on, corresponding to the positive slope stage of the main branch current, and the compensation branch implements the third synchronous freewheeling switch tube S6 turning on and the third switch tube S5 blocking strategy; when the main power device enters the alternating conduction mode, the main circuit current turns to a negative slope characteristic, and the auxiliary compensation circuit immediately switches to the third switch tube S5 turning on and the third synchronous freewheeling switch tube S6 blocking state. This complementary control mechanism realizes the phase cancellation effect of the current ripple of the main power circuit and the auxiliary compensation circuit, maintaining the ripple suppression effect.

[0072] The generation mechanism of the auxiliary compensation circuit drive signal is based on the current ripple slope characteristics of the main power circuit. The ripple dynamic identification is performed by real-time monitoring of the conduction state of each phase switch tube. Finally, a drive timing with phase compensation characteristics is generated according to the slope polarity, thereby establishing an effective ripple suppression closed-loop control system.

[0073] In some embodiments, the overall and amplified waveforms of the first inductor current iL1 and the second inductor current iL2 of the main power circuit of the present invention are shown as follows: Figure 5 and Figure 6 As shown, the main power inductor current presents a strict phase interleaving characteristic and a dynamic change process; the waveform of the synthesized main power circuit current ia is as follows Figure 7 As shown, it reflects the synthesis effect of current and ripple suppression capability; the auxiliary compensation circuit generates current ib through the precise ripple phase inversion mechanism as shown Figure 8 As shown, it reflects the dynamic adjustment process of the compensation current and the phase offset effect; the final output current io is as follows Figure 9 As shown in the figure, the main circuit ripple component Δia and the compensation component Δib are vector superimposed and offset in the time domain, reflecting the stability and ripple level of the output current.

[0074] The converter's main power circuit architecture can be considered an improvement on the traditional two-phase interleaved parallel buck topology. By adding a non-polar capacitor C1, first and second anti-parallel diodes S1a and S2a, and using PWM signals to control the network switch module, automatic current sharing in the main power circuit is achieved. This innovation effectively eliminates the circulating current problem found in traditional parallel structures, reduces control system complexity, and improves converter efficiency.

[0075] Comparison diagram with the proposed converter model without any current sharing control strategy Figure 10 As shown in the figure, when a conventional two-phase interleaved parallel buck converter is not subject to current sharing control, the two-phase inductor currents exhibit significant asymmetry. During the initial system startup, the current amplitude oscillations in the main power circuit exhibit temporal differences, which gradually improves as the circuit enters steady-state operation. The figure shows that when the system runs for 0.01 seconds, the two-phase current fluctuations are ultimately balanced through dynamic adjustment of the non-polar capacitor C1 during the startup phase.

[0076] The above description is only a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Any simple modification, equivalent replacement and improvement made by any technician familiar with the profession to the above embodiment without departing from the scope of the technical solution of the present invention and based on the technical essence of the present invention shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A low output ripple, automatic current-sharing interleaved parallel buck converter, characterized by: It includes a main power circuit and an auxiliary compensation circuit arranged in parallel; The main power circuit is composed of a first main branch and a second main branch connected in parallel, and is used to convert the input voltage into the required output voltage, transmit current, and achieve automatic current sharing; The auxiliary compensation circuit adopts the current mirror compensation principle to construct a closed-loop control system for suppressing output current ripple.

2. The low output ripple, automatic current sharing interleaved parallel buck converter according to claim 1, characterized in that: The first main branch and the second main branch are controlled and modulated by staggered PWM with a phase difference of 180° to achieve staggered parallel connection, and the two-phase inductor current ripple peaks of the first main branch and the second main branch are complementary and superimposed on the time axis.

3. The low output ripple, automatic current sharing interleaved parallel buck converter according to claim 2, characterized in that: The first main branch and the second main branch integrate a network switch module composed of a switch tube and a non-polar capacitor.

4. The low output ripple, automatic current sharing interleaved parallel buck converter according to claim 3, characterized in that: The network switch module realizes dynamic conduction state switching through PWM signal control, so that the converter can automatically share the current.

5. The low output ripple, automatic current sharing interleaved parallel buck converter according to claim 1, characterized in that: The first main branch comprises a first switch tube S1 and a first anti-parallel diode S1a connected in parallel, a first inductor L1 connected between the load and the output end of the first switch tube S1 and the non-polar capacitor C1, a first synchronous freewheeling switch tube S3 connected between the first inductor L1 and the load, and a non-polar capacitor C1 connected in parallel across the load, together forming a standard buck topology structure for reducing the input voltage to the required output.

6. The low output ripple, automatic current sharing interleaved parallel buck converter according to claim 5, characterized in that: The second switch tube S2 and the second anti-parallel diode S2a are connected in parallel, the second inductor L2 is connected between the load and the output end of the second switch tube S2 and the non-polar capacitor C1, the second synchronous freewheeling switch tube S4 is connected between the second inductor L2 and the load, and shares the non-polar capacitor C1 with the first main branch. The second main branch and the first main branch form a symmetrical structure for realizing voltage conversion and energy transmission.

7. The low output ripple, automatic current sharing interleaved parallel buck converter according to claim 1, characterized in that: The auxiliary compensation circuit includes a third switch tube S5, a third inductor LS and a DC blocking capacitor CS connected in series in sequence; the auxiliary compensation circuit also includes a third synchronous freewheeling switch tube S6, and the third synchronous freewheeling switch tube S6 is arranged between the third switch tube S5 and the first synchronous freewheeling switch tube S3 and the second synchronous freewheeling switch tube S4 connected in parallel with each other.

8. The low output ripple, automatic current sharing interleaved parallel buck converter according to claim 1, characterized in that: The auxiliary compensation circuit drives the switch tube of the network switch module by comparing the difference between the output current of the main power circuit and the reference current, and adjusts the magnitude of the compensation current with a specific duty cycle to achieve active compensation of the ripple amplitude.

9. A control method for an interleaved parallel buck converter with low output ripple and automatic current sharing, characterized in that: The following steps are involved: Step S1, first continuously monitor the output voltage Vout at the load end of the interleaved parallel buck converter; compare and analyze the monitored output voltage Vout with a preset reference value Vref; through the comparison and analysis, generate an error vector, the error vector reflecting the difference between the current output voltage and the expected output voltage; In step S2, the generated error vector is sent to the PI regulator for processing. The PI regulator forms a control deviation based on the preset reference value and the actual output voltage value, and forms a control quantity through linear combination of the proportion and integral of the control deviation to control the controlled object. The PI regulator performs steady-state accuracy compensation on the error vector through proportional and integral operations. The adjusted control quantity is input to the limiting module, which imposes upper and lower limit constraints on the output value: when the output value exceeds the upper limit, the output is limited to the upper limit value; when the output value is lower than the lower limit, the output is limited to the lower limit value; when the output value is between the upper and lower limits, the original output is maintained. Step S3: After the amplitude is adjusted, the control quantity is duty cycle modulated with a sawtooth carrier whose amplitude-frequency characteristics are consistent with those of the first main branch and the second main branch and whose phases are strictly opposite to each other; the first anti-parallel diode S1a, the second anti-parallel diode S2a, and the first switch S1, the second switch S2 use the same-phase drive pulses, and the driving logic of the first synchronous freewheeling switch S3, the second synchronous freewheeling switch S4 forms a complementary relationship with the first switch S1, the second switch S2, that is, the first synchronous freewheeling switch S3, the second synchronous freewheeling switch S4 are 180° out of phase with the first switch S1, the second switch S2. In step S4, the staggered parallel structure of the topology is used. When the current ripple of the main power circuit is in the negative change phase, the third switch tube S5 is turned on and the third synchronous freewheeling switch tube S6 is locked. When the current ripple enters the positive change phase, the third synchronous freewheeling switch tube S6 is turned on and the third switch tube S5 is locked. The current amplitudes in the two phases are the same, and the phase complementarity realizes the phase cancellation effect of the current ripple of the main power circuit and the auxiliary compensation circuit.

10. The control method of the low output ripple, automatic current sharing interleaved parallel buck converter according to claim 9, characterized in that: A switching modal analytical method for multivariable state space is established. Its state vector is composed of the continuous state quantities of the system. The dynamic response characteristics of the converter near the steady-state operating point are characterized by the state continuity constraint equation during the topology switching process. The modeling is as follows: Among them, including the first main branch duty cycle D1, the second main branch duty cycle D2, the capacitor parameter Co, the capacitor voltage iCo, R is the resistance of the entire circuit, L is the inductance of the entire circuit, N is the number of phases of the converter, the first inductor current iL1, the second inductor current iL2, is defined as the Laplace transform constant of the inductor current, The definition of is the Laplace transform constant of the output filter capacitor voltage, The definition of is the Laplace transform constant of the input voltage and the Laplace transform constant of the output voltage, is defined as the Laplace transform constant of the output voltage, is defined as the Laplace transform constant of the input voltage, The definition of is the change of input voltage over time, The definition of is the time differential of the first branch input voltage, The definition of is the change of the current of the second inductor L2 over time, The definition of is the change of the current of the first inductor L1 over time, The definition of is the time differential of the second branch input voltage, The definition of is the change of output voltage over time, The definition of is the change of the voltage of capacitor C0 over time, The definition of is the change of the current of capacitor C0 over time, RL1, RL2, RL are the parasitic resistances of the first inductor L1, the second inductor L2, and the third inductor Ls respectively, and s is the Laplace transform constant of the entire circuit; After performing Laplace transform on the above formula, the complex frequency domain model is obtained: From the above, we can get the transfer function G of the converter Vd (s) is:

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