Signal transmitting apparatus

Abstract

In the present invention, an output terminal is connected to a power supply voltage application end through a pull-up resistor and a backflow prevention diode. An output transistor is provided between the output terminal and ground. A capacitor is connected between the gate of the output transistor and the output terminal. A charge-discharge circuit charges or discharges the gate of the output transistor in accordance with an input signal, turns on or off the output transistor accordingly, to thereby generate an output signal, corresponding to the input signal, at the output terminal. The charge-discharge circuit sets charging current and discharging current, which are to be applied to the gate of the output transistor, to adjustment target current, and changes the adjustment target current non-linearly in accordance with the power supply voltage.

Description

signal transmitting device

[0001] The present disclosure relates to a signal transmission device.

[0002] There is a signal transmission device that transmits an output signal from an output terminal. One type of signal transmission device must satisfy both the required performance regarding the slew rate of the output signal and the required performance regarding radiation noise.

[0003] Japanese Patent Application Laid-Open No. 2017-200103

[0004] However, there is a trade-off between the slew rate of the output signal and the radiated noise, and some ingenuity is required to simultaneously satisfy these performance requirements.

[0005] An object of the present disclosure is to provide a signal transmission device that contributes to achieving both the required performance regarding the slew rate of an output signal and the required performance regarding radiation noise.

[0006] The signal transmission device according to the present disclosure comprises an output terminal configured to be connected to an application terminal of a power supply voltage via a pull-up resistor and a backflow prevention diode, an output transistor provided between the output terminal and ground, a capacitor connected between the gate of the output transistor and the output terminal, and a charge / discharge circuit configured to charge or discharge the gate of the output transistor in accordance with an input signal, wherein an output signal in accordance with the input signal is generated at the output terminal by turning the output transistor on or off through charging or discharging the gate of the output transistor, the backflow prevention diode has a forward direction from the application terminal of the power supply voltage toward the output terminal, and the charge / discharge circuit sets the charge current and discharge current for the gate of the output transistor to a current to be adjusted and changes the current to be adjusted nonlinearly in accordance with the power supply voltage.

[0007] According to the present disclosure, it is possible to provide a signal transmission device that contributes to achieving both the required performance regarding the slew rate of the output signal and the required performance regarding radiation noise.

[0008] FIG. 1 is an overall configuration diagram of a communication system according to an embodiment of the present disclosure. FIG. 2 is an external perspective view of a transceiver according to an embodiment of the present disclosure. FIG. 3 is a configuration diagram of a transmission circuit in the transceiver according to an embodiment of the present disclosure. FIG. 4 is a diagram for explaining signal output conditions according to an embodiment of the present disclosure. FIG. 5 is a diagram schematically illustrating waveforms of a control input signal and an output voltage according to a reference method. FIG. 6 is a diagram illustrating a relationship between a power supply voltage and a charging current or a discharging current according to a reference method. FIG. 7 is a diagram illustrating the ease with which output signal conditions and radiation noise conditions are met in the relationship between a power supply voltage and a charging current or a discharging current according to a reference method. FIG. 8 is a diagram schematically illustrating waveforms of a control input signal and an output voltage when the power supply voltage is relatively high. FIG. 9 is a diagram schematically illustrating waveforms of a control input signal and an output voltage when the power supply voltage is relatively low. FIG. 10 is a diagram illustrating a relationship between a power supply voltage and a charging current or a discharging current according to an embodiment of the present disclosure. FIG. 11 is a diagram illustrating a relationship between a power supply voltage and an output slew rate according to an embodiment of the present disclosure. FIG. 12 is a configuration diagram of a current generating circuit according to an embodiment of the present disclosure.

[0009] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and duplicate descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, this specification may use symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components, and may omit or abbreviate the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs. For example, the bus connection terminal BUS referred to by "BUS" (see FIG. 1) described below may be written as a bus connection terminal BUS or abbreviated as a terminal BUS, but they all refer to the same thing.

[0010] First, some terms used in describing the embodiments of the present disclosure will be explained. A line refers to a wiring through which an electrical signal is propagated or applied. A ground refers to a reference conductive portion having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductive portion may be formed using a conductor such as metal. A potential of 0 V is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0011] A level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, when the signal or voltage is at a high level, strictly speaking, the signal or voltage level is at a high level, and when the signal or voltage is at a low level, strictly speaking, the signal or voltage level is at a low level. A level for a signal may be expressed as a signal level, and a level for a voltage may be expressed as a voltage level.

[0012] In any signal or voltage of interest, a transition from a low level to a high level is referred to as an up-edge, which may be read as a rising edge. Similarly, in any signal or voltage of interest, a transition from a high level to a low level is referred to as a down-edge, which may be read as a falling edge.

[0013] For any transistor configured as a FET (field effect transistor), including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Furthermore, unless otherwise specified, the back gate of any MOSFET can be considered to be short-circuited to the source.

[0014] For any signal that takes a high or low signal level, the period during which the signal level is high is referred to as a high-level period, and the period during which the signal level is low is referred to as a low-level period. The same applies to any voltage that takes a high or low voltage level.

[0015] Unless otherwise specified, the connection between a plurality of parts that form a circuit, such as any circuit element, wiring (line), node, etc., may be understood to refer to an electrical connection.

[0016] 1 shows an overall configuration diagram of a communication system 1 according to an embodiment of the present disclosure. The communication system 1 includes a transceiver 10, a microcomputer 20, and a counterpart device 30. The components of the communication system 1 also include a bus line 51, a pull-up resistor 52, a backflow prevention diode 53, a capacitor 54, a data line 61, a data line 62, and a pull-up resistor 63.

[0017] FIG. 2 is a perspective view of the transceiver 10. The transceiver 10 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and multiple external terminals exposed from the housing to the outside of the transceiver 10. The transceiver 10 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals and the type of housing of the transceiver 10 shown in FIG. 2 are merely examples and can be designed as desired. FIG. 1 shows the multiple external terminals, including a power supply terminal VIN, a bus connection terminal BUS, a ground terminal GND, a receive data output terminal RXD, and a transmit data input terminal TXD. Other external terminals (such as a sleep control input terminal) may also be provided in the transceiver 10.

[0018] A power supply voltage VDD is supplied to the power supply terminal VIN from a voltage source (not shown). The power supply voltage VDD has a predetermined positive DC voltage value. The transceiver 10 is driven based on the power supply voltage VDD. The ground terminal GND is connected to ground. The bus connection terminal BUS is connected to one end of a bus line 51, and the other end of the bus line 51 is connected to the counterpart device 30. That is, the bus connection terminal BUS is connected to the counterpart device 30 via the bus line 51. The counterpart device 30 also has a terminal that receives the power supply voltage VDD and a terminal that is connected to ground, and is driven based on the power supply voltage VDD.

[0019] The bus line 51 is connected to an application terminal 50 of a power supply voltage VDD via a pull-up resistor 52 and a backflow prevention diode 53. The application terminal 50 is a terminal to which the power supply voltage VDD is applied. The forward direction of the backflow prevention diode 53 is from the application terminal 50 toward the bus line 51 and the bus connection terminal BUS. The backflow prevention diode 53 blocks current flow from the bus line 51 to the application terminal 50. More specifically, the anode of the backflow prevention diode 53 is connected to the application terminal 50, the cathode of the backflow prevention diode 53 is connected to one end of the pull-up resistor 52, and the other end of the pull-up resistor 52 is connected to the bus line 51.

[0020] However, the positions of the pull-up resistor 52 and the blocking diode 53 may be reversed from those shown in Fig. 1. That is, the application terminal 50 may be connected to the anode of the blocking diode 53 via the pull-up resistor 52, and the cathode of the blocking diode 53 may be connected to the bus line 51.

[0021] The capacitor 54 is connected between the bus line 51 and the ground. That is, one end of the capacitor 54 is connected to the bus line 51, and the other end of the capacitor 54 is connected to the ground. The capacitor 54 may be composed of a plurality of capacitors that are separated from each other. The capacitor 54 may also be omitted.

[0022] The receive data output terminal RXD is connected to one end of a data line 61, the other end of which is connected to the microcomputer 20. The transmit data input terminal TXD is connected to one end of a data line 62, the other end of which is connected to the microcomputer 20. That is, the terminals RXD and TXD are connected to the microcomputer 20 via the data lines 61 and 62. The data line 61 is connected to the application terminal of the power supply voltage VCC via a pull-up resistor 63. The power supply voltage VCC has a predetermined positive DC voltage value. It does not matter whether the values ​​of the power supply voltages VCC and VDD match or not. The microcomputer 20 has a terminal that receives the power supply voltage VCC and a terminal that is connected to ground, and is driven based on the power supply voltage VCC.

[0023] The transceiver 10 comprises a receiving circuit RX and a transmitting circuit TX. The receiving circuit RX is connected to a receiving data output terminal RXD and a bus connection terminal BUS. The transmitting circuit TX is connected to a transmitting data input terminal TXD and a bus connection terminal BUS.

[0024] The transceiver 10 and the counterpart device 30 perform bidirectional communication in a half-duplex manner via a bus line 51. The bidirectional communication assumed in this embodiment is single-wire serial communication (i.e., serial communication using a single wire, the bus line 51). In the half-duplex bidirectional communication, the transceiver 10 may function as a master and the counterpart device 30 as a slave, or the counterpart device 30 may function as a master and the transceiver 10 as a slave. The bidirectional communication between the transceiver 10 and the counterpart device 30 may be bidirectional communication conforming to, for example, the LIN (Local Interconnect Network) standard or the CXPI (Clock Extension Peripheral Interface) standard.

[0025] In half-duplex two-way communication, either the transceiver 10 or the other device 30 operates as a transmitting device, and the other functions as a receiving device.

[0026] When the transceiver 10 functions as a receiving device, the other device 30 transmits a signal (hereinafter, signal SR The receiving circuit RX receives the signal S transmitted from the other device 30 at the bus connection terminal BUS. R The receiving circuit RX receives the received signal S R is transmitted from terminal RXD to microcomputer 20 via data line 61. When transceiver 10 functions as a receiving device, bus connection terminal BUS functions as an input terminal (signal receiving terminal) that receives a signal transmitted from counterpart device 30.

[0027] When the transceiver 10 functions as a transmitting device, the microcomputer 20 transmits a signal (hereinafter, signal S T ) is transmitted to the transceiver 10. The signal S T When the transceiver 10 functions as a transmitting device, the transmitting circuit TX receives the signal S from the microcomputer 20. T The other device 30 may be configured with a transceiver and a microcomputer set equivalent to the transceiver 10 and the microcomputer 20. In this case, the signal S received from the transceiver 10 is T is transmitted from the transceiver in the remote device 30 to the microcomputer in the remote device 30. When the transceiver 10 functions as a transmitting device, the bus connection terminal BUS functions as an output terminal (signal transmitting terminal) from which a signal to be transmitted from the transceiver 10 appears.

[0028] The transmission of a signal via the bus line 51 is realized by controlling the level of the bus line 51 to a high level or a low level. The level of the bus line 51 and the level of the bus connection terminal BUS are the same. The level of the bus line 51 is a level that is equal to or higher than 0 V and equal to or lower than the power supply voltage VDD. When the bus line 51 is at a voltage (VDD×k H ), the level of the bus line 51 corresponds to a high level, and the bus line 51 has a voltage (VDD×k L ) or less, the level of the bus line 51 corresponds to a low level.H >0.5>k L >0" holds, for example, (k H , k L )=(0.7, 0.3). The voltages at the bus line 51 and the bus connection terminal BUS are represented by the symbol "V BUS " is expressed as

[0029] Unless otherwise specified, the operation and configuration of the transceiver 10 when it functions as a transmitting device will be described below. BUS corresponds to the output voltage (output voltage of the transmitter circuit TX). Therefore, when focusing on the configuration or operation of the transmitter circuit TX, the voltage V BUS may be referred to as the output voltage hereinafter. BUS The signal indicated by V can be referred to as an output signal. When transmitting a signal via the bus line 51, the transmitting circuit TX in the transceiver 10 changes the level of the bus line 51 between a high level and a low level, in order to reduce radiation noise. BUS It has the function of controlling the slew rate.

[0030] [Basic Configuration of Transmitter Circuit TX] The basic configuration of the transmitter circuit TX is shown in Fig. 3. The transmitter circuit TX according to the basic configuration includes an output transistor 111, a capacitor (feedback capacitor) 112, a backflow prevention diode 113, a charge / discharge circuit 120, a control input signal supply circuit 130, and a gate voltage limiting circuit 140.

[0031] The output transistor 111 is an N-channel MOSFET. The output transistor 111 is provided between the bus connection terminal BUS, which functions as an output terminal, and ground, and the transmission circuit TX transmits signals using the output transistor 111 with an open-drain configuration. However, a backflow prevention diode 113 is provided between the output transistor 111 and the bus connection terminal BUS to block the flow of current from ground toward the bus line 51 via the output transistor 111 and the bus connection terminal BUS. Specifically, the drain of the output transistor 111 is connected to the cathode of the backflow prevention diode 113, and the anode of the backflow prevention diode 113 is connected to the bus connection terminal BUS. The source of the output transistor 111 is connected to ground. The gate voltage of the output transistor 111 (i.e., the voltage applied to the gate of the output transistor 111) is represented by the symbol "V G The gate threshold voltage of the output transistor 111 is represented by the symbol "V G_TH The gate threshold voltage V G_TH has a positive voltage value that depends on the characteristics of the output transistor 111. The gate voltage V of the output transistor 111 G is the gate threshold voltage V G_TH When the gate voltage V G is the gate threshold voltage V G_TH When this is the case, the output transistor 111 is in an ON state.

[0032] It should be noted that a modification in which the backflow prevention diode 113 is not provided in the transmission circuit TX is also possible, and when this modification is adopted, the drain of the output transistor 111 is directly connected to the bus connection terminal BUS.

[0033] The capacitor 112 is connected between the gate of the output transistor 111 and the bus connection terminal BUS. That is, one end of the capacitor 112 is connected to the gate of the output transistor 111, and the other end of the capacitor 112 is connected to the bus connection terminal BUS.

[0034] The charge / discharge circuit 120 receives a control input signal S INThe charge / discharge circuit 120 can control the output transistor 111 to be in the ON state by charging the gate of the output transistor 111, and can control the output transistor 111 to be in the OFF state by discharging the gate of the output transistor 111. IN is a binary signal having a high or low signal level. A high-level control input signal S IN is essentially the internal power supply voltage V REG and the control input signal S IN The power supply voltage VDD is supplied to the transceiver 10 via a regulator (not shown) to generate an internal power supply voltage V REG The charge / discharge circuit 120 includes a charging circuit 121 and a discharging circuit 122.

[0035] The charging circuit 121 receives a control input signal S IN During the high level period, a charging current is supplied to the gate of the output transistor 111, thereby increasing the gate voltage V G However, the gate voltage V G There is an upper limit to the gate voltage V G The gate voltage V G The upper limit voltage is the internal power supply voltage V REG or the internal power supply voltage V REG The gate voltage V G The upper limit voltage of the output transistor 111 is the gate threshold voltage V G_TH Higher gate voltage V G In the process of rising from a sufficiently low voltage (for example, 0 V), the gate voltage V G is the gate threshold voltage V G_TH When the gate voltage V reaches the G In the process of rising from a sufficiently low voltage (for example, 0 V), the gate voltage V G is the gate threshold voltage V G_THWhen this occurs, the resistance value of the channel of the output transistor 111 drops sharply, and the resistance value of the channel of the output transistor 111 becomes sufficiently smaller than the resistance value of the pull-up resistor 52, and the voltage V BUS drops to substantially 0 V. The resistance value of the channel of the output transistor 111 refers to the resistance value between the drain and source of the output transistor 111 .

[0036] The discharge circuit 122 receives a control input signal S IN During the low level period, a discharge current is drawn from the gate of the output transistor 111, thereby increasing the gate voltage V G However, the gate voltage V G There is a lower limit to the gate voltage V G The gate voltage V G The lower limit voltage of the gate voltage V G is the gate threshold voltage V G_TH In the process of decreasing from a voltage higher than G is the gate threshold voltage V G_TH When the gate voltage V falls below 0 V, the output transistor 111 switches from the ON state to the OFF state. G is the gate threshold voltage V G_TH In the process of decreasing from a voltage higher than G is the gate threshold voltage V G_TH When the resistance value of the channel of the output transistor 111 becomes less than 1 / 2, the resistance value of the channel of the output transistor 111 increases sharply, and the resistance value of the channel of the output transistor 111 becomes sufficiently larger than the resistance value of the pull-up resistor 52, and the output voltage V BUS rises to near the power supply voltage VDD.

[0037] 3, the charging circuit 121 is configured with a series circuit of a charging current source 121a and a switch 121b, and the discharging circuit 122 is configured with a series circuit of a discharging current source 122a and a switch 122b. The charging current source 121a is connected to the internal power supply voltage V REG and the switch 121b, and REG Based on the current I CThe switch 121b is provided between the charging current source 121a and a node 123. The discharging current source 122a is provided between the ground and the switch 122b, and generates the internal power supply voltage V REG Based on the current I D The switch 122b is provided between the discharging current source 122a and a node 123. The node 123 is connected to the gate of the output transistor 111. The switches 121b and 122b generate a control input signal S IN The power supply is controlled to be on or off based on the power supply voltage.

[0038] Control input signal S IN During the high level period of the control input signal S, the switch 121b is turned on, while the switch 122b is turned off. IN During the high level period, the gate voltage V G Current I to increase C (Hereinafter, charging current I C ) is supplied from the charging current source 121a to the gate of the output transistor 111 via the switch 121b and the node 123. IN During the low level period, no charge is transferred between the gate of the output transistor 111 and the charging circuit 121 .

[0039] Control input signal S IN During the low level period of the control input signal S, the switch 121b is turned off and the switch 122b is turned on. IN During the low level period, the gate voltage V G Current I to reduce D (Hereinafter, discharge current I D ) is drawn from the gate of the output transistor 111 to the discharging current source 122a via the node 123 and the switch 122b. IN During the high level period, no charge is transferred between the gate of the output transistor 111 and the discharge circuit 122 .

[0040] The control input signal supply circuit 130 receives the signal S from the microcomputer 20. T Based on the control input signal S INand generates a control input signal S IN to the charge / discharge circuit 120. The control input signal supply circuit 130 supplies, for example, a signal S T The binary signal obtained by shaping the waveform of the control input signal S IN It may be generated as

[0041] Incidentally, the control input signal S IN During the high level period, the charging current I C The charging circuit 121 may have any configuration as long as it can supply the control input signal S IN During the low level period, the charging circuit 121 supplies a charging current I C In any case, the generation of the control input signal S IN During the low level period of C is zero. Similarly, the control input signal S IN During the low level period, the discharge current I D The discharge circuit 122 may have any configuration as long as it can draw in the control input signal S from the gate of the output transistor 111. IN During the high level period, the discharge circuit 122 discharges the discharge current I D In any case, the generation of the control input signal S IN During the high level period, a discharge current I flows from the gate of the output transistor 111 to the discharge circuit 122. D is zero.

[0042] The gate voltage limiting circuit 140 is connected to the gate of the output transistor 111 and ground. The gate voltage limiting circuit 140 has two diodes 141 and 142. The anode of the diode 141 is connected to the gate of the output transistor 111, and the cathode of the diode 141 is connected to the anode of the diode 142, and the cathode of the diode 142 is connected to ground. The gate voltage limiting circuit 140 limits the gate voltage V G is a predetermined limit voltage V LIM Any circuit can be used as long as it has the function of preventing the limit voltage V LIM is the gate threshold voltage VG_TH 3, it corresponds to the sum of the forward voltages of the diodes 141 and 142. The circuit 140 may be formed by a series circuit of three or more diodes.

[0043] Charging current I C Gate voltage V based on G In the process in which the output transistor 111 switches from the OFF state to the ON state due to the rise of BUS decreases, and the output voltage V BUS The decrease in the discharge current I is fed back to the gate of the output transistor 111 via the capacitor 112. D Gate voltage V based on G When the output transistor 111 switches from the ON state to the OFF state due to the decrease in BUS rises, and the output voltage V BUS The increase in the capacitance is fed back to the gate of the output transistor 111 via the capacitor 112. Therefore, to the charge / discharge circuit 120, the capacitance value of the capacitor 112 appears to be equivalently larger than the actual capacitance value of the capacitor 112 due to the Miller effect. In other words, the capacitor 112 functions as a Miller capacitance.

[0044] [Output signal conditions] Output voltage V BUS The slew rate of the output voltage V BUS The rising slew rate is the slew rate when the output voltage V BUS The rising slew rate is the rate at which the output voltage V BUS When the output voltage V rises BUS The falling slew rate refers to the maximum or average rate of change of the output voltage V BUS When the output voltage V BUS The rising slew rate refers to the maximum or average value of the rate of change of the output signal. Hereinafter, the rising slew rate and the falling slew rate will be collectively referred to as the output slew rate. In the following description, the output slew rate will be understood to refer to either the rising slew rate or the falling slew rate, or to refer to both the rising slew rate and the falling slew rate.

[0045] While a reduction in the output slew rate contributes to a reduction in radiated noise, the transceiver 10 must satisfy the following output signal conditions when operating as a transmitting device: These output signal conditions may be, for example, those specified in the LIN standard or the CXPI standard.

[0046] The output signal conditions that the transceiver 10 must meet will now be described with reference to FIG. 4. FIG. 4 shows the control input signal S IN and output voltage V BUS The waveforms of the control input signal S IN is the output voltage V BUS an output high indication level that indicates that the output voltage V BUS (i.e., the output signal) has a low level.

[0047] The charge / discharge circuit 120 receives a control input signal S IN The gate of the output transistor 111 is charged during the period when the control input signal S has an output low indication level, thereby controlling the output transistor 111 to be in an on state. IN The output transistor 111 is controlled to be in an OFF state by discharging the gate of the output transistor 111 during the period when the control input signal S IN The output low indication level at IN The output high indication level at is low, but the control input signal S IN In this case, the output low indication level may be set to a low level and the output high indication level may be set to a high level.

[0048] Control input signal S IN During the low level period of the control input signal S IN The length of time during which the output has a high indication level is defined as time T A The control input signal S IN The low level period and the high level period of the control input signal S IN The length of one low level period of interest is time T ASpecifically, at time t1, the control input signal S IN Then, at time t3, the control input signal S IN In this case, the time from time t1 to time t3 is the time T A 4, time t2 is later than time t1 and earlier than time t3, and time t4 is later than time t3.

[0049] From time t1, a discharge current I from the gate of the output transistor 111 D The discharge current I D The gate voltage V G is the gate threshold voltage V G_TH When the resistance value of the channel of the output transistor 111 increases, the output voltage V BUS starts to rise from 0 V or a voltage close to 0 V. Then, at time t2, the output voltage V BUS is the voltage (VDD x k REF ) reaches the voltage (VDD × k REF ) is the k of the power supply voltage VDD REF It is times. REF has a positive predetermined value less than 1 defined in a standard (e.g., LIN standard or CXPI standard) applied to the communication system 1, and the coefficient k H Here, "k REF = k H = 0.7". The output voltage V BUS continues to rise after time t2.

[0050] Then, at time t3, the control input signal S IN When a rising edge occurs at the output transistor 111, the discharging of the gate of the output transistor 111 is stopped and instead the charging of the gate of the output transistor 111 is started. C The gate voltage V G is the gate threshold voltage V G_TH When the resistance of the channel of the output transistor 111 increases to BUS is the voltage (VDD x k REF ) and then begins to drop.BUS is the voltage (VDD x k REF ) The output voltage V BUS continues to decrease after time t4.

[0051] The length between times t2 and t4 is time T B The output signal condition is expressed as A Time T B The ratio of (T B / T A ) is a predetermined threshold R TH The condition is that the value is equal to or greater than "T B / T A ≧R TH ", the output signal condition is satisfied, and "T B / T A <R TH ", the output signal condition is not satisfied. TH has a positive predetermined value less than 1 defined in a standard (e.g., LIN standard or CXPI standard) applied to the communication system 1, and is, for example, "R TH = 0.8".

[0052] The forward voltage of the reverse current prevention diode 53 is represented by the symbol "Vf." IN During the low level period, the output voltage V BUS does not rise above the voltage (VDD-Vf).

[0053] Furthermore, signal S T The control input signal supply circuit 130 also alternates between the output high indication level and the output low indication level, and the control input signal supply circuit 130 supplies the output high indication level signal S T In response to the control input signal S IN The level of the signal S is set to the output high indication level, and the level of the signal S is set to the output low indication level. T In response to the control input signal S IN The level of the output is set to the low indication level. A is the signal S T may be interpreted as corresponding to the length of the period during which the output has a high indication level. IN is the signal S from the microcomputer 20 T The control input signal SIN is signal S T The signal S may be equivalent to T Itself is the control input signal S IN It can be understood as follows.

[0054] On the other hand, in the communication system 1, the power supply voltage VDD is the minimum voltage VDD MIN to maximum voltage VDD MAX The minimum voltage is VDD. MIN and maximum voltage VDD MAX is "0<VDD MIN <VDD MAX ". As long as the power supply voltage VDD falls within the power supply voltage range, it is required that the output signal condition is always met. If the output slew rate is always set to be sufficiently large, the output signal condition can be easily met, but an increase in the output slew rate increases radiation noise.

[0055] [Radiation Noise Conditions] The transceiver 10 must also satisfy the radiation noise conditions in accordance with the standard (e.g., LIN standard or CXPI standard) applied to the communication system 1. The radiation noise conditions for the transceiver 10 are satisfied when the amount of radiation noise from the communication system 1 when the transceiver 10 is operated as a transmitting device in a specified noise test environment is equal to or less than a specified value. Typically, a radiation noise test is performed to actually measure the amount of radiation noise from the communication system 1 when the transceiver 10 is operated as a transmitting device in a specified noise test environment, and whether the radiation noise conditions are satisfied or not is determined based on the actual measurement value. Here, the power supply voltage VDD in the noise test environment is a test voltage VDD having a representative value within the power supply voltage range. TYP Test voltage VDD TYP is the minimum voltage VDD MIN Higher and maximum voltage VDD MAX Lower. For example, VDD TYP = (VDD MIN +VDD MAX ) / 2.

[0056] [Reference Method] As a method for satisfying both the output signal condition and the radiation noise condition, a method (reference method) for making the output slew rate proportional to the power supply voltage VDD is considered. IN and output voltage V BUS 5, the rectangular waveform 910 is a waveform of the control input signal S IN The solid broken line waveform 911 is a waveform of "VDD=VDD MAX The output voltage V BUS The broken line waveform 912 is a waveform of "VDD=VDD MIN The output voltage V BUS The waveforms 911 and 912 are partially overlapping.

[0057] In the reference method, as shown in FIG. C and discharge current I D 6, the solid line 920 represents the relationship between the power supply voltage VDD and the charging current I C or discharge current I D There is a trade-off between the output slew rate and the radiation noise. That is, in the reference method, the charging current I C and discharge current I D If the proportionality constant when making each value of I proportional to the power supply voltage VDD is increased, the output signal condition becomes easier to meet as the output slew rate increases, but the radiation noise condition becomes more difficult to meet. C and discharge current I D If the proportionality constant when making each value of √{square root over (V)} proportional to the power supply voltage VDD is reduced, the output slew rate will decrease, making it easier to satisfy the radiation noise condition but harder to satisfy the output signal condition.

[0058] [Regarding the compatibility of output signal conditions and radiation noise conditions] Here, the output signal conditions are basically more difficult to satisfy as the power supply voltage VDD becomes lower. B / T A ) is required to be increased, but as the proportion of the forward voltage Vf (the forward voltage Vf of the backflow prevention diode 53) that occupies the power supply voltage VDD increases, the ratio (T B / T A ) tends to decline.

[0059] In FIG. MAX When the control input signal S IN and output voltage V BUS The waveforms of VDD and VDD are shown in FIG. MIN When the control input signal S IN and output voltage V BUS The waveforms of the waveforms are shown in the figure. An explanation will be given with specific numerical examples. As mentioned above, here, REF = 0.7". Furthermore, (VDD MAX , VDD MIN , Vf)=(27V, 5V, 0.7V).

[0060] "VDD = VDD MAX For the case where "(VDD MAX -Vf)=26.3V”, “VDD×k REF = VDD MAX × 0.7 = 18.9V and 18.9 / 26.3 ≒ 0.719. Therefore, VDD = VDD MAX In the case where ", the control input signal S IN After the falling edge of BUS is the voltage (VDD x k REF ) the output voltage V BUS must rise above 0V. "VDD = VDD MIN For the case where "(VDD MIN -Vf)=4.3V”, “VDD×k REF = VDD MIN × 0.7 = 3.5V and 3.5 / 4.3 ≒ 0.814. Therefore, VDD = VDD MIN In the case where ", the control input signal S IN After the falling edge of BUS is the voltage (VDD x kREF ) the output voltage V BUS must rise above 0V.

[0061] In the reference method, the output voltage V BUS The time required for the output voltage V to rise by approximately 0.814 times the voltage (VDD-Vf) is BUS As a result, in the reference method, the power supply voltage VDD is increased to the minimum voltage VDD. MIN (Conversely, if the output slew rate is increased to satisfy the output signal condition, it becomes difficult to satisfy the radiation noise condition.)

[0062] [Improvement Method] Therefore, the transceiver 10 according to this embodiment employs an improvement method different from the reference method. In the transceiver 10 according to the improvement method, the charging current I C and discharge current I D 10, the solid polygonal line 620 shows the relationship between the power supply voltage VDD and the current to be adjusted according to the improved method, i.e., the relationship between the power supply voltage VDD and the current to be adjusted in the transceiver 10. The current to be adjusted refers to a current whose value is adjusted according to the power supply voltage VDD, and the charge / discharge circuit 120 changes the current to be adjusted (the value of the current to be adjusted) nonlinearly according to the power supply voltage VDD. The control input signal S IN Charging current I during the high level period C and the control input signal S IN Discharge current I during the low level period D 10 correspond to the currents to be adjusted. The dashed line 920 in FIG. 10 indicates the same as the corresponding solid line 920 in FIG.

[0063] The voltage VDD shown in FIG. MID is a predetermined boundary voltage, and the minimum voltage VDD MIN Higher than the maximum voltage VDD MAX The charging current source 121a supplies a charging current I C The discharge current source 122a is configured as a variable current source with a variable value of DThe charge / discharge circuit 120 is configured as a variable current source whose value is variable. C and the discharge current I D In other words, the value of the current to be adjusted is set.

[0064] Specifically, the power supply voltage VDD is the boundary voltage VDD. MID When the value of the current to be adjusted (charging current I C and discharge current I D Each value of the reference current VAL REF The power supply voltage VDD is set to and maintained at the boundary voltage VDD. MID When the value of the current to be adjusted (charging current I C and discharge current I D Each value of the reference current value VAL REF It is made larger and increases with increasing power supply voltage VDD.

[0065] For example, "VDD>VDD" MID When the value of the current to be adjusted is represented by the symbol "VAL", "VAL = k P × (VDD-VDD MID ) + VAL REF " may be. P is a coefficient having a predetermined positive value. Thus, in the improved method, there is a nonlinear relationship between the power supply voltage VDD and the current to be regulated.

[0066] Furthermore, the charging current I C The reference current value VAL for REF and the discharge current I D The reference current value VAL for REF The boundary voltage VDD may be the same as or different from the boundary voltage VDD. MID is the test voltage VDD mentioned above TYP Alternatively, the voltage may be equal to the boundary voltage VDD. MID is the test voltage VDD TYP It is close to the test voltage VDD TYP It could be higher.

[0067] According to the improved method, "VDD = VDD MINIn the "" environment, the value of the current to be adjusted can be made larger than that of the reference method (920), and in the noise test environment, the value of the current to be adjusted can be made smaller than that of the reference method (920). Therefore, it is easy to satisfy both the output signal conditions and the radiation noise conditions (both the required performance related to the output slew rate and the required performance related to the radiation noise). MID ", then "VDD>VDD MID ", the current to be adjusted may be increased in accordance with an increase in the power supply voltage VDD so that the output signal condition is satisfied.

[0068] Since the output slew rate is roughly proportional to the current to be adjusted, the relationship between the power supply voltage VDD and the output slew rate in the improved method is as shown in FIG. 11. In FIG. 11, SR1 is "VDD=VDD" MIN ", and SR2 represents the output slew rate when "VDD = VDD MAX " represents the output slew rate when

[0069] Now, the values ​​J1 and J2 are defined as follows: The value J1 is the output slew rate SR1 at the minimum voltage VDD. MIN (i.e., J1 = SR1 / VDD) MIN The value J2 is the output slew rate SR2 at the maximum voltage VDD. MAX (i.e., J2 = SR2 / VDD) MAX 10 and 11. The charge / discharge circuit 120 according to the improved method changes the current to be adjusted in accordance with the power supply voltage VDD so that the value J1 is higher than the value J2. "J1>J2" is an inequality that expresses part of the characteristics of FIGS. 10 and 11.

[0070] In the characteristics of FIG. MIN ≦VDD≦VDD MID When the condition "is satisfied," the output slew rate is maintained at the output slew rate SR1. MID The value J3 obtained by dividing by SR1 (therefore J3 = SR1 / VDD) MID ) is smaller than the value J1. "J1>J3" is an inequality that expresses part of the characteristics of FIGS.

[0071] 12 shows a current generating circuit 200 as an example of a circuit that generates a current to be adjusted. The current generating circuit 200 can be provided in the charge / discharge circuit 120. The current to be adjusted generated by the current generating circuit 200 is denoted by the symbol "I ADJ ". The current to be adjusted I ADJ is the charging current I C or discharge current I D is.

[0072] The current generating circuit 200 includes a transistor 201, which is a P-channel MOSFET, and a clamp voltage V CLMP The circuit includes a clamper 202 that generates and outputs a voltage, resistors 203 to 206, an operational amplifier 207, and a V / I conversion circuit 208.

[0073] A power supply voltage VDD is applied to the source of the transistor 201 and one end of the resistor 203. The gate of the transistor 201 and the other end of the resistor 203 are connected to each other, and a clamp voltage V CLMP The clamp voltage V CLMP has a predetermined positive DC voltage value. MID is the clamp voltage V CLMP The drain of the transistor 201 is connected to a node 211 via a resistor 204. A positive constant voltage V CNST is applied to the resistor 205, and the other end of the resistor 205 is connected to a node 211. One end of the resistor 206 is connected to the node 211, and the other end of the resistor 206 is connected to the ground. The voltage applied to the node 211 is referred to as a voltage Va.

[0074] The operational amplifier 207 constitutes an impedance conversion circuit that outputs the voltage Va at the node 211 to the node 212 with low impedance. The voltage applied to the node 212 is referred to as the voltage Vb. The operational amplifier 207 functions as a voltage follower, and the voltage Vb is equal to the voltage Va (however, an error is ignored). Specifically, the non-inverting input terminal of the operational amplifier 207 is connected to the node 211, and the inverting input terminal and the output terminal of the operational amplifier 207 are connected to the node 212. The V / I conversion circuit 208 is connected to the node 212, and converts the voltage Vb into the current I to be regulated.ADJ The V / I conversion circuit 208 converts a current value proportional to the value of the voltage Vb into a current to be adjusted I ADJ to hold.

[0075] The operation of the current generating circuit 200 that depends on the power supply voltage VDD will be described. MID ", no voltage to turn on the transistor 201 is applied between the gate and source of the transistor 201, and the transistor 201 is maintained in an off state. MID ", the voltages Va and Vb are determined by the resistance ratio between the resistors 205 and 206 and the constant voltage V CNST As a result, the reference current value VAL is a constant current value corresponding to the constant voltage value. REF (see FIG. 10) is the current to be adjusted I ADJ "VDD = VDD MID " even when "VDD < VDD MID " can be interpreted in the same way as when

[0076] "VDD>VDD MID ", the source potential of the transistor 201 becomes equal to or higher than the gate threshold voltage of the transistor 201 when viewed from the gate potential of the transistor 201, and the transistor 201 is turned on. "VDD>VDD MID ", a current according to the power supply voltage VDD flows from the application terminal of the power supply voltage VDD to the node 211 via the transistor 201 and the resistor 204, and the voltages Va and Vb increase due to the current passing through the transistor 201. Therefore, "VDD>VDD MID ", the current to be adjusted I ADJ The value of is the reference current value VAL REF and increases with increasing power supply voltage VDD.

[0077] Current to be adjusted I ADJ As the charging current I C and a current generating circuit 200 for generating a current to be adjusted I ADJ As the discharge current I DAlternatively, two V / I conversion circuits 208 may be provided in a single current generation circuit 200. In this case, the first V / I conversion circuit 208 is connected to a node 212 and converts the voltage Vb at the node 212 into a charging current I C and a second V / I conversion circuit 208 is connected to node 212 to convert the voltage Vb at node 212 into a discharge current I D Just convert it to .

[0078] [Supplementary Notes] Supplementary notes, applied techniques, modified techniques, etc. regarding the above-described embodiments will be described.

[0079] The communication system 1 can be mounted in a vehicle such as an automobile. In the vehicle, the communication system 1 can be used as a system for performing two-way communication in accordance with the LIN standard or the CXPI standard. More specifically, the communication between the transceiver 10 and the counterpart device 30 can be used for communication of signals for realizing body control of the vehicle, such as power windows, mirrors, power seats, or door locks.

[0080] However, the communication system 1 is not limited to in-vehicle applications, and can be applied to any application in which relatively low-speed communication is performed.

[0081] The transceiver 10 includes a signal transmitter that generates an output signal corresponding to an input signal at a bus connection terminal BUS that functions as an output terminal (in other words, transmits from the bus connection terminal BUS). Components of the signal transmitter include a transmitter circuit TX and may also include the bus connection terminal BUS. An input signal for the signal transmitter is a control input signal S IN The control input signal S IN is the signal S from the microcomputer 20 T Since the signal is based on the signal S T A semiconductor device incorporating the functions of the transceiver 10 and the microcomputer 20 may be formed, in which case a signal transmitting device is provided within the semiconductor device.

[0082] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0083] The channel types of the FETs (field effect transistors) shown in each embodiment are merely examples. The channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0084] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor other than an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0085] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0086] <<Supplementary Notes>> Supplementary notes are provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0087] A signal transmission device (10) according to one aspect of the present disclosure includes an output terminal (BUS) configured to be connected to an application terminal (50) of a power supply voltage (VDD) via a pull-up resistor (52) and a backflow prevention diode (53), an output transistor (111) provided between the output terminal and ground, a capacitor (112) connected between the gate of the output transistor and the output terminal, and an input signal (S IN ) and a charge / discharge circuit (120) configured to charge or discharge the gate of the output transistor in response to the input signal, and an output signal (V BUS ) at the output terminal, the backflow prevention diode has a forward direction from the application terminal of the power supply voltage toward the output terminal, and the charge / discharge circuit generates a charging current (I C ) and discharge current (I D ) is set as the current to be adjusted, and the current to be adjusted is changed nonlinearly in accordance with the power supply voltage (first configuration).

[0088] This makes it easier to satisfy both the required performance related to the output slew rate and the required performance related to radiation noise.

[0089] In the signal transmission device according to the first configuration, the charging circuit is configured to charge the power supply voltage to a predetermined first voltage value (for example, VDD MIN or VDD MID ) when the power supply voltage has a predetermined second voltage value (e.g., VDD) greater than the first voltage value. MAX ), the current to be adjusted may be set to a large value, and a nonlinear relationship may be established between the power supply voltage and the current to be adjusted (second configuration).

[0090] In the signal transmission device according to the first configuration, the charging circuit is configured to MID ), the value of the current to be adjusted is set to a predetermined reference current value (VAL REF), and when the power supply voltage exceeds the boundary voltage, the value of the current to be adjusted is made larger than the reference current value and is increased in accordance with an increase in the power supply voltage (third configuration).

[0091] In the signal transmitting device according to any one of the first to third configurations, the power supply voltage is a predetermined minimum voltage (VDD MIN ) to a predetermined maximum voltage (VDD MAX ), the charging circuit changes the current to be adjusted in accordance with the power supply voltage to make a first value (J1) higher than a second value (J2), the first value being a value obtained by dividing the slew rate of the output signal when the power supply voltage is equal to the minimum voltage by the minimum voltage, and the second value being a value obtained by dividing the slew rate of the output signal when the power supply voltage is equal to the maximum voltage by the maximum voltage (fourth configuration).

[0092] In the signal transmission device according to any of the first to fourth configurations, the charge / discharge circuit may be configured (fifth configuration) to turn on the output transistor by charging the gate of the output transistor when the input signal has a first level (e.g., a high level), and to turn off the output transistor by discharging the gate of the output transistor when the input signal has a second level (e.g., a low level), and the charge / discharge circuit may have a charging circuit (121) configured to supply the charging current to the gate of the output transistor during a period when the input signal has the first level, and a discharging circuit (122) configured to draw the discharging current from the gate of the output transistor during a period when the input signal has the second level.

[0093] In the signal transmission device according to any of the first to fifth configurations, the drain of the output transistor may be connected to the output terminal via another backflow prevention diode (113) having a forward direction from the output terminal toward ground, or the drain of the output transistor may be directly connected to the output terminal (sixth configuration).

[0094] 1 Communication system 10 Transceiver 20 Microcomputer 30 Counterpart device 50 Application terminal 51 Bus line 52 Pull-up resistor 53 Backflow prevention diode 54 Capacitor 61, 62 Data line 63 Pull-up resistor VIN Power supply terminal BUS Bus connection terminal GND Ground terminal RXD Received data output terminal TXD Transmitted data input terminal RX Receive circuit TX Transmit circuit 111 Output transistor 112 Capacitor 113 Backflow prevention diode 120 Charging / discharging circuit 121 Charging circuit 121a Charging current source 122 Discharging circuit 122a Discharging current source 121b, 122b Switch 130 Control input signal supply circuit 140 Gate voltage limiting circuit 141, 142 Diode S IN Control input signal V G Gate voltage V BUS Voltage 200 Current generating circuit 201 Transistor 202 Clamp 203-206 Resistor 207 Operational amplifier 208 V / I conversion circuit

Claims

1. an output terminal configured to be connected to an application terminal of a power supply voltage via a pull-up resistor and a reverse current prevention diode; an output transistor provided between the output terminal and ground; a capacitor connected between the gate of the output transistor and the output terminal; a charge / discharge circuit configured to charge or discharge the gate of the output transistor in response to an input signal, and generating an output signal corresponding to the input signal at the output terminal by turning on or off the output transistor through charging or discharging the gate of the output transistor; the reverse current prevention diode has a forward direction from the application terminal of the power supply voltage toward the output terminal, The charge / discharge circuit sets a charging current and a discharging current for the gate of the output transistor as a current to be adjusted, and changes the current to be adjusted nonlinearly in response to the power supply voltage. , signal transmitting device.

2. The charge / discharge circuit sets the current to be adjusted to be larger when the power supply voltage has a second voltage value that is greater than the first voltage value, as compared with when the power supply voltage has a first voltage value, and provides a nonlinear relationship between the power supply voltage and the current to be adjusted.

2. A signal transmitting device according to claim 1.

3. The charge / discharge circuit maintains the value of the current to be regulated at a predetermined reference current value when the power supply voltage is equal to or lower than a predetermined boundary voltage, and increases the value of the current to be regulated above the reference current value and with an increase in the power supply voltage when the power supply voltage exceeds the boundary voltage.

2. A signal transmitting device according to claim 1.

4. the power supply voltage falls within a voltage range from a predetermined minimum voltage to a predetermined maximum voltage; the charge / discharge circuit changes the current to be adjusted in response to the power supply voltage to make the first value higher than the second value; the first value is a value obtained by dividing a slew rate of the output signal when the power supply voltage is equal to the minimum voltage by the minimum voltage, The second value is a value obtained by dividing the slew rate of the output signal when the power supply voltage is equal to the maximum voltage by the maximum voltage. A signal transmitting device according to any one of claims 1 to 3.

5. the charge / discharge circuit turns on the output transistor by charging a gate of the output transistor when the input signal has a first level, and turns off the output transistor by discharging the gate of the output transistor when the input signal has a second level; The charge / discharge circuit includes a charging circuit configured to supply the charging current to the gate of the output transistor during a period when the input signal has a first level, and a discharging circuit configured to sink the discharging current from the gate of the output transistor during a period when the input signal has a second level. A signal transmitting device according to any one of claims 1 to 3.

6. The drain of the output transistor is connected to the output terminal via another backflow prevention diode having a forward direction from the output terminal to the ground, or the drain of the output transistor is directly connected to the output terminal. A signal transmitting device according to any one of claims 1 to 3.