Layered ceramic capacitor

Abstract

Provided is a layered ceramic capacitor that makes it possible to improve moistureproofing reliability.　In the present invention, a multi-layer ceramic capacitor 1 comprises a laminate 2 and an external electrode 3. The laminate 2 has an inner layer portion 11, a first side margin portion 20A and a second side margin portion 20B that are positioned on both sides of the inner layer portion 11 in the width direction W, and a pair of outer layer portions 12 that are positioned on both sides of the inner layer portion 11 in the lamination direction T and are positioned so as to be sandwiched between the side margin portions 20. The layered ceramic capacitor 1 comprises a first cover region 4A and a second cover region 4B that are made from an inorganic material and are positioned so as to span across the boundary between the first side margin portion 20A or the second side margin portion 20B and the outer layer portion 12 on the outer surface of the laminate 2. End surfaces C of the layered ceramic capacitor 1 each have a non-covered portion Ca that is not covered by the cover regions 4, said end surfaces C being connected to the external electrode 3 at the non-covered portions Ca.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, efforts have been made to reduce the size and increase the capacitance of multilayer ceramic electronic components such as multilayer ceramic capacitors. In order to achieve this reduction in size and increase the capacitance of multilayer ceramic capacitors, it is effective to increase the areas of the mutually opposing internal electrode layers by thinning the side margins on each side of a laminate in which a plurality of dielectric ceramic layers and a plurality of internal electrode layers are stacked.

[0003] For example, Patent Documents 1 and 2 describe a method of retrofitting a side margin to a laminated chip with internal electrodes exposed on the side surfaces to ensure insulation around the internal electrodes, which makes it possible to make the side margin thinner and increase the crossing area of ​​the internal electrodes relatively large.

[0004] JP 2012-191159 A JP 2014-204116 A

[0005] However, in the multilayer ceramic capacitors of Patent Documents 1 and 2, there is a risk that moisture may penetrate into the interior of the laminate through the boundary between the laminate and the side margin, which may result in a decrease in the moisture resistance reliability of the multilayer ceramic capacitor.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that can improve the moisture resistance reliability.

[0007] The multilayer ceramic capacitor of the present invention is a multilayer ceramic capacitor comprising: a laminate including an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately laminated, the laminate having a pair of main surfaces facing each other in the lamination direction, a pair of end faces facing each other in a length direction perpendicular to the lamination direction, and a pair of side faces facing each other in a width direction perpendicular to both the lamination direction and the length direction; and a pair of external electrodes respectively disposed on each of the end faces and connected to the internal electrode layers, wherein the laminate has a pair of side margin portions respectively disposed on both sides of the inner layer portion in the width direction, and a pair of outer layer portions respectively disposed on both sides of the inner layer portion in the lamination direction and sandwiched between the side margin portions. the pair of side surfaces are a first side surface and a second side surface, the pair of side margin portions are a first side margin portion arranged on the first side surface and a second side margin portion arranged on the second side surface, and the laminate is provided with a first cover region made of an inorganic material, arranged on the outer surface of the laminate so as to straddle the boundary between the first side margin portion and each of the outer layer portions, and a second cover region made of an inorganic material, arranged on the outer surface of the laminate so as to straddle the boundary between the second side margin portion and each of the outer layer portions, and each of the end faces has an uncovered portion that is not covered by either the first cover region or the second cover region, and is connected to each of the external electrodes at each of the uncovered portions.

[0008] According to the present invention, moisture can penetrate into the interior of the multilayer ceramic capacitor through the boundaries between each side margin portion and each outer layer portion, thereby improving the moisture resistance reliability of the multilayer ceramic capacitor.

[0009] Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor taken along line III-III in Fig. 1. Fig. 4 is a schematic perspective view of a state in which a cover region is provided on a laminate. Fig. 5 is a view showing a manufacturing process of a multilayer ceramic capacitor. Fig. 6 is a view showing a manufacturing process of a multilayer ceramic capacitor. Fig. 7 is a view corresponding to Fig. 2 showing the configuration of a multilayer ceramic capacitor according to a modified example of the present invention.

[0010] Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

[0011] (Multilayer Ceramic Capacitor 1) As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2.

[0012] In the following description, the terms used to represent the orientation of the multilayer ceramic capacitor 1 are: a length direction L, which is the direction in which a pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1; a stacking direction T, which is the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked; and a width direction W, which is the direction intersecting both the length direction L and the stacking direction T. In the embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.

[0013] In the following description, of the six outer peripheral surfaces of the laminate 2 shown in FIG. 1 , a pair of outer surfaces facing each other in the stacking direction T will be referred to as two main surfaces A, a pair of outer surfaces facing each other in the width direction W will be referred to as two side surfaces B, and a pair of outer surfaces facing each other in the length direction L will be referred to as two end surfaces C. Of the two main surfaces A, one will be referred to as a first main surface AA, and the other will be referred to as a second main surface AB (see FIG. 2 ). Of the two end surfaces C, one will be referred to as a first end surface CA, and the other will be referred to as a second end surface CB. When it is not necessary to particularly distinguish between the first main surface AA and the second main surface AB, they will be collectively referred to as the main surface A. When it is not necessary to particularly distinguish between the first end surface CA and the second end surface CB, they will be collectively referred to as the end surface C.

[0014] (Laminate 2) The laminate 2 includes a laminate chip 10 and a side margin portion 20. The laminate 2 has a rectangular parallelepiped shape. It is preferable that the corners and ridges of the laminate 2 are rounded. The corners are portions where three surfaces of the laminate intersect, and the ridges are portions where two surfaces of the laminate intersect.

[0015] (Laminated chip 10) The laminated chip 10 includes an inner layer portion 11 and outer layer portions 12 disposed on both main surface A sides of the inner layer portion 11. Of the outer layer portions 12, the one disposed on the first main surface AA side is referred to as the first outer layer portion 12A, and the one disposed on the second main surface AB side is referred to as the second outer layer portion 12B. Hereinafter, unless there is a particular need to distinguish between them, the first outer layer portion 12A and the second outer layer portion 12B will be collectively referred to as the "outer layer portion 12."

[0016] (Inner Layer Portion 11) The inner layer portion 11 is configured by laminating a plurality of dielectric layers 14 and a plurality of internal electrode layers 15.

[0017] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material, more specifically, a dielectric ceramic material. The dielectric layer 14 includes ceramic particles. These ceramic particles are particles (main crystal particles) that are the main component of the dielectric layer 14, and are made of a compound having a perovskite structure containing Ba and Ti. In other words, the dielectric layer 14 is a sintered polycrystalline body whose main component is a compound having a perovskite structure.

[0018] The dielectric layer 14 may contain an additive other than the main component. The additive may be, for example, at least one element selected from the group consisting of Si, Mg, Ba, and Mn. In the dielectric layer 14, the additive is present, for example, between the ceramic particles.

[0019] The thickness of the dielectric layer 14 is preferably 0.2 μm or more and 0.8 μm or less, and more preferably 0.2 μm or more and 0.55 μm or less, which allows the number of layers to be increased even for a laminate 2 of the same size, thereby ensuring capacitance.

[0020] (Internal electrode layer 15) The internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are arranged alternately. Note that the first internal electrode layers 15A and the second internal electrode layers 15B will be collectively referred to as the internal electrode layers 15 unless there is a particular need to distinguish between them.

[0021] The internal electrode layers 15 are preferably made of a metal material such as Ni, Cu, Ag, Pd, an Ag—Pd alloy, or Au.

[0022] The first internal electrode layer 15A includes a first opposing portion 152a opposing the second internal electrode layer 15B, and a first lead portion 151a led from the first opposing portion 152a toward the first end face CA. An end of the first lead portion 151a is exposed at the first end face CA and is electrically connected to a first external electrode 3A described below.

[0023] The second internal electrode layer 15B includes a second opposing portion 152b opposing the first internal electrode layer 15A, and a second lead portion 151b extending from the second opposing portion 152b to the second end face CB. An end of the second lead portion 151b is electrically connected to a second external electrode 3B described below.

[0024] According to the above internal electrode layers 15, charges are accumulated in the first opposing portions 152a of the first internal electrode layers 15A and the second opposing portions 152b of the second internal electrode layers 15B, and the characteristics of a capacitor are exhibited.

[0025] Each end of the internal electrode layer 15 on the first side face BA side is flush with the surface of the inner layer portion 11 on the first side face BA side. Each end of the internal electrode layer 15 on the second side face BB side is flush with the surface of the inner layer portion 11 on the second side face BB side.

[0026] The thickness of each of the internal electrode layers 15 is preferably 0.2 μm or more and 2.0 μm or less, and more preferably 0.2 μm or more and 0.5 μm or less. This allows the number of layers to be increased even for laminates 2 of the same size, thereby ensuring capacitance. In addition, the number of internal electrode layers 15 is preferably 15 or more and 1,000 or less.

[0027] (Outer layer portion 12) The outer layer portion 12 can be made of a dielectric ceramic material. The outer layer portion 12 may be made of the same dielectric ceramic material as the dielectric layer 14 of the inner layer portion 11, or may be made of a dielectric ceramic material different from that of the dielectric layer 14 of the inner layer portion 11. The thickness of each outer layer portion 12 is set to be 15 μm or more and 60 μm or less.

[0028] Each of the outer layer portions 12 may have a multi-layer structure. When the outer layer portion 12 contains Si, the outer layer portion 12 may have a segregated portion of Si. In such a case, it is preferable that, of the multiple layers constituting one outer layer portion 12, the layer located farther from the inner layer portion 11 has a larger amount of segregated Si than the layer located closest to the inner layer portion 11. This can improve the flexural strength of the multilayer ceramic capacitor 1 in the stacking direction T.

[0029] The total number of dielectric layers 14, internal electrode layers 15 and outer layer portions 12 (i.e., the number of layers stacked in the laminate 2) is preferably, for example, 15 or more and 1000 or less.

[0030] (Side margin portion 20) The side margin portion 20 can be made of a dielectric ceramic material. The side margin portion 20 may be made of the same dielectric ceramic material as the dielectric layer 14 of the inner layer portion 11, or may be made of a dielectric ceramic material different from that of the dielectric layer 14 of the inner layer portion 11. The side margin portion 20 is provided on each of both side surfaces B of the portion where the inner layer portion 11 and the outer layer portion 12 are stacked. The side margin portion 20 sandwiches the outer layer portion 12 in the stacking direction T. The side margin portion 20 covers the widthwise W-side ends of the internal electrode layers 15 exposed on both side surfaces of the laminate chip 10 along those ends.

[0031] Of the side margin portions 20, the portion located on the first side surface BA side is referred to as the first side margin portion 20A, and the portion located on the second side surface BB side is referred to as the second side margin portion 20B. When there is no particular need to distinguish between the first side margin portion 20A and the second side margin portion 20B, they may be collectively referred to as the "side margin portion 20."

[0032] The dimension of the width direction W of the first side margin portion 20A is preferably 5 μm or more and 40 μm or less, and more preferably 5 μm or more and 20 μm or less. The dimension of the width direction W of the second side margin portion 20B is preferably 5 μm or more and 40 μm or less, and more preferably 5 μm or more and 20 μm or less. This allows the capacitance of the multilayer ceramic capacitor 1 to be increased while ensuring the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0033] The width W of the first side margin 20A and the second side margin 20B can be measured, for example, by observing the WT cross section of the laminate 2 exposed by polishing with a scanning electron microscope. Each value is obtained by averaging measurements taken at multiple locations in the stacking direction T.

[0034] The first side margin 20A is composed of multiple layers, specifically, two layers (see FIG. 3). The first side margin 20A has a first inner layer 21A, which is positioned closer to the inner layer 11 of the two layers, and a first outer layer 22A, which is positioned farther away from the inner layer 11 of the multiple layers.

[0035] The second side margin portion 20B is composed of multiple layers, specifically, two layers: a second inner layer 21B that is positioned closer to the inner layer portion 11 of the two layers, and a second outer layer 22B that is positioned farther away from the inner layer portion 11 of the two layers.

[0036] In the following description, the first inner layer 21A and the second inner layer 21B may be collectively referred to as the "inner layer 21" unless there is a need to distinguish between them. The first outer layer 22A and the second outer layer 22B may be collectively referred to as the "outer layer 22" unless there is a need to distinguish between them.

[0037] The side margin portion 20 is not limited to a two-layer structure, but may have a single-layer structure or may be composed of three or more layers. When the side margin portion 20 is composed of three or more layers, the layer of the side margin portion 20 that is positioned closest to the inner layer portion 11 is referred to as the inner layer, and the layer of the multiple layers that is positioned furthest from the inner layer portion 11 is referred to as the outer layer. The first side margin portion 20A and the second side margin portion 20B may have different numbers of layers.

[0038] When the side margin portion 20 has a two-layer structure including an inner layer and an outer layer, the difference in sinterability between the inner layer and the outer layer can be observed using an optical microscope in a dark field to confirm that it has a two-layer structure and to confirm the interface between the layers. The same applies when the side margin portion 20 has a structure of three or more layers. Note that the inner layer and the outer layer may not be recognizable as a two-layer structure after sintering. Even when they cannot be recognized as a two-layer structure, they may be distinguishable as two regions based on differences in the type and content of elements.

[0039] (Ceramic Grains) The dielectric layers 14, the outer layer portions 12, and the side margin portions 20 may contain ceramic grains. In this case, interfacial resistance occurs at the interfaces between the ceramic grains, which can increase the insulation resistance between the internal electrode layers 15. As a result, the occurrence of short circuits in the multilayer ceramic capacitor 1 can be suppressed.

[0040] It is preferable that rare earth elements are present at the interfaces of the ceramic grains. The presence of rare earth elements at the interfaces of the ceramic grains can be confirmed by elemental analysis using TEM-EDX. Examples of rare earth elements include La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y. The presence of rare earth elements at the interfaces of the ceramic grains can further increase the interface resistance of the dielectric ceramic layer. This can further improve the reliability of the multilayer ceramic capacitor. Note that Mg, Mn, Si, and the like may also be present.

[0041] The rare earth element is preferably present in an amount of 0.2 mol % or more and 5 mol % or less relative to 100 mol of Ti. The 100 mol of Ti mentioned here means that the dielectric ceramic material constituting the dielectric ceramic layer has a perovskite structure (ABO ３ The amount of rare earth element present relative to 100 moles of Ti is determined on the premise that the main component is a compound having a structure represented by the formula: where B=Ti. The amount of rare earth element present can be confirmed by TEM-EDX.

[0042] (Composition of laminate 2) When the dielectric layer 14, the outer layer portion 12, and the side margin portion 20 are made of dielectric ceramic, the composition of at least one of the dielectric ceramic layers constituting the dielectric layer 14, the dielectric ceramic layers constituting the outer layer portion 12, and the dielectric ceramic layers constituting the side margin portion 20 may be different from the composition of the other dielectric ceramic layers.

[0043] The dielectric layers 14, the outer layer portions 12, and the side margin portions 20 all have different purposes for their placement and different characteristics required for their manufacturing methods. Therefore, by making the composition of at least one of the dielectric ceramic layers constituting each of the dielectric layers 14, the outer layer portions 12, and the side margin portions 20 different from the composition of the others, it is possible to achieve an optimal composition according to the location where they are placed. This can improve the reliability of the multilayer ceramic capacitor 1.

[0044] In addition, when the side margin portion 20 is composed of multiple dielectric ceramic layers, the multiple dielectric ceramic layers that make up the side margin portion 20 may have the same composition or different compositions.

[0045] When the composition of any one of the plurality of dielectric ceramic layers constituting the side margin portion 20 is different from that of the dielectric layer 14, it can be said that the composition of the side margin portion 20 is different from that of the dielectric layer 14. Also, when the composition of any one of the plurality of dielectric ceramic layers constituting the side margin portion 20 is different from that of the outer layer portion 12, it can be said that the composition of the side margin portion 20 is different from that of the outer layer portion 12.

[0046] Among the dielectric ceramic layers constituting the dielectric layer 14, the dielectric ceramic layers constituting the outer layer portion 12, and the dielectric ceramic layers constituting the side margin portion 20, it is preferable that the dielectric ceramic layers having different compositions have a common main component with the other dielectric ceramic layers but different additives. ３ , CaTiO ３ or SrTiO ３ The additive elements are preferably Si, Mg, Mn, Sn, Cu, rare earth elements, Ni, and Al. The dielectric ceramic layers constituting the dielectric layer 14, the dielectric ceramic layers constituting the outer layer portion 12, and the dielectric ceramic layers constituting the side margin portion 20 may contain two or more of the additive elements.

[0047] Here, "same composition" means that the types of elements contained in the dielectric ceramic constituting each dielectric ceramic layer are the same, and the contents (molar ratios) of other elements relative to Ti are all within ±0.5%. Differences in the diameter of the ceramic grains constituting each dielectric ceramic layer and differences in porosity are not included in the differences in the composition of the dielectric ceramic layers.

[0048] The composition of each dielectric ceramic layer can be determined by cutting the multilayer ceramic capacitor 1 to expose the dielectric ceramic layer and performing elemental analysis on the cut surface using wavelength dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (TEM-EDX). At this time, the composition of each dielectric ceramic layer is measured at five points and the average value is calculated.

[0049] When the side margin portion 20 has a multilayer structure, the composition of each layer is measured at five locations, and the composition is the sum of the values ​​obtained by multiplying the composition by the proportion of the thickness (i.e., the dimension in the width direction W) that each layer occupies in the side margin portion 20. Note that when element segregation is observed near the interface with another dielectric ceramic layer or internal electrode layer 15, the location where element segregation is observed is not subject to WDX measurement.

[0050] (Additive Element) Mg is a preferred additive element to be added to the dielectric layers 14 and the outer layer portions 12. The Mg content in the dielectric layers 14 and the outer layer portions 12 is preferably 0.05 mol % or more and 3.0 mol % or less per 100 mol of Ti. This increases the relative dielectric constant of the dielectric layers 14, thereby improving the capacitance of the multilayer ceramic capacitor 1. Note that there are cases where it is preferable for the Mg content in the dielectric layers 14 and the outer layer portions 12 to be as small as possible.

[0051] Si is preferred as an element of the additive added to the side margin portion 20. The Si content in the side margin portion 20 is preferably 0.05 mol % or more and 5.0 mol % or less relative to 100 mol of Ti. The Si content in the side margin portion 20 is preferably higher than the Si content in the dielectric layer 14 and the outer layer portion 12. By increasing the Si content in the side margin portion 20, the sinterability of the side margin portion 20 can be improved, and deterioration of the internal electrode layer 15 due to penetration of moisture or the like from the side surface B of the laminate 2 can be suppressed.

[0052] Mg is preferred as an element of the additive added to the side margin portion 20. The Mg content in the side margin portion 20 is preferably 0.05 mol % or more and 5.0 mol % or less relative to 100 mol of Ti. The Mg content in the side margin portion 20 is preferably higher than the Mg content in the dielectric layer 14 and the outer layer portion 12. By increasing the Mg content in the side margin portion 20, grain growth of the ceramic grains contained in the side margin portion 20 can be suppressed, making it less likely that a short circuit will occur between the internal electrode layers 15.

[0053] Mn is preferred as an element of the additive added to the side margin portion 20. The Mn content in the side margin portion 20 is preferably 0.01 mol % or more and 3.0 mol % or less relative to 100 mol of Ti. The Mn content in the side margin portion 20 is preferably higher than the Mn content in the dielectric layer 14 and the outer layer portion 12. Increasing the Mn content in the side margin portion 20 can suppress the grain growth of ceramic grains contained in the side margin portion 20, thereby making it less likely for short circuits to occur between the internal electrode layers 15.

[0054] (Segregation of Elements) In the side margin portion 20, elements derived from the dielectric layer 14 may be segregated in the vicinity of the interface with the dielectric layer 14. In the side margin portion 20, elements derived from the outer layer portion 12 may be segregated in the vicinity of the interface with the outer layer portion 12.

[0055] In the internal electrode layer 15, an element derived from the dielectric layer 14 may be segregated in the vicinity of the interface with the dielectric layer 14. The segregated element is preferably Ni. In the internal electrode layer 15, an element derived from the outer layer portion 12 may be segregated in the vicinity of the interface with the outer layer portion 12. The segregated element is preferably Ni.

[0056] In the internal electrode layer 15, Si is segregated near the interface with the side margin portion 20. In the internal electrode layer 15, a Si segregation region is formed in the range where the distance from the end on the side margin portion 20 side to the center side in the width direction W is within 0.5 μm. This improves the flexural strength of the internal electrode layer 15.

[0057] (Porosity of Laminate 2) The porosity of the dielectric layer 14, the porosity of the outer layer portion 12, and the porosity of the side margin portion 20 may be the same or different from each other.

[0058] To calculate these void ratios, the multilayer ceramic capacitor 1 is cut to expose the dielectric layers 14, outer layer portions 12, and side margin portions 20, and the cut surface is observed at 20,000x magnification using a scanning electron microscope (SEM). Five areas with a field of view of 6.3 μm × 4.4 μm are photographed so that no overlapping areas exist, and the ratio of the area occupied by voids to the entire field of view is calculated from each obtained SEM image by image analysis. The average of the calculated ratios over the five fields of view is taken as the void ratio.

[0059] However, if the side margin portion 20 is composed of multiple layers, the void ratio of each layer is determined individually, and then the sum of the products of the width direction W dimension of each layer divided by the width direction W dimension of the side margin portion 20 and the void ratio of each layer is determined to be the void ratio of the side margin portion 20.

[0060] (Comparison between inner layer 21 and outer layer 22) (Regarding element content) The Si content of the outer layer 22 is greater than the Si content of the inner layer 21. This improves the flexural strength of the side margin portion 20. Furthermore, since the occurrence of cracks or chips in the side margin portion 20 can be suppressed, the moisture resistance reliability of the multilayer ceramic capacitor 1 can be improved.

[0061] In the outer layer 22, Si is added so that the molar ratio of Si to 1 mole of Ti is 3.0 or more and 7.0 or less, while in the inner layer 21, Si is added so that the molar ratio of Si to 1 mole of Ti is 1.0 or more and 4.0 or less. In particular, the amount of segregated Si in the outer layer 22 is greater than the amount of segregated Si in the inner layer 21.

[0062] The content of Ba as an additive in the inner layer 21 is greater than the content of Ba as an additive in the outer layer 22. The content of Ba as an additive in the outer layer 22 is also greater than the content of Ba as an additive in the dielectric layer 14. In this way, the content of Ba as an additive in the inner layer 21, the content of Ba as an additive in the outer layer 22, and the content of Ba as an additive in the dielectric layer 14 are different from one another. The difference in Ba content can be confirmed by TEM analysis.

[0063] The Ba content in the inner layer 21 is adjusted so that the molar ratio of Ba to 1 mole of Ti is greater than 1.020 and less than 1.040 as a center value. The Ba content in the outer layer 22 is adjusted so that the molar ratio of Ba to 1 mole of Ti is greater than 1.01 and not more than 1.020 as a center value. The Ba content in the dielectric layer 14 is adjusted so that the molar ratio of Ba to 1 mole of Ti is greater than 0.99 and less than 1.01 as a center value.

[0064] The molar ratio can be confirmed by scraping off the surface vicinity of the inner layer 21, the outer layer 22, or the dielectric layer 14 from the multilayer ceramic capacitor 1, dissolving the obtained powder in acid, and performing ICP analysis on the solution.

[0065] The content of Ba as an additive in the inner layer 21 is in the range of more than 100% and less than 140% of the content of Ba as an additive in the outer layer 22 .

[0066] (Regarding voids) The side margins 20 are formed so that the voids decrease from the inner layer portion 11 side toward the side away from the inner layer portion 11. The voids in the outer layer 22 are fewer than the voids in the inner layer 21. This makes it possible to prevent moisture and the like from penetrating into the interior of the laminate 2 through the side margins 20, thereby improving the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0067] (Regarding Additives) It is preferable that the elements contained as additives in the inner layer 21 are different from the elements contained as additives in the outer layer 22. In this case, the inner layer 21 can improve the adhesion between the side margin portion 20 and the inner layer portion 11, while the outer layer 22 can suppress the penetration of moisture into the multilayer ceramic capacitor 1.

[0068] It is considered that there may be cases where the inner layer 21 and the outer layer 22 cannot be visually distinguished from each other. Even in such cases, the inner layer 21 and the outer layer 22 can be distinguished from each other based on the types of elements contained therein, the amount of each element contained therein, and the like.

[0069] (Regarding the Dimension in the Width Direction W) The dimension in the width direction W of the outer layer 22 is preferably larger than the dimension in the width direction W of the inner layer 21. This can significantly enhance the effect of the outer layer 22 in suppressing moisture penetration.

[0070] It is preferable that the dimension in the width direction W of the outer layer 22 is 5 μm or more and 20 μm or less, and the dimension in the width direction W of the inner layer 21 is 0.1 μm or more and 20 μm or less, thereby effectively improving the moisture resistance reliability of the multilayer ceramic capacitor 1 while increasing the adhesion between the side margin portion 20 and the inner layer portion 11.

[0071] (External electrode 3) The external electrode 3 includes a first external electrode 3A provided on a first end face CA of the laminate 2 and a second external electrode 3B provided on a second end face CB of the laminate 2. Note that, unless there is a particular need to distinguish between the first external electrode 3A and the second external electrode 3B, they will be collectively referred to as the external electrode 3. The external electrode 3 covers not only the end face C but also a portion of the main face A and the side face B on the end face C side.

[0072] The external electrode 3 includes a base electrode layer 31 and a plating layer 32 (see FIG. 2).

[0073] The base electrode layer 31 may include, for example, at least one of a baked layer, a conductive resin layer, and a thin film layer. The base electrode layer 31 may be disposed at least on the end face C, and may not extend onto the main face A or the side face B.

[0074] When the baking layer is used as the base electrode layer 31, the baking layer contains a glass component and a metal. The baking layer, which will be described in detail later, is formed by applying and baking a conductive paste containing a conductive metal and glass.

[0075] The glass component of the baking layer may contain an oxide containing at least one element selected from the group consisting of B, Si, Ba, Mg, Al, and Ti. The oxide may be SiO ２ , Al ２ O ３ , TiO ２ , BaO ２ or ZrO ２ The glass component of the baking layer more preferably contains an oxide containing Ba or Ti, and the oxide is BaO ２ or TiO ２ The glass component is preferably BaO ２ or TiO ２ When the resin contains the above, the content of impurities is small and the resin has excellent flexibility.

[0076] The metal of the baked layer can be, for example, at least one metal selected from the group consisting of Cu, Ni, Ag, Pd, an Ag-Pd alloy, and Au.

[0077] The portions of the baked layer disposed on the end faces C preferably have a thickness (dimension in the length direction L) of 3 μm or more and 100 μm or less at the center as viewed in the stacking direction T.

[0078] The portions of the baked layer disposed on the main surface A preferably have a thickness at the center in the length direction L (dimension in the stacking direction T) of 3 μm or more and 70 μm or less.

[0079] The portions of the baking layer disposed on the side surface B preferably have a thickness of 3 μm or more and 70 μm or less at the center as viewed in the longitudinal direction L.

[0080] When a conductive resin layer is used as the base electrode layer 31, the conductive resin layer contains a metal and a thermosetting resin.

[0081] The metal of the conductive resin layer provides electrical conductivity to the conductive resin layer, and may be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these.

[0082] The metal of the conductive resin layer can also be a metal powder with an Ag coating on its surface. The coated metal powder (base material) is preferably Cu, Ni, Sn, Bi, or an alloy containing any of these. In this case, the properties of Ag, such as low resistivity and resistance to oxidation, can improve the performance of the base electrode layer 31. Furthermore, using an inexpensive metal as the base material can help prevent costs from rising.

[0083] The metal of the conductive resin layer may be Cu or Ni that has been subjected to an anti-oxidation treatment.

[0084] The metal of the conductive resin layer may be a metal powder whose surface is coated with Si, Ni, or Cu. Preferably, the metal powder (base material) to be coated is Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these.

[0085] The metal of the conductive resin layer can be, for example, a spherical metal powder or a flat metal powder. It is preferable to use a mixture of spherical metal powder and flat metal powder as the metal of the conductive resin layer.

[0086] The thermosetting resin provides flexibility to the conductive resin layer, which allows the conductive resin layer to function as a suitable buffer layer when a physical impact or an impact due to a thermal cycle is applied to the multilayer ceramic capacitor 1. This makes it possible to suppress the occurrence of cracks in the multilayer ceramic capacitor 1.

[0087] The thermosetting resin may be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin. The thermosetting resin is preferably an epoxy resin. Epoxy resins have excellent heat resistance, moisture resistance, and adhesion, and therefore can further improve the performance of the conductive resin layer.

[0088] The conductive resin layer preferably contains a curing agent, which may be any of various known compounds such as phenolic compounds, amine compounds, acid anhydride compounds, imidazole compounds, active ester compounds, and amide-imide compounds when the thermosetting resin is an epoxy resin.

[0089] The conductive resin layer preferably has a thickness of 10 μm or more and 150 μm or less at its thickest portion.

[0090] The conductive resin layer may be provided directly on the laminate 2, or may be provided on the outside of a baked layer that is provided on the laminate 2. When the conductive resin layer is provided on the outside of the baked layer, the conductive resin layer may completely cover the outside of the baked layer, or may only partially cover the outside of the baked layer.

[0091] The conductive resin layer may have a single layer structure or a multi-layer structure.

[0092] When the base electrode layer 31 is a thin film layer, the thin film layer is a layer on which metal particles are deposited. The thin film layer has a thickness of 1 μm or less. The thin film layer is formed by a thin film formation method such as a sputtering method or a vapor deposition method, which will be described in detail later.

[0093] The plating layer 32 contains at least one metal selected from the group consisting of, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0094] The plating layer 32 has a first plating layer 321 disposed on the base electrode layer 31 and a second plating layer 332 disposed on the first plating layer 321. Note that the plating layer 32 does not necessarily have a two-layer structure, and may have a single-layer structure or a multi-layer structure of three or more layers.

[0095] The first plating layer 331 is preferably a Ni plating layer, which can prevent the base electrode layer 31 from being eroded by solder when the multilayer ceramic capacitor 1 is mounted on the circuit board 50. The thickness of the first plating layer 331 is preferably 1 μm or more and 15 μm or less.

[0096] The second plating layer 332 is preferably a Sn plating layer, which improves the wettability of solder when mounting the multilayer ceramic capacitor 1 on the circuit board 50, facilitating mounting of the multilayer ceramic capacitor 1. The thickness of the second plating layer 332 is preferably 1 μm or more and 15 μm or less.

[0097] (Covered Area 4) In the multilayer ceramic capacitor 1, there is a risk of moisture or the like penetrating into the interior of the multilayer ceramic capacitor 1 through the boundary between the side margin portion 20 and the laminate chip 10. Therefore, the multilayer ceramic capacitor 1 is provided with a covered area 4. Note that in each drawing, the covered area 4 is indicated by dot hatching.

[0098] The cover region 4 is made of an inorganic material. The inorganic material making up the cover region 4 contains at least one element selected from the group consisting of Si, Ti, Ba, and Zr. This ensures the density of the cover region 4, thereby preventing moisture and other contaminants from penetrating the cover region 4. The inorganic material making up the cover region 4 is preferably Si. This allows for improved moisture resistance with baking at a lower temperature.

[0099] The coverage area 4 includes a first coverage area 4 A and a second coverage area 4 B. Hereinafter, the first coverage area 4 A and the second coverage area 4 B may be collectively referred to as the “coverage area 4” unless there is a need to particularly distinguish between them.

[0100] The first cover region 4A is strip-shaped and is arranged on the main surface A of the laminate 2 so as to straddle the boundary between the first side margin portion 20A and the outer layer portion 12, and is also arranged on the end surface C of the laminate 2 so as to straddle the boundary between the first side margin portion 20A and the inner layer portion 11. The first cover region 4A has an annular shape that goes around in the length direction L (see FIG. 4 ). The first cover region 4A covers the entire boundary between the first side margin portion 20A and the outer layer portion 12. The first cover region 4A covers the entire boundary between the first side margin portion 20A and the inner layer portion 11.

[0101] The second cover region 4B is strip-shaped and is arranged on the outer surface of the laminate 2 so as to straddle the boundary between the second side margin portion 20B and the outer layer portion 12, and is also arranged on the end face C of the laminate 2 so as to straddle the boundary between the second side margin portion 20B and the inner layer portion 11. The second cover region 4B is annular and extends in the longitudinal direction L. The second cover region 4B covers the entire boundary between the second side margin portion 20B and the outer layer portion 12. The second cover region 4B covers the entire boundary between the second side margin portion 20B and the inner layer portion 11.

[0102] This makes it possible to prevent moisture and other substances from penetrating into the interior of the multilayer ceramic capacitor 1 through the boundary between the side margin portion 20 and the laminate chip 10, thereby improving the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0103] The thickness of the first cover region 4A is preferably 1 μm or more and 10 μm or less, and the thickness of the second cover region 4B is preferably 1 μm or more and 10 μm or less, thereby enabling the multilayer ceramic capacitor 1 to be made low-profile while improving the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0104] The first end face CA has a first uncovered portion CAa that is not covered by either the first cover area 4A or the second cover area 4B. The first end face CA is connected to the first external electrode 3A at the first uncovered portion CAa.

[0105] The second end face CB has a second uncovered portion CBa that is not covered by either the first cover region 4A or the second cover region 4B. The second end face CB is connected to the second external electrode 3B at the second uncovered portion CBa.

[0106] In the following description, the first uncoated portion CAa and the second uncoated portion CBa may be collectively referred to as "uncoated portion Ca" unless there is a particular need to distinguish between them.

[0107] The dimension in the width direction W of the first cover region 4A is preferably 10% or more and 20% or less of the dimension in the width direction W of the laminate 2. The dimension in the width direction W of the second cover region 4B is preferably 10% or more and 20% or less of the dimension in the width direction W of the laminate 2. This makes it possible to improve the moisture resistance reliability of the multilayer ceramic capacitor 1 while sufficiently ensuring the connection between the end faces C and the external electrodes 3.

[0108] The shape of the boundary line between the cover region 4 and the laminate 2 is not particularly limited. The boundary line between the cover region 4 and the laminate 2 can sometimes be confirmed by observing the cover region 4 and the laminate 2 using an optical microscope in a dark field. If the boundary line can be confirmed, the cover region 4 can also be recognized as a cover layer. On the other hand, there are cases where the cover region 4 and the laminate 2 are integrated, making it impossible to confirm the boundary line between the cover region 4 and the laminate 2. In such cases, the main surface A and the side surface B of the laminate 2 are each considered to be flat surfaces, and the portion protruding from these flat surfaces is determined to be the cover region 4.

[0109] (Method for Manufacturing Multilayer Ceramic Capacitor) Next, a method for manufacturing the multilayer ceramic capacitor 1 will be described with reference to Fig. 5 to Fig. 7. Fig. 5 to Fig. 7 are all diagrams showing the manufacturing process of the multilayer ceramic capacitor.

[0110] The manufacturing process of the multilayer ceramic capacitor 1 includes a laminate manufacturing step, a cover region forming step, and an external electrode forming step.

[0111] (Stack Manufacturing Process) The stack manufacturing process includes a stack chip manufacturing process and a side margin portion forming process.

[0112] (Laminated Chip Manufacturing Process) First, ceramic green sheets for lamination are prepared by forming ceramic slurry into sheets. The ceramic green sheets for lamination contain ceramic raw materials including a dielectric ceramic material, a binder, and a solvent. Additives including rare earth elements may be added to the ceramic raw materials. By changing the elements contained in the additives, the compositions of the dielectric layer 14, the outer layer portion 12, and the side margin portion 20 can be made different from one another.

[0113] A conductive paste that will become the internal electrode layers is printed on the multilayer ceramic green sheets. The conductive paste is printed on the surfaces of the multilayer ceramic green sheets so that multiple stripes are aligned in the width direction of the stripes. The conductive paste can be printed by, for example, screen printing or gravure printing.

[0114] A predetermined number of ceramic green sheets not printed with conductive paste are stacked. Next, a predetermined number of ceramic green sheets printed with conductive paste are stacked while being alternately shifted in the direction in which the multiple conductive pastes are printed side by side. Next, a predetermined number of ceramic green sheets not printed with conductive paste are stacked. This produces a mother laminate.

[0115] The mother laminate is pressed. As a method for pressing the mother laminate, for example, a rigid press or an isostatic press can be used.

[0116] The pressed mother laminate is cut into a chip shape, thereby obtaining a laminate chip 10 as shown in Fig. 5(a) . Note that methods that can be used to cut the mother laminate include, for example, press cutting, dicing, and laser cutting.

[0117] Of the pair of end faces of the laminate chip 10, only the conductive paste that will become the first internal electrode layer 15A of the internal electrode layers 15 is exposed on one end face, and only the conductive paste that will become the second internal electrode layer 15B of the internal electrode layers 15 is exposed on the other end face. Both the conductive paste that will become the first internal electrode layer 15A and the conductive paste that will become the second internal electrode layer 15B are exposed on a pair of side faces of the laminate chip 10. On the pair of side faces of the laminate chip 10, the ends of the conductive paste on each side face of the laminate chip 10 and each side face of the laminate chip 10 are flush with each other.

[0118] (Side Margin Forming Step) An inner layer ceramic slurry for producing an inner layer ceramic green sheet is prepared. The inner layer ceramic slurry contains BaTiO ３ The ceramic slurry for the inner layer includes a dielectric ceramic material mainly composed of silicon, a binder, and a solvent. The ceramic slurry for the inner layer may contain Si as a sintering aid. The ceramic slurry for the inner layer may also contain a liquid-phase metal. The ceramic slurry for the inner layer may contain more rare earth elements, Mg, and Mn than the ceramic green sheets for forming the laminate chip 10.

[0119] An outer layer ceramic slurry is prepared for producing the outer layer ceramic green sheet. The outer layer ceramic slurry contains BaTiO ３ The outer layer ceramic slurry contains a dielectric ceramic material containing the above as a main component, a binder, and a solvent. The outer layer ceramic slurry may contain Si as a sintering aid.

[0120] The amount of Si contained in the ceramic sheet for the inner layer is preferably greater than the amount of Si contained in the ceramic sheet for the outer layer. The amount of Si contained in the ceramic sheet for the inner layer and the ceramic sheet for the outer layer is determined by imaging the cross sections of the ceramic sheet for the inner layer and the ceramic sheet for the outer layer by WDX and based on the area of ​​the region where Si is detected.

[0121] The outer layer ceramic slurry is applied to the surface of the resin film and dried. As a result, an outer layer ceramic green sheet 22a is formed on the resin film. The inner layer ceramic slurry is applied to the surface of the outer layer ceramic green sheet and dried. As a result, an inner layer ceramic green sheet 21a is formed on the outer layer ceramic green sheet. As a result of the above, a side margin ceramic green sheet 20a having a two-layer structure is obtained, as shown in FIG. 5(b).

[0122] The side margin ceramic green sheet 20a having a two-layer structure may be obtained, for example, by laminating together a pre-formed outer layer ceramic green sheet 22a and an pre-formed inner layer ceramic green sheet 21a.

[0123] The side margin ceramic green sheet 20a is peeled off from the resin film.

[0124] The side margin ceramic green sheet 20a is pressed against the laminate chip 10 with its inner layer side surface facing the surface on side B of the laminate chip 10, and is punched out by the laminate chip 10. This forms a side margin portion 20 in the laminate chip 10. As a result, the laminate 2 is obtained as shown in Figure 5(c). It is preferable that an organic solvent that will serve as an adhesive has been applied to the side surface of the laminate chip 10 in advance.

[0125] The laminate 2 is preferably subjected to barrel polishing or the like, so that the corners and ridges of the laminate 2 are rounded.

[0126] The laminate 2 is degreased in a nitrogen atmosphere. Then, the laminate 2 is fired in a mixed atmosphere of nitrogen, hydrogen, and water vapor. The temperature at which the laminate 2 is fired is preferably, for example, 900° C. or higher and 1300° C. or lower.

[0127] (Cover Region Forming Process) First, as shown in FIG. 6( a ), the laminate 2 is placed in a state where the second side surface BB faces downward.

[0128] As shown in FIG. 6( b), a paste bath filled with cover region paste P that will become the cover region 4 is prepared. The cover region paste P contains at least one of the inorganic materials Si, Ti, Ba, and Zr. The laminate 2 is dipped into the cover region paste P with the second side surface BB facing downward. At this time, a portion of the laminate 2 on the second side surface BB side is dipped into the cover region paste P. More specifically, a portion of the laminate 2 that includes at least the boundary between the laminate chip 10 and the second side margin portion 20B is dipped into the cover region paste P. At this time, the dimension of the width direction W of the cover region 4 can be adjusted by adjusting the depth to which the laminate 2 is dipped into the cover region paste P.

[0129] 6(c), the laminate 2 is pulled up from the paste bath filled with the cover region paste P. The laminate 2 is in a state in which the cover region paste P is applied to the entire second side surface BB, a portion of the main surface A on the second side surface BB side, and a portion of the end surface C on the second side surface BB side. The cover region paste P is arranged so as to straddle the boundary between the second side margin portion 20B and the outer layer portion 12. The cover region paste P is arranged so as to straddle the boundary between the second side margin portion 20B and the inner layer portion 11.

[0130] As shown in FIG. 7( a), any unnecessary cover area paste P arranged on the laminate 2 is wiped off. For example, the cover area paste P arranged on the second side surface BB is wiped off. The thickness and width direction W dimensions of the cover area 4 are also adjusted to the desired dimensions. Wiping off the cover area paste P is not essential and may be performed as needed. The cover area paste P is then dried to form the second cover area 4B. The drying temperature and drying time are appropriately set depending on the type of cover area paste P. As a result, the second cover area 4B is formed on the laminate 2. The orientation of the laminate 2 in FIG. 7( a) is the same as that of the laminate 2 in FIG. 6( c) rotated 180 degrees around the longitudinal direction L.

[0131] Thereafter, the above-described step of the cover area forming process is performed again with the orientation of the laminate 2 changed, thereby forming the first cover area 4A on the first side surface BA side of the laminate 2. As a result, the first cover area 4A and the second cover area 4B are formed on the laminate 2, as shown in Fig. 7(b) . Note that the order in which the first cover area 4A and the second cover area 4B are formed on the laminate 2 is not limited to the order described above. Also, the orientation of the laminate 2 in Fig. 7(b) is obtained by rotating the laminate 2 in Fig. 7(a) by 180 degrees around the longitudinal direction L as an axis.

[0132] (External electrode forming process) First, a base electrode layer 31 is formed on the end surface C of the laminate 2. For example, the base electrode layer 31 is formed as a baked layer. The end surface C of the laminate 2 is sequentially immersed in a conductive paste, which is an electrode material for the base electrode. In this way, the conductive paste is applied to each end surface C of the laminate 2. Then, this conductive paste is fired together with the laminate 2. The firing temperature is, for example, 700°C or higher and 900°C or lower. In this way, the base electrode layer 31 is formed on each end surface C of the laminate 2. The end surface of the laminate 2 and the base electrode layer 3 are connected at the uncovered portion Ca.

[0133] The baking layer may contain a ceramic component. In this case, the baking layer may contain a ceramic component instead of a glass component, or may contain both a glass component and a ceramic component. The ceramic component is preferably the same ceramic component as that of the laminate 2. When the baking layer contains a ceramic component, it is preferable that a conductive paste for the base electrode is applied to the laminate 2 before firing, and the laminate 2 and the conductive paste for the base electrode are fired simultaneously. The firing temperature is preferably 900°C or higher and 1300°C or lower.

[0134] Next, a first plating layer 321 is formed on the base electrode layer 31. The first plating layer 321 is formed so that the ends of the first plating layer 321 on the main surface A and side surface B side cover the ends of the base electrode layer 31 on the main surface A and side surface B side. The first plating layer 321 is, for example, a Ni plating layer. The first plating layer 321 can be formed by, for example, barrel plating.

[0135] Next, the second plating layer 332 is formed on the first plating layer 32. The second plating layer 332 is formed so that the ends of the second plating layer 332 on the main surface A and side surface B side cover the ends of the first plating layer 321 and the adhesion relaxation layer 35 on the main surface A and side surface B side. The second plating layer 322 is, for example, a Sn plating layer. The second plating layer 332 can be formed by, for example, barrel plating.

[0136] Through the above steps, a multilayer ceramic capacitor 1 is manufactured in which the external electrodes 3 are formed on the laminate 2, as shown in FIG. 7(c).

[0137] The base electrode layer 31 may be formed as a conductive resin layer. The conductive resin layer may be formed on the surface of the baked layer, or may be formed directly on the surface of the laminate 2.

[0138] First, a conductive paste containing a thermosetting resin and a metal component is applied onto the baking layer or the laminate 2. Next, a heat treatment is performed at a temperature of 250°C or higher and 550°C or lower. This solidifies the thermosetting resin to form a conductive resin layer. The heat treatment is preferably performed in a nitrogen atmosphere. During the heat treatment, the oxygen concentration is preferably 100 ppm or lower. This prevents the resin from scattering and also prevents the metal from oxidizing.

[0139] Alternatively, the base electrode layer 31 may be formed as a thin film layer. In this case, a layer of deposited metal particles is formed by a thin film formation method such as sputtering or vapor deposition. This results in a thin film layer. The thickness of the thin film layer is set to 1 μm or less.

[0140] Furthermore, the base electrode layer 31 is not an essential component, and a plating layer may be formed directly on the laminate 2. In this case, a base plating film is formed on each end face C of the laminate 2 by plating. The plating may be an electrolytic plating method or an electroless plating method. However, electrolytic plating is preferred because it is a simpler process. Barrel plating is preferred as the plating method. Furthermore, if necessary, a plating electrode may be further formed on the surface of the plating layer by a similar method.

[0141] (Effects) According to the above embodiment, the following effects can be obtained.

[0142] According to the above embodiment, the first cover region 4A is made of an inorganic material and is arranged on the outer surface of the laminate 2 so as to straddle the boundary between the first side margin portion 20A and the outer layer portion 12. The second cover region 4B is made of an inorganic material and is arranged on the outer surface of the laminate 2 so as to straddle the boundary between the second side margin portion 20B and the outer layer portion 12. This allows moisture to penetrate into the interior of the multilayer ceramic capacitor 1 through the boundary between the side margin portion 20A and the outer layer portion 12, thereby improving the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0143] According to the above embodiment, the inorganic material constituting the cover region 4 contains at least one element selected from the group consisting of Si, Ti, Ba, and Zr, thereby improving the density of the cover region 4. This effectively prevents moisture from penetrating into the multilayer ceramic capacitor 1, thereby effectively improving the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0144] According to the above embodiment, the first cover region 4A has an annular shape that goes around in the length direction L. The second cover region 4B has an annular shape that goes around in the length direction L. In this case, the cover region 4 can cover the entire boundary between the side margin portion 20 and the outer layer portion 12. It can also cover the entire boundary between the side margin portion 20 and the inner layer portion 11. This can effectively prevent moisture from penetrating into the multilayer ceramic capacitor, thereby effectively improving the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0145] According to the above embodiment, the thickness of the first cover region 4A is preferably 1 μm or more and 10 μm or less. The thickness of the second cover region 4B is preferably 1 μm or more and 10 μm or less. In this case, the height of the multilayer ceramic capacitor 1 can be reduced and the moisture resistance reliability of the multilayer ceramic capacitor 1 can be improved.

[0146] According to the above embodiment, the dimension in the width direction W of the first cover region 4A is preferably 10% or more and 20% or less of the dimension in the width direction W of the laminate 2. The dimension in the width direction W of the second cover region 4B is preferably 10% or more and 20% or less of the dimension in the width direction W of the laminate 2. In this case, the moisture resistance reliability of the multilayer ceramic capacitor 1 can be improved while sufficiently ensuring the connection between the end faces C and the external electrodes 3.

[0147] According to the above embodiment, the dimension of the first side margin portion 20A in the width direction W is preferably 5 μm or more and 40 μm or less. The dimension of the second side margin portion 20B in the width direction W is preferably 5 μm or more and 40 μm or less. In this case, the capacitance of the multilayer ceramic capacitor 1 can be increased while improving the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0148] In the side margin portion 20, for example, the surface of the side margin portion 20 facing the inner layer portion 11 desirably has high adhesion to the inner layer portion 11 in order to reliably fix the side margin portion 20 to the inner layer portion 11. The surface of the side margin portion 20 opposite the inner layer portion 11 does not need to have adhesion to the inner layer portion 11, but desirably can suitably prevent moisture from penetrating into the multilayer ceramic capacitor 1. In this way, the functions required of the portion of the side margin portion 20 facing the inner layer portion 11 are different from those required of the portion of the side margin portion 20 facing away from the inner layer portion 11.

[0149] According to the above embodiment, the side margin portion 20 is composed of two layers, the inner layer 21 being disposed closer to the inner layer portion 11, and the outer layer 22 being disposed farther from the inner layer portion 11. Therefore, for example, by varying the amount of resin contained in the inner layer 21 and the outer layer 22, it is possible to impart different properties to the inner layer 21 and the outer layer 22. This allows, for example, the inner layer 21 to improve adhesion between the side margin portion 20 and the inner layer portion 11, while the outer layer 22 can effectively suppress moisture penetration into the inner layer portion 11.

[0150] According to the above embodiment, it is preferable that the elements used as additives in the inner layer 21 are different from the elements used as additives in the outer layer 22. In this case, different properties can be imparted to the inner layer 21 and the outer layer 22, thereby improving the functionality of the side margin portion 20.

[0151] According to the above embodiment, the dimension of the outer layer 22 in the width direction W is preferably larger than the dimension of the inner layer 21 in the width direction W. In this case, the effect of the outer layer 22 in suppressing moisture penetration can be made more pronounced.

[0152] According to the above embodiment, the dimension in the width direction W of the inner layer 21 is preferably 0.1 μm or more and 20 μm or less. The dimension in the width direction W of the outer layer 22 is preferably 5 μm or more and 20 μm or less. In this case, it is possible to effectively improve the moisture resistance reliability of the multilayer ceramic capacitor 1 while increasing the adhesion between the side margin portion 20 and the inner layer portion 11.

[0153] According to the above embodiment, it is preferable that the thickness of each of the internal electrode layers 15 is 0.8 μm or less. In this case, the number of laminated layers can be increased even for laminates 2 of the same size, and therefore the capacitance of the multilayer ceramic capacitor 1 can be ensured.

[0154] Furthermore, according to the above embodiment, it is preferable that the thickness of each of the dielectric layers 14 is 0.55 μm or less. In this case, the number of laminated layers can be increased even for laminates 2 of the same size, thereby ensuring the capacitance of the multilayer ceramic capacitor 1.

[0155] (Experimental Example) A multilayer ceramic capacitor was fabricated as a sample using the manufacturing method according to the above embodiment. A moisture resistance test was performed on the sample. As an example, a multilayer ceramic capacitor including a first cover area and a second cover area was prepared. As a comparative example, a multilayer ceramic capacitor including neither the first cover area nor the second cover area was prepared.

[0156] Fifty samples were prepared for each of the example and comparative example.

[0157] The moisture resistance test was conducted based on the PCBT test method. More specifically, each sample was mounted on a wiring board using eutectic solder, and then placed in a high-temperature, high-humidity chamber at a temperature of 125°C and a relative humidity of 95%RH. A direct current of 2V was applied between the pair of external electrodes, and this condition was maintained for 72 hours. A sample whose insulation resistance value decreased by two orders of magnitude or more before and after the test was judged to be "failure."

[0158] (Configuration of Example) Dimensions of multilayer ceramic capacitor: L×W×T=1.0 mm×0.5 mm×0.5 mm Ceramic material of dielectric layer: BaTiO ３ ・Capacity: 22 μF ・Rated voltage: 4 V ・Metal material of internal electrode layer: Ni ・Structure of external electrode: Base electrode layer: baked layer Base electrode layer material: electrode containing conductive metal (Cu) and glass component Base electrode layer thickness: End face thickness: 20 μm (thickness at the height center of the base electrode layer arranged on end face C) Main face thickness: 0.25 μm (thickness at the length center of the base electrode layer arranged on main face A) Plating layer: two-layer structure of Ni plating and Sn plating Ni plating thickness: End face thickness: 4 μm (thickness at the height center of the Ni plating layer arranged on end face C) Main face thickness: 4 μm (thickness at the length center of the Ni plating layer arranged on main face A) Sn plating thickness: End face thickness: 4 μm (thickness at the height center of the Sn plating layer arranged on end face C) Main surface thickness: 4 μm (thickness at the center in the longitudinal direction of the Sn plating layer disposed on the main surface A) Structure of the first cover region and the second cover region Material of the first cover region and the second cover region: SiO ２ Thickness of the first cover region and the second cover region: 5 μm Width dimension of the first cover region: 15% of the width dimension of the laminated body Width dimension of the second cover region: 15% of the width dimension of the laminated body

[0159] (Configuration of Comparative Example) The comparative example had the same configuration as the example, except that it did not have either the first cover area or the second cover area.

[0160] (Results) In the example, 0 out of 50 pieces were defective. In the comparative example, 4 out of 50 pieces were defective.

[0161] A comparison between the examples and the comparative examples revealed that the moisture resistance reliability of the multilayer ceramic capacitor is improved by providing the multilayer ceramic capacitor with a cover region.

[0162] (Modifications) Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these, and includes the following scope.

[0163] The multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a multi-layer structure. The configuration of the multilayer ceramic capacitor 1 having a multilayer structure will be described with reference to Fig. 8. Fig. 8 is a diagram corresponding to Fig. 2, which shows the configuration of a multilayer ceramic capacitor 1 according to a modified example.

[0164] As shown in FIG. 8, the multilayer ceramic capacitor 1 may include, in addition to the first internal electrode layer 15A and the second internal electrode layer 15B, a floating internal electrode layer 16 that is not extended to either the first end face CA or the second end face CB.

[0165] For example, the multilayer ceramic capacitor 1 shown in Fig. 8(a) is a multilayer ceramic capacitor with a double structure including a first floating internal electrode layer 16A as the floating internal electrode layer 16. The multilayer ceramic capacitor 1 shown in Fig. 8(b) is a multilayer ceramic capacitor with a triple structure including a first floating internal electrode layer 16A and a second floating internal electrode 16B as the floating internal electrode layers 16. The multilayer ceramic capacitor 1 shown in Fig. 8(c) is a multilayer ceramic capacitor with a quadruple structure including a first floating internal electrode layer 16A, a second floating internal electrode 16B, and a floating internal electrode 16C as the floating internal electrode layers 16.

[0166] By providing the floating internal electrode layers 16, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. This results in multiple capacitor components being formed between the opposing internal electrode layers, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby enabling the multilayer ceramic capacitor 1 to withstand a high voltage. The multilayer ceramic capacitor 1 may also have a multi-element structure with four or more elements.

[0167] In the above embodiment, both the first cover region 4A and the second cover region 4B are formed in an annular shape, but this is not limited thereto. The first cover region and the second cover region may be arranged so as to straddle at least the boundary between the side margin portion and the outer layer portion. However, from the viewpoint of further improving moisture resistance reliability, it is preferable that the first cover region and the second cover region also straddle the boundary between the side margin portion and the inner layer portion, and it is even more preferable that each be formed in an annular shape.

[0168] In the above embodiment, the multilayer ceramic capacitor 1 uses a dielectric ceramic, but is not limited to this. The multilayer ceramic capacitor may use, for example, a piezoelectric ceramic, a semiconductor ceramic, or a magnetic ceramic. When a piezoelectric ceramic is used, the multilayer ceramic capacitor functions as a piezoelectric component. Examples of piezoelectric ceramics include PZT-based ceramics. When a semiconductor ceramic is used, the multilayer ceramic capacitor functions as a thermistor. Examples of semiconductor ceramics include spinel-based ceramics. When a magnetic ceramic is used, the multilayer ceramic capacitor functions as an inductor. Examples of magnetic ceramics include ferrite.

[0169] Although the preferred embodiments and modifications of the present invention have been described above, the present invention is not limited to these, and includes the following scope.

[0170] <1> A multilayer ceramic capacitor comprising: a laminate including an inner layer portion in which a plurality of dielectric layers and inner electrode layers are alternately laminated, the laminate having a pair of main surfaces facing each other in a lamination direction, a pair of end faces facing each other in a length direction perpendicular to the lamination direction, and a pair of side surfaces facing each other in a width direction perpendicular to both the lamination direction and the length direction; and a pair of external electrodes respectively disposed on each of the end faces and connected to the inner electrode layers, wherein the laminate has a pair of side margin portions respectively disposed on both sides of the inner layer portion in the width direction, and a pair of outer layer portions respectively disposed on both sides of the inner layer portion in the lamination direction and sandwiched between the side margin portions, and the pair of side surfaces are first side surfaces and a second side surface, the pair of side margin portions being a first side margin portion arranged on the first side surface and a second side margin portion arranged on the second side surface, a first cover region made of an inorganic material and arranged on the outer surface of the laminate so as to straddle the boundary between the first side margin portion and each of the outer layer portions, and a second cover region made of an inorganic material and arranged on the outer surface of the laminate so as to straddle the boundary between the second side margin portion and each of the outer layer portions, each of the end faces having an uncovered portion that is not covered by either the first cover region or the second cover region, and each of the end faces is connected to each of the external electrodes at each of the uncovered portions.

[0171] <2> The multilayer ceramic capacitor according to <1>, wherein the inorganic material contains at least one element selected from the group consisting of Si, Ti, Ba, and Zr.

[0172] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the first cover region has a ring shape that goes around in the length direction, and the second cover region has a ring shape that goes around in the length direction.

[0173] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the thickness of the first cover region is 1 μm or more and 10 μm or less, and the thickness of the second cover region is 1 μm or more and 10 μm or less.

[0174] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the multilayer ceramic capacitor has a substantially rectangular parallelepiped shape, the width dimension of the first cover region is 10% or more of the width dimension of the laminate and 20% or less of the width dimension of the laminate, and the width dimension of the second cover region is 10% or more of the width dimension of the laminate and 20% or less of the width dimension of the laminate.

[0175] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the dimension of the first side margin portion in the width direction is 5 μm or more and 40 μm or less, and the dimension of the second side margin portion in the width direction is 5 μm or more and 40 μm or less.

[0176] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein each of the side margin portions is composed of a plurality of layers, and each side margin portion has an inner layer that is arranged closest to the inner layer portion among the plurality of layers, and an outer layer that is arranged on the side farthest from the inner layer portion among the plurality of layers.

[0177] <8> The multilayer ceramic capacitor according to <7>, wherein the inner layer and the outer layer are both made of ceramic, each containing dielectric ceramic particles and an element as an additive present between the dielectric ceramic particles, and the element as the additive in the inner layer and the element as the additive in the outer layer are different from each other.

[0178] <9> The multilayer ceramic capacitor according to <7> or <8>, wherein the outer layer has a larger width dimension than the inner layer.

[0179] <10> The multilayer ceramic capacitor according to <9>, wherein the inner layer has a width dimension of 0.1 μm or more and 20 μm or less, and the outer layer has a width dimension of 5 μm or more and 20 μm or less.

[0180] <11> The multilayer ceramic capacitor according to any one of <1> to <10>, wherein the thickness of each of the internal electrode layers is 0.8 μm or less.

[0181] <12> The multilayer ceramic capacitor according to <11>, wherein the thickness of each of the dielectric layers is 0.55 μm or less.

[0182] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 External electrode 4A First cover area 4B Second cover area 11 Inner layer portion 12 Outer layer portion 14 Dielectric layer 15 Internal electrode layer 20 Side margin portion 20A First side margin portion 20B Second side margin portion 21 Inner layer 21A First inner layer 21B Second inner layer 22 Outer layer 22A First outer layer 22B Second outer layer A Main surface B Side surface BA First side surface BB Second side surface C End surface Ca Uncovered portion

Claims

1. A laminated body including an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately laminated, a pair of main surfaces facing each other in the lamination direction, a pair of end surfaces facing each other in the length direction orthogonal to the lamination direction, and a pair of side surfaces facing each other in the width direction orthogonal to both the lamination direction and the length direction; A pair of external electrodes respectively disposed on the respective end surfaces and connected to the internal electrode layers; A multilayer ceramic capacitor comprising: The laminated body has a pair of side margin portions respectively disposed on both sides in the width direction of the inner layer portion, and a pair of outer layer portions respectively disposed on both sides in the lamination direction of the inner layer portion and sandwiched between the respective side margin portions; The pair of side surfaces are a first side surface and a second side surface; The pair of side margin portions are a first side margin portion disposed on the first side surface and a second side margin portion disposed on the second side surface; A first cover region made of an inorganic material and disposed on the outer surface of the laminated body so as to straddle the boundary between the first side margin portion and each outer layer portion; A second cover region made of an inorganic material and disposed on the outer surface of the laminated body so as to straddle the boundary between the second side margin portion and each outer layer portion; Comprising; Each of the end surfaces has a non-covered portion that is not covered by any of the first cover region and the second cover region, and each external electrode is connected to each non-covered portion, respectively. A multilayer ceramic capacitor.

2. The multilayer ceramic capacitor according to claim 1, wherein the inorganic material contains at least one element selected from the group consisting of Si, Ti, Ba, and Zr.

3. The first cover region forms an annular shape that circulates in the length direction; The multilayer ceramic capacitor according to claim 1 or 2, wherein the second cover region forms an annular shape that circulates in the length direction.

4. The thickness of the first cover region is 1 μm or more and 10 μm or less; The multilayer ceramic capacitor according to claim 1 or 2, wherein the thickness of the second cover region is 1 μm or more and 10 μm or less.

5. The multilayer ceramic capacitor has a substantially rectangular parallelepiped shape; The dimension of the first cover region in the width direction is 10% or more and 20% or less of the dimension of the laminated body in the width direction. The dimension of the second cover region in the width direction is 10% or more and 20% or less of the dimension of the laminate in the width direction. The multilayer ceramic capacitor according to claim 1 or 2.

6. The dimension of the first side margin portion in the width direction is 5 μm or more and 40 μm or less, The dimension of the second side margin portion in the width direction is 5 μm or more and 40 μm or less. The multilayer ceramic capacitor according to claim 1 or 2.

7. Each side margin portion is composed of a plurality of layers, and has an inner layer disposed closest to the inner layer portion among the plurality of layers, and an outer layer disposed on the side farthest from the inner layer portion among the plurality of layers. The multilayer ceramic capacitor according to claim 1 or 2.

8. Both the inner layer and the outer layer are made of ceramic, and each contains dielectric ceramic particles and an element as an additive existing between the dielectric ceramic particles, The element as an additive in the inner layer and the element as an additive in the outer layer are different from each other. The multilayer ceramic capacitor according to claim 7.

9. The dimension of the outer layer in the width direction is larger than the dimension of the inner layer in the width direction. The multilayer ceramic capacitor according to claim 7.

10. The dimension of the inner layer in the width direction is 0.1 μm or more and 20 μm or less, The dimension of the outer layer in the width direction is 5 μm or more and 20 μm or less. The multilayer ceramic capacitor according to claim 9.

11. The thickness of each internal electrode layer is 0.8 μm or less. The multilayer ceramic capacitor according to claim 1 or 2.

12. The thickness of each dielectric layer is 0.55 μm or less. The multilayer ceramic capacitor according to claim 11.

13. The dimension of the outer layer in the width direction is larger than the dimension of the inner layer in the width direction. The multilayer ceramic capacitor according to claim 8.