Semiconductor device, inverter, dc / dc converter, switching power supply device, motor drive circuit, and vehicle

Abstract

This semiconductor device includes: a switching element; a shunt resistor that has a first resistor unit and that is for detecting a current flowing in the switching element; and an RC network circuit connected in parallel with the shunt resistor. The RC network circuit has a second resistor unit and a capacitor connected in series with the second resistor unit. The semiconductor device is configured to suppress an influence, on the RC network circuit, due to a magnetic flux change caused by a current flowing in the shunt resistor.

Description

Semiconductor device, inverter, DC / DC converter, switching power supply device, motor drive circuit, and vehicle

[0001] The present invention relates to a semiconductor device, and to an inverter, a DC / DC converter, a switching power supply device, a motor drive circuit, and a vehicle that use the semiconductor device.

[0002] 2. Description of the Related Art There is known a semiconductor device that measures a current flowing through a switching element using a shunt resistor connected in series with the switching element (see, for example, Japanese Patent Application Laid-Open No. 2003-121998).

[0003] JP 2014-121139 A

[0004] There is a demand for a semiconductor device, an inverter, a switching power supply, a motor drive circuit, and a vehicle that can more accurately measure the current flowing through a switching element.

[0005] In order to achieve the above object, the present disclosure provides a semiconductor device comprising: a switching element; a shunt resistor having at least one first resistor, connected to one end of the switching element for detecting a current flowing through the switching element; and an RC network circuit connected in parallel with the shunt resistor. The RC network circuit comprises a second resistor and a capacitor connected in series with the second resistor. The semiconductor device is configured to suppress the influence of a change in magnetic flux caused by a current flowing through the shunt resistor on the RC network circuit, and satisfies the following formula: (Rsen / Lsen)=1 / (Rs·Cs), where Rsen is the resistance value of the shunt resistor, Lsen is the parasitic inductance value of the shunt resistor, Rs is the resistance value of the second resistor, and Cs is the capacitance of the capacitor.

[0006] According to the present disclosure, the current flowing through the switching element can be measured more accurately.

[0007] FIG. 1 is a schematic circuit diagram of a semiconductor device. FIG. 2 is a schematic perspective view of the semiconductor device as seen from above. FIG. 3 is an enlarged plan view of a portion of a substrate on which a shunt resistor and an RC network circuit are mounted. FIG. 4 is an enlarged plan view of a portion of a semiconductor device according to a first modification on which a shunt resistor and an RC network circuit are mounted. FIG. 5 is an enlarged cross-sectional view of a substrate on which a shunt resistor and an RC network circuit are mounted in a semiconductor device according to a second modification. FIG. 6 is a schematic circuit diagram of a switching power supply device using a semiconductor device according to a third modification. FIG. 7 is a schematic circuit diagram of a motor drive circuit using a semiconductor device according to a fourth modification. FIG. 8 is an external view (front) of a vehicle on which a light-emitting device is mounted. FIG. 9 is an external view (rear) of a vehicle on which a light-emitting device is mounted. FIG. 10 is an external view of an LED headlight module. FIG. 11 is an external view of an LED turn lamp module. FIG. 12 is an external view of an LED rear lamp module.

[0008] In this specification, a MOS (Metal Oxide Semiconductor field effect transistor) refers to a transistor whose gate structure is made up of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-channel, N-channel, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this specification, when it is stated that elements are connected to each other, this includes not only a mechanical connection but also an electrical connection, in other words, a state in which electricity flows. Therefore, "connect" includes an "electrical connection."

[0010] <Semiconductor Device 100> Fig. 1 is a schematic circuit diagram of the semiconductor device 100. Fig. 2 is a schematic perspective view of the semiconductor device 100 as viewed from above.

[0011] 1 is an inverter. The semiconductor device 100 includes a first switching element 2, a resistor 3, a shunt resistor 4, and an RC network circuit 5. The semiconductor device 100 includes a substrate 1 on which the first switching element 2, the resistor 3, the shunt resistor 4, and the RC network circuit 5 are mounted.

[0012] The substrate 1 is plate-shaped, and both end surfaces in the thickness direction are component mounting surfaces. In this embodiment, the thickness direction of the substrate 1 is the vertical direction in which gravity acts, and will be described as the upper surface 11 and the lower surface 12 of the substrate 1. The upper surface 11 and the lower surface 12 do not limit the directions of the semiconductor device 100 when in use. Pattern wiring 13 is formed on the upper surface 11 and the lower surface 12 of the substrate 1.

[0013] The first switching element 2 is an N-channel MOS transistor. The drain, which is a first terminal of the first switching element 2, is connected to a voltage source VIN via a resistor 3. The voltage source VIN is a power supply that supplies a constant voltage. A connection point P1 between the drain of the first switching element 2 and the resistor 3 is connected to an output terminal POUT.

[0014] The gate, which is the second terminal of the first switching element 2, is connected to the input terminal PIN. The source, which is the third terminal of the first switching element 2, is connected to the ground potential GND via the shunt resistor 4.

[0015] The first switching element 2 may be a SiC MOS transistor. Alternatively, an IGBT (Insulated Gate Bipolar Transistor) may be used instead of a MOS transistor. Although the detailed circuit configuration differs, the semiconductor device 100 may also use a P-channel MOS transistor.

[0016] In the semiconductor device 100, a high-level or low-level voltage signal is input to the input terminal PIN. When a high-level signal is input, the first switching element 2 is turned ON. As a result, the current flowing through the resistor 3 flows through the first switching element 2 and to the ground potential GND. In other words, the output signal output from the output terminal POUT is low-level. Furthermore, when a low-level signal is input to the input terminal PIN, the first switching element 2 is turned OFF. Therefore, the current flowing through the resistor 3 is supplied to the output terminal POUT. Therefore, the output signal output from the output terminal POUT is a high-level signal. In other words, the semiconductor device 100 is an inverter circuit that outputs an output signal that is an inverted version of the input signal.

[0017] In the semiconductor device 100, the current flowing through the first switching element 2 may be used for various controls or as information for acquiring the state of the first switching element 2. In the semiconductor device 100, a shunt resistor 4 is provided to detect the current flowing through the first switching element 2.

[0018] The shunt resistor 4 has one first resistor 41. Here, the shunt resistor 4 is connected in series with the source of the first switching element 2 so that the current that has flowed through the first switching element 2 flows into the shunt resistor 4. Furthermore, based on the voltage across the shunt resistor 4, the current flowing between the drain and source of the first switching element 2 can be obtained.

[0019] During the switching operation of the first switching element 2, a voltage is induced in the voltage of the shunt resistor 4 based on the time change (dI / dt) of the current due to the parasitic inductance. When the frequency of the switching operation of the first switching element 2 increases, the voltage induced by the time change (dI / dt) of the current due to the parasitic inductance increases.

[0020] As a result, during the switching operation of the first switching element 2, particularly when it is turned on and off, the voltage induced by the parasitic inductance due to the change in current over time becomes a spike voltage several times the voltage across the shunt resistor 4.

[0021] When the first switching element 2 is turned on and off, a spike voltage is generated, and it is difficult to accurately obtain the current flowing through the first switching element 2 based on the voltage across the shunt resistor 4.

[0022] Therefore, the semiconductor device 100 uses an RC network circuit 5 to eliminate the effect of spike voltages induced by the parasitic inductance of the shunt resistor 4. The RC network circuit 5 is connected in parallel with the shunt resistor 4. The RC network circuit 5 is a circuit in which a second resistor 51 and a capacitor 52 are connected in series. The second resistor 51 is connected to a connection point P2 between the source of the first switching element 2 and the shunt resistor 4. In addition, the capacitor 52 is connected to a connection point P3 between the shunt resistor 4 and the ground potential GND.

[0023] The second resistor 51 and the capacitor 52 of the RC network circuit 5 will be described in detail. It is known that in the semiconductor device 100, by making the resonant frequency of the RC network circuit 5 and the resonant frequency of the shunt resistor 4 the same, it is possible to separate the voltage induced by the parasitic inductance of the shunt resistor 4 from the voltage generated in the resistance component of the shunt resistor 4.

[0024] Therefore, the second resistor 51 and the capacitor 52 are determined so that the following equation holds between the resistance value Rsen and the parasitic inductance Lsen of the shunt resistor 4 and the resistance value Rs of the second resistor 51 and the capacitance Cs of the capacitor 52 of the RC network circuit 5: Rsen / Lsen=1 / (Rs×Cs).

[0025] Increasing the capacitance Cs of the capacitor 52 in the RC network circuit 5 increases the charging current to the capacitance Cs at turn-on when the parasitic inductance Lsen is large. Therefore, the capacitance Cs of the capacitor 52 in the RC network circuit 5 is preferably approximately 500 pF or less, and is set to 200 pF here. Note that the capacitance Cs of the capacitor 52 is an example and is not limited to this value. Furthermore, although the wiring that constitutes the RC network circuit 5 also contains parasitic inductance, the parasitic inductance of the wiring is small and negligible.

[0026] The semiconductor device 100 has a detection unit 6 that detects the voltage Vs across the capacitor 52 of the RC network circuit 5. The voltage waveform of the voltage Vs across the capacitor 52 detected by the detection unit 6 is free of the influence of spike voltages due to the parasitic inductance of the shunt resistor 4. In other words, the detection unit 6 can obtain the voltage Vs across the capacitor 52 that corresponds to the voltage across the shunt resistor 4 free of the influence of spike voltages due to the parasitic inductance.

[0027] 1 , a lifetime estimation unit 7 is connected to the detection unit 6. The lifetime estimation unit 7 can obtain the current that flows during the switching operation of the first switching element 2 from the voltage Vs across the capacitor 52 detected by the detection unit 6, and the drain-source voltage of the first switching element 2 from a voltage detection unit 8 that detects the drain-source voltage of the first switching element 2.

[0028] As described above, the voltage Vs across the capacitor 52 is free from the effect of spike voltages due to the parasitic inductance of the shunt resistor 4. The life estimation unit 7 can obtain an accurate value of the current at turn-on from the voltage Vs across the capacitor 52 immediately after the first switching element 2 is turned on. The life estimation unit 7 can then calculate the switching loss at turn-on of the first switching element 2 from the current at turn-on and the drain-source voltage. The switching loss at turn-on of the first switching element 2 calculated by the life estimation unit 7 is free from the effect of spike voltages due to the parasitic inductance of the shunt resistor.

[0029] It is known that the gate threshold voltage of a SiC MOS transistor increases as degradation progresses. It is also known that an increase in the gate threshold voltage corresponds to an increase in switching loss during turn-on. Therefore, the lifetime estimation unit 7 estimates the degradation of the first switching element 2 based on the switching loss during turn-on of the first switching element 2. For example, when the switching loss during turn-on exceeds a threshold, the lifetime estimation unit 7 estimates that the first switching element 2 has reached the end of its lifetime.

[0030] 2, in the semiconductor device 100, the first switching element 2, the resistor 3, and the shunt resistor 4 are mounted on the upper surface 11 of the substrate 1. In addition, in the semiconductor device 100, the RC network circuit 5 is mounted on the lower surface 12 as shown in FIG.

[0031] In the semiconductor device 100 of this embodiment, when the first switching element 2 is switched, the current flowing through the first switching element 2 is concentrated in the shunt resistor 4. In the shunt resistor 4, a change in magnetic flux over time (dΦ / dt) occurs due to a change in current over time (dI / dt). When the change in current over time (dI / dt) increases, the change in magnetic flux over time (dΦ / dt) also increases.

[0032] In the semiconductor device 100, when the change in magnetic flux over time (dΦ / dt) of the shunt resistor 4 acts on the RC network circuit 5, noise due to the change in magnetic flux over time (dΦ / dt) may be superimposed on the waveform of the voltage Vs across the capacitor 52. Therefore, in the semiconductor device 100 of this embodiment, the circuits that make up the RC network circuit 5 are placed on the substrate 1 at a position that is not affected by the change in magnetic flux over time (dΦ / dt) of the shunt resistor 4.

[0033] The arrangement of the shunt resistor 4 and the RC network circuit 5 on the substrate 1 will now be described with reference to the drawings. Fig. 3 is an enlarged plan view of the portion of the substrate 1 on which the shunt resistor 4 and the RC network circuit 5 are mounted.

[0034] As shown in Fig. 3, the shunt resistor 4 is formed by a single first resistor 41. Terminals of the first resistor 41 are connected to a first pattern wiring 131 and a second pattern wiring 132 formed on the upper surface 11 of the substrate 1. A current flows through the first resistor 41 from the first pattern wiring 131 side to the second pattern wiring 132 side. At this time, a magnetic flux Mg is generated around the first resistor 41 due to the current flow. Around the first resistor 41, a magnetic flux Mg is generated above the shunt resistor 4 toward the back of the page in Fig. 3 and below the first resistor 41 toward the front of the page.

[0035] 3 , in the semiconductor device 100, the RC network circuit 5 is mounted at a position that does not overlap with the position 14 where the magnetic flux Mg and the substrate 1 overlap. The RC network circuit 5 also includes a pattern wiring that connects the second resistor 51 to the connection point P2 and a pattern wiring that connects the capacitor 52 to the connection point P3. By arranging the RC network circuit 5 in this manner, the RC network circuit 5 is positioned so as not to intersect with the magnetic flux Mg that is generated by passing a current through the first resistor 41. In other words, the semiconductor device 100 is configured to suppress the effect of a change in magnetic flux caused by the current in the shunt resistor 4 on the RC network circuit 5.

[0036] As a result, even if the time change (dΦ / dt) of the magnetic flux due to the time change (dI / dt) of the current flowing through the shunt resistor 4 becomes large when the first switching element 2 is turned on during switching operation, it is possible to prevent noise due to the time change (dΦ / dt) of the magnetic flux from being superimposed on the voltage between both ends of the capacitor 52 of the RC network circuit 5.

[0037] As a result, the current flowing through the first switching element 2 can be accurately observed from the voltage Vs across the capacitor 52 of the RC network circuit 5. As a result, the switching loss when the first switching element 2 is turned on can be obtained with high accuracy. This makes it possible to accurately grasp the state of the first switching element 2 and accurately estimate the lifespan of the first switching element 2.

[0038] According to the semiconductor device 100 of this embodiment, by optimizing the layout of the RC network circuit 5 connected in parallel in the current detection circuit of the switching element, it is possible to acquire a voltage waveform from which the influence of the parasitic inductance component of the shunt resistor 4 and noise due to changes over time in magnetic flux generated by passing a current through the shunt resistor 4 have been removed. Furthermore, in the semiconductor device 100, the lifetime of the first switching element 2 is estimated from the acquired voltage waveform, but the voltage waveform may be used for purposes other than lifetime estimation.

[0039] <First Modification> A semiconductor device 100A according to a first modification will be described with reference to the drawings. Fig. 4 is an enlarged plan view of a portion of the semiconductor device 100A according to the first modification where the shunt resistor 4A and the RC network circuit 5 are mounted. The semiconductor device 100A according to this modification differs from the semiconductor device 100 in that it has the shunt resistor 4A, but otherwise has the same configuration as the semiconductor device 100. In the semiconductor device 100A, portions that are substantially the same as those in the semiconductor device 100 are designated by the same reference numerals, and detailed descriptions of the same portions will be omitted.

[0040] 4, in the semiconductor device 100A, the shunt resistor 4A includes a plurality of resistors (here, three first resistors 41). The three first resistors 41A are connected to the first pattern wiring 131 and the second pattern wiring 132, respectively, in parallel with each other.

[0041] The three first resistors 41A are arranged in a straight line. This allows magnetic fluxes Mg generated by currents flowing through adjacent first resistors 41A to cancel each other out. More specifically, the direction of current flow through the three first resistors 41A shown in FIG. 4 is from right to left in all cases. Therefore, the magnetic fluxes Mg generated when currents flow through each first resistor 41A flow toward the front of the page at the top of the first resistor 41A in FIG. 4 and toward the front of the page at the bottom. In this way, the magnetic fluxes Mg generated when currents flow through adjacent first resistors 41A are combined to cancel each other out. In the shunt resistor 4A, the magnetic fluxes Mg overlap with the substrate 1 in the portion above the top first resistor 41A and the portion below the bottom first resistor 41A in FIG. 4.

[0042] In the semiconductor device 100A, the RC network circuit 5 overlaps the central first resistor 41A of the three first resistors 41A connected in parallel in the thickness direction of the substrate 1. By arranging the RC network circuit 5 in this manner, the RC network circuit 5 is positioned so as not to intersect with the magnetic flux Mg, which is a composite of magnetic fluxes generated by passing current through each of the first resistors 41A. In other words, the semiconductor device 100A is configured to suppress the effect of magnetic flux changes caused by the current in the shunt resistor 4 on the RC network circuit 5.

[0043] By configuring in this manner, even if the time change (dΦ / dt) of the magnetic flux due to the time change (dI / dt) of the current flowing through the shunt resistor 4A (first resistor 41A) becomes large when the first switching element 2 is turned on in its switching operation, it is possible to prevent noise due to the time change (dΦ / dt) of the magnetic flux from being superimposed on the voltage between both ends of the capacitor 52 of the RC network circuit 5.

[0044] As a result, the switching loss when the first switching element 2 is turned on can be accurately obtained from the voltage Vs across the capacitor 52 of the RC network circuit 5. This makes it possible to accurately grasp the state of the first switching element 2 and to accurately predict the life of the first switching element 2.

[0045] In this modification, the RC network circuit 5 is arranged so as to overlap the central first resistor 41A of the three first resistors 41A connected in parallel in the thickness direction of the substrate 1. However, this is not limited thereto, and the RC network circuit 5 may be arranged so as to overlap either the upper or lower first resistor 41A. Furthermore, the RC network circuit 5 may be arranged so as to overlap two or more first resistors 41A. Any configuration may be adopted in which the magnetic fluxes generated by the three first resistors 41A do not intersect with the combined magnetic flux Mg.

[0046] Furthermore, in this modification, the number of first resistors 41A connected in parallel to the shunt resistor 4A is not limited to three, but may be two, or four or more. Any number may be used as long as it can reduce the proportion of the substrate 1 occupied by the shunt resistor 4A and form a portion that does not intersect with the magnetic flux generated by the RC network circuit 5 passing a current through the first resistor 41A.

[0047] <Second Modification> A semiconductor device 100B according to a second modification will be described with reference to the drawings. Fig. 5 is an enlarged cross-sectional view of the substrate 1B on which the shunt resistor 4 and the RC network circuit 5 of the semiconductor device 100B according to the second modification are mounted. The semiconductor device 100B according to this modification differs from the substrate 1 in that the substrate 1B on which the shunt resistor 4 and the RC network circuit 5 are mounted is different from the substrate 1, but otherwise has the same configuration as the semiconductor device 100. In the semiconductor device 100B, parts that are substantially the same as those in the semiconductor device 100 are designated by the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0048] In the semiconductor device 100 described above, the RC network circuit 5 is mounted on the underside 12 of the substrate 1 at a position overlapping the shunt resistor 4 in the thickness direction. Many electronic components are mounted on the substrate 1B. In some cases, the RC network circuit 5 cannot be mounted because electronic components are mounted in the portion overlapping the shunt resistor 4 in the thickness direction of the substrate 1B, or the RC network circuit 5 is susceptible to electromagnetic waves from the electronic components.

[0049] In such a case, the RC network circuit 5 may intersect with the magnetic flux Mg that is generated when a current flows through the first resistor 41. Even in such a case, the semiconductor device 100B has a shield 16 for suppressing the magnetic flux Mg that is generated when a current flows through the first resistor 41, i.e., noise due to the change in magnetic flux over time (dΦ / dt).

[0050] 5, the substrate 1B of the semiconductor device 100B is a multi-layer substrate, and a shield 16 made of a conductive material is formed as an intermediate layer. The shield 16 is arranged so as to overlap, in the thickness direction of the substrate 1B, with a portion where the magnetic flux Mg generated by passing a current through the first resistor 41 of the shunt resistor 4 overlaps with the substrate 1B. The shield 16 is also arranged so as to overlap with the RC network circuit 5 in the thickness direction of the substrate 1B. In other words, the semiconductor device 100B is configured so that the shield 16 suppresses the effect of magnetic flux changes caused by the current through the shunt resistor 4 on the RC network circuit 5.

[0051] In this way, by disposing the shield 16 as an intermediate layer of the multilayer substrate 1B, it is possible to prevent the magnetic flux Mg that is generated when a current flows through the first resistor 41 of the shunt resistor 4 from acting on the RC network circuit 5. This makes it possible to prevent noise due to the change in magnetic flux over time (dΦ / dt) from being superimposed on the voltage Vs across the capacitor 52 of the RC network circuit 5.

[0052] Alternatively, the shield 16 may be grounded. By maintaining the potential of the shield 16 at the ground potential GND, noise due to changes in the potential of the shield 16 over time is suppressed, and the noise can be prevented from being superimposed on the voltage Vs across the capacitor 52 of the RC network circuit 5.

[0053] By configuring in this manner, even if the time change (dΦ / dt) of the magnetic flux due to the time change (dI / dt) of the current flowing through the shunt resistor 4 (first resistor 41) becomes large when the first switching element 2 is turned on during switching operation, it is possible to prevent noise due to the time change (dΦ / dt) of the magnetic flux from being superimposed on the voltage between both ends of the capacitor 52 of the RC network circuit 5.

[0054] As a result, the switching loss when the first switching element 2 is turned on can be accurately obtained from the voltage Vs across the capacitor 52 of the RC network circuit 5. This makes it possible to accurately grasp the state of the first switching element 2 and to accurately predict the life of the first switching element 2.

[0055] Furthermore, since the intermediate layer of the multilayer substrate 1B is configured as the shield 16, the degree of freedom of the pattern wiring 13 formed on each of the upper surface 11B and the lower surface 12B of the substrate 1B can be increased. This allows the layout of the pattern wiring 13 to be configured in a way that is less likely to generate EMI. Furthermore, the degree of freedom of the arrangement of electronic components can be increased, allowing electronic components to be mounted efficiently.

[0056] <Third Modification> Figure 6 is a schematic circuit diagram of a switching power supply 300 using a semiconductor device 100C of a third modification. The switching power supply 300 shown in Figure 6 is a power supply including a step-up DC / DC converter that boosts an input voltage V1 to generate an output voltage V2 and supplies the output voltage V2 to a load Z. The switching power supply 300 has the semiconductor device 100C, an inductor L1, and a capacitor C1. The inductor L1 and the capacitor C1 are externally connected to the semiconductor device 100C. In the switching power supply 300, the semiconductor device 100C supplies the output voltage V2 to the load Z.

[0057] <Semiconductor device 100C> The semiconductor device 100C has a first switching element 21C, a second switching element 22C, and a control circuit 9. The semiconductor device 100C differs from the semiconductor device 100 in that it has the first switching element 21C, the second switching element 22C, and the control circuit 9, and has an inductor L1 instead of the resistor 3. In all other respects, the semiconductor device 100C has the same configuration as the semiconductor device 100. Therefore, parts of the semiconductor device 100C that are substantially the same as those of the semiconductor device 100 are denoted by the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0058] Here, the first switching element 21C is an N-channel MOS transistor. Here, the second switching element 22C is a P-channel MOS transistor. Note that the second switching element 22C is not limited to a P-channel MOS transistor and may be an N-channel MOS transistor.

[0059] 6, a first end of the load Z is connected to the connection point P4 of the switching power supply device 300, and a second end thereof is connected to the ground potential GND. A first end of the capacitor C1 is connected to the connection point P4, and a second end thereof is connected to the ground potential GND. Furthermore, a first end of the inductor L1 is connected to the voltage source VIN. A second end thereof is connected to the drain, which is a first terminal of the first switching element 21C, and the source, which is a first terminal of the second switching element 22C.

[0060] The drain, which is the third terminal of the second switching element 22C, is connected to a connection point P4, i.e., to a first end of the load Z and a first end of the capacitor C1. The source, which is the third terminal of the first switching element 21C, is connected to a shunt resistor 4 and an RC network circuit 5, similar to the first switching element 2.

[0061] The control circuit 9 supplies a first drive signal G1 that controls ON / OFF of the first switching element 21C by PWM (Pulse Width Modulation) control to the gate, which is the second terminal of the first switching element 21C. The control circuit 9 also supplies a second drive signal G2 that controls ON / OFF of the second switching element 22C to the gate, which is the second terminal of the second switching element 22C.

[0062] The first switching element 21C is ON when the second drive signal G1 is at a high level and OFF when the second drive signal G1 is at a low level. The second switching element 22C is OFF when the second drive signal G2 is at a high level and ON when the second drive signal G2 is at a low level. In other words, the first switching element 21C and the second switching element 22C are subjected to complementary ON / OFF control.

[0063] Here, "complementary" refers to a state in which the first switching element 21C and the second switching element 22C alternate between ON and OFF. To explain further, this does not only mean a complete switching state, but may also mean, for example, a state in which both the first switching element 21C and the second switching element 22C are OFF.

[0064] In the semiconductor device 100C, the detection unit 6 obtains the current flowing during the switching operation of the first switching element 22C from the voltage across the capacitor 52 of the RC network circuit 5 when the first switching element 21C is turned on, and the voltage detection unit 8 obtains the drain-source voltage of the first switching element 21C. The lifetime estimation unit 7 obtains the switching loss of the first switching element 21C when it is turned on from the current and drain-source voltage of the first switching element 21C when it is turned on. The lifetime estimation unit 7 estimates the state and lifetime of the first switching element 21C from the switching loss. Furthermore, the lifetime estimation unit 7 can estimate the state and lifetime of the second switching element 22C from the estimated state and lifetime of the first switching element 21C.

[0065] In this way, by accurately estimating the state and lifespan of the switching elements, it is possible to provide a switching power supply device that can supply stable power.

[0066] The above-described switching power supply device 300 has been described using an example of a configuration including a step-up DC / DC converter, but the state and lifespan of the switching elements included in the semiconductor device can also be accurately estimated in a similar manner in a configuration including a step-down DC / DC converter.

[0067] 7 is a schematic circuit diagram of a motor drive circuit 400 using a semiconductor device 100D according to a fourth modification. The semiconductor device 100D shown in FIG. 7 is used as the motor drive circuit 400 that drives a DC brushless motor 200.

[0068] DC brushless motor 200 has U-phase coil 201U, V-phase coil 201V, and W-phase coil 201W. Semiconductor device 100D has U-phase first switching element 21U, U-phase second switching element 22U, V-phase first switching element 21V, V-phase second switching element 22V, W-phase first switching element 21W, W-phase second switching element 22W, and control circuit 91.

[0069] The U-phase first switching element 21U is an N-channel MOS transistor. The first switching element 2U has the same configuration as the first switching element 2 shown in FIG. 1 . The U-phase second switching element 22U is an N-channel MOS transistor. A first terminal (source) of the second switching element 22U is connected to a voltage source VIN. A second terminal (gate) of the second switching element 22U is connected to a control circuit 91. A third terminal (drain) of the second switching element 22U and a first terminal (drain) of the first switching element 21U are connected to a U-phase coil 201U. A shunt resistor 4U and an RC network circuit 5U are connected to a third terminal (source) of the U-phase first switching element 21U, similar to the first switching element 2 shown in FIG. 1 .

[0070] Similarly, the V-phase first switching element 21V and the V-phase second switching element 22V have the same configuration as the U-phase first switching element 21U and the U-phase second switching element 22U, and a shunt resistor 4V and an RC network circuit 5V are connected to the source (third terminal) of the V-phase first switching element 21V, similar to the first switching element 2 shown in FIG. 1 . The V-phase first switching element 21V and the V-phase second switching element 22V are connected to the V-phase coil 201V. The W-phase first switching element 21W and the W-phase second switching element 22W have the same configuration as the U-phase first switching element 21U and the U-phase second switching element 22U, and a shunt resistor 4W and an RC network circuit 5W are connected to the source (third terminal) of the W-phase first switching element 21W, similar to the first switching element 2 shown in FIG. 1 . The W-phase first switching element 21W is connected to the W-phase coil 201W.

[0071] As shown in FIG. 7, in the semiconductor device 100D, the second switching elements 22U, 22V, and 22W of each phase are high-side switching elements, and the first switching elements 21U, 21V, and 21W of each phase are low-side switching elements.

[0072] The control circuit 91 supplies drive signals G1U, G1V, and G1W to the first switching elements 21U, 21V, and 21W of each phase of the semiconductor device 100D. The control circuit 91 also supplies drive signals G2U, G2V, and G2W to the gates of the second switching elements 22U, 22V, and 22W of each phase. Each switching element is ON / OFF controlled by the control circuit 91. Although details are omitted, the U-phase first switching element 21U and the U-phase second switching element 22U are ON / OFF controlled in a complementary manner.

[0073] Similar to U-phase first switching element 21U and U-phase second switching element 22U, V-phase first switching element 21V and V-phase second switching element 22V, and W-phase first switching element 21W and W-phase second switching element 22W are complementarily ON / OFF controlled. DC brushless motor 200 rotates by switching ON / OFF of first switching elements 21U, 21V, 21W and second switching elements 22U, 22V, 22W of each phase in a timely manner.

[0074] In the semiconductor device 100D, the detection unit 6 acquires the voltage across the capacitor 52 of the RC network circuits 5U, 5V, 5W of each phase when the U-phase first switching element 21U, the V-phase first switching element 21V, and the W-phase first switching element 21W are turned on. The lifetime estimation unit 7 acquires the switching loss of the first switching elements 21U, 21V, 21W of each phase when they are turned on, and estimates the state and lifetime of the first switching elements 21U, 21V, 21W of each phase from the switching loss. Furthermore, the lifetime estimation unit 7 estimates the state and lifetime of the second switching elements 22U, 22V, 22W of each phase from the estimated state and lifetime of the first switching elements 21U, 21V, 21W of each phase.

[0075] In this way, by accurately estimating the state and life of the switching elements, it is possible to stabilize the operation of the motor 200 and make adjustments before the operation becomes unstable.

[0076] <Applications> The semiconductor device 100 described above can be a light-emitting device that employs an LED as a load connected to the output terminal Pout. Such a light-emitting device can be suitably used as a light-emitting device for a vehicle X10, such as a headlight X11 (including high beam / low beam / parking lamp / fog lamp, etc., as appropriate), a daylight / night driving (DRL) light source X12, a tail lamp X13 (including parking lamp, backup lamp, etc., as appropriate), a stop lamp X14, and a turn lamp X15, as shown in Figures 8 and 9 .

[0077] The light emitting device described above may be provided as a light emitting device for a module (such as the LED headlight module Y10 in FIG. 10, the LED turn lamp module Y20 in FIG. 11, and the LED rear lamp module Y30 in FIG. 12). Furthermore, the DC / DC converter A may be provided in the form of a light emission control device that controls the light emission of the LEDs.

[0078] <Others> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present invention is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0079] The semiconductor device (100) described above includes a switching element (2), a shunt resistor (4) having at least one first resistor (41) and connected to one end of the switching element (2) for detecting a current flowing through the switching element (2), and an RC network circuit (5) connected in parallel with the shunt resistor (4). The RC network circuit (5) includes a second resistor (51) and a capacitor (52) connected in series with the second resistor (51). This configuration (first configuration) is configured to suppress the influence of magnetic flux changes caused by a current flowing through the shunt resistor (4) on the RC network circuit (5), and satisfies the following formula: (Rsen / Lsen)=1 / (Rs·Cs), where Rsen is the resistance value of the shunt resistor, Lsen is the parasitic inductance value of the shunt resistor, Rs is the resistance value of the second resistor, and Cs is the capacitance of the capacitor.

[0080] In the semiconductor device (100) of the first configuration, the RC network circuit (5) is arranged at a position where it does not cross the magnetic flux caused by the current flowing through the shunt resistor (4) (second configuration).

[0081] In the semiconductor device (100) of the second configuration, the shunt resistor (4) is mounted on one surface (11) of the substrate (1), and the RC network circuit (5) is mounted on the other surface (12) of the substrate (1) at a position overlapping the shunt resistor (4) in the thickness direction (third configuration).

[0082] In the semiconductor device (100A) of any one of the first to third configurations, the shunt resistor (4A) has a plurality of first resistors (41A), which are connected in parallel to generate magnetic fluxes that cancel out magnetic fluxes generated by adjacent first resistors (41A) (fourth configuration).

[0083] In the semiconductor device (100B) of any one of the first to fourth configurations, a shield (16) is formed between the RC network circuit (5) and the shunt resistor (4) (fifth configuration).

[0084] In the semiconductor device (100B) of the fifth configuration, the shield is connected to a ground potential (sixth configuration).

[0085] In the semiconductor device (100, 100A, 100B, 100C) of any one of the first to sixth configurations, the switching element (4, 4A) is a SiC MOSFET (seventh configuration).

[0086] In the semiconductor device (100, 100A, 100B, 100C) of any one of the first to sixth configurations, the switching element (4, 4A) is an IGBT (eighth configuration).

[0087] In the semiconductor device (100, 100A, 100B, 100C) of any one of the first to sixth configurations, the switching element (4, 4A) is a Si-based MOSFET (ninth configuration).

[0088] In the semiconductor device (100, 100A, 100B, 100C) of any of the first to ninth configurations, the capacitance of the capacitor (52) of the RC network circuit (5) is 500 pF or less (tenth configuration).

[0089] In the semiconductor device (100, 100A, 100B, 100C) of any of the first to tenth configurations, a configuration (eleventh configuration) is provided which includes a lifetime estimation unit (7) that estimates the lifetime of the switching element (2) from the voltage across the capacitor (52) of the RC network circuit (5).

[0090] The present invention has a configuration (twelfth configuration) in which the semiconductor device has any one of the semiconductor devices (100, 100A, 100B, 100C) according to the first to eleventh configurations.

[0091] The present invention is directed to a configuration (thirteenth configuration) that is a DC / DC converter having a semiconductor device (100C) according to any one of the first to twelfth configurations.

[0092] This is a configuration (fourteenth configuration) that is a switching power supply device having the DC / DC converter of the thirteenth configuration.

[0093] A motor drive circuit 400 having a semiconductor device (100D) of any of the first to eleventh configurations described above, having a plurality of sets of switching elements each having a first switching element (21U, 21V, 21W) connected to a shunt resistor (4U, 4V, 4W) and a second switching element (22U, 22V, 22W) connected in series with the first switching element (21U, 21V, 21W), and a connection point between the first switching element (21U, 21V, 21W) and the second switching element (22U, 22V, 22W) of each set is connectable to a coil (201U, 201V, 201W) of the motor 200 (fifteenth configuration).

[0094] A vehicle (sixteenth configuration) includes a semiconductor device (100, 100A, 100B, 100C) according to any one of the first to tenth configurations.

[0095] DESCRIPTION OF SYMBOLS 1, 1B Substrate 2 First switching element 3 Resistor 4, 4A, 4U, 4V, 4W Shunt resistor 5, 5U, 5V, 5W RC network circuit 6 Detection unit 7 Lifetime estimation unit 8 Control circuit 11 Upper surface 11B Upper surface 12 Lower surface 12B Lower surface 13 Pattern wiring 14 Position 16 Shield 21U U-phase first switching element 21V V-phase first switching element 21W W-phase first switching element 22U U-phase second switching element 22V V-phase second switching element 22W W-phase second switching element 41, 41A First resistor 51 Second resistor 52 Capacitor 100, 100A, 100B, 100C, 100D Semiconductor device 131 First pattern wiring 132 Second pattern wiring 200 DC brushless motor 201U U-phase coil 201V V-phase coil 201W W-phase coil X10 Light source for vehicle X12 X14 Stop lamp X15 Turn lamp Y10 LED headlight module Y20 LED turn lamp module Y30 LED rear lamp module

Claims

1. A switching element; a shunt resistor having at least one first resistor, connected to one end of the switching element for detecting a current flowing through the switching element; an RC network circuit connected in parallel with the shunt resistor; The RC network circuit comprises: a second resistor; a capacitor connected in series with the second resistor; A semiconductor device configured to suppress the influence of a change in magnetic flux caused by a current flowing through the shunt resistor on the RC network circuit, and satisfying the following formula: (Rsen / Lsen)=1 / (Rs・Cs) Rsen: Resistance value of shunt resistor Lsen: Parasitic inductance value of shunt resistor Rs: resistance value of the second resistor Cs: Capacitance of the capacitor

2. 2. The semiconductor device according to claim 1, wherein the RC network circuit is disposed at a position where it does not cross a magnetic flux caused by a current flowing through the shunt resistor.

3. The shunt resistor is mounted on one surface of the substrate, 2. The semiconductor device according to claim 1, wherein the RC network circuit is mounted on the other surface of the substrate at a position overlapping the shunt resistor in the thickness direction.

4. The shunt resistor includes a plurality of first resistors; 2. The semiconductor device according to claim 1, wherein the first resistors are connected in parallel to generate magnetic fluxes that cancel out magnetic fluxes generated by adjacent first resistors.

5. 2. The semiconductor device according to claim 1, wherein a shield is formed between the RC network circuit and the shunt resistor.

6. The semiconductor device according to claim 5 , wherein the shield is connected to a ground potential.

7. The semiconductor device according to claim 1 , wherein the switching element is a SiC MOSFET.

8. 2. The semiconductor device according to claim 1, wherein the switching element is an IGBT.

9. 2. The semiconductor device according to claim 1, wherein the switching element is a Si-based MOSFET.

10. 2. The semiconductor device according to claim 1, wherein the capacitance of the capacitor in the RC network circuit is 500 pF or less.

11. 2. The semiconductor device according to claim 1, further comprising a lifetime estimation unit that estimates a lifetime of the switching element from a voltage across the capacitor of the RC network circuit.

12. An inverter comprising the semiconductor device according to any one of claims 1 to 11.

13. A DC / DC converter comprising the semiconductor device according to any one of claims 1 to 11.

14. A switching power supply device comprising the DC / DC converter according to claim 13.

15. A motor drive circuit including the semiconductor device according to any one of claims 1 to 11, a plurality of pairs of switching elements, each pair including a first switching element connected to the shunt resistor and a second switching element connected in series with the first switching element; A motor drive circuit having a configuration in which a connection point between the first switching element and the second switching element of each pair can be connected to a coil of the motor.

16. A vehicle comprising the semiconductor device according to any one of claims 1 to 11.