Charge pump circuit, semiconductor device, switch control device, and vehicle

Abstract

When the operation of a charge pump circuit (10) is stopped, a first control circuit (1) brings each of a first transistor (M1) and a second transistor (M2) into an ON state.

Description

Charge pump circuit, semiconductor device, switch control device, and vehicle

[0001] The present disclosure relates to a charge pump circuit.

[0002] 2. Description of the Related Art Conventionally, charge pump circuits are known that are used when a voltage higher than a power supply voltage is required (see, for example, Japanese Patent Application Laid-Open No. 2003-122999). The charge pump circuit is configured to be able to boost the power supply voltage.

[0003] Japanese Patent Application Laid-Open No. 2021-90308

[0004] In conventional charge pump circuits, there is room for improvement in the discharge speed of the capacitor used in the charge pump circuit.

[0005] An object of the present disclosure is to provide a charge pump circuit that can increase the discharge speed of a capacitor.

[0006] For example, a charge pump circuit according to the present disclosure comprises: a first transistor having a first main electrode connectable to a first end of a first capacitor; a second transistor having a first main electrode connected to a second main electrode of the first transistor and a second main electrode connectable to an application end of a first power supply voltage; a third transistor having a first main electrode connectable to an application end of a second power supply voltage; a fourth transistor having a first main electrode connected to the second main electrode of the third transistor and a second main electrode connectable to an application end of a ground potential; a first control circuit configured to control the driving of the first transistor and the second transistor; and a second control circuit configured to control the driving of the third transistor and the fourth transistor; wherein the voltage of the first main electrode of the first transistor is an output voltage; a first end of a second capacitor can be connected to a first node to which the second main electrode of the first transistor and the first main electrode of the second transistor are connected; A second end of the second capacitor can be connected to a second node where the second main electrode of the third transistor and the first main electrode of the fourth transistor are connected, and when the operation of the charge pump circuit is stopped, the first control circuit is configured to turn on each of the first transistor and the second transistor.

[0007] The charge pump circuit according to the present disclosure can increase the discharge speed of the capacitor.

[0008] FIG. 1 is a diagram illustrating a first driving state of a charge pump circuit. FIG. 2 is a diagram illustrating a second driving state of the charge pump circuit. FIG. 3 is a timing chart illustrating an example of operation of a charge pump circuit according to a comparative example. FIG. 4 is a diagram illustrating a driving state during a stop operation of the charge pump circuit. FIG. 5 is a timing chart illustrating an example of operation of a charge pump circuit according to an embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example in which an overvoltage detection configuration is applied to a charge pump circuit according to an embodiment of the present disclosure. FIG. 7 is a timing chart illustrating an example of overvoltage detection. FIG. 8 is a diagram illustrating a configuration of a switch control device according to an embodiment of the present disclosure. FIG. 9 is a diagram illustrating an example of operation of a switch control device according to an embodiment of the present disclosure. FIG. 10 is an external view illustrating an example of a configuration of a vehicle.

[0009] Exemplary embodiments of the present disclosure will now be described with reference to the drawings.

[0010] 1. Configuration of the Charge Pump Circuit The configuration of the charge pump circuit will be described with reference to Fig. 1. The charge pump circuit 10 shown in Fig. 1 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first control circuit 1, and a second control circuit 2.

[0011] The first transistor M1 is configured by a PMOS transistor (P-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)). The source of the first transistor M1 is connected to a first end of the first capacitor C1 via the VCPH terminal. The second end of the first capacitor C1 is connected to an application terminal of a first power supply voltage VB. The first power supply voltage VB is, for example, a battery voltage.

[0012] The second transistor M2 is an NMOS transistor (N-channel MOSFET). The drain of the first transistor M2 is connected to the drain of the second transistor M2 at a node N1. The source of the second transistor M2 is connected to an application terminal of the first power supply voltage VB. The node N1 is connected to a first terminal of the second capacitor C2 via the CPH terminal.

[0013] The third transistor M3 is a PMOS transistor. The source of the third transistor M3 is connected to the application terminal of the second power supply voltage V1. The fourth transistor M4 is an NMOS transistor. The drain of the third transistor M3 is connected to the drain of the fourth transistor M4 at the node N2. The source of the fourth transistor M4 is connected to the application terminal of the ground potential.

[0014] A first end of the second capacitor C2 is connected to the node N1 via the CPH terminal, and a second end of the second capacitor C2 is connected to the node N2 via the CPL terminal.

[0015] The first control circuit 1 drives the first transistor M1 and the second transistor M2 by applying a drive signal G1 to the gate of the first transistor M1 and a drive signal G2 to the gate of the second transistor M2. The first control circuit 1 generates the drive signal G1 based on the output voltage VCPH of the VCPH terminal, and generates the drive signal G2 based on the first power supply voltage VB.

[0016] The second control circuit 2 drives the third transistor M3 and the fourth transistor M4 by applying a drive signal G3 to the gate of the third transistor M3 and a drive signal G4 to the gate of the fourth transistor M4. The second control circuit 2 generates the drive signal G3 based on the second power supply voltage V1 and generates the drive signal G4 based on the ground potential.

[0017] 2. Steady-State Operation of Charge Pump Circuit Next, the steady-state operation of the charge pump circuit 10 configured as described above will be described with reference to FIGS. 1 to 3. FIGS. 1 and 2 are diagrams showing the driving state of the charge pump circuit 10 during steady-state operation. FIG. 3 is a timing chart showing an example of the operation of the charge pump circuit 10. In FIG. 3, the upper row shows the voltage CPH at the CPH terminal and the output voltage VCPH at the VCPH terminal, and the lower row shows the voltage CPL at the CPL terminal.

[0018] At timing t1 in Figure 3, the first control circuit 1 and the second control circuit 2 switch the second transistor M2 and the fourth transistor M4 from an OFF state to an ON state. At this time, the first control circuit 1 and the second control circuit 2 keep the first transistor M1 and the third transistor M3 in an OFF state. Therefore, the charge pump circuit 10 is in the operating state shown in Figure 1. When the first and third transistors M1 and M3 are switched from an ON state to an OFF state and when the second and fourth transistors M2 and M4 are switched from an OFF state to an ON state, a so-called dead time is provided between the first and second transistors M1 and M2 and between the third and fourth transistors M3 and M4, which is a period during which the transistors are simultaneously OFF.

[0019] At this time, the voltage CPH becomes the first power supply voltage VB, the voltage CPL becomes the ground potential (0 V), and the first power supply voltage VB is applied to the second capacitor C2, which charges it. Furthermore, in order to turn on the second transistor M2, the gate capacitance of the second transistor M2 is charged, and a discharge current Idsg flows from the first capacitor C1 to the first control circuit 1 via the VCPH terminal, as shown in FIG. 1, causing the output voltage VCPH to drop slightly. Thereafter, the first capacitor C1 is discharged by the discharge current Idsg due to the steady-state operating current in the first control circuit 1, and the output voltage VCPH drops at a slope determined by the discharge current Idsg and the capacitance of the first capacitor C1.

[0020] Thereafter, at timing t2, the first control circuit 1 and the second control circuit 2 switch the first transistor M1 and the third transistor M3 from the OFF state to the ON state, respectively. At this time, the first control circuit 1 and the second control circuit 2 keep the second transistor M2 and the fourth transistor M4 in the OFF state, respectively. Therefore, the charge pump circuit 10 is in the operating state shown in FIG. 2. Note that when the first and third transistors M1 and M3 are switched from the OFF state to the ON state, and when the second and fourth transistors M2 and M4 are switched from the ON state to the OFF state, dead time is provided between the first and second transistors M1 and M2 and between the third and fourth transistors M3 and M4.

[0021] At this time, the voltage CPH and the output voltage VCPH become VB+V1, and the voltage CPL becomes V1. Also, V1 is applied to the first capacitor C1 and it is charged. Thereafter, the driving states shown in Figures 1 and 2 are repeated. As a result, the output voltage VCPH, which is higher than the first power supply voltage VBB, is output from the VCPH terminal.

[0022] <3. Shutdown Operation of Charge Pump Circuit> Next, the shutdown operation of the charge pump circuit 10 will be described. In the comparative charge pump circuit 10, when the shutdown operation is performed, the first control circuit 1 and the second control circuit 2 turn off the first and third transistors M1 and M3 and turn on the second and fourth transistors M2 and M4. That is, the charge pump circuit 10 is in the drive state shown in FIG. 1. In the example of FIG. 3, the shutdown operation is performed at timing t3 in the drive state shown in FIG. 2. As a result, the voltage CPH becomes VB and the voltage CPL becomes ground potential. Furthermore, the output voltage VCPH decreases slightly due to a transient discharge current Idsg, and then gradually decreases due to the discharge current Idsg. Therefore, there is a problem in that the discharge rate of the first capacitor C1 is slow.

[0023] Therefore, in the charge pump circuit 10 according to the embodiment of the present disclosure, when a stopping operation is performed, the first control circuit 1 and the second control circuit 2 turn on the first, second, and fourth transistors M1, M2, and M4, respectively, and turn off the third transistor M3. That is, the charge pump circuit 10 is driven as shown in Fig. 4. Note that the state is not limited to that shown in Fig. 4, and the third transistor M3 may be turned on and the fourth transistor M4 may be turned off.

[0024] FIG. 5 is a timing chart illustrating an example of operation of the charge pump circuit 10 according to an embodiment of the present disclosure. In the example of FIG. 5, a stopping operation is performed at timing t3 during the driving state shown in FIG. 2 . As a result, the voltage CPH becomes VB and the voltage CPL becomes ground potential. Furthermore, because the first transistor M1 is on, the output voltage VCPH rapidly decreases toward VB due to the rapid discharge of the first capacitor C1. As shown in FIG. 5, after the rapid decrease in the output voltage VCPH, the second transistor M2 is off, and the first capacitor C1 is discharged by the discharge current Idsg, causing the output voltage VCPH to decrease gradually. Thus, according to an embodiment of the present disclosure, the discharge of the first capacitor C1 can be accelerated during the stopping operation. Furthermore, a separate component such as a switch for discharging the first capacitor C1 is not required.

[0025] 4. Overvoltage Detection Configuration An embodiment in which an overvoltage detection configuration is applied to the charge pump circuit 10 according to the embodiment of the present disclosure as described above will be described. Fig. 6 is a diagram showing the configuration of the charge pump circuit 10 according to the embodiment of the present disclosure, including the overvoltage detection configuration. Note that in Fig. 6, part of the configuration shown in Fig. 1 (the configuration on the CPL side) is omitted from the illustration.

[0026] 6, the charge pump circuit 10 includes an overvoltage detection unit 3. The overvoltage detection unit 3 includes a first overvoltage detection unit 3A, a second overvoltage detection unit 3B, and a third overvoltage detection unit 3C. The first overvoltage detection unit 3A includes a first comparator 31 and voltage-dividing resistors R1 and R2. The second overvoltage detection unit 3B includes a second comparator 32 and voltage-dividing resistors R3 and R4. The third overvoltage detection unit 3C includes a third comparator 33.

[0027] The voltage-dividing resistors R1 and R2 are connected in series between the application terminal of the first power supply voltage VB and the application terminal of the ground potential. The non-inverting input terminal (+) of the first comparator 31 is connected to the node to which the voltage-dividing resistors R1 and R2 are connected. The inverting input terminal (-) of the first comparator 31 is connected to the application terminal of the reference voltage Vref1. As a result, the first comparator 31 compares the voltage obtained by dividing the first power supply voltage VB using the voltage-dividing resistors R1 and R2 with the first reference voltage Vref1 and outputs a first detection signal DET1. When the divided voltage exceeds the first reference voltage Vref1, an overvoltage of the first power supply voltage VB relative to the ground potential is detected, and the first detection signal DET1 goes high.

[0028] The voltage-dividing resistors R3 and R4 are connected in series between the application terminal of the output voltage VCPH and the application terminal of the ground potential. The non-inverting input terminal (+) of the second comparator 32 is connected to the node to which the voltage-dividing resistors R3 and R4 are connected. The inverting input terminal (-) of the second comparator 32 is connected to the application terminal of the reference voltage Vref2. As a result, the second comparator 32 compares the voltage obtained by dividing the output voltage VCPH using the voltage-dividing resistors R3 and R4 with the second reference voltage Vref2 and outputs a second detection signal DET2. When the divided voltage exceeds the second reference voltage Vref2, an overvoltage of the output voltage VCPH with respect to the ground potential is detected, and the second detection signal DET2 goes high.

[0029] The non-inverting input terminal of the third comparator 33 is connected to the terminal to which the output voltage VCPH is applied. The inverting input terminal of the third comparator 33 is connected to the terminal to which a third reference voltage Vref3, which is based on the first power supply voltage VB, is applied. As a result, the third comparator 33 outputs a high-level third detection signal DET3 when VCPH-VB exceeds Vref3. In other words, the third comparator 33 detects an overvoltage of VCPH-VB (the voltage between VCPH and VB).

[0030] The first to third detection signals DET1 to DET3 are input to, for example, an OR circuit (not shown) provided in the overvoltage detection unit 3, and the output of the OR circuit is input to the first control circuit 1. In this case, when an overvoltage is detected by at least one of the first to third comparators 31 to 33, the output of the OR circuit becomes high level, and the first control circuit 1 performs a stop operation.

[0031] An example of overvoltage detection will be described with reference to Fig. 7. Fig. 7 is a timing chart showing an example of the behavior of the first power supply voltage VB and the output voltage VCPH when a test is conducted in which the first power supply voltage VB is increased from a predetermined value VB1 to a predetermined value VB2. The increase from VB1 to VB2 takes a predetermined time T.

[0032] Assume that initially, VB = VB1, and VCPH = VB1 + V1 due to steady-state operation of the charge pump circuit 10. Then, at timing t11, VB starts to rise, and since VCPH = VB + V1, VCPH also starts to rise. After that, when VB exceeds the first overvoltage detection threshold OVP1 at timing t12, an overvoltage is detected by the first comparator 31 ( FIG. 6 ), and the first detection signal DET1 goes high.

[0033] As a result, the first control circuit 1 performs a shutdown operation. That is, the first and second transistors M1 and M2 are turned on. Therefore, the first capacitor C1 is discharged at high speed, and VCPH rapidly decreases toward VB. Thereafter, VCPH gradually decreases toward VB, and at timing t13, VB reaches VB2.

[0034] If the shutdown operation according to the comparative example described above were performed when overvoltages on VB and VCPH were detected, i.e., if the first transistor M1 were turned off and the second transistor M2 were turned on, the discharge rate of the first capacitor C1 would be slow, and VCPH could exceed the breakdown voltage VT of the first and second transistors M1 and M2 after timing t12, as shown by the dashed line in Figure 7. Therefore, by performing the shutdown operation according to the embodiment of the present disclosure, the first capacitor C1 is discharged quickly, preventing VCPH from exceeding the breakdown voltage VT. This eliminates the need to increase the breakdown voltages of the first and second transistors M1 and M2.

[0035] To explain this using a specific numerical example, for example, if VB1=48V, V1=12V, VB2=70V, OVP1=60V, OVP2=72V, VT=80V, and T=1 ms, then while VB is increasing from 48V to 70V, VB exceeds OVP1=60V and VCPH exceeds OVP2=72V, an overvoltage is detected, and a shutdown operation is performed. This makes it possible to prevent VCPH from exceeding VT=80V.

[0036] The overvoltage detection unit 3 may include at least one of the first to third overvoltage detection units 3A to 3C.

[0037] 5. Switch Control Device Next, an example in which the charge pump circuit 10 according to an embodiment of the present disclosure is applied to a switch control device will be described. Fig. 8 is a diagram showing the configuration of a switch control device 15 equipped with the charge pump circuit 10 according to an embodiment of the present disclosure. The switch control device 15 drives and controls a high-side switch QH and a low-side switch QL that form a half bridge.

[0038] The high-side switch QH and the low-side switch QL are configured by NMOS transistors and are connected in series between an application terminal of the first power supply voltage VB and an application terminal of the ground potential.

[0039] The switch control device 15 is a semiconductor device that integrates a charge pump circuit 10, a control logic unit 4, a Vds (drain-source voltage) detection unit 5, a Vgs (gate-source voltage) detection unit 6, and pre-drivers 7 and 8. The switch control device 15 also has a VB terminal, an EN terminal, a VCPH terminal, a CPH terminal, a CPL terminal, a DRN terminal, a GH terminal, an SH terminal, and a GL terminal as external terminals for establishing electrical connection with the outside.

[0040] The VB terminal is connected to an application terminal of the first power supply voltage VB. The EN terminal is connected to an application terminal of the enable signal EN. The enable signal EN is input to the control logic unit 4 via the EN terminal.

[0041] As described above, the first capacitor C1 is connected to the VCPH terminal, and the second capacitor C2 is connected between the CPH terminal and the CPL terminal.

[0042] The Vds detection unit 5 is connected to the DRN terminal and also to the source of the high-side switch QH via the SH terminal. The DRN terminal is connected to the drain of the high-side switch QH. A switch SW is connected between the application terminal of the first power supply voltage VB and the DRN terminal. The on / off of the switch SW is controlled by the output voltage VCPH. The Vds detection unit 5 detects an overvoltage of Vds of the high-side switch QH.

[0043] The gate of the high-side switch QH is connected via a GH terminal to the Vgs detection unit 6, and the source of the high-side switch QH is connected via an SH terminal to the Vgs detection unit 6. The Vgs detection unit 6 detects an overvoltage of Vgs of the high-side switch QH.

[0044] The pre-driver 7 drives the high-side switch QH via the GH terminal under the control of the control logic unit 4. The pre-driver 7 applies the output voltage VCPH to the gate of the high-side switch QH, turning on the high-side switch QH, which is an NMOS transistor. The pre-driver 8 drives the low-side switch QL via the GL terminal under the control of the control logic unit 4.

[0045] Next, the operation of the switch control device 15 will be described using the timing chart shown in Fig. 9. In Fig. 9, from the top to the bottom, examples of the state of the switch control device 15, the behavior of the first power supply voltage VB, the enable signal EN, and the behavior of the output voltage VCPH are shown.

[0046] First, the startup operation will be described. At an initial timing t21, the first power supply voltage VB starts from 0 V, and VCPH also starts up accordingly. Then, at timing t22, when the first power supply voltage VB reaches a predetermined value, the control logic unit 4 enters a sleep state.

[0047] Thereafter, the enable signal is activated at timing t23. When the enable signal EN reaches a predetermined level at timing t24, the control logic unit 4 is activated and executes a self-diagnostic operation called BIST (Built-In Self Test).

[0048] Then, at timing t25, the control logic unit 4 commands the charge pump circuit 10 to start boosting operation. As a result, the output voltage VCPH rises to VB+V1. This turns on the switch SW. Then, at timing t26, the control logic unit 4 executes BIST on the Vds detection unit 5 and the Vgs detection unit 6. Specifically, it is confirmed whether the comparators included in the Vds detection unit 5 and the Vgs detection unit 6 are operating normally.

[0049] When the BIST is completed, the charge pump circuit 10 stops operating at timing t27 in response to a command from the control logic unit 4. This causes the first capacitor C1 to discharge, lowering VCPH. When the discharge is complete, the circuit transitions to a standby state (timing t28).

[0050] In this way, in the switch control device 15 including the charge pump circuit 10 according to the embodiment of the present disclosure, the discharge rate of the first capacitor C1 can be increased during the shutdown operation of the charge pump circuit 10, and the startup time from timing t23 when the enable signal EN is activated to timing t28 when the charge pump circuit 10 transitions to the standby state after passing through a BIST that requires a boost operation can be reduced to Ts1. In the case of the shutdown operation according to the comparative example, as shown by the dashed line VCPH in FIG. 9 , the discharge rate of the first capacitor C1 is slow, and the startup time is Ts2, and the startup time can be reduced from Ts2 to Ts1.

[0051] After entering the standby state, the charge pump circuit 10 starts boosting (timing t29), and when VCPH is boosted (timing t30), the circuit enters the active state. Thereafter, when an abnormality is detected by the protection circuit in the switch control device 15 (for example, an overvoltage is detected by the overvoltage detection unit 3) (timing t31), the charge pump circuit 10 stops and the first capacitor C1 is discharged. As a result, VCPH decreases. When the discharge is completed (timing t32), the circuit enters the standby state.

[0052] In this way, in the switch control device 15 including the charge pump circuit 10 according to the embodiment of the present disclosure, the discharge rate of the first capacitor C1 can be increased during the shutdown operation of the charge pump circuit 10, thereby shortening the restart wait time to Tw1 from timing t31 when the protection operation is started to timing t32 when the device transitions to the standby state. In the case of the shutdown operation according to the comparative example, as shown by the dashed line VCPH in FIG. 9 , the discharge rate of the first capacitor C1 is slow, and the restart wait time is Tw2, thereby shortening the restart wait time from Tw2 to Tw1.

[0053] 6. Application to Vehicles The above-described switch control device 15 is used, for example, to drive an in-vehicle motor. Fig. 10 shows an external view of an example configuration of a vehicle equipped with the switch control device 15 in this case. Fig. 10 shows various motors X11 to X17 equipped on a vehicle X as application examples of the switch control device 15.

[0054] X11 is an electric power steering motor. X12 is an electric oil pump motor. X13 is a headlight drive motor. X14 is an electric parking brake motor. X15 is a seat cooling fan motor. X16 is a door opening / closing motor. X17 is a door lock motor.

[0055] <7. Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0056] For example, the charge pump circuit according to the embodiment of the present disclosure is not limited to a single-stage boosting circuit, but may support two or more stages of boosting.

[0057] 8. Supplementary Note As described above, for example, a charge pump circuit (10) according to one aspect of the present disclosure includes: a first transistor (M1) having a first main electrode configured to be connectable to a first end of a first capacitor (C1); a second transistor (M2) having a first main electrode connected to a second main electrode of the first transistor and a second main electrode configured to be connectable to an application end of a first power supply voltage (VB); a third transistor (M3) having a first main electrode configured to be connectable to an application end of a second power supply voltage (V1); a fourth transistor (M4) having a first main electrode connected to the second main electrode of the third transistor and a second main electrode configured to be connectable to an application end of a ground potential; a first control circuit (1) configured to control driving of the first transistor and the second transistor; and a second control circuit (2) configured to control driving of the third transistor and the fourth transistor, wherein the voltage of the first main electrode of the first transistor is an output voltage (VCPH), A first end of a second capacitor (C2) can be connected to a first node (N1) where the second main electrode of the first transistor and the first main electrode of the second transistor are connected, and a second end of the second capacitor can be connected to a second node (N2) where the second main electrode of the third transistor and the first main electrode of the fourth transistor are connected, and when stopping operation of the charge pump circuit, the first control circuit is configured to turn on each of the first transistor and the second transistor (first configuration).

[0058] In addition, in the first configuration, when the operation of the charge pump circuit (10) is stopped, the first control circuit (1) turns on the first transistor (M1) and the second transistor (M2), thereby performing high-speed discharge of the first capacitor (C1) (second configuration).

[0059] In addition, in the first or second configuration, a first overvoltage detection unit (3A) configured to detect an overvoltage of the first power supply voltage (VB) based on the ground potential may be further provided, and when an overvoltage is detected by the first overvoltage detection unit, the charge pump circuit may be configured to perform a stop operation (third configuration).

[0060] Furthermore, in any of the first to third configurations, a second overvoltage detection unit (3B) configured to detect an overvoltage of the output voltage (VCPH) relative to the ground potential may be further provided, and when an overvoltage is detected by the second overvoltage detection unit, the charge pump circuit may be configured to perform a stop operation (fourth configuration).

[0061] Furthermore, in any of the first to fourth configurations, a third overvoltage detection unit (3C) configured to detect an overvoltage between the output voltage (VCPH) and the first power supply voltage (VB) may be further provided, and when an overvoltage is detected by the third overvoltage detection unit, the charge pump circuit may be configured to perform a stop operation (fifth configuration).

[0062] Furthermore, one aspect of the present disclosure is a semiconductor device (15) including a charge pump circuit (10) of any one of the first to fifth configurations described above and a control unit (4), wherein the control unit goes into a sleep state when the first power supply voltage (VB) starts up and reaches a predetermined value, the control unit then causes the charge pump circuit to start a boost operation, the control unit then executes a self-diagnostic operation (BIST), and the control unit then causes the charge pump circuit to perform a stop operation (sixth configuration).

[0063] In addition, in the sixth configuration, the semiconductor device (15) is configured to drive a high-side switch (QH) and a low-side switch (QL) that form a half bridge, and the semiconductor device includes a Vds detection unit (5) configured to detect an overvoltage between the drain and source of the high-side switch, and the control unit may be configured to execute the self-diagnosis operation of the Vds detection unit (seventh configuration).

[0064] In addition, in the sixth or seventh configuration, the semiconductor device (15) is configured to drive a high-side switch (QH) and a low-side switch (QL) that form a half bridge, and the semiconductor device includes a Vgs detection unit (6) configured to detect an overvoltage between the gate and source of the high-side switch, and the control unit may be configured to execute the self-diagnosis operation of the Vgs detection unit (eighth configuration).

[0065] Furthermore, a switch control device (15) according to one aspect of the present disclosure includes a charge pump circuit (10) having any one of the first to fifth configurations, and is configured to drive a high-side switch (QH) and a low-side switch (QL) that form a half bridge (ninth configuration).

[0066] Furthermore, a vehicle (X) according to one aspect of the present disclosure includes the switch control device (15) of the ninth configuration (tenth configuration).

[0067] The present disclosure can be used, for example, in switch control devices for various applications.

[0068] REFERENCE SIGNS LIST 1 First control circuit 2 Second control circuit 3 Overvoltage detection unit 4 Control logic unit 5 Vds detection unit 6 Vgs detection unit 7, 8 Pre-driver 10 Charge pump circuit 15 Switch control device 31 First comparator 32 Second comparator 33 Third comparator C1 First capacitor C2 Second capacitor M1 First transistor M2 Second transistor M3 Third transistor M4 Fourth transistor QH High-side switch QL Low-side switch R1 to R4 Voltage dividing resistors SW Switch X Vehicle

Claims

1. a first transistor having a first main electrode configured to be connectable to a first end of the first capacitor; a second transistor having a first main electrode connected to the second main electrode of the first transistor and a second main electrode configured to be connectable to an application terminal of a first power supply voltage; a third transistor having a first main electrode configured to be connectable to an application terminal of a second power supply voltage; a fourth transistor having a first main electrode connected to the second main electrode of the third transistor and a second main electrode configured to be connectable to a terminal to which a ground potential is applied; a first control circuit configured to control driving of the first transistor and the second transistor; a second control circuit configured to control the driving of the third transistor and the fourth transistor; Equipped with The voltage of the first main electrode of the first transistor becomes an output voltage, a first end of a second capacitor can be connected to a first node at which the second main electrode of the first transistor and the first main electrode of the second transistor are connected; a second end of the second capacitor can be connected to a second node to which the second main electrode of the third transistor and the first main electrode of the fourth transistor are connected; When the operation of the charge pump circuit is stopped, the first control circuit turns on the first transistor and the second transistor.

2. 2. The charge pump circuit according to claim 1, wherein when the operation of the charge pump circuit is stopped, the first control circuit turns on the first transistor and the second transistor, thereby discharging the first capacitor at high speed.

3. a first overvoltage detection unit configured to detect an overvoltage of the first power supply voltage relative to the ground potential; 2. The charge pump circuit according to claim 1, wherein when an overvoltage is detected by said first overvoltage detection unit, said charge pump circuit performs a stop operation.

4. a second overvoltage detection unit configured to detect an overvoltage of the output voltage relative to the ground potential; 2. The charge pump circuit according to claim 1, wherein when an overvoltage is detected by said second overvoltage detection unit, said charge pump circuit performs a stop operation.

5. a third overvoltage detection unit configured to detect an overvoltage between the output voltage and the first power supply voltage; 2. The charge pump circuit according to claim 1, wherein when an overvoltage is detected by said third overvoltage detection unit, said charge pump circuit performs a stop operation.

6. A semiconductor device comprising the charge pump circuit according to any one of claims 1 to 5 and a control unit, When the first power supply voltage is activated and reaches a predetermined value, the control unit goes into a sleep state, Thereafter, the control unit causes the charge pump circuit to start a boosting operation, Thereafter, the control unit executes a self-diagnosis operation, Thereafter, the control unit causes the charge pump circuit to perform a stop operation.

7. The semiconductor device is configured to drive a high-side switch and a low-side switch that configure a half bridge, The semiconductor device includes a Vds detection unit configured to detect an overvoltage between the drain and source of the high-side switch, The semiconductor device according to claim 6 , wherein said control section executes said self-diagnosis operation of said Vds detection section.

8. The semiconductor device is configured to drive a high-side switch and a low-side switch that configure a half bridge, The semiconductor device includes a Vgs detection unit configured to detect an overvoltage between the gate and source of the high-side switch, The semiconductor device according to claim 6 , wherein said control section executes said self-diagnosis operation of said Vgs detection section.

9. A switch control device comprising the charge pump circuit according to any one of claims 1 to 5, and configured to drive a high-side switch and a low-side switch that form a half bridge.

10. A vehicle comprising the switch control device according to claim 9.