Switch control device, switch device, engine ignition device, and vehicle

Abstract

A switch control device (12) comprises: a current limiting unit (125) that is configured to limit a current flowing in a switch element (111), on the basis of a limiting current value and via a drive circuit (122); and a soft shut-off unit (126) that is configured to carry out charging of a capacitor (C3). A switch control unit (121) switches the switch element ON when an input signal (S) is switched to a first logic level. If a command is received from the switch control unit on the basis of abnormality detection by abnormality detection units (123, 124), the soft shut-off unit starts charging of the capacitor and lowers the limiting current value in accordance with an increase of the voltage (VC3) of the capacitor.

Description

Switch control device, switch device, engine ignition device, and vehicle

[0001] The present disclosure relates to a switch control device.

[0002] An igniter is a type of switch device that includes a switch element and a switch control device. In the igniter, the switch control device controls the switch element to control the primary voltage of an ignition coil connected to an ignition plug of an engine (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2020-101152

[0004] When an igniter detects an abnormality such as overheating, it abruptly turns off the switch element as a protective function, causing a sudden decrease in the current flowing through the switch element, which generates a secondary voltage in the ignition coil and generates a spark, which can cause an unintended ignition.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a switch control device that can suppress the occurrence of malfunctions when a switch element is turned off in the event of an abnormality.

[0006] For example, a switch control device according to the present disclosure includes: a drive circuit configured to apply a drive voltage to a control end of a switch element; a switch control unit configured to control the switch element via the drive circuit based on an input signal; an abnormality detection unit configured to detect at least one of an overcurrent state and an overheat state of the switch element; a current limiting unit configured to limit a current flowing through the switch element via the drive circuit based on a limited current value; and a soft shutoff unit configured to charge a capacitor, wherein the switch control unit switches the switch element to an ON state when the input signal switches to a first logic level, and the soft shutoff unit starts charging the capacitor when receiving a command from the switch control unit based on the detection of an abnormality by the abnormality detection unit, and reduces the limited current value in accordance with an increase in the voltage of the capacitor.

[0007] According to the switch control device according to the present disclosure, it is possible to suppress the occurrence of malfunctions that may occur when a switch element is turned off in the event of an abnormality.

[0008] FIG. 1 is a diagram illustrating a configuration of an engine ignition device according to a comparative example. FIG. 2 is a timing chart illustrating an example of the operation of a switch device according to a comparative example. FIG. 3 is a diagram illustrating a configuration of an engine ignition device including a switch device according to an exemplary embodiment of the present disclosure. FIG. 4 is a plan view illustrating an example of the layout of the internal configuration of the switch device. FIG. 5 is a diagram illustrating a specific example of the configuration of a temperature sensor and an overheat detection unit. FIG. 6 is a diagram illustrating a specific example of the configuration of a soft shutoff unit and a current limiting unit. FIG. 7 is a circuit diagram illustrating a more specific example of the configuration of the soft shutoff unit, the current limiting unit, and a drive circuit. FIG. 8A is a timing chart illustrating an example of operation during normal operation. FIG. 8B is a timing chart illustrating an example of operation when an overcurrent abnormality occurs. FIG. 9 is a diagram illustrating an example of the configuration of a vehicle.

[0009] 1. Comparative Example First, before describing an embodiment according to the present disclosure, a comparative example will be described. In comparison with the comparative example, the problems of the embodiment according to the present disclosure will become clearer.

[0010] 1 is a diagram showing the configuration of an engine ignition device 1 according to a comparative example. The engine ignition device 1, a power source 2, and an engine control unit 3 (hereinafter abbreviated as ECU 3) are mounted on a vehicle as means for driving a gasoline engine (not shown). The power source 2 is configured as a car battery.

[0011] The engine ignition device 1 operates by receiving power from a power source 2, and is a means for igniting fuel (a mixture of gasoline and air) inside the gasoline engine in response to an ignition command signal S from an ECU 3, and includes a switch device 10, an ignition coil 20, and an ignition plug 30. The switch device 10 is configured as an igniter.

[0012] The switch device 10 is a means for turning on / off the primary coil current (corresponding to the collector current Ic of the switch element 111) of the ignition coil 20, and is provided as a semiconductor device in which a switch chip 11 and a switch control device 12 are packaged. The switch device 10 also includes a shunt resistor 13. Furthermore, the switch device 10 includes a VDD terminal, an OUT terminal, an IN terminal, and a GND terminal as external terminals.

[0013] The switch chip 11 is a semiconductor chip that integrates a switch element 111 and a temperature sensor 112. In this example, an IGBT (insulated gate bipolar transistor) is used as the switch element 111. The switch element 111 has a gate (control end) connected to a drive circuit 122, a collector connected to a primary coil 21 of an ignition coil 20 via an OUT terminal, and an emitter connected to a GND terminal via a shunt resistor 13. A ground potential is applied to the GND terminal. Note that instead of an IGBT, a MOSFET (metal oxide semiconductor field effect transistor), for example, may be used as the switch element 111. The temperature sensor 112 is an element for detecting the temperature of the switch element 111.

[0014] The switch control device 12 is a semiconductor chip that integrates a switch control unit 121, a drive circuit 122, an overcurrent detection unit 123, an overheat detection unit 124, and a current limiting unit 125.

[0015] The switch control unit 121 controls the drive circuit 122 based on the ignition instruction signal S received from the ECU 3 via the IN terminal, causing the drive circuit 122 to perform on / off control of the switch element 111. The ECU 3 executes various controls related to the operation of the vehicle engine. In particular, as one of the various controls, the ECU 3 outputs the ignition instruction signal S (= a pulse signal driven by PWM) used to control the operation of the switch device 10 (particularly the switch control unit 121). More specifically, when the ECU 3 turns on the switch element 111, the ECU 3 sets the ignition instruction signal S to an on-logic level (e.g., high level), and when the ECU 3 turns off the switch element 111, the ECU 3 sets the ignition instruction signal S to an off-logic level (e.g., low level).

[0016] The drive circuit 122 generates a drive voltage Gd and applies it to the gate of the switch element 111 to drive the switch element 111. When the ignition instruction signal S is at an on logic level, the drive circuit 122 generates a high-level drive voltage Gd under the control of the switch control unit 121, thereby turning the switch element 111 into an on state. On the other hand, when the ignition instruction signal S is at an off logic level, the drive circuit 122 generates a low-level drive voltage Gd under the control of the switch control unit 121, thereby turning the switch element 111 into an off state.

[0017] The overcurrent detection unit 123 detects overcurrent of the switch element 111. Specifically, the overcurrent detection unit 123 detects whether the period during which the ignition signal S is at the ON logic level is excessively long.

[0018] The overheat detection unit 124 detects an overheat state of the switch element 111. Specifically, the overheat detection unit 124 detects whether the temperature detected by the temperature sensor 112 is equal to or higher than a predetermined temperature. The temperature sensor 112 is integrated into the switch chip 11 together with the switch element 111, and therefore, the temperature of the switch element 111 can be detected with high accuracy.

[0019] When an abnormality is detected by the overcurrent detection unit 123 or the overheat detection unit 124, the switch control unit 121 turns off the switch element 111 via the drive circuit 122 in response to a command from the overcurrent detection unit 123 or the overheat detection unit 124. This allows a protective operation to be performed.

[0020] The current limiting unit 125 controls the gate voltage Gt via the drive circuit 122 based on the current detection signal Vis generated by the primary coil current flowing through the shunt resistor 13, thereby limiting (clamping) the primary coil current to a predetermined limit current value so that it does not exceed the limit current value.

[0021] The ignition coil 20 includes a primary coil 21 with a number of turns M1 and a secondary coil 22 with a number of turns M2 (>M1), and serves to convert (boost) the input voltage (= power supply voltage Vdd) supplied from the power supply 2 to a higher output voltage. A first end of the primary coil 21 and a first end of the secondary coil 22 are both connected to the output end (= application end of the power supply voltage Vdd) of the power supply 2. A second end of the primary coil 21 is connected to the collector of the switch element 111. A second end of the secondary coil 22 is connected to the spark plug 30, and the output voltage generated at the second end of the secondary coil 22 is supplied to the spark plug 30.

[0022] The spark plug 30 uses the high voltage obtained by the ignition coil 20 to generate a spark for igniting fuel injected into the engine (not shown).

[0023] The power supply 2 supplies power to various electrical components mounted on the vehicle, including the engine ignition device 1 .

[0024] Next, the operation of the switch device 10 configured as above will be described using the timing chart shown in Fig. 2. In Fig. 2, waveform examples are shown, from top to bottom, for the ignition instruction signal S, the drive voltage Gd, the primary coil current, the collector voltage VCE of the switch element 111, and the secondary voltage V22 of the ignition coil 20. In the following description, the high level of the ignition instruction signal S is the logic level when it is on, and the low level is the logic level when it is off.

[0025] First, when the ignition instruction signal S rises from low to high at timing t1, the drive circuit 122 raises the drive voltage Gd from low to high under the control of the switch control unit 121. Then, the switch element 111 is turned on, and the primary coil current begins to flow.

[0026] While the primary coil current is increasing, the collector voltage VCE is lower than Vdd. Then, when the ignition command signal S falls to low level at timing t2, the drive circuit 122 falls to low level under the control of the switch control unit 121. This causes the switch element 111 to be turned off, and the primary coil current drops sharply to 0 A. This causes the collector voltage VCE to become much higher than Vdd, generating a high voltage in the secondary voltage V22. At this time, a spark SP is generated by the spark plug 30, igniting the fuel.

[0027] In this way, under normal circumstances, control is performed by the ignition instruction signal S so that ignition occurs at an appropriate timing when the piston is pushed by the crank in the engine and the space inside the cylinder is compressed.

[0028] However, an abnormality may occur in the ignition command signal S due to an abnormality in the ECU 3. Such a case will be described again with reference to Figure 2. When the ignition command signal S rises to a high level at timing t3, the drive voltage Gd also rises to a high level, as with timing t1 described above, and the primary coil current begins to flow as the switch element 111 is turned on.

[0029] Thereafter, the ignition instruction signal S is maintained at a high level beyond the normal high level period Ts, and when the primary coil current attempts to exceed the predetermined limit current value Icp at timing t4, the drive voltage Gd is adjusted to be lower than the high level by the control of the current limiting unit 125, and the primary coil current is clamped to the limit current value Icp.

[0030] The overcurrent detection unit 123 starts timing when the ignition instruction signal S rises to a high level. When it detects that the high level has been maintained for a predetermined period Tsth (>Ts), it transmits a command to the switch control unit 121 indicating that an overcurrent has occurred. If timing is started at timing t1, the ignition instruction signal S falls to a low level before the predetermined period Tsth has elapsed, and no overcurrent is detected. However, if timing is started at timing t3 and the ignition instruction signal S remains high at timing t5, after the predetermined period Tsth has elapsed, the overcurrent is detected, and the switch control unit 121 controls the drive circuit 122 to lower the drive voltage Gd to a low level. This turns off the switch element 111, and the primary coil current rapidly decreases to 0 A. At this time, a high voltage is generated in the secondary voltage V22, causing a spark SP.

[0031] However, in such a protective operation based on overcurrent detection, the sudden drop in drive voltage Gd causes the switch element 111 to turn off, resulting in a sudden decrease in the primary coil current, i.e., hard shutoff, which may result in ignition with excessive energy and accelerate deterioration of the spark plug 30. Furthermore, ignition may occur at an unintended timing (timing t5), which may result in engine backfire, knocking, or the like, depending on the timing.

[0032] Furthermore, even if an overheat state is detected by the overheat detection unit 124, protection can be provided by hard shutoff by the switch control unit 121. However, as in the case described above, there is a possibility that an ignition may occur at an unintended timing.

[0033] In order to solve such problems, the embodiments of the present disclosure described below are implemented.

[0034] 3 is a diagram showing the configuration of an engine ignition device 1 including a switch device 101 according to an exemplary embodiment of the present disclosure. The configuration of the switch device 101 will be described while appropriately omitting explanations of matters similar to those described in the switch device 10 according to the comparative example described above.

[0035] In the switch device 101, the switch control device 12 is provided with a soft shutoff unit 126. During a protection operation, the soft shutoff unit 126 softly shuts off the switch element 111 using the current limiting unit 125 and the drive circuit 122. The soft shutoff will be described in detail later.

[0036] A capacitor C3, which is connected externally to the switch control device 12, is connected to the soft shutoff unit 126. The soft shutoff unit 126 performs soft shutoff using the charge of the capacitor C3. The capacitor C3 is formed of a chip capacitor.

[0037] The switch control device 12 also includes an ignition confirmation unit 127. The ignition confirmation unit 127 generates an ignition confirmation signal IGF based on the primary coil current and outputs it to the ECU 3 via the feedback pad Pfb. The ignition confirmation unit 127 generates the ignition confirmation signal IGF by comparing the primary coil current with reference currents Iref1 and Iref2 (>Iref1). In practice, the ignition confirmation unit 127 generates the ignition confirmation signal IGF by comparing the current detection signal Vis with a reference voltage Vref1 corresponding to the reference current Iref1 and a reference voltage Vref2 (>Vref1) corresponding to the reference current Iref2. The ignition confirmation unit 127 sets the ignition confirmation signal IGF to a first level (e.g., a low level) when the current detection signal Vis is a voltage between the reference voltage Vref1 and the reference voltage Vref2 (Vref1<Vis<Vref2), and sets the ignition confirmation signal IGF to a second level (e.g., a high level) otherwise (Vis<Vref1, Vref2<Vis).

[0038] 3, the switch chip 11 is provided with electrode pads such as a collector pad Pc, an emitter pad Pe, and a gate pad Pg1, while the switch control device 12 is provided with electrode pads such as a power supply pad Pvdd, an input pad Pin, a capacitor connection pad Pcc, a sense input pad Psi, and a gate pad Pg2.

[0039] FIG. 4 is a plan view showing an example of the layout of the internal configuration of the switch device 101. The switch device 101 is a package formed by sealing with a sealing material such as resin. The switch device 101 has leads (lead frames) 41 to 48. The layout shown in FIG. 4 will be described using the X direction along one side of the rectangular package in plan view and the Y direction perpendicular to the X direction. In FIG. 4, one side in the X direction is indicated as X1 and the other side as X2, and one side in the Y direction is indicated as Y1 and the other side as Y2.

[0040] Lead 41 has a power supply terminal VDD and is arranged at the end of the package on the other side in the X direction and the other side in the Y direction. Lead 42 is arranged adjacent to lead 41 on one side in the Y direction. Lead 43 has a GND terminal and is formed from the end of the package on the other side in the Y direction to the end of the package on one side in the Y direction. In other words, lead 43 is a lead for ground connection. Lead 43 is arranged adjacent to leads 41 and 42 on one side in the X direction.

[0041] Lead 44 has an IN terminal and is located at the other end of the package in the Y direction. Lead 48 has a feedback terminal FB and is located adjacent to lead 44 on the other side in the X direction. Leads 44 and 48 are located adjacent to lead 43 on the other side in the Y direction.

[0042] Lead 45 has an OUT terminal and is arranged adjacent to one side in the X direction of lead 43. Lead 45 is formed from the other end of the package in the Y direction to one end in the Y direction. Lead 46 is arranged adjacent to one side in the Y direction of leads 45 and 43.

[0043] The switch control device 12 is mounted on the leads 43. A power supply pad Pvdd, an input pad Pin, a gate pad Pg2, a ground pad Pgnd1, an anode pad Pad2, a sense input pad Psi, a capacitor connection pad Pcc, and a ground pad Pgnd2 are formed on the surface of the switch control device 12 (the front side of the paper).

[0044] The power supply pad Pvdd is connected to the lead 42 by a bonding wire 51. The input pad Pin is connected to the lead 44 by a bonding wire 52. As a result, the ignition instruction signal S output from the ECU 3 is input to the switch control unit 121 via the IN terminal and the input pad Pin. The feedback pad Pfb is connected to the lead 48 by a bonding wire 59.

[0045] The switch chip 11 is mounted on the lead 45. The switch chip 11 has an emitter pad Pe, an anode pad Pad1, a cathode pad Pcd1, and a gate pad Pg1 on its front side (near the page), and a collector pad (back electrode) Pc on its back side (farther from the page). The collector pad Pc is connected to the lead 45. As a result, the collector of the switch element 111 is connected to the OUT terminal via the collector pad Pc. The OUT terminal is connected to the second end of the primary coil 21 ( FIG. 3 ).

[0046] The gate pad Pg1 is connected to the gate pad Pg2 by a bonding wire W1. The anode pad Pad1 is connected to the anode pad Pad2 by a bonding wire W2. As a result, the drive voltage Gd generated by the drive circuit 122 is applied to the gate of the switch element 111 via the gate pads Pg2 and Pg1.

[0047] FIG. 5 is a diagram showing a specific example configuration of the temperature sensor 112 and the overheat detection unit 124. The temperature sensor 112 has one or more diodes Di. When multiple diodes Di are used, the diodes Di are connected in series as shown in FIG. 5. The anode end of the temperature sensor 112 is connected to an anode pad Pad1. The anode pad Pad1 is connected to an anode pad Pad2 by a bonding wire W2 as shown in FIG. 4. The cathode end of the temperature sensor 112 is connected to a cathode pad Pcd1. The cathode pad Pcd1 is connected to a ground pad Pgnd1 by a bonding wire W3 as shown in FIG. 4.

[0048] 5, the overheat detection unit 124 includes a constant current circuit 124A and a comparator 124B. The constant current circuit 124A supplies a constant current I124 through a path that passes through the anode pads Pad2 and Pad1 and the temperature sensor 112. The temperature sensor 112 detects the temperature by utilizing the fact that the forward voltage Vf changes in response to changes in temperature when the constant current I124 is supplied. The higher the temperature, the lower the forward voltage Vf.

[0049] The non-inverting input terminal (+) of the comparator 124B is connected to the anode terminal of the temperature sensor 112 via the anode pads Pad2 and Pad1. A reference voltage Vt, which is based on the potential of the ground pad Pgnd1, is input to the inverting input terminal (-) of the comparator 124B. This allows the comparator 124B to detect an overheating state by comparing the forward voltage Vf with the reference voltage Vt. More specifically, if the forward voltage Vf is higher than the reference voltage Vt, the comparator 124B determines that the temperature is normal and outputs a high-level detection signal Scmp. If the forward voltage Vf is equal to or lower than the reference voltage Vt, the comparator 124B determines that an overheating state has occurred and outputs a low-level detection signal Scmp. The detection signal Sscmp is input to the switch control unit 121 (FIG. 3).

[0050] As shown in Fig. 4, emitter pad Pe is not directly connected to lead 43, but is connected to lead 46 by bonding wire 54. Lead 46 is connected to lead 43 by bonding wire 55. Lead 46 is connected to sense input pad Psi by bonding wire 56. Lead 43 is connected to ground pad Pgnd2 by bonding wire 57. Therefore, as shown in Fig. 3, the impedance of bonding wire 55 is used as shunt resistor 13. A current detection signal Vis generated by the primary coil current flowing through shunt resistor 13 is input to current limiter 125 via sense input pad Psi.

[0051] The repeated heating and cooling of the switching element 111 due to power cycles causes the sealing material around the bonding wire 54 to expand and contract repeatedly. However, the lead 46 and the bonding wire 55 are less susceptible to the effects of power cycles. Therefore, even if the bond between the bonding wire 54 and the emitter pad Pe deteriorates due to the effects of power cycles, the resistance value of the shunt resistor 13 is prevented from changing.

[0052] As shown in FIG. 3 , the switch device 101 includes a high-frequency filter 14 between the VDD terminal and the power supply pad Pvdd of the switch control device 12. The high-frequency filter 14 is a π-type low-pass filter including capacitors C1 and C2 and a resistor R1. As shown in FIG. 4 , the resistor R1 is bridge-connected between the lead 41 (VDD terminal) and the lead 42. The capacitor C1 is bridge-connected between the lead 41 and the lead 43 (GND terminal). The capacitor C2 is bridge-connected between the lead 42 and the lead 43 (GND terminal). The lead 42 is connected to the power supply pad Pvdd by a bonding wire 51. This completes the high-frequency filter 14, which removes high-frequency noise input from the VDD terminal.

[0053] 4, capacitor C3 is bridge-connected between lead 43 (GND terminal) and lead 47. Lead 47 is connected to capacitor connection pad Pcc by bonding wire 58. As a result, one end of capacitor C3 is connected to soft shutoff unit 126 via capacitor connection pad Pcc, and the other end of capacitor C3 is connected to the terminal to which ground potential is applied.

[0054] In this way, the capacitor C3 used by the soft shutoff unit 126 is an external chip capacitor attached to the switch control device 12, so the capacitance of the capacitor C3 can be increased. Also, as shown in Figure 4, the capacitor C3 is disposed between the bonding wire 55 and the switch control device 12, so dead space can be effectively utilized. Furthermore, the capacitor connection pad Pcc is disposed along the side 12A of the switch control device 12 that faces the bonding wire 55 in the Y direction, so the length of the bonding wire 58 can be shortened.

[0055] The bonding wires 51 to 59 and the bonding wires W1 to W3 are made of, for example, Al, but may be made of other metals such as Al alloys, Au, and Cu.

[0056] 3. Configuration of Soft Shut-Off Unit Here, we will explain the configuration of the soft shut-off unit 126. Note that we will also explain the configurations of the current limiting unit 125 and the drive circuit 122.

[0057] Fig. 6 is a diagram showing an example of the configuration of the soft shutoff unit 126 and the current limiting unit 125. Note that Fig. 6 also shows the drive circuit 122 provided in the switch control device 12, the switch element 111, and the shunt resistor 13.

[0058] 6, the soft shutoff unit 126 includes a constant current source 126A, a switch 126B, and a reference voltage adjustment unit 126C. The constant current source 126A is connected between the application terminal of the power supply voltage Vcc1 and a capacitor connection pad Pcc. The switch 126B is connected between the capacitor connection pad Pcc and the application terminal of the ground potential. The capacitor connection pad Pcc is connected to the input terminal of the reference voltage adjustment unit 126C.

[0059] By switching the switch 126B from the on state to the off state, a constant current I126 from the constant current source 126A is supplied to the capacitor C3 via the capacitor connection pad Pcc, thereby charging the capacitor C3. Note that by switching the switch 126B to the on state, the capacitor C3 is discharged. The reference voltage adjustment unit 126C generates an adjustment signal Adj based on the voltage VC3 of the capacitor C3 generated at the capacitor connection pad Pcc and outputs the adjustment signal Adj to the current limiting unit 125.

[0060] The current limiting unit 125 includes a reference voltage generating unit 125A and a differential amplifier 125B. The reference voltage generating unit 125A generates a reference voltage REF1 based on a change in the reference value Vref based on an adjustment signal Adj from a reference voltage adjusting unit 126C. The reference voltage REF1 is input to one input terminal of the differential amplifier 125B. A current detection signal Vis generated across the shunt resistor 13 is input to the other input terminal of the differential amplifier 125B. The drive circuit 122 generates a drive voltage Gd based on the output of the differential amplifier 125B. As a result, when the current detection signal Vis attempts to exceed the reference voltage REF1, the drive voltage Gd is controlled by the differential amplifier 125B to clamp the current detection signal Vis to the reference voltage REF1. In other words, the primary coil current is limited to a limit current value determined by the reference voltage REF1 and the resistance value of the shunt resistor 13.

[0061] 7 is a circuit diagram showing a more specific example configuration of the soft shutoff unit 126, the current limiting unit 125, and the drive circuit 122. Note that Fig. 7 also shows the configuration of the pre-current detection unit 128 provided in the switch control device 12.

[0062] As described above, the soft shutoff unit 126 includes the constant current source 126 A, the switch 126 B, and the reference voltage adjustment unit 126 C. The switch 126 B is controlled to be turned on and off by the switch control unit 121 .

[0063] The reference voltage adjusting unit 126C includes a constant current source CS1, transistors Tr1 and Tr2, a resistor R1, current mirrors CM1 and CM2, and a switch SW1. The transistors Tr1 to Tr12 and the transistors TrA to TrC are bipolar transistors.

[0064] The constant current source CS1 is connected between the application terminal of the power supply voltage Vcc1 and the emitter of the transistor Tr1. The base of the transistor Tr1 is connected to the capacitor connection pad Pcc. The collector of the transistor Tr1 is connected to the application terminal of the ground potential. The base of the transistor Tr2 is connected to the emitter of the transistor Tr1. The emitter of the transistor Tr2 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the application terminal of the ground potential. The collector of the transistor Tr2 is connected to the input terminal of the current mirror CM1. The output terminal of the current mirror CM1 is connected to the input terminal of the current mirror CM2. A switch SW1 is connected between the collector of the input-side transistor of the current mirror CM2 and the application terminal of the ground potential.

[0065] With this configuration, voltage VC3 from capacitor C3 is applied to the base of transistor Tr1, and a voltage that is higher than VC3 by the Vbe (base-emitter voltage) of transistor Tr1 and lower by the Vbe of transistor Tr2 is applied to resistor R1. This generates current I1 flowing through resistor R1, and current I1 is mirrored by current mirror CM1 to become current I2, and current I2 is mirrored by current mirror CM2 to become current I3. Current I3 is the output of reference voltage adjuster 126C and corresponds to adjustment signal Adj (FIG. 6).

[0066] When the switch SW1 is in the on state, the current mirror CM2 is disabled and the current I3 does not flow. On the other hand, when the switch SW1 is in the off state, the current mirror CM2 is enabled. The on / off of the switch SW1 is controlled by the switch control unit 121.

[0067] The switch control device 12 is also provided with resistors Ra, Rb, and Rc, transistors TrA, TrB, and TrC, a transistor Tr3, a resistor Rc, and a constant current source CSA. The resistors Ra and Rb are connected in series between a reference voltage VA application terminal and a ground potential application terminal. The node connecting the resistors Ra and Rb is connected to the base of the transistor TrA. The constant current source CSA is connected between a power supply voltage Vcc2 application terminal and the emitter of the transistor TrA. The collector of the transistor TrA is connected to the ground potential application terminal. The base of the transistor TrB is connected to the emitter of the transistor TrA. The emitter of the transistor TrB is connected to one end of the resistor Rc. The other end of the resistor Rc is connected to the ground potential application terminal.

[0068] The transistor Tr3 is an input transistor common to the current mirrors CM3 and CM4. The collector of the transistor TrB is connected to the collector of the transistor Tr3, i.e., the input terminals of the current mirrors CM3 and CM4.

[0069] With this configuration, a voltage VAd, which is the reference voltage VA divided by resistors Ra and Rb, is applied to the base of transistor TrA. A voltage VAd that is higher than voltage VAd by the Vbe of transistor TrA and lower than voltage VAd by the Vbe of transistor TrB, is applied to resistor Rc. This generates a current I4 that flows through resistor Rc. Current I4 is mirrored by current mirrors CM3 and CM4, respectively, to become currents I5 and I6 that flow through transistors Tr4 and Tr5, which are the output transistors of current mirrors CM3 and CM4, respectively. Therefore, currents I5 and I6 are constant currents.

[0070] As described above, the current limiter 125 includes a reference voltage generator 125A and a differential amplifier 125B. The reference voltage generator 125A includes a transistor Tr4, an input transistor of the current mirror CM5, and a resistor R3. The differential amplifier 125B includes a current mirror CM5, a resistor R2, a transistor Tr5, a resistor R4, and a capacitor C4. The resistor R3 is a resistor for generating the reference voltage REF1. The capacitor C4 and the resistors R2 and R4 filter out high-frequency noise input to each input terminal of the differential amplifier 125B.

[0071] The collector of the input transistor of current mirror CM5 is connected to the collector of transistor Tr4 and the output terminal of current mirror CM2 at node N1. The emitter of the input transistor of current mirror CM5 is connected to one end of resistor R2. The other end of resistor R2 is connected to one end of resistor R3. The other end of resistor R3 is connected to a terminal to which ground potential is applied.

[0072] As a result, current I7 flows through resistors R2 and R3 as the remaining current after current I3 is extracted from current I5 at node N1. That is, I7 = I5 - I3. Therefore, current I7 is adjusted by current I3, which is adjusted according to voltage VC3. As current I7 flows through resistor R3, reference voltage REF1 is generated at one end of resistor R3. When current I3 is not flowing (I3 = 0), I7 = I5, and reference voltage REF1 in this case becomes reference value Vref (FIG. 6) (REF = Vref). As voltage VC3 increases, current I3 increases and current I7 decreases, causing reference voltage REF1 to decrease from reference value Vref. In this way, reference voltage generator 125A generates reference voltage REF1 according to current I3, which serves as adjustment signal Adj.

[0073] The collector of transistor Tr5 is connected to the collector of the output transistor of current mirror CM5 at node N2. The emitter of the output transistor of current mirror CM5 is connected to one end of resistor R4. The other end of resistor R4 is connected to one end of shunt resistor 13 via sense input pad Psi. A capacitor C4 is connected between one end of resistor R2 and one end of resistor R4.

[0074] As a result, current I7 is mirrored by current mirror CM5 to become current I8 depending on the magnitude relationship between current detection signal Vis generated in shunt resistor 13 and reference voltage REF1. The current remaining after current I8 is extracted from current I6 at node N2 becomes current I9, which is output from node N2. In other words, I9 = I6 - I8. Current I9 flows into drive circuit 122.

[0075] The drive circuit 122 includes a PMOS transistor PM, a resistor R11, an NMOS transistor NM, an OR circuit OR1, and inverters IV1 and IV2. The PMOS transistor PM is a P-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The NMOS transistor NM is an N-channel MOSFET. The PMOS transistor PM and the NMOS transistor NM form a CMOS. Specifically, the source of the PMOS transistor PM is connected to a terminal to which a power supply voltage VCC4 is applied. The drain of the PMOS transistor PM is connected to the drain of the NMOS transistor NM at a node N4 via a resistor R11. The source of the NMOS transistor NM is connected to a terminal to which a ground potential is applied. The node N4 is connected to a node N3, which will be described later.

[0076] The gate of the PMOS transistor PM is connected to the output terminal of the OR circuit OR1. A signal obtained by inverting the control signal DET using an inverter IV1 is input to a first input terminal of the OR circuit OR1. The control signal DET is output from the switch control unit 121. A signal obtained by inverting the ignition instruction signal S using an inverter IV2 is input to a second input terminal of the OR circuit OR1. A detection signal Pre_Ic output from a pre-current detection unit 128 (described later) is input to a third input terminal of the OR circuit OR1. A signal obtained by inverting the ignition instruction signal S using the inverter IV2 is input to the gate of the NMOS transistor NM. When the output OR of the OR circuit OR1 is at a low level and the ignition instruction signal S is at a high level, the PMOS transistor PM is in an on state, the NMOS transistor NM is in an off state, and the voltage of the node N4 is at a high level. On the other hand, when the output OR of the OR circuit OR1 is at a high level and the ignition instruction signal S is at a low level, the PMOS transistor PM is in an off state, the NMOS transistor NM is in an on state, and the voltage of the node N4 is at a low level. Also, when the output OR of the OR circuit OR1 is at a high level and the ignition instruction signal S is at a high level, both the PMOS transistor PM and the NMOS transistor NM are in an off state.

[0077] The drive circuit 122 also includes a constant current source CS2, a current mirror CM6, resistors R5, R6, and R7, and a transistor Tr7. The constant current source CS2 is connected to the input terminal of the current mirror CM6. A node N2 is connected to the base of the transistor Tr6 via a resistor R5. The collector of the transistor Tr6 is connected to the terminal to which the power supply voltage VCC3 is applied. The emitter of the transistor Tr6 is connected to one terminal of a resistor R6. The other terminal of the resistor R6 is connected to the terminal to which the ground potential is applied. One terminal of the resistor R6 is connected to the base of the transistor Tr7. The emitter of the transistor Tr7 is connected to the terminal to which the ground potential is applied. The collector of the transistor Tr7 is connected to the output terminal of the current mirror CM6 at a node N3. The node N3 is connected to the gate of the switch element 111 via the resistor R7 and a gate pad Pg2.

[0078] When current I9 flows into the base of transistor Tr6, the emitter current of transistor Tr6 flows through resistor R6. Then, the voltage generated across resistor R6 is applied to the base of transistor Tr7, generating current I11 that flows through transistor Tr7. Meanwhile, the constant current from constant current source CS2 is mirrored by current mirror CM6 to become current I10. The balance between current I10 flowing into node N3 and current I11 drawn out of node N3 generates drive voltage Gd that is applied to the gate of switch element 111.

[0079] The driver circuit 122 also includes a gain adjustment circuit 122A. The gain adjustment circuit 122A includes resistors R8 to R10 and transistors Tr8 to Tr10. One end of the resistor R8 is connected to a node N3. The other end of the resistor R8 is connected to the collector of the transistor Tr8. The collector of the transistor Tr8 is connected to one end of a resistor R5. The emitter of the transistor Tr8 is connected to a terminal to which the ground potential is applied. The collector of the transistor Tr10 is connected to a terminal to which the power supply voltage VCC5 is applied. The emitter of the transistor Tr10 is connected to one end of a resistor R10. The other end of the resistor R10 is connected to a terminal to which the ground potential is applied. The base of the transistor Tr9 is connected to one end of the resistor R10 and the base of the transistor Tr8. The emitter of the transistor Tr9 is connected to a terminal to which the ground potential is applied. The collector of the transistor Tr9 is connected to the node N3 via the resistor R9. The base of the transistor Tr10 is connected to the collector of the transistor Tr9.

[0080] Such a gain adjustment circuit 122A reduces the gain of the differential amplifier 125B (increases the output impedance) to slow down the feedback operation response of the differential amplifier 125B, thereby suppressing abrupt changes in the drive voltage Gd during limited current operation.

[0081] The preliminary current detection unit 128 includes transistors Tr11 and Tr12, a current mirror CM9, resistors R12, R13, and R14, a capacitor C5, and a buffer IVA.

[0082] A current mirror CM7 is formed by transistors Tr3 and Tr11. The collector of the input transistor of current mirror CM9 is connected to the collector of transistor Tr11. The emitter of the input transistor of current mirror CM9 is connected to one end of resistor R12. The other end of resistor R12 is connected to one end of resistor R13. The other end of resistor R13 is connected to a terminal to which ground potential is applied.

[0083] Transistors Tr3 and Tr12 form a current mirror CM8. The collector of the output transistor of current mirror CM9 is connected to the collector of transistor Tr12 at node N5. The emitter of the output transistor of current mirror CM9 is connected to one end of resistor R14. The other end of resistor R14 is connected to one end of shunt resistor 13 via sense input pad Psi. Capacitor C5 is connected between one end of resistor R12 and one end of resistor R14. Resistor R13 is a resistor for generating reference voltage REF2. Capacitor C5 and resistors R12 and R14 filter out high-frequency noise.

[0084] The node N5 is connected to the input terminal of the OR circuit OR1 via a buffer IVA. The buffer IVA is configured by connecting two inverters. The output of the buffer IVA becomes the detection signal Pre_Ic. Note that the buffer IVA is not necessarily provided.

[0085] Current I4 is mirrored by current mirror CM7 to become current I12. As current I12 flows through resistor R13, a reference voltage REF2 is generated at one end of resistor R13. Current I4 is mirrored by current mirror CM8 to become current I13. Current I13 flows into node N5. Current I14 is mirrored by current mirror CM9 to become current I15. Current I15 is drawn out from node N5.

[0086] The base of the transistor TrC is connected to the node where the resistors Ra and Rb are connected, the emitter is connected to the capacitor connection pad Pcc, and the collector is connected to the terminal to which the ground potential is applied. When the capacitor C3 is charged, the transistor TrC clamps the voltage VC3 to a voltage that is higher than the voltage VAd by the Vbe of the transistor TrC.

[0087] 4. Soft Shut-Off Operation Next, the operation of the switch device 101 configured as described above according to the embodiment of the present disclosure will be described. First, the operation during normal operation will be described using the timing chart of FIG. 8A. In FIG. 8A, from the top to the bottom, the ignition instruction signal S, the drive voltage Gd, the primary coil current Ic, the collector voltage VCE, the secondary voltage V22, the detection signal Pre_Ic, the control signal DET, and the output OR are shown.

[0088] Under normal circumstances, the switch control unit 121 turns on the switch 126B, and the capacitor C3 is discharged, causing the voltage VC3 to be 0 V. At this time, the switch control unit 121 turns on the switch SW1, the current mirror CM2 is disabled, and no current I3 flows. Therefore, the reference voltage REF1 is equal to the reference value Vref.

[0089] Immediately before timing t1 in FIG. 8A, the ignition instruction signal S is at a low level. When the ignition instruction signal S is at a low level, the control signal DET is forcibly set to a low level. Therefore, immediately before timing t1, the control signal DET is at a low level. Therefore, the output OR is at a high level, and the PMOS transistor PM is in an off state. On the other hand, the NMOS transistor NM is in an on state. As a result, the drive voltage Gd is at a low level, and the switch element 111 is in an off state.

[0090] Then, when the ignition instruction signal S rises to a high level at timing t1, the switch control unit 121 turns on the constant current source CS2 in the drive circuit 22. Here, the control signal DET is set to a high level when the ignition instruction signal S is at a high level and neither overcurrent protection nor overheat protection is detected. Therefore, at timing t1, the control signal DET is at a high level. Also, because the current detection signal Vis is equal to or lower than the reference voltage REF2, the detection signal Pre_Ic is at a low level. Therefore, the output OR is at a low level, and the PMOS transistor PM is turned on. Meanwhile, the NMOS transistor NM is turned off. This causes the drive voltage Gd to rise to a high level, turning on the switch element 111 and starting the primary coil current to flow. If the ignition instruction signal S is normal, even if the primary coil current increases during the high-level period Ts, the current detection signal Vis does not reach the reference voltage REF1. In other words, the primary coil current does not reach the limited current value, so the current I9 does not flow and the drive voltage Gd is maintained at a high level by the drive circuit 12.

[0091] Then, when the ignition instruction signal S falls to a low level at timing t2, the control signal DET is forced to a low level, and the output OR goes to a high level. This turns off the PMOS transistor. Meanwhile, the NMOS transistor NM is turned on. Therefore, the gate voltage Gd falls sharply to a low level. This turns off the switch element 111, and the primary coil current falls sharply to 0 A. This hard shutoff generates a high voltage in the secondary voltage V22, causing a spark SP.

[0092] Next, the operation when an abnormality occurs will be described. Fig. 8B is a timing chart showing an example of the operation when an overcurrent abnormality occurs. In Fig. 8B, from the top to the bottom, example waveforms of the ignition instruction signal S, the drive voltage Gd, the voltage VC3, the reference voltage REF1, the primary coil current Ic, the collector voltage VCE, the secondary voltage V22, the detection signal Pre_Ic, the control signal DET, and the output OR are shown.

[0093] When the ignition instruction signal S rises to a high level at timing t11 in FIG. 8B, the switch control unit 121 turns on the constant current source CS2 in the drive circuit 22. Also, the output OR is set to a low level, turning on the PMOS transistor PM. Meanwhile, the NMOS transistor NM is turned off. Therefore, the drive voltage Gd goes to a high level. This turns on the switch element 111, and the primary coil current begins to flow.

[0094] After that, at timing t12, when the current detection signal Vis exceeds the reference voltage REF2 due to an increase in the primary coil current, the detection signal Pre_Ic goes high. The reference voltage REF2<REF1. In other words, it is detected that the primary coil current has exceeded the preliminary current value Ipre (<the limit current value Icp). This causes the output OR to go high, turning off the PMOS transistor PM. At this time, both the PMOS transistor PM and the NMOS transistor NM are in the off state. The drive voltage Gd is maintained at a high level.

[0095] Thereafter, at timing t13, when the primary coil current increases and the current detection signal Vis attempts to exceed the reference voltage REF1, the current I8 decreases and the current I9 flows, causing the drive circuit 122 to adjust the drive voltage Gd to a voltage lower than the high level, and the primary coil current is clamped to the limited current value Icp.

[0096] The overcurrent detection unit 123 starts timing using the timer 123A (FIG. 3) from time t11 when the ignition instruction signal S rises to a high level. If the high level is maintained even after a predetermined high-level period Tsth (a period longer than the normal high-level period Ts) has elapsed, the overcurrent detection unit 123 detects an overcurrent. When an overcurrent is detected at time t14, the switch control unit 121 switches the switch 126B to the OFF state in response to a command from the overcurrent detection unit 123. This starts charging the capacitor C3 using the constant current source 126A. Therefore, the voltage VC3 starts to rise. At this time, the switch control unit 121 switches the switch SW1 to the OFF state, enabling the current mirror CM2. Furthermore, the control signal DET is set to a low level when the ignition instruction signal S is at a high level and overcurrent protection or overheat protection is detected. As a result, the control signal DET is set to a low level at time t14.

[0097] As voltage VC3 increases, current I3 increases, and reference voltage REF1 decreases from reference value Vref. As reference voltage REF1 decreases, differential amplifier 125B controls drive circuit 122, drive voltage Gd decreases, and the primary coil current gradually decreases. Then, at timing t15, when the primary coil current falls below the preliminary current value Ipre, detection signal Pre_Ic becomes low level. Thereafter, as reference voltage REF1 decreases, the primary coil current decreases to 0 A.

[0098] In this way, soft shutoff is performed, which causes the primary coil current to decrease gradually, so a high voltage is not generated in the secondary voltage V22, and no sparks are generated. Therefore, ignition due to excessive energy is not generated, and deterioration of the spark plug 30 can be suppressed. In addition, ignition at an unintended timing can be suppressed.

[0099] After timing t15, when the ignition instruction signal S falls to a low level at timing t16, the switch control unit 121 switches the switch 126B to the ON state, and the capacitor C3 discharges, causing the voltage VC3 to become 0 V. The switch control unit 121 also switches the switch SW1 to the ON state, disabling the current mirror CM2 and preventing the current I3 from flowing. As a result, the reference voltage REF1 becomes the reference value Vref.

[0100] Furthermore, if the overheat detection unit 124 detects an overheat state when the ignition instruction signal S is at a high level, the switch control unit 121 performs the same soft shutoff as described above. This makes it possible to prevent unintended ignition.

[0101] In this embodiment, since capacitor C3 is not charged under normal circumstances, it is less susceptible to the effects of DC bias and deterioration of capacitor C3 is suppressed. Furthermore, since soft shutoff is performed by reducing the primary coil current by lowering reference voltage REF1, i.e., the limited current value, it is possible to suppress characteristic variations without relying on the characteristics of switch element 111. Furthermore, various soft shutoff specifications can be accommodated simply by changing the current value of constant current source 126A that charges capacitor C3.

[0102] 5. Vehicle FIG. 9 is a diagram showing an example of the configuration of a vehicle on which the engine ignition device 1 according to the embodiment is mounted.

[0103] The vehicle X1 shown in Figure 9 includes the power supply 2 and ECU 3 described above, an engine unit 61 with a generator, a high-power DC / DC converter 62, an inverter 63, a motor 64, a drive unit 65, a high-voltage battery 66, and a DC / DC converter 67. The mounting positions of the components in Figure 9 are different from the actual positions for the sake of convenience. The vehicle X1 shown in Figure 8 is a so-called series hybrid vehicle.

[0104] The generator-equipped engine section 61 includes a generator, a dedicated power generation engine that rotates the generator, and the engine ignition device 1 according to the various embodiments described above. Since the energy conversion efficiency of the engine varies greatly depending on the timing of ignition, the ignition timing must be controlled by the ECU 3 in consideration of the rotation angle of the crank that converts the reciprocating motion of the piston in the cylinder into rotational motion and the required amount of power generation. For this reason, the engine ignition device 1 according to the embodiments is provided for each cylinder of the engine.

[0105] The high-power DC / DC converter 62 converts DC power generated by the generator of the generator-equipped engine unit 61 into high-voltage DC power. The high-power DC / DC converter 62 supplies the high-voltage DC power to the inverter 63 and the high-voltage battery 66. The high-power DC / DC converter 62 can also supply discharge power discharged from the high-voltage battery 66 to the inverter 63. Furthermore, the high-power DC / DC converter 62 can also charge the high-voltage battery 66 with regenerative power supplied from the inverter 63 when the vehicle X1 is decelerating.

[0106] The inverter 63 receives DC power from the high-power DC / DC converter 62 and converts the received DC power into three-phase AC power.

[0107] The motor 64 has a shaft and rotates the shaft using three-phase AC power supplied from the inverter 63 .

[0108] The drive unit 65 transmits power generated by the rotation of the shaft of the motor 64 to the drive wheels of the vehicle X1. Note that, although the rear wheels of the vehicle X1 are drive wheels in Fig. 8, the drive wheels are not limited to the rear wheels. In other words, the front wheels may be drive wheels, or both the front and rear wheels may be drive wheels.

[0109] The DC / DC converter 67 receives DC power from the high-power DC / DC converter 62 and converts the received DC power into low-voltage DC power. The power supply 2, which is a low-voltage battery, is charged with the low-voltage DC power output from the DC / DC converter 67. The discharge power discharged from the power supply 2 is supplied to the engine ignition device 1 according to the embodiment and the like.

[0110] The vehicle on which the engine ignition device 1 according to the embodiment is mounted is not limited to a hybrid vehicle such as the vehicle X1 shown in FIG. 9 , but may be any vehicle equipped with an engine. 6. Others The embodiments of the present disclosure may be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The various embodiments and modifications described so far may be combined as appropriate within a consistent range. The above-described embodiments are merely examples of embodiments of the present disclosure, and the meanings of the terms used in the present disclosure and the respective constituent elements are not limited to those described in the above-described embodiments.

[0111] For example, in the above-described embodiment, an igniter has been described as an example of a switch device, but the switch device may be a switch device other than an igniter.

[0112] <7. Supplementary Note> As described above, a switch control device (12) according to an aspect of the present disclosure includes: a drive circuit (122) configured to apply a drive voltage (Gd) to a control end of a switch element (111); a switch control unit (121) configured to control the switch element via the drive circuit based on an input signal (S); an abnormality detection unit (123, 124) configured to detect at least one of an overcurrent state and an overheat state of the switch element; a current limiting unit (125) configured to limit a current flowing through the switch element via the drive circuit based on a limited current value; and a soft shutoff unit (126) configured to charge a capacitor (C3), wherein the switch control unit switches the switch element to an on state when the input signal is switched to a first logic level; and the soft shutoff unit, when receiving a command from the switch control unit based on the detection of an abnormality by the abnormality detection unit, starts charging the capacitor and reduces the limited current value in accordance with an increase in the voltage (VC3) of the capacitor (first configuration).

[0113] Furthermore, in the first configuration, the soft shutoff unit (126) may have a reference voltage adjustment unit (126C) configured to generate an adjustment signal (Adj) in accordance with the voltage (VC3) of the capacitor (C3), and the current limiting unit (125) may have: a reference voltage generation unit (125A) configured to variably generate a reference voltage (REF) in accordance with the adjustment signal; and a differential amplifier (125B) configured to receive as input the reference voltage and a current detection signal (Vis) that detects the current flowing through the switch element (111) and control the drive circuit (122) (second configuration).

[0114] Furthermore, in the second configuration, the reference voltage adjusting unit (126C) may have: a first constant current source (CS1); a first transistor (Tr1) including an emitter connected to the first constant current source and a base connected to a first end of the capacitor (C3); a first resistor (R1); a second transistor (Tr2) including a base connected to the emitter of the first transistor and an emitter connected to a first end of the first resistor; and a first current mirror unit (CM1, CM2) including an input end connected to the collector of the second transistor; and the reference voltage generating unit (125A) may have: a third transistor which is an input side transistor of a second current mirror unit (CM5) and is connected to a first node (N1) into which the first constant current (I5) flows and from which a current (I3) is drawn by the first current mirror unit; and a second resistor (R3) connected to the third transistor (third configuration).

[0115] Furthermore, in the third configuration, the reference voltage adjustment unit (126C) may be configured to have a first switch (SW1) that switches between enabling and disabling the first current mirror unit (CM2) and whose on / off is controlled by the switch control unit (fourth configuration).

[0116] In addition, in the third or fourth configuration, the differential amplifier (125B) may have the second current mirror unit (CM5), and a second node (N2) into which the second constant current (I6) flows and which is connected to the output side transistor in the second current mirror unit may be connected to the drive circuit (122) (fifth configuration).

[0117] Furthermore, in the fifth configuration, the drive circuit (122) may have: a second constant current source (CS2); a third current mirror unit (CM6) including an input terminal connected to the second constant current source; a fourth transistor (Tr6) including a base connected to the second node; a third resistor (R6) connected to the emitter of the fourth transistor; and a fifth transistor (Tr7) including a base connected to the third resistor, and a third node (N3) where the output side transistor of the third current mirror unit and the fifth transistor are connected may be configured to be connectable to the control terminal of the switch element (111) (sixth configuration).

[0118] In addition, in any of the first to sixth configurations, the soft shutoff unit (126) may be configured to include: a third constant current source (126A) connectable to a first end of the capacitor (C3); and a second switch (126B) connectable to the first end of the capacitor and controlled to be turned on and off by the switch control unit (seventh configuration).

[0119] Furthermore, in any of the first to seventh configurations, a preliminary current detection unit (128) configured to compare the current flowing through the switch element (111) with a predetermined preliminary current value (Ipre) lower than the limit current value and output a detection signal (Pre_Ic), and the drive circuit may have: a CMOS configured by connecting a PMOS transistor (PM) and an NMOS transistor (NM); and logic circuits (OR1, IV1, IV2) that control the gate of the PMOS transistor based on a control signal (DET), the input signal (S), and the detection signal output from the switch control unit (121), wherein the gate of the NMOS transistor is controlled based on the input signal, and the output terminal of the CMOS is connected to the control terminal of the switch element (eighth configuration).

[0120] In addition, in any of the first to eighth configurations, the abnormality detection unit (123) may be configured to detect an overcurrent state when the period during which the input signal, measured by a timer (123A), is at the first logic level reaches a predetermined period (ninth configuration).

[0121] Furthermore, a switch device (101) according to one aspect of the present disclosure includes a switch control device (12) having any one of the first to ninth configurations described above, and a semiconductor chip (11) having the switch element (111) and a temperature sensor (112) integrated therein, and the abnormality detection unit (124) is configured to detect the overheating state based on a detection signal of the temperature sensor (tenth configuration).

[0122] Moreover, a switch device (101) according to one aspect of the present disclosure includes a switch control device (12) having any one of the first to ninth configurations, the switch element (111), and the capacitor (C3) externally connected to the switch control device (eleventh configuration).

[0123] In addition, the 11th configuration may further include a first lead (43) connected to a ground electrode (Pgnd2) of the switch control device (12), and a bonding wire (55) for connecting between a first end of the switch element (111) and the first lead, and the capacitor (C3) may be arranged between the bonding wire and the switch control device in a plan view (12th configuration).

[0124] In addition, in the above-mentioned twelfth configuration, the capacitor connection electrode (Pcc) for connecting the capacitor (C3) may be configured to be arranged along the side (12A) of the switch control device (12) that faces the bonding wire (55) (thirteenth configuration).

[0125] Also, a switch device (101) according to one aspect of the present disclosure includes a switch control device (12) having any one of the first to ninth configurations, and the switch element (111) configured as an IGBT (14th configuration).

[0126] Furthermore, a switch device (101) according to one aspect of the present disclosure includes a switch control device (12) having any one of the first to ninth configurations and the switch element (111), and the switch element is connectable to a primary coil (21) of an ignition coil (20) (15th configuration).

[0127] Furthermore, an engine ignition device (1) according to one aspect of the present disclosure includes a switch device (101) of the fifteenth configuration, the ignition coil (20) including the primary coil (21) and the secondary coil (22), and an ignition plug (30) connected to the secondary coil (sixteenth configuration).

[0128] Furthermore, a vehicle (X1) according to one aspect of the present disclosure includes the engine ignition device (1) of the sixteenth configuration (seventeenth configuration).

[0129] The present disclosure can be used, for example, in an igniter.

[0130] 1 Engine ignition device 2 Power supply 3 Engine control unit 10 Switch device 11 Switch chip 12 Switch control device 13 Shunt resistor 14 High frequency filter 20 Ignition coil 21 Primary coil 22 Secondary coil 30 Spark plug 41 to 47 Leads 51 to 59 Bonding wire 61 Engine part with generator 62 High power DC / DC converter 63 Inverter 64 Motor 65 Drive device 66 High voltage battery 67 DC / DC converter 101 Switch device 111 Switch element 112 Temperature sensor 121 Switch control part 122 Drive circuit 122A Gain adjustment circuit 123 Overcurrent detection part 123A Timer 124 Overheat detection part 124A Constant current circuit 124B Comparator 125 Current limiting part 125A Reference voltage generation part 125B Differential amplifier 126 Soft shutoff section 126A Constant current source 126B Switch 126C Reference voltage adjustment section 127 Ignition confirmation section 128 Pre-current detection section C1 to C3 Capacitors C4, C5 Capacitors CM1 to CM9 Current mirrors CS1, CS2, CSA Constant current source Di Diode IV1, IV2 Inverter IVA Buffer NM NMOS transistor OR1 OR circuit PM PMOS transistor Pe Emitter pad Pad1 Anode pad Pad2 Anode pad Pc Collector pad Pcc Capacitor connection pad Pcd1 Cathode pad Pe Emitter pad Pg1, Pg2 Gate pads Pgnd1 Ground pad Pgnd2 Ground pad Pin Input pad Psi Sense input pad Pvdd Power supply pad R1 to R14 Resistors Ra, Rb,Rc Resistor SP Spark SW1 Switch Tr1 to Tr12 Transistors TrA, TrB, TrC Transistors W1 to W3 Bonding wires X1 Vehicle,

Claims

1. a drive circuit configured to apply a drive voltage to a control end of the switch element; a switch control unit configured to control the switch element via the drive circuit based on an input signal; an abnormality detection unit configured to detect at least one of an overcurrent state and an overheat state of the switch element; a current limiting unit configured to limit a current flowing through the switch element via the drive circuit based on a limit current value; a soft shutoff unit configured to charge a capacitor; Equipped with the switch control unit switches the switch element to an ON state when the input signal switches to a first logic level; When the soft shutoff unit receives a command from the switch control unit based on the abnormality detected by the abnormality detection unit, the soft shutoff unit starts charging the capacitor and reduces the limited current value in accordance with an increase in the voltage of the capacitor.

2. the soft shutoff unit includes a reference voltage adjustment unit configured to generate an adjustment signal in response to a voltage of the capacitor; The current limiting unit a reference voltage generating unit configured to variably generate a reference voltage in response to the adjustment signal; a differential amplifier configured to receive the reference voltage and a current detection signal that detects a current flowing through the switch element and control the drive circuit; The switch control device according to claim 1 , further comprising:

3. The reference voltage adjusting unit a first constant current source; a first transistor having an emitter connected to the first constant current source and a base connected to a first end of the capacitor; A first resistor; a second transistor having a base connected to the emitter of the first transistor and an emitter connected to the first end of the first resistor; a first current mirror unit including an input terminal connected to the collector of the second transistor; and The reference voltage generation unit a third transistor connected to a first node into which a first constant current flows and from which a current is drawn by the first current mirror section, and serving as an input-side transistor of the second current mirror section; a second resistor connected to the third transistor; The switch control device according to claim 2 , further comprising:

4. 4. The switch control device according to claim 3, wherein the reference voltage adjusting section has a first switch that switches between enabling and disabling the first current mirror section and is controlled to be turned on and off by the switch control section.

5. the differential amplifier has the second current mirror unit, 4. The switch control device according to claim 3, wherein a second node into which a second constant current flows and which is connected to an output-side transistor in the second current mirror section is connected to the drive circuit.

6. The drive circuit a second constant current source; a third current mirror unit including an input terminal connected to the second constant current source; a fourth transistor including a base connected to the second node; a third resistor connected to the emitter of the fourth transistor; a fifth transistor including a base connected to the third resistor; and 6. The switch control device according to claim 5, wherein a third node to which the output transistor of the third current mirror section and the fifth transistor are connected is connectable to the control end of the switch element.

7. The soft shutoff unit is a third constant current source connectable to the first end of the capacitor; a second switch connectable to the first end of the capacitor and controlled to be turned on and off by the switch control unit; The switch control device according to claim 1 , further comprising:

8. a preliminary current detection unit configured to compare the current flowing through the switch element with a predetermined preliminary current value lower than the limit current value and output a detection signal; The drive circuit a CMOS formed by connecting a PMOS transistor and an NMOS transistor; a logic circuit that controls a gate of the PMOS transistor based on a control signal output from the switch control unit, the input signal, and the detection signal; and The gate of the NMOS transistor is controlled based on the input signal; 2. The switch control device according to claim 1, wherein an output terminal of the CMOS is connected to a control terminal of the switch element.

9. The switch control device according to claim 1 , wherein the abnormality detection unit detects an overcurrent state when a period during which the input signal is at the first logic level, measured by a timer, reaches a predetermined period.

10. A switch control device according to any one of claims 1 to 9; a semiconductor chip having the switch element and the temperature sensor integrated therein; The abnormality detection unit detects the overheating state based on a detection signal from the temperature sensor.

11. A switch control device according to any one of claims 1 to 9; The switch element; the capacitor externally connected to the switch control device.

12. a first lead connected to a ground electrode of the switch control device; a bonding wire for connecting a first end of the switch element and the first lead; Equipped with The switch device according to claim 11 , wherein the capacitor is disposed between the bonding wire and the switch control device in a plan view.

13. 13. The switch device according to claim 12, wherein a capacitor connection electrode for connecting the capacitor is arranged along a side of the switch control device opposite to the bonding wire.

14. A switch control device according to any one of claims 1 to 9; The switch element is configured as an IGBT.

15. A switch control device comprising: the switch control device according to any one of claims 1 to 9; and the switch element; A switch device, wherein the switch element is connectable to a primary coil of an ignition coil.

16. A switch device according to claim 15; the ignition coil including the primary coil and a secondary coil; a spark plug connected to the secondary coil; An engine ignition device comprising:

17. A vehicle comprising the engine ignition device of claim 16.