Qubit allocation program, qubit allocation method, and qubit allocation device

Abstract

A qubit allocation program according to an embodiment of the present invention causes a computer to execute: a process for transformation; a process for second graph creation; a process for identification; and a process for circuit information creation. The process for transformation involves transforming a quantum circuit of calculation target into a first graph indicating the connection relationship between gates included in the quantum circuit. The process for the second graph creation involves creating, on the basis of the first graph, a second graph having removed therefrom gates other than two quantum gates included in the first graph. The process for identification involves identifying, from among third graphs created on the basis of a plurality of quantum circuits, a graph of the same type as the second graph. The process for circuit information creation involves creating circuit information corresponding to the quantum circuit of calculation target, to which qubits are allocated on the basis of the plurality of quantum circuits corresponding to the identified third graph.

Description

Quantum bit allocation program, quantum bit allocation method, and quantum bit allocation device

[0001] FIELD Embodiments of the present invention relate to a quantum bit allocation program, a quantum bit allocation method, and a quantum bit allocation device.

[0002] In recent years, the emergence of quantum computers called NISQ (Noisy Intermediate-Scale Quantum Computers) has made it possible to perform operations using quantum circuits. However, since the types of gates (native gates) that can be used on actual quantum computers are limited, quantum circuits are converted into native gates and quantum bits (qubits) are assigned to satisfy the constraints of the actual machine before operations can be performed.

[0003] In quantum computer quantum bit allocation, a configuration that reduces the number of gates, such as swap gates, is desirable to improve the fidelity of the entire circuit. One conventional technique for improving fidelity involves preparing multiple templates in which optimal allocations are pre-calculated for frequently occurring patterns in quantum circuits. Then, when an actual quantum circuit matches a predetermined template pattern, the calculation results of the template are used.

[0004] Patent Document 1: JP 2022-510394 A, US Patent Application Publication No. 2021 / 0350056, US Patent Application Publication No. 2020 / 0272926

[0005] D. M. Miller, D. Maslov, and G. W. Dueck. 2003. A transformation based algorithm for reversible logic synthesis. In Proceedings of the 2003 Design Automation Conference, Anaheim, CA, USA. 318-323. URL:https: / / doi.org / 10.1145 / 775832.775915D. Maslov, G.W. Dueck, and D. M. Miller. 2003. Simplification of Toffoli networks via templates. In 16th Symposium on Integrated Circuits and Systems Design, Sao Paulo, Brazil. 53-58. URL:https: / / doi.org / 10.1109 / SBCCI.2003.1232806A Quantum Circuit Optimization FrameworkBased on Pattern Matching Mingyu Chen, Yu Zhang and Yongshang Li URL:https: / / doi.org / 10.1142 / S2010324721400087Raban Iten, Romain Moyard, Tony Metger, David Sutter, and Stefan Woerner. 2022. Exact and Practical Pattern Matching for Quantum Circuit Optimization. ACM Transactions on Quantum Computing 3, 1, Article 4 (March 2022), 41 pages. URL:https: / / doi.org / 10.1145 / 3498325

[0006] However, in the above-mentioned prior art, when pattern matching with a template, a search is performed for a perfect match with all gates, and therefore there is a problem that matching with many templates requires a long calculation time.

[0007] In one aspect, an object of the present invention is to provide a quantum bit allocation program, a quantum bit allocation method, and a quantum bit allocation device that can easily perform quantum bit allocation.

[0008] In one proposal, the quantum bit allocation program causes a computer to execute a conversion process, a second graph creation process, an identification process, and a circuit information creation process. The conversion process converts the quantum circuit to be operated on into a first graph showing the connection relationships of each gate included in the quantum circuit. The second graph creation process creates a second graph based on the first graph by removing gates other than the two-quantum gate included in the first graph. The identification process identifies a graph isomorphic to the second graph from third graphs created based on each of multiple quantum circuits. The circuit information creation process creates circuit information corresponding to the quantum circuit to be operated on, to which quantum bits are assigned based on multiple quantum circuits corresponding to the identified third graph.

[0009] Qubit allocation can be easily performed.

[0010] FIG. 1 is a block diagram illustrating an example of the hardware configuration of a quantum bit allocation device according to an embodiment. FIG. 2 is a block diagram illustrating an example of the functional configuration of a quantum bit allocation device according to an embodiment. FIG. 3 is a flowchart illustrating an example of the operation of a quantum bit allocation device according to an embodiment. FIG. 4 is an explanatory diagram illustrating an example of target quantum circuit information. FIG. 5 is an explanatory diagram illustrating an example of a divided circuit and actual machine constraints. FIG. 6 is an explanatory diagram illustrating an example of decomposition into native gates. FIG. 7 is an explanatory diagram illustrating conversion of a circuit into a standard form (graph). FIG. 8 is an explanatory diagram illustrating deletion of gates that are not eligible for matching included in the standard form (graph). FIG. 9 is an explanatory diagram illustrating an example of a template. FIG. 10 is an explanatory diagram illustrating a graph of the template. FIG. 11 is an explanatory diagram illustrating graph isomorphism determination. FIG. 12 is an explanatory diagram illustrating creation of assigned circuit information. FIG. 13 is an explanatory diagram illustrating synthesis of circuit information.

[0011] Hereinafter, a quantum bit allocation program, a quantum bit allocation method, and a quantum bit allocation device according to embodiments will be described with reference to the drawings. Components having the same functions in the embodiments will be assigned the same reference numerals, and duplicated descriptions will be omitted. Note that the quantum bit allocation program, quantum bit allocation method, and quantum bit allocation device described in the following embodiments are merely examples and do not limit the embodiments. Furthermore, the following embodiments may be combined as appropriate within a consistent range.

[0012] 1 is a block diagram showing an example of the hardware configuration of a quantum bit allocation device according to an embodiment. As shown in Fig. 1, the quantum bit allocation device 1 receives target quantum circuit information 101 relating to a quantum circuit to be operated on (target), and actual machine constraint information 102 relating to gates (native gates) that can be used in a quantum operation unit 21 of a quantum computer 2, and creates quantum bit-allocated circuit information 103 indicating a circuit to which quantum bits have been allocated so as to satisfy the actual machine constraints.

[0013] Specifically, the quantum bit allocation device 1 prepares a plurality of templates 121 in which optimal allocations are calculated in advance for each frequently occurring pattern of quantum circuits. Then, when the quantum circuit to be operated on matches the pattern of a predetermined template 121, the quantum bit allocation device 1 creates quantum bit-allocated circuit information 103 in which quantum bits are allocated based on the matching template 121 (details will be described later).

[0014] The quantum computer 2 allocates quantum bits in the quantum operation unit 21 based on the quantum bit allocated circuit information 103 generated by the quantum bit allocation device 1. As a result, the quantum operation unit 21 of the quantum computer 2 performs an operation on the quantum circuit to be operated on.

[0015] The quantum bit allocation device 1 has a calculation unit 11 and a storage unit 12, and may be, for example, a personal computer (PC). In addition to the calculation unit 11 and the storage unit 12, the quantum bit allocation device 1 may also have a communication interface for communicating with the outside, an input device such as a keyboard or a mouse, and an output device such as a display.

[0016] The calculation unit 11 is realized by, for example, a central processing unit (CPU), a graphics processing unit (GPU), or hardwired logic such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

[0017] The storage unit 12 corresponds to a semiconductor memory element such as a random access memory (RAM) or a flash memory, or a storage device such as a hard disk drive (HDD). The storage unit 12 stores, for example, a template 121 and a program 122.

[0018] The template 121 is a pre-calculated optimal quantum bit allocation for each frequent pattern of quantum circuits (plural quantum circuits) to be operated on in the quantum computer 2. The program 122 is program code for executing various processes in the functional configuration of the operation unit 11 (see FIG. 2).

[0019] The calculation unit 11 reads out and sequentially executes the programs 122 stored in the storage unit 12 to perform processes such as quantum bit allocation.

[0020] 2 is a block diagram showing an example of the functional configuration of the quantum bit allocation device 1 according to the embodiment. As shown in FIG. 2, the calculation unit 11 executes a program 122 to provide functions as a circuit conversion unit 111 and a matching execution unit 112.

[0021] The circuit conversion unit 111 is a processing unit that converts the quantum circuit to be operated on into a graph indicating the connection relationships of each gate included in the quantum circuit based on the target quantum circuit information 101, and creates a matching target graph 113 to be matched with the template 121. Specifically, the circuit conversion unit 111 has a standard form creation unit 111a and a matching non-target gate deletion unit 111b.

[0022] The canonical form creation unit 111a is a processing unit that converts the quantum circuit to be operated on into a canonical form based on the target quantum circuit information 101. For the conversion of the quantum circuit into the canonical form, a known technique described in "Md. Mazder Rahman, Gerhard W. Dueck, and Joseph D. Horton. 2014. An algorithm for quantum template matching. J. Emerg. Technol. Comput. Syst. 11, 3, Article 31 (Dec. 2014), 20 pages. https: / / doi.org / 10.1145 / 2629537" is used.

[0023] For example, when converting a quantum circuit to a standard form, the standard form creation unit 111a treats circuits obtained by rearranging commutative gates as identical. Furthermore, when converting to a standard form, commutative gates are connected in parallel and non-commutative gates are connected in series. In this way, the standard form creation unit 111a converts the quantum circuit to be operated on into a standard form (graph) that shows the connection relationships of each gate included in the quantum circuit.

[0024] The non-matching gate removal unit 111b is a processing unit that creates a matching target graph 113 by removing gates other than two-quantum gates from among the gates included in the graph, based on the standard form (graph) converted by the standard form creation unit 111a.

[0025] The two-quantum gates included in the standard form (graph) are gates related to the graph shape (topology) and are gates directly related to the allocation of quantum bits. In contrast, one-quantum gates other than the two-quantum gates are gates that are not directly related to the allocation of quantum bits.

[0026] The non-matching gate removal unit 111b removes gates other than two quantum gates from the standard form (graph) converted by the standard form creation unit 111a, thereby removing gates that are not directly related to the allocation of quantum bits as gates that are not eligible for matching, and creates a matching graph 113.

[0027] The matching execution unit 112 is a processing unit that matches the matching target graph 113 with a graph based on the circuits included in each of a plurality of prepared templates 121 (searching for an isomorphic graph). The matching execution unit 112 creates quantum bit-allocated circuit information 103 in which quantum bits are allocated based on the matched template 121 and the actual machine constraint information 102. Specifically, the matching execution unit 112 has a graph isomorphism determination unit 112a, an allocation correspondence calculation unit 112b, and an allocation / gate placement unit 112c.

[0028] The graph isomorphism determination unit 112a compares the matching target graph 113 with the graphs of multiple prepared templates 121 (details will be described later), and searches for (identifies) isomorphic graphs in which the nodes (gate types) of the graphs match.

[0029] The assignment correspondence calculation unit 112b calculates the correspondence (correspondence of quantum bit assignment) between the nodes (gates) of the graph searched by the graph isomorphism determination unit 112a and the graph of the matching target graph 113. Specifically, the assignment correspondence calculation unit 112b collects constraints (correspondence) of quantum bits in each of two quantum gates included in the graph. As an example, in a CNOT where two quantum gates have quantum bit a as a control bit and quantum bit b as a target bit, ａ→ｂ In this case, a → b is the constraint (correspondence) of the quantum bit.

[0030] The assignment correspondence calculation unit 112b collects constraints for each node for the graph searched by the graph isomorphism determination unit 112a and the matching target graph 113, and determines whether the constraints correspond without contradiction. If there is no contradiction in the constraints (correspondence), the assignment correspondence calculation unit 112b determines that the graph searched by the graph isomorphism determination unit 112a matches the graph of the matching target graph 113 (pattern match successful). Conversely, if there is a contradiction in the constraints (correspondence), the assignment correspondence calculation unit 112b determines that the pattern match failed.

[0031] The allocation / gate placement unit 112c is a processing unit that allocates quantum bits and places gates based on the template 121 corresponding to the graph for which pattern matching is successful, and creates quantum bit-allocated circuit information 103.

[0032] Specifically, the allocation / gate placement unit 112c allocates quantum bits to the quantum circuit of the template 121 corresponding to the graph where the pattern match was successful, so as to satisfy the actual machine constraints of the quantum computer 2 indicated by the actual machine constraint information 102. The allocation / gate placement unit 112c also places two-quantum gates and swap gates in accordance with the template 121. Here, the allocation / gate placement unit 112c arbitrarily places one-quantum gates, etc., within the range where the calculation result of the circuit does not change. In this way, the allocation / gate placement unit 112c creates quantum bit-allocated circuit information 103 and outputs it to the quantum computer 2.

[0033] 3 is a flowchart showing an example of the operation of the quantum bit allocation device 1 according to the embodiment. As shown in FIG. 3, when the target quantum circuit information 101 and the actual machine constraint information 102 are received and processing is started, the canonical form creation unit 111a converts the quantum circuit to be operated on into a canonical form (S1).

[0034] FIG. 4 is an explanatory diagram illustrating an example of the target quantum circuit information 101. As shown in FIG. 4, the target quantum circuit information 101 includes (x ０ ∨x １ )∧(￢x １ ∨x ２ )∧(￢x ２ ∨￢x ３ ) satisfiability problem (2-SAT problem) is illustrated.

[0035] The calculation unit 11 of the quantum bit allocation device 1 divides the quantum circuits included in the target quantum circuit information 101, and creates circuit information to which quantum bits have been assigned for each divided circuit. For example, in the case of the target quantum circuit information 101 illustrated in FIG. 4, the information may be divided into circuit parts such as Uω and Us. This division of the quantum circuit is performed by the user as appropriate. Next, the calculation unit 11 of the quantum bit allocation device 1 combines the multiple pieces of circuit information created for each divided circuit by inserting a swap gate to match the allocation of quantum bits, and creates quantum bit-allocated circuit information 103 corresponding to the quantum circuit to be operated on.

[0036] 5 is an explanatory diagram illustrating an example of a divided circuit and a real-machine constraint. As shown in FIG. 5, for the target quantum circuit information 101, a part of the circuit part of Uω is divided into circuits 101a, 101b, and 101c for processing.

[0037] The actual machine constraint information 102 also includes the direction of CNOT for the quantum bit (Q: also called physical qubit) on the quantum computer 2 side. In the illustrated example, the actual machine constraint information 102 indicates that for Q0 and Q2, Q2 → Q0 and Q0 → Q4 are actual machine constraints (directions of CNOT). For Q1 and Q3, Q1 → Q4 and Q3 → Q1 are actual machine constraints. For Q4, Q5, and Q6, Q4 → Q5 and Q4 → Q6 are actual machine constraints.

[0038] 6 is an explanatory diagram illustrating an example of decomposition into native gates. The circuits 101a, 101b, and 101c illustrated in FIG. 5 can be decomposed into native gates as shown in FIG. 6 if the physical qubit connections are ignored. Note that the native gates are assumed to be X, √X, CONT, and Rz, as examples. Note that for gates other than CONT in the native gates, the notation π / 4, π / 2, -π / 4, etc. is simplified.

[0039] 7 is an explanatory diagram illustrating the conversion of the circuit 101a into a standard form (graph). As shown in FIG. 7, the standard form creation unit 111a converts the circuit 101a into a standard form (graph) 113a that shows the connection relationships between one quantum gate 131 (X, √X, Rz) and two quantum gates 132a to 132f (CNOT). The labels (numbers) in the diagram indicate the quantum bits (q: also referred to as logical qubits) of the target quantum circuit information 101. Furthermore, the two quantum gates 132a to 132f will be referred to as the two quantum gates 132 unless otherwise distinguished.

[0040] Returning to Figure 3, after S1, the matching non-target gate deletion unit 111b performs a process of deleting matching non-target gates (1-quantum gate 131) other than the 2-quantum gate 132 from among the gates included in the standard form (graph) 113a (S2).

[0041] Specifically, the non-matching gate deletion unit 111b determines whether or not there is one quantum gate 131 in the standard form (graph) 113a (S2a), and if there is not one quantum gate 131 (S2a: No), proceeds to S3.

[0042] If one quantum gate 131 is present (S2a: Yes), the non-matching gate deletion unit 111b randomly selects one node (n) corresponding to the one quantum gate 131 and deletes it from the standard form (graph) 113a (S2b). Next, for all nodes a and b, if a → n and n → b are on the edges of the standard form (graph) 113a, the non-matching gate deletion unit 111b deletes a → n and n → b from the edges. The non-matching gate deletion unit 111b also adds a → b to the edge (S2c). In this way, the non-matching gate deletion unit 111b reconnects the deleted node portion to the standard form (graph) 113a and then returns to S2a.

[0043] 8 is an explanatory diagram illustrating the deletion of non-matching gates included in a standard form (graph). As shown in FIG. 8, the non-matching gate deletion unit 111b creates a matching target graph 113 by deleting one-quantum gates 131 other than two-quantum gates 132a to 132f related to the graph shape (topology) included in the standard form (graph) 113a.

[0044] Returning to FIG. 3, after S2, the matching execution unit 112 compares the matching target graph 113 created by the circuit conversion unit 111 with graphs based on the circuits included in each of the multiple prepared templates 121, and performs graph isomorphism determination (S3).

[0045] Specifically, the graph isomorphism determination unit 112a compares the shapes of the created matching target graph 113 with graphs based on the circuits included in each of the multiple prepared templates 121, ignoring the labels (numbers) related to the quantum bits, and determines whether they are isomorphic (S3a).

[0046] 9 is an explanatory diagram illustrating an example of the template 121. As shown in FIG. 9, the template 121 includes a pair of a circuit pattern 121a and assigned circuit information 121b. The circuit pattern 121a is an example of a short circuit that has been decomposed into native gates of the quantum bit allocation device 1. The assigned circuit information 121b is circuit information in which optimal allocation (quantum bits have been assigned and swap gates have been inserted) has been made to the circuit pattern 121a so as to improve overall reliability (fidelity).

[0047] The matching execution unit 112 compares a graph based on the circuit pattern 121a included in the template 121 with a matching target graph 113 created by the circuit conversion unit 111. The graph based on the circuit pattern 121a may be created in advance when the template 121 is created, or may be created by the circuit conversion unit 111 at the time of comparison.

[0048] 10 is an explanatory diagram illustrating a graph of the template 121. As shown in FIG. 10, for the template 121, a canonical form (graph) 121c is created by converting a circuit pattern 121a into a canonical form. Here, the canonical form (graph) 121c may be graph 121d obtained by removing the one-quantum gates 141 other than the two-quantum gates 142 from among the gates in the graph.

[0049] In the comparison of the graph shape with the matching target graph 113, the graph based on the circuit pattern 121a may be either the standard form (graph) 121c or the graph 121d, but in order to reduce the amount of calculation during comparison, it is preferable to use the graph 121d, which has a smaller number of nodes. In this embodiment, the graph 121d based on the circuit pattern 121a is compared with the matching target graph 113.

[0050] 11 is an explanatory diagram for explaining graph isomorphism determination. As shown in FIG. 11, the graph isomorphism determination unit 112a compares the matching target graph 113 with the graph 121d and determines whether they are isomorphic or not using an existing graph isomorphism determination method. At this stage, the graph isomorphism determination unit 112a performs a CNOT operation between the 2-quantum gate 132 of the matching target graph 113 and the 2-quantum gate 142 of the graph 121d. ａ→ｂ The labels (a, b) in are ignored, and only whether the shapes of the graphs are isomorphic or not is determined.

[0051] 3, if the graphs are not isomorphic in S3a, the matching execution unit 112 outputs a failure because there is no corresponding template 121 (S4), and ends the process. If the graphs are isomorphic in S3a, the assignment correspondence calculation unit 112b collects correspondences between nodes (gates) between the graph 121d determined to be isomorphic and the matching target graph 113 (S3b), and determines whether there is a contradiction in the collected node correspondences (S3c).

[0052] 11, the correspondence (quantum bit assignment correspondence) between the node (two-quantum gate 132) of the matching target graph 113 and the node (two-quantum gate 142) of the graph 121d is {0 → 0, 1 → 1, 4 → 2}, and there is no contradiction in the correspondence. Therefore, the assignment correspondence calculation unit 112b determines that there is no contradiction.

[0053] If there is a contradiction in S3c, the matching execution unit 112 outputs a failure because there is no corresponding template 121 (S4) and terminates processing. If there is no contradiction in S3c, the allocation / gate placement unit 112c assigns quantum bits according to the correspondence without contradiction and places two quantum gates and swap gates according to the assigned circuit information 121b of the template 121 (S5). Next, the allocation / gate placement unit 112c places one quantum gate so that the meaning (circuit calculation result) does not change (S6). Next, the allocation / gate placement unit 112c outputs the quantum bit assigned circuit information 103 created by the processes of S5 and S6 (S7) and terminates processing.

[0054] 12 is an explanatory diagram illustrating the creation of assigned circuit information. As shown in FIG. 12, the assignment / gate placement unit 112c assigns quantum bits (q0, q1, q2) according to the consistent correspondence relationship {0→0, 1→1, 4→2}. The matching execution unit 112 also places the two-quantum gate and swap gate according to the assigned circuit information 121b of the template 121, and places the one-quantum gate so that its meaning is not changed, thereby creating circuit information 103a corresponding to the circuit 101a.

[0055] The matching execution unit 112 creates corresponding circuit information 103b and 103c for the circuits 101b and 101c, respectively, in the same way as for the circuit 101a. Next, the matching execution unit 112 inserts swap gates to combine the circuits 101a, 101b, 101c, etc. so as to match the allocation of quantum bits, and creates quantum bit-allocated circuit information 103 corresponding to the quantum circuit to be operated on.

[0056] 13 is an explanatory diagram illustrating the combination of circuit information 103a, 103b, and 103c. As shown in FIG. 13, matching execution unit 112 combines circuit information 103a, 103b, and 103c by inserting swap gates 103d and 103e so as to match the allocation of quantum bits (q0 to q6), thereby creating quantum bit-allocated circuit information 103.

[0057] As described above, the quantum bit allocation device 1 converts the quantum circuit to be operated on into a first graph (standard form (graph) 113a) that shows the connection relationships of each gate included in the quantum circuit. Based on the first graph, the quantum bit allocation device 1 creates a second graph (matching target graph 113) by removing gates other than the two-quantum gate 132 included in the first graph. The quantum bit allocation device 1 identifies a graph of the same type as the second graph from among third graphs (graph 121d) created based on each quantum circuit of template 121. The quantum bit allocation device 1 creates quantum bit-allocated circuit information 103 corresponding to the quantum circuit to be operated on, to which quantum bits are assigned based on the quantum circuit of template 121 that corresponds to the identified third graph.

[0058] As a result, in the quantum bit allocation device 1, the number of gates included in the graph to be matched is reduced, so that the calculation time for matching with the template can be reduced and quantum bit allocation can be easily performed.

[0059] Furthermore, in the quantum bit allocation device 1, the third graph (graph 121d) is a graph (standard form (graph) 121c) showing the connection relationships of each gate included in the quantum circuit of template 121, with all gates included in this graph removed except for the two-quantum gate 142. In this way, by removing all gates included in the third graph (graph 121d) except for the two-quantum gate 142, the quantum bit allocation device 1 can reduce the calculation time for matching with the template and can easily perform quantum bit allocation.

[0060] Furthermore, the quantum bit allocation device 1 combines multiple pieces of circuit information 103a, 103b, and 103c created for each partitioned circuit of the quantum circuit to be operated on by inserting swap gates 103d and 103e to match the allocation of quantum bits, thereby creating quantum bit-allocated circuit information 103 corresponding to the quantum circuit to be operated on. As a result, the quantum bit allocation device 1 does not need to prepare a huge number of templates assuming the entire quantum circuit to be operated on. For example, the quantum bit allocation device 1 can simply prepare a versatile template that is expected to be used in common for many quantum circuits, as a template assuming the partitioned circuits of the quantum circuit to be operated on. As a result, the quantum bit allocation device 1 is able to match many circuits to a single template, which is expected to reduce the number of templates.

[0061] Note that the components of each device shown in the figure do not necessarily have to be physically configured as shown in the figure. In other words, the specific form of distribution and integration of each device is not limited to that shown in the figure, and all or part of them can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc.

[0062] For example, the various processing functions of the circuit conversion unit 111 and the matching execution unit 112 performed in the calculation unit 11 of the quantum bit allocation device 1 may be executed in whole or in part on a CPU (or a microcomputer such as an MPU or MCU (Micro Controller Unit)). Needless to say, the various processing functions may be executed in whole or in part on a program analyzed and executed by the CPU (or a microcomputer such as an MPU or MCU), or on hardware using wired logic. The various processing functions performed in the quantum bit allocation device 1 may be executed by multiple computers working together using cloud computing.

[0063] Furthermore, the program 122 does not have to be stored in the storage unit 12. For example, the quantum bit allocation device 1 may read and execute the program 122 stored in a readable storage medium. Examples of the readable storage medium for the quantum bit allocation device 1 include portable storage media such as CD-ROMs, DVD disks, and USB (Universal Serial Bus) memories, semiconductor memories such as flash memories, and hard disk drives. Furthermore, the program 122 may be stored in a device connected to a public line, the Internet, a LAN, or the like, and the quantum bit allocation device 1 may read and execute the program 122 from the device.

[0064] In addition, in this embodiment, the case where the two-quantum gate included in the quantum circuit is CNOT has been exemplified, but the two-quantum gate is not limited to CNOT. For example, the two-quantum gate included in the quantum circuit may be a gate other than CNOT, such as CX, CY, CZ, CRx, CRy, or CRz.

[0065] 1... Quantum bit allocation device 2... Quantum computer N... Network 11... Calculation unit 12... Memory unit 21... Quantum calculation unit 101... Target quantum circuit information 101a to 101c... Circuit 102... Actual machine constraint information 103... Quantum bit allocated circuit information 103a to 103c... Circuit information 103d, 103e... Swap gate 111... Circuit conversion unit 111a... Standard form creation unit 111b... Matching non-target gate deletion unit 112... Matching execution unit 112a... Graph isomorphism determination unit 112b... Allocation correspondence calculation unit 112c... Allocation / gate placement unit 113... Matching target graph 113a, 121c... Standard form (graph) 121... Template 121a... Circuit pattern 121b... Allocated circuit information 121d... Graph 122... Program 131, 141...1 quantum gate 132, 132a to 132f, 142...2 quantum gates

Claims

1. converting the quantum circuit to be operated on into a first graph indicating the connection relationships of the gates included in the quantum circuit; creating a second graph based on the first graph by removing gates other than the two-quantum gate included in the first graph; Identifying a graph that is isomorphic to the second graph from among third graphs created based on each of a plurality of quantum circuits; creating circuit information corresponding to the quantum circuit to be operated on, to which quantum bits are assigned based on the plurality of quantum circuits corresponding to the identified third graph; A quantum bit allocation program that causes a computer to execute a process.

2. the third graph is a graph showing the connection relationships of the gates included in the plurality of quantum circuits, with gates other than the two quantum gates included in the graph removed; 2. The quantum bit allocation program according to claim 1 .

3. The process of creating the circuit information includes inserting a swap gate to combine a plurality of pieces of circuit information created for each partition circuit obtained by partitioning the quantum circuit to be operated on, so as to match the allocation of the quantum bits, and creating circuit information corresponding to the quantum circuit to be operated on.

2. The quantum bit allocation program according to claim 1 .

4. The two quantum gates are CNOT gates.

2. The quantum bit allocation program according to claim 1 .

5. converting the quantum circuit to be operated on into a first graph indicating the connection relationships of the gates included in the quantum circuit; creating a second graph based on the first graph by removing gates other than the two-quantum gate included in the first graph; Identifying a graph that is isomorphic to the second graph from among third graphs created based on each of a plurality of quantum circuits; creating circuit information corresponding to the quantum circuit to be operated on, to which quantum bits are assigned based on the plurality of quantum circuits corresponding to the identified third graph; A quantum bit allocation method characterized in that the processing is executed by a computer.

6. converting the quantum circuit to be operated on into a first graph indicating the connection relationships of the gates included in the quantum circuit; creating a second graph based on the first graph by removing gates other than the two-quantum gate included in the first graph; Identifying a graph isomorphic to the second graph from among third graphs created based on each of a plurality of quantum circuits; creating circuit information corresponding to the quantum circuit to be operated on, to which quantum bits are assigned based on the plurality of quantum circuits corresponding to the identified third graph; A quantum bit allocation device having an arithmetic unit that executes processing.