Information processing program, information processing method, and information processing device

Abstract

This information processing device (100) generates a logical bell state of two logical qubits by performing entanglement, between the two logical qubits, of ancillary qubits which are positioned in each of said two logical qubits. Specifically, the information processing device (100) performs entanglement, between two logical qubits without a data qubit therebetween, of all ancillary qubits positioned in each of the logical qubits on the side thereof which connects to another logical qubit instead of a data qubit. Specifically, according to an example in fig. 1, the information processing device (100) generates a logical bell state of two logical qubits by entangling ancillary qubits (10, 11) between two logical qubits without a data qubit therebetween.

Description

[Technical Field]

[0001] The present invention relates to an information processing program, an information processing method, and an information processing device. [Background technology]

[0002] Conventionally, there exists a logical qubit in which multiple data qubits and multiple auxiliary qubits for error correction are arranged in a two-dimensional lattice to counter errors caused by environmental noise, etc. There is also technology to generate a logical Bell state of two logical qubits, each of which is further equipped with an auxiliary qubit for merging. For example, it is conceivable to generate a logical Bell state of two logical qubits by entangling the auxiliary qubits for merging arranged in each logical qubit, then performing a merge operation and a split operation to repair each logical qubit.

[0003] Prior art techniques include, for example, determining the measurement value of a coded Bell measurement based on the calculated probability of the coded Bell measurement. Other techniques include, for example, providing a data qubit that holds a quantum state, a transfer qubit that transfers the quantum state of the data qubit, and a measurement qubit that measures the quantum state of the data qubit transferred via the transfer qubit. Other techniques include, for example, coupling a physical qubit to a logical qubit. Other techniques include, for example, coupling each data qubit to one or more auxiliary qubits. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-090341 [Patent Document 2] Japanese Patent Publication No. 2022-057269 [Patent Document 3] U.S. Patent Application Publication No. 2020-0394101 [Patent Document 4] U.S. Patent Application Publication No. 2020-0119748 Summary of the Invention [Problem to be solved by the invention]

[0005] However, conventional techniques can increase the processing time required to generate a logical Bell state, for example, by entangling auxiliary qubits for the merge process, then performing a merge process and a split process to repair each logical qubit, which increases the processing time required to generate a logical Bell state.

[0006] In one aspect, the present invention aims to suppress an increase in processing time required to generate a logical Bell state. [Means for solving the problem]

[0007] According to one embodiment, an information processing program, an information processing method, and an information processing device are proposed that generate a logical Bell state of two logical quantum bits by entangling all of the auxiliary quantum bits that are arranged on the side that is connected to the other logical quantum bit relative to the data quantum bit in an arrangement of multiple quantum bits, including multiple data quantum bits and multiple auxiliary quantum bits, between the two logical quantum bits without going through the data quantum bits. [Effects of the Invention]

[0008] According to one aspect, it is possible to suppress an increase in the processing time required to generate a logical Bell state. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is an explanatory diagram illustrating an example of an information processing method according to an embodiment. [Figure 2]FIG. 2 is a block diagram showing an example of the hardware configuration of the information processing device 100. As shown in FIG. [Figure 3] FIG. 3 is a block diagram showing an example of the functional configuration of the information processing device 100. As shown in FIG. [Figure 4] FIG. 4 is a diagram (part 1) illustrating an example of generating logical Bell states of logical qubits 410 and 420. [Figure 5] FIG. 5 is a diagram (part 2) illustrating an example of generating logical Bell states of logical qubits 410 and 420. [Figure 6] FIG. 6 is a flowchart (part 1) illustrating an example of the first connection processing procedure. [Figure 7] FIG. 7 is a flowchart (part 2) illustrating an example of the first connection processing procedure. [Figure 8] FIG. 8 is an explanatory diagram showing a quantum circuit 800 in which the information processing device 100 generates logical Bell states of the logical qubits 410 and 420 and performs error correction. [Figure 9] FIG. 9 is a flowchart (part 1) illustrating an example of the second connection processing procedure. [Figure 10] FIG. 10 is a flowchart (part 2) illustrating an example of the second connection processing procedure. [Figure 11] FIG. 11 is an explanatory diagram (part 1) showing a conventional example of generating logical Bell states of logical qubits 1110 and 1120. [Figure 12] FIG. 12 is an explanatory diagram (part 2) showing a conventional example of generating logical Bell states of logical qubits 1110 and 1120. [Figure 13] FIG. 13 is an explanatory diagram (part 3) showing a conventional example of generating logical Bell states of logical qubits 1110 and 1120. [Figure 14] FIG. 14 is a flowchart (part 1) showing an example of a conventional processing procedure. [Figure 15] FIG. 15 is a flowchart (part 2) showing an example of a conventional processing procedure. [Figure 16] FIG. 16 is a flowchart (part 3) showing an example of a conventional processing procedure. [Figure 17] FIG. 17 is an explanatory diagram (part 1) showing an example of the accuracy of the measurement results of a data qubit. [Figure 18] FIG. 18 is a diagram (part 2) illustrating an example of the accuracy of the measurement results of a data qubit. [Figure 19] FIG. 19 is an explanatory diagram (part 3) showing an example of the accuracy of the measurement results of a data qubit. [Figure 20] FIG. 20 is an explanatory diagram (part 4) showing an example of the accuracy of the measurement results of a data qubit. [Figure 21] FIG. 21 is an explanatory diagram (part 5) showing an example of the accuracy of the measurement results of a data qubit. [Figure 22] FIG. 22 is an explanatory diagram (part 1) showing an example of the accuracy of the measurement results of a data qubit. [Figure 23] FIG. 23 is a diagram (part 2) illustrating an example of the accuracy of the measurement results of a data qubit. [Figure 24] FIG. 24 is an explanatory diagram (part 3) showing an example of the accuracy of the measurement results of a data qubit. [Figure 25] FIG. 25 is an explanatory diagram (part 4) showing an example of the accuracy of the measurement results of a data qubit. [Figure 26] FIG. 26 is an explanatory diagram (part 5) showing an example of the accuracy of the measurement results of a data qubit. [Figure 27] FIG. 27 is an explanatory diagram (part 6) showing an example of the accuracy of the measurement results of a data qubit. [Figure 28] FIG. 28 is an explanatory diagram (part 7) showing an example of the accuracy of the measurement results of a data quantum bit. [Figure 29] FIG. 29 is an explanatory diagram (part 1) showing an example of generating logical Bell states of logical qubits 2910 and 2920. [Figure 30] FIG. 30 is an explanatory diagram (part 2) showing an example of generating logical Bell states of logical qubits 2910 and 2920. [Figure 31] FIG. 31 is an explanatory diagram (part 1) showing the reason why split processing is performed. [Figure 32]FIG. 32 is an explanatory diagram (part 2) showing the reason why split processing is performed. [Figure 33] FIG. 33 is an explanatory diagram (part 1) showing why split processing does not need to be performed. [Figure 34] FIG. 34 is an explanatory diagram (part 2) showing why split processing does not need to be performed. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an information processing program, an information processing method, and an information processing device according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0011] (An example of an information processing method according to an embodiment) FIG. 1 is an explanatory diagram illustrating an example of an information processing method according to an embodiment. Information processing device 100 is a computer that handles logical quantum bits. Information processing device 100 is, for example, a quantum computer. Information processing device 100 specifically includes a quantum bit chip. The quantum bit chip represents, for example, a logical quantum bit.

[0012] A logical qubit is formed by arranging multiple qubits. The multiple qubits include multiple data qubits and multiple ancillary qubits. The data qubits represent a data value. The multiple ancillary qubits include an ancillary qubit for error correction and an ancillary qubit for merging.

[0013] A logical qubit includes a plurality of data qubits arranged in a matrix to provide redundancy for the data qubits, for example, to counter errors caused by environmental noise, etc. A logical qubit includes an auxiliary qubit for error correction arranged adjacent to at least one data qubit, for example, to counter errors caused by environmental noise, etc. Specifically, a logical qubit includes an auxiliary qubit for error correction arranged between two different data qubits.

[0014] The logical qubit includes, for example, an auxiliary qubit for merging arranged outside a plurality of data qubits arranged in a matrix to generate a logical Bell state with other logical qubits. A logical Bell state is a state of quantum entanglement of two different logical qubits, in which the value of one of the two different logical qubits is determined in response to the value of the other logical qubit being determined by observation.

[0015] Conventionally, the logical Bell state of two logical qubits is generated by entangling auxiliary qubits for the merge operation placed on each logical qubit, then performing a merge operation and a split operation to repair each logical qubit. For example, the logical state of each logical qubit may be destroyed depending on the merge operation, so a split operation is performed to repair each logical qubit.

[0016] However, conventionally, it is difficult to generate a logical Bell state of two different logical qubits. For example, generating a logical Bell state of two different logical qubits can result in an increase in the processing time required. Specifically, after entangling the auxiliary qubits for the merge process placed on each logical qubit, a merge process is performed and a split process is performed to repair each logical qubit, which increases the processing time required to generate the logical Bell state. In addition, the merge process poses a risk of error propagation.

[0017] Furthermore, conventionally, it is difficult to perform error correction using auxiliary quantum bits for error correction. For example, this can result in an increase in the time required to start performing error correction. Specifically, there is a problem that error correction cannot be performed until the logical Bell states of two different logical quantum bits are completely generated. Therefore, there is a problem that the error rate of data quantum bits is likely to increase when generating the logical Bell states of two different logical quantum bits.

[0018] Therefore, in this embodiment, an information processing method that can facilitate the generation of logical Bell states will be described. For example, the information processing method can suppress an increase in the processing time required to generate logical Bell states.

[0019] In FIG. 1, there are two logical qubits to be connected that are handled by information processing device 100. The connection is to generate a logical Bell state. Each logical qubit includes multiple qubits. The multiple qubits include multiple data qubits and multiple ancillary qubits. In the example of FIG. 1, the two logical qubits are specifically first logical qubit 110 and second logical qubit 120.

[0020] First logical qubit 110 specifically includes four data qubits 1 to 4 arranged in a matrix of two rows and two columns. First logical qubit 110 specifically includes an auxiliary qubit 9 for error correction Z measurement, which is connected to data qubits 1 and 2. First logical qubit 110 specifically includes an auxiliary qubit 10 for error correction Z measurement and a merging process, which is connected to data qubits 3 and 4. Ancillary qubit 10 is for a merging process and is an entangled auxiliary qubit. First logical qubit 110 specifically includes an auxiliary qubit 13 for error correction X measurement, which is connected to data qubits 1 to 4.

[0021] Second logical qubit 120 specifically includes four data qubits 5 to 8 arranged in a matrix of two rows and two columns. Second logical qubit 120 specifically includes an auxiliary qubit 12 for error correction Z measurement, which is connected to data qubits 7 and 8. Second logical qubit 120 specifically includes an auxiliary qubit 11 for error correction Z measurement and for merging, which is connected to data qubits 5 and 6. Ancillary qubit 11 is for merging and is an entangled auxiliary qubit. Second logical qubit 120 specifically includes an auxiliary qubit 16 for error correction X measurement, which is connected to data qubits 5 to 8.

[0022] 1, qubits 1 to 13 and 16 are arranged to minimize the number of entangled pairs of ancillary qubits in first logical qubit 110 and second logical qubit 120. Specifically, the entangled pair of ancillary qubits is a single pair of ancillary qubits 10 and 11.

[0023] (1-1) The information processing device 100 generates a logical Bell state of two logical quantum bits. For example, the information processing device 100 generates a logical Bell state of two logical quantum bits by entangling auxiliary quantum bits arranged in the respective logical quantum bits of the two logical quantum bits between the two logical quantum bits.

[0024] Specifically, in each logical qubit, information processing device 100 entangles all of the auxiliary qubits that are arranged closer to the other logical qubit than the data qubit, between the two logical qubits without using the data qubit. Entanglement is achieved, for example, by quantum state transfer technology.

[0025] 1, the auxiliary qubit arranged in first logical qubit 110 closer to the second logical qubit 120 than the data qubit is specifically auxiliary qubit 10. Similarly, the auxiliary qubit arranged in second logical qubit 120 closer to the first logical qubit 110 than the data qubit is specifically auxiliary qubit 11. Therefore, information processing device 100 specifically generates logical Bell states of the two logical qubits by entangling auxiliary qubits 10 and 11 between the two logical qubits without using a data qubit.

[0026] This allows the information processing device 100 to prevent the logical states of each logical quantum bit from being destroyed in response to the merge process, and eliminates the need for a split process to repair each logical quantum bit. This allows the information processing device 100 to easily generate the logical Bell states of two different logical quantum bits. For example, the information processing device 100 can reduce the processing time required to generate the logical Bell states of two different logical quantum bits. For example, the information processing device 100 can eliminate the need for a split process, and reduce the error rate of the data quantum bits.

[0027] Furthermore, the information processing device 100 can prevent the logical states of each logical quantum bit from being destroyed in response to the merge process, and can perform error correction before completing generation of the logical Bell states of two different logical quantum bits. Therefore, the information processing device 100 can reduce the time required to start performing error correction. The information processing device 100 can reduce the time required from starting generation of the logical Bell states of two different logical quantum bits to completing error correction. The information processing device 100 can reduce the error occurrence rate of data quantum bits.

[0028] Here, we have described a case where multiple qubits are arranged in each logical qubit so as to minimize the number of pairs of entangled ancillary qubits, but this is not limited to this. For example, multiple qubits may be arranged in each logical qubit regardless of the number of entangled ancillary qubits. Specifically, there may be three pairs of entangled ancillary qubits, such as logical qubits 130 and 140 shown in FIG. 1.

[0029] Here, the case where the information processing device 100 is a quantum computer including a qubit chip has been described, but this is not limiting. For example, the information processing device 100 may execute a quantum computer simulator. In this case, the information processing device 100 generates logical Bell states of two different logical qubits in the quantum computer simulator.

[0030] (Example of hardware configuration of information processing device 100) Next, an example of the hardware configuration of the information processing device 100 will be described with reference to FIG.

[0031] Fig. 2 is a block diagram showing an example of the hardware configuration of the information processing device 100. In Fig. 2, the information processing device 100 has a CPU (Central Processing Unit) 201, a memory 202, a network I / F (Interface) 203, a recording medium I / F 204, and a recording medium 205. The information processing device 100 further has an arithmetic device I / F 206 and a quantum arithmetic device 207. In addition, each component is connected to each other by a bus 200.

[0032] Here, the CPU 201 is responsible for overall control of the information processing device 100. The memory 202 includes, for example, a read-only memory (ROM), a random access memory (RAM), and a flash ROM. Specifically, for example, the flash ROM and the ROM store various programs, and the RAM is used as a work area for the CPU 201. The programs stored in the memory 202 are loaded into the CPU 201, causing the CPU 201 to execute the coded processes.

[0033] The network I / F 203 is connected to a network 210 via a communication line, and is connected to other computers via the network 210. The network I / F 203 manages an internal interface with the network 210 and controls input and output of data from other computers. The network I / F 203 is, for example, a modem or a LAN (Local Area Network) adapter.

[0034] The recording medium I / F 204 controls reading / writing of data from / to the recording medium 205 under the control of the CPU 201. The recording medium I / F 204 is, for example, a disk drive, a solid state drive (SSD), a universal serial bus (USB) port, etc. The recording medium 205 is a non-volatile memory that stores data written under the control of the recording medium I / F 204. The recording medium 205 is, for example, a disk, a semiconductor memory, a USB memory, etc. The recording medium 205 may be detachable from the information processing device 100.

[0035] The arithmetic unit I / F 206 controls access to the quantum arithmetic unit 207 under the control of the CPU 201. The arithmetic unit I / F 206 converts an output signal from the CPU 201 into an input signal for the quantum arithmetic unit 207 using a microwave pulse generator, and transmits the input signal to the quantum arithmetic unit 207. The arithmetic unit I / F 206 converts an output signal from the quantum arithmetic unit 207 into an input signal for the CPU 201 using a microwave pulse demodulator, and transmits the input signal to the CPU 201. The quantum arithmetic unit 207 is an arithmetic unit equipped with one or more quantum bit chips cooled to an extremely low temperature of 10 mK (kelvin). The quantum bit chip represents, for example, a logical quantum bit. The quantum arithmetic unit 207 performs a predetermined operation in response to an input signal using one or more quantum bit chips, and outputs an output signal corresponding to the result of the predetermined operation.

[0036] In addition to the above-mentioned components, the information processing device 100 may also include, for example, a keyboard, a mouse, a display, a printer, a scanner, a microphone, a speaker, etc. The information processing device 100 may also include a plurality of recording medium I / Fs 204 and recording media 205. The information processing device 100 may also not include the recording medium I / Fs 204 and recording media 205.

[0037] (Example of functional configuration of information processing device 100) Next, an example of the functional configuration of the information processing device 100 will be described with reference to FIG.

[0038] 3 is a block diagram showing an example of the functional configuration of the information processing device 100. The information processing device 100 includes a storage unit 300, an acquisition unit 301, a calculation unit 302, an operation unit 303, and an output unit 304.

[0039] The storage unit 300 is realized by, for example, a storage area such as the memory 202 or the recording medium 205 shown in Fig. 2. In the following, a case where the storage unit 300 is included in the information processing device 100 will be described, but this is not limiting. For example, the storage unit 300 may be included in a device different from the information processing device 100, and the stored contents of the storage unit 300 may be accessible from the information processing device 100.

[0040] The acquiring unit 301 to the output unit 304 function as an example of a control unit. Specifically, the acquiring unit 301 to the output unit 304 realize their functions by causing the CPU 201 to execute a program stored in a storage area such as the memory 202 or the recording medium 205 shown in Fig. 2, or by the network I / F 203. The processing results of each functional unit are stored in a storage area such as the memory 202 or the recording medium 205 shown in Fig. 2, for example.

[0041] The storage unit 300 stores various information that is referenced or updated in the processing of each functional unit. The storage unit 300 stores, for example, the arrangement of multiple quantum bits in a logical quantum bit. A logical quantum bit is formed by arranging multiple quantum bits.

[0042] The qubit is, for example, a superconducting qubit. The qubit may be, for example, a type other than a superconducting qubit. The plurality of qubits includes a plurality of data qubits and a plurality of auxiliary qubits. The data qubit represents a data value. The plurality of auxiliary qubits includes an auxiliary qubit for error correction and an auxiliary qubit for merging.

[0043] Specifically, storage unit 300 stores the arrangement of multiple qubits in each logical qubit of two logical qubits to be connected. For example, the arrangement of multiple qubits in each logical qubit preferably satisfies the condition that all of the ancillary qubits that are closer to the other logical qubit than the data qubits in that logical qubit are to be entangled.

[0044] Each logical qubit is preferably a logical qubit in which multiple qubits are arranged so as to minimize the number of ancillary qubits to be entangled. For example, each logical qubit is arranged in a binary tree shape, with two or more data qubits arranged on the side connected to the other logical qubit as leaves and one or more ancillary qubits as nodes, with one ancillary qubit that is directly entangled as the root.

[0045] Each logical qubit is specifically arranged with four data qubits in a matrix of two rows and two columns, and each logical qubit is specifically arranged with one ancillary qubit directly connected to two data qubits arranged on the side that connects to the other logical qubit.

[0046] Specifically, each logical qubit has nine data qubits arranged in a matrix of three rows and three columns. Furthermore, each logical qubit has three data qubits arranged on the side connected to the other logical qubit as leaves, and three ancillary qubits arranged as nodes in a binary tree with one ancillary qubit directly entangled as the root. The arrangement is set in advance by the user, for example.

[0047] The acquiring unit 301 acquires various pieces of information used in the processing of each functional unit. The acquiring unit 301 stores the acquired various pieces of information in the storage unit 300 or outputs them to each functional unit. The acquiring unit 301 may also output the various pieces of information stored in the storage unit 300 to each functional unit. The acquiring unit 301 acquires various pieces of information based on, for example, a user's operation input. The acquiring unit 301 may receive various pieces of information from, for example, a device different from the information processing device 100. The acquiring unit 301 acquires, for example, a processing request requesting the generation of a logical Bell state of two logical quantum bits.

[0048] The acquisition unit 301 may receive a start trigger for starting processing by one of the functional units. The start trigger may be, for example, a predetermined operation input by a user. The start trigger may be, for example, reception of predetermined information from another computer. The start trigger may be, for example, output of predetermined information by one of the functional units. Specifically, the acquisition unit 301 receives the acquisition of a processing request as a start trigger for starting processing by the operation unit 303.

[0049] The computing unit 302 realizes a logical quantum bit. The computing unit 302 uses multiple quantum bit chips, each representing a different quantum bit, to realize a logical quantum bit formed by multiple quantum bits arranged as described above. This allows the computing unit 302 to make the logical quantum bit available.

[0050] The operation unit 303 controls the calculation unit 302 to generate a logical Bell state of two logical qubits. The operation unit 303 generates the logical Bell state of two logical qubits, for example, by entangling the auxiliary qubits arranged in each logical qubit of the two logical qubits between the two logical qubits. Specifically, the operation unit 303 entangles all of the auxiliary qubits arranged on the side of each logical qubit that is connected to the other logical qubit rather than the data qubit, between the two logical qubits without using the data qubit. This allows the operation unit 303 to reduce the processing time required to generate the logical Bell state of two logical qubits.

[0051] When generating the logical Bell states of the two logical qubits, the operation unit 303 performs error correction on the data qubits using auxiliary qubits for error correction among the multiple qubits in each logical qubit, thereby enabling the operation unit 303 to reduce the time required to start performing error correction.

[0052] The output unit 304 outputs the processing results of at least one of the functional units. The output format may be, for example, display on a display, printout on a printer, transmission to an external device via the network I / F 203, or storage in a storage area such as the memory 202 or the recording medium 205. This enables the output unit 304 to notify the user of the processing results of at least one of the functional units, thereby improving the convenience of the information processing device 100. The output unit 304 outputs, for example, a notification indicating that logical Bell states of two logical quantum bits have been generated, so that the user can refer to it.

[0053] (An example of the operation of the information processing device 100) Next, an example of the operation of information processing device 100 will be described with reference to Figures 4 to 32. Specifically, first, an example in which information processing device 100 generates logical Bell states of logical qubits 410 and 420 will be described with reference to Figures 4 and 5.

[0054] 4 and 5 are explanatory diagrams showing an example of generating logical Bell states for logical qubits 410 and 420. Specifically, Figure 4 shows an example of an arrangement of multiple qubits in logical qubits 410 and 420 for which logical Bell states are to be generated.

[0055] For example, the arrangement of multiple qubits in logical qubits 410 and 420 satisfies the condition that all of the ancillary qubits present in one logical qubit that are closer to the other logical qubit than the data qubits are to be entangled.

[0056] As shown in FIG. 4, logical qubit 410 exists, for example, at node A. Logical qubit 410 specifically includes four data qubits 1 to 4 arranged in a matrix of two rows and two columns. Logical qubit 410 specifically includes an auxiliary qubit 9 for error correction Z measurement connected to data qubits 1 and 2. Logical qubit 410 specifically includes an auxiliary qubit 10 for error correction Z measurement and merging processing connected to data qubits 3 and 4. Logical qubit 410 specifically includes an auxiliary qubit 13 for error correction X measurement connected to data qubits 1 to 4.

[0057] As shown in FIG. 4, logical qubit 420 exists, for example, at node B. Logical qubit 420 specifically includes four data qubits 5 to 8 arranged in a matrix of two rows and two columns. Logical qubit 420 specifically includes an auxiliary qubit 12 for error correction Z measurement, which is connected to data qubits 7 and 8. Logical qubit 420 specifically includes an auxiliary qubit 11 for error correction Z measurement and merging processing, which is connected to data qubits 5 and 6. Logical qubit 420 specifically includes an auxiliary qubit 16 for error correction X measurement, which is connected to data qubits 5 to 8. Next, we move on to the description of FIG. 5.

[0058] Figure 5 shows a quantum circuit 500 that generates logical Bell states for logical qubits 410 and 420. In Figure 5, each horizontal line in quantum circuit 500 represents a time axis corresponding to one of the qubits.

[0059] Qubits 1 to 4 are each in the logical state |0 L A 〉. The notation |x〉 denotes a state in which x is observed with 100% probability. x is, for example, a value. Logical state |0 L A 〉 is, for example, |0000〉+|1111〉. Qubits 5 to 8 each have the logical state |0 L B 〉. Logical state |0 L B 〉 is, for example, |0000〉+|1111〉. Quantum bits 10 and 11 are each in the state |0〉.

[0060] Information processing device 100 executes quantum state transfer 501, which sets quantum bits 10 and 11 to states |00〉+|11〉, respectively. This enables information processing device 100 to entangle quantum bits 10 and 11. Information processing device 100 executes controlled NOT gate 502, with quantum bit 10 as the control bit and quantum bit 3 as the target bit. Information processing device 100 executes controlled NOT gate 503, with quantum bit 10 as the control bit and quantum bit 4 as the target bit.

[0061] Information processing device 100 executes Hadamard gate 504 on quantum bit 10. Information processing device 100 executes controlled NOT gate 505 with quantum bit 11 as the control bit and quantum bit 5 as the target bit. Information processing device 100 executes controlled NOT gate 506 with quantum bit 11 as the control bit and quantum bit 6 as the target bit.

[0062] Information processing device 100 executes Hadamard gate 507 on quantum bit 11. Information processing device 100 executes Z measurement 508 on quantum bits 10 and 11. If the product of the measurement results of quantum bits 10 and 11 is 1, information processing device 100 executes Z gate 509 on quantum bits 1 and 3.

[0063] This allows information processing device 100 to generate the logical Bell states of logical qubits 410 and 420 without performing splitting. Specifically, information processing device 100 splits qubits 1 to 8 into the logical Bell states |Φ L + >. Therefore, information processing device 100 can reduce the processing time required to generate the logical Bell states of logical qubits 410 and 420.

[0064] (First connection processing procedure) Next, an example of a first connection processing procedure executed by information processing device 100 will be described with reference to Figures 6 and 7. The first connection processing corresponds to the operation of generating logical Bell states of logical quantum bits 410 and 420 shown in Figure 5. The first connection processing is realized by, for example, CPU 201, storage areas such as memory 202 and recording medium 205, and network I / F 203 shown in Figure 2.

[0065] 6 and 7 are flowcharts showing an example of a first connection process procedure. In FIG. 6, the information processing device 100 sets the quantum bits 1 to 4 in the logical state |0 L A 〉, and qubits 5 to 8 are each set to the logical state |0 L B > (step S601).

[0066] Information processing device 100 sets quantum bits 10 and 11 to the state |0〉 (step S602). Information processing device 100 executes quantum state transfer to set quantum bits 10 and 11 to the state |00〉+|11〉 (step S603).

[0067] Information processing device 100 executes a controlled NOT gate with quantum bit 10 as the control bit and quantum bit 3 as the target bit (step S604). Information processing device 100 executes a controlled NOT gate with quantum bit 10 as the control bit and quantum bit 4 as the target bit (step S605). Information processing device 100 executes a Hadamard gate on quantum bit 10 (step S606).

[0068] Information processing device 100 executes a controlled NOT gate with quantum bit 11 as the control bit and quantum bit 5 as the target bit (step S607). Information processing device 100 executes a controlled NOT gate with quantum bit 11 as the control bit and quantum bit 6 as the target bit (step S608). Next, we move on to the description of FIG. 7.

[0069] 7, information processing device 100 executes a Hadamard gate on quantum bit 11 (step S701). Information processing device 100 executes Z measurement on quantum bits 10 and 11 (step S702). Information processing device 100 determines whether the product of the measurement results of quantum bits 10 and 11 is 1 (step S703).

[0070] Here, if the product of the measurement results of quantum bits 10 and 11 is not 1 (step S703: No), the information processing device 100 executes a Z gate for quantum bits 1 and 3 (step S704) and ends the first connection process. On the other hand, if the product of the measurement results of quantum bits 10 and 11 is 1 (step S703: Yes), the information processing device 100 ends the first connection process. As a result, the information processing device 100 changes the logical state |0 L A 〉|0 L B 〉+|1 L A 〉|1 L B 〉 can be generated.

[0071] Next, an example in which information processing device 100 generates logical Bell states of logical qubits 410 and 420 and performs error correction will be described with reference to FIG.

[0072] 8 is an explanatory diagram showing a quantum circuit 800 in which information processing device 100 generates logical Bell states of logical qubits 410 and 420 and performs error correction. In FIG. 8, each horizontal line in quantum circuit 800 represents a time axis corresponding to one of the qubits.

[0073] Qubits 1 to 4 are each in the logical state |0 L A 〉. qubits 5 to 8 are in the logical state |0 L B >. Quantum bits 9 to 13, and 16 are each in the state |0>. Specifically, information processing device 100 performs multiple quantum operations on quantum bits 1 to 13, and 16 in stages, as shown below. For example, two or more quantum operations belonging to the same stage may be executed in parallel. The thick lines in FIG. 8 represent quantum operations that are executed for error correction among the multiple quantum operations.

[0074] (8-1) To generate a logical Bell state, the information processing device 100 executes a Hadamard gate 801 on the quantum bits 13 and 16 in step 1.

[0075] (8-2) To generate a logical Bell state, in step 2, information processing device 100 executes quantum state transfer 802, which sets quantum bits 10 and 11 to states |00〉+|11〉, respectively. For error correction, in step 2, information processing device 100 executes controlled NOT gate 803, with quantum bits 13 and 16 as control bits and quantum bits 1 and 7 as target bits.

[0076] (8-3) To generate a logical Bell state, in step 3, information processing device 100 executes controlled NOT gate 804 with quantum bit 10 as the control bit and quantum bit 3 as the target bit. To generate a logical Bell state, in step 3, information processing device 100 executes controlled NOT gate 804 with quantum bit 11 as the control bit and quantum bit 5 as the target bit. For error correction, in step 3, information processing device 100 executes controlled NOT gate 805 with quantum bits 13 and 16 as the control bits and quantum bits 2 and 8 as the target bits.

[0077] (8-4) To generate a logical Bell state, in step 4, information processing device 100 executes controlled NOT gate 806 with quantum bit 10 as the control bit and quantum bit 4 as the target bit. To generate a logical Bell state, in step 4, information processing device 100 executes controlled NOT gate 806 with quantum bit 11 as the control bit and quantum bit 6 as the target bit. For error correction, in step 4, information processing device 100 executes controlled NOT gate 807 with quantum bits 13 and 16 as the control bits and quantum bits 3 and 5 as the target bits.

[0078] (8-5) To generate the logical Bell state, the information processing device 100 executes the Hadamard gate 808 on the quantum bits 10 and 11 in step 5.

[0079] (8-6) To generate a logical Bell state, in step 6, the information processing device 100 performs Z measurement 809 on quantum bits 10 and 11. For error correction, in step 6, the information processing device 100 performs controlled NOT gate 810 on quantum bits 13 and 16 as control bits and quantum bits 4 and 6 as target bits.

[0080] (8-7) For error correction, in step 7, the information processing device 100 executes the controlled NOT gate 811 with the quantum bits 1, 3, 5, and 7 as control bits and the quantum bits 9, 10, 11, and 12 as target bits.

[0081] (8-8) For error correction, in step 8, information processing device 100 executes controlled NOT gate 812 on quantum bits 2, 4, 6, and 8 as control bits and quantum bits 9, 10, 11, and 12 as target bits. For error correction, in step 8, information processing device 100 executes Hadamard gate 813 on quantum bits 13 and 16.

[0082] (8-9) For error correction, the information processing device 100 performs Z measurement 814 on qubits 9 to 13, and 16. This allows the information processing device 100 to generate the logical Bell states of the logical qubits 410 and 420 without performing splitting. Specifically, the information processing device 100 performs Z measurement 814 on qubits 9 to 13, and 16, and generates ..., without performing splitting. L + >. Therefore, information processing device 100 can reduce the processing time required to generate the logical Bell states of logical qubits 410 and 420.

[0083] Furthermore, information processing device 100 can perform error correction while generating the logical Bell states of logical qubits 410 and 420. Specifically, information processing device 100 converts qubits 1 to 8 into the logical Bell states |Φ L + >. Therefore, the information processing device 100 can reduce the time required to start performing error correction. The information processing device 100 can reduce the time required from starting to generate the logical Bell states of the logical qubits 410 and 420 until completing the performance of error correction. The information processing device 100 can reduce the risk of error propagation.

[0084] (Second connection processing procedure) Next, an example of a second connection processing procedure executed by information processing device 100 will be described with reference to Figures 9 and 10. The second connection processing corresponds to the operation of generating logical Bell states of logical quantum bits 410 and 420 and performing error correction, as shown in Figure 8. The second connection processing is realized by, for example, CPU 201, storage areas such as memory 202 and recording medium 205, and network I / F 203, as shown in Figure 2.

[0085] 9 and 10 are flowcharts showing an example of the second connection processing procedure. In FIG. 8, the information processing device 100 sets the quantum bits 1 to 4 in the logical state |0 L A 〉, and qubits 5 to 8 are each set to the logical state |0 L B > (step S901). The information processing device 100 sets each of the quantum bits 9 to 13 and 16 to the state |0> (step S902).

[0086] Information processing device 100 executes a Hadamard gate on quantum bits 13 and 16 (step S903). Information processing device 100 executes quantum state transfer to set quantum bits 10 and 11 to the state |00〉+|11〉, respectively (step S904).

[0087] Information processing device 100 executes a controlled NOT gate with quantum bits 13 and 16 as control bits and quantum bits 1 and 7 as target bits (step S905). Information processing device 100 executes a controlled NOT gate with quantum bit 10 as the control bit and quantum bit 3 as the target bit (step S906). Information processing device 100 executes a controlled NOT gate with quantum bit 11 as the control bit and quantum bit 5 as the target bit (step S907).

[0088] Information processing device 100 executes a controlled NOT gate with quantum bits 13 and 16 as control bits and quantum bits 2 and 8 as target bits (step S908). Information processing device 100 executes a controlled NOT gate with quantum bit 10 as the control bit and quantum bit 4 as the target bit (step S909). Information processing device 100 proceeds to the processing of step S1001, which will be described later with reference to FIG. 10.

[0089] In FIG. 10, information processing device 100 executes a controlled NOT gate with quantum bit 11 as the control bit and quantum bit 6 as the target bit (step S1001).

[0090] Information processing device 100 executes a controlled NOT gate for each of qubits 13 and 16 as control bits and qubits 3 and 5 as target bits (step S1002). Information processing device 100 executes a Hadamard gate for qubits 10 and 11 (step S1003). Information processing device 100 executes a Z measurement for qubits 10 and 11 (step S1004).

[0091] Information processing device 100 executes controlled NOT gates with quantum bits 13 and 16 as control bits and quantum bits 4 and 6 as target bits (step S1005). Information processing device 100 executes controlled NOT gates with quantum bits 1, 3, 5, and 7 as control bits and quantum bits 9, 10, 11, and 12 as target bits (step S1006).

[0092] The information processing device 100 executes a controlled NOT gate for each of the qubits 2, 4, 6, and 8 as control bits and the qubits 9, 10, 11, and 12 as target bits (step S1007). The information processing device 100 executes a Hadamard gate for the qubits 13 and 16 (step S1008). The information processing device 100 executes Z measurements for the qubits 9 to 13 and 16 (step S1009). The information processing device 100 ends the second connection process. As a result, the information processing device 100 changes the logical state |0 L A 〉|0L B 〉+|1 L A 〉|1 L B 〉 can be generated.

[0093] Next, a conventional method for generating logical Bell states of logical qubits 1110 and 1120 will be described with reference to FIGS. 11 to 13, and the conventional method will be compared with the method of information processing device 100. FIG.

[0094] 11 to 13 are explanatory diagrams showing a conventional example of generating logical Bell states of logical quantum bits 1110 and 1120. Specifically, Fig. 11 shows a conventional example of an arrangement of multiple quantum bits in logical quantum bits 1110 and 1120 for which logical Bell states are to be generated.

[0095] As shown in FIG. 11 , logical qubit 1110 exists, for example, at node A. Logical qubit 1110 specifically includes four data qubits 1 to 4 arranged in a matrix of two rows and two columns. Logical qubit 1110 specifically includes an auxiliary qubit 9 for error correction Z measurement connected to data qubits 1 and 2. Logical qubit 1110 specifically includes an auxiliary qubit 10 for error correction Z measurement connected to data qubits 3 and 4. Logical qubit 1110 specifically includes an auxiliary qubit 14 for merging connected to data qubit 3, and an auxiliary qubit 15 for merging connected to data qubit 4. Logical qubit 1110 specifically includes an auxiliary qubit 13 for error correction X measurement connected to data qubits 1 to 4.

[0096] As shown in FIG. 11 , logical qubit 1120 resides, for example, at node B. Logical qubit 1120 specifically includes four data qubits 5 to 8 arranged in a matrix of two rows and two columns. Logical qubit 1120 specifically includes an auxiliary qubit 12 for error correction Z measurement connected to data qubits 7 and 8. Logical qubit 1120 specifically includes an auxiliary qubit 11 for error correction Z measurement connected to data qubits 5 and 6. Logical qubit 1120 specifically includes an auxiliary qubit 17 for merging connected to data qubit 5, and an auxiliary qubit 18 for merging connected to data qubit 6. Logical qubit 1120 specifically includes an auxiliary qubit 16 for error correction X measurement connected to data qubits 5 to 8. Next, we move on to the description of FIG. 12 .

[0097] 12 and 13 show a quantum circuit 1200 that generates logical Bell states of logical qubits 1110 and 1120 and performs error correction. In Fig. 12, each horizontal line in quantum circuit 1200 represents a time axis corresponding to one of the qubits.

[0098] Qubits 1 to 4 are each in the logical state |0 L A 〉. qubits 5 to 8 are in the logical state |0 L B >. Quantum bits 9 to 18 are each in the state |0>. A conventional computer implementing a conventional method performs multiple quantum operations on quantum bits 1 to 18 in stages, specifically as shown below. For example, two or more quantum operations belonging to the same stage may be executed in parallel. The thick lines in FIG. 13 represent quantum operations executed for error correction among multiple quantum operations.

[0099] (12-1) To generate the logical Bell state, in step 1, a conventional computer performs quantum state transfer 1201, setting qubits 14 and 17 and qubits 15 and 18 to the state |00〉+|11〉, respectively.

[0100] (12-2) To generate a logical Bell state, in step 2, a conventional computer executes controlled NOT gate 1202 with qubit 14 as the control bit and qubit 3 as the target bit. To generate a logical Bell state, in step 2, a conventional computer executes controlled NOT gate 1202 with qubit 17 as the control bit and qubit 5 as the target bit.

[0101] To generate a logical Bell state, a conventional computer executes controlled NOT gate 1202 in step 2 with qubit 15 as the control bit and qubit 4 as the interest bit. To generate a logical Bell state, a conventional computer executes controlled NOT gate 1202 in step 2 with qubit 18 as the control bit and qubit 6 as the interest bit.

[0102] (12-3) To generate the logical Bell state, in step 3, a conventional computer executes Hadamard gate 1203 on qubits 14-18.

[0103] (12-4) To generate a logical Bell state, the conventional computer performs Z measurement 1204 on qubits 14 to 18 in step 4. To generate a logical Bell state, the conventional computer performs Z gate 1205 on qubits 1 and 3 if the product of the measurement results of qubits 14 to 18 in step 4 is 1.

[0104] (12-5) To generate the logical Bell state, a conventional computer executes controlled NOT gate 1206 in step 5, with qubit 3 as the control bit and qubit 10 as the target bit.

[0105] (12-6) To generate the logical Bell state, a conventional computer executes controlled NOT gate 1207 in step 6, with qubit 4 as the control bit and qubit 10 as the target bit. We now turn to a discussion of Figure 13, which specifically illustrates a continuation of quantum circuit 1200.

[0106] (13-1) To generate the logical Bell state, the conventional computer performs Z measurement 1301 on qubit 10 in step 7. For error correction, the conventional computer performs Hadamard gate 1302 on qubits 13 and 16 in step 7.

[0107] (13-2) For error correction, in step 8, the conventional computer executes controlled NOT gate 1303 with qubits 13, 16, 3, and 7 as control bits and qubits 1, 5, 10, and 12 as target bits.

[0108] (13-3) For error correction, in step 9, the conventional computer executes controlled NOT gate 1304 with qubits 13, 16, 4, and 8 as control bits and qubits 2, 6, 10, and 12 as target bits.

[0109] (13-4) For error correction, in step 10, the conventional computer executes controlled NOT gate 1306 with qubits 13, 16, 1, and 5 as control bits and qubits 3, 7, 9, and 11 as target bits. For error correction, in step 10, the conventional computer executes Z measurement 1307 on qubits 10 and 12.

[0110] (13-5) For error correction, in step 11, a conventional computer executes controlled NOT gate 1308 with qubits 13, 16, 2, and 6 as control bits and qubits 4, 8, 9, and 11 as target bits.

[0111] (13-6) To correct the error, the conventional computer performs a Hadamard gate 1309 on qubits 13 and 16 in step 12.

[0112] (13-7) For error correction, the conventional computer performs Z measurements 1310 on qubits 9, 11, 13, and 16 in step 13. This allows the conventional computer to generate the logical Bell states of logical qubits 1110 and 1120 and perform error correction.

[0113] (Conventional processing procedure) Next, an example of a conventional processing procedure executed by a conventional computer will be described with reference to FIGS.

[0114] 14 to 16 are flowcharts showing an example of a conventional processing procedure. In FIG. 14, a conventional computer sets quantum bits 1 to 4 in the logical state |0 L A 〉, and qubits 5 to 8 are each set to the logical state |0 L B > (step S1401).

[0115] The conventional computer sets each of quantum bits 9 to 18 to the state |0〉 (step S1402). The conventional computer then executes quantum state transfer, setting each of quantum bits 14 and 17 and quantum bits 15 and 18 to the state |00〉+|11〉 (step S1403).

[0116] The conventional computer executes a controlled NOT gate with qubit 14 as the control bit and qubit 3 as the target bit (step S1404). The conventional computer executes a controlled NOT gate with qubit 17 as the control bit and qubit 5 as the target bit (step S1405).

[0117] The conventional computer executes a controlled NOT gate with quantum bit 15 as the control bit and quantum bit 4 as the target bit (step S1406). The conventional computer executes a controlled NOT gate with quantum bit 18 as the control bit and quantum bit 6 as the target bit (step S1407). The conventional computer proceeds to the processing of step S1501, which will be described later with reference to FIG. 15.

[0118] 15, the conventional computer executes a Hadamard gate on the quantum bits 14 to 18 (step S1501). The conventional computer executes a Z measurement on the quantum bits 14 to 18 (step S1502).

[0119] The conventional computer determines whether the product of the measurement results of quantum bits 14 to 18 is 1 (step S1503). If the product of the measurement results of quantum bits 14 to 18 is not 1 (step S1503: No), the conventional computer executes a Z gate on quantum bits 1 and 3 (step S1504) and proceeds to the processing of step S1505. On the other hand, if the product of the measurement results of quantum bits 14 to 18 is 1 (step S1503: Yes), the conventional computer proceeds to the processing of step S1505.

[0120] At step S1505, the conventional computer executes a controlled NOT gate with quantum bit 3 as the control bit and quantum bit 10 as the target bit (step S1505). The conventional computer executes a controlled NOT gate with quantum bit 4 as the control bit and quantum bit 10 as the target bit (step S1506).

[0121] The conventional computer performs Z measurement on quantum bit 10 (step S1507). The conventional computer performs Hadamard gates on quantum bits 13 and 16 (step S1508). The conventional computer proceeds to the processing of step S1601, which will be described later with reference to FIG.

[0122] In FIG. 16, the conventional computer executes controlled NOT gates with quantum bits 13, 16, 3, and 7 as control bits and quantum bits 1, 5, 10, and 12 as target bits (step S1601).

[0123] The conventional computer executes controlled NOT gates with qubits 13, 16, 4, and 8 as control bits and qubits 2, 6, 10, and 12 as target bits (step S1602). The conventional computer executes controlled NOT gates with qubits 13, 16, 1, and 5 as control bits and qubits 3, 7, 9, and 11 as target bits (step S1603).

[0124] The conventional computer executes a controlled NOT gate for each of the qubits 13, 16, 2, and 6 as control bits and the qubits 4, 8, 9, and 11 as target bits (step S1604). The conventional computer executes a Hadamard gate for the qubits 13 and 16 (step S1605). The conventional computer executes Z measurements for the qubits 9 to 13 and 16 (step S1606). The conventional computer then ends the conventional processing. As a result, the conventional computer returns to the logical state |0 L A 〉|0 L B 〉+|1 L A 〉|1 L B 〉 can be generated.

[0125] 4 to 10, information processing device 100 can generate the logical Bell states of logical qubits 410 and 420 without performing split processing by performing the merge processing of steps S601 to S608 and S701 to S704. On the other hand, as shown in FIGS. 11 to 16, conventional methods perform the merge processing of steps S1401 to S1407 and S1501 to S1503, and then perform the split processing of steps S1504 to S1507. In this way, information processing device 100 can reduce the processing time required to generate the logical Bell states of logical qubits 410 and 420 compared to conventional methods.

[0126] 4 to 10, information processing device 100 can perform error correction while generating the logical Bell states of logical qubits 410 and 420. Information processing device 100 can perform error correction while generating the logical Bell states of logical qubits 410 and 420, for example, in steps S901 to S909 and S1001 to S1009.

[0127] 11 to 16, in conventional methods, error correction is performed after generating the logical Bell states of logical quantum bits 1110 and 1120. In conventional methods, for example, after generating the logical Bell states of logical quantum bits 1110 and 1120 in steps S1401 to S1407 and S1501 to S1507, error correction is performed in steps S1508 and S1601 to S1606.

[0128] In this way, information processing device 100 can reduce the time required to start error correction compared to conventional methods. Information processing device 100 can reduce the time required from starting to generate the logical Bell states of logical qubits 410 and 420 to completing error correction compared to conventional methods.

[0129] 17 to 21, an example of the accuracy of the measurement results of data quantum bits in information processing device 100 will be described. Specifically, an example of the accuracy of the measurement results of data quantum bits will be shown when information processing device 100 generates logical Bell states of logical quantum bits 1710 and 1720 shown in FIG. 17 and performs error correction.

[0130] 17 to 21 are explanatory diagrams showing an example of the accuracy of measurement results of data qubits. Specifically, Fig. 17 shows an example of an arrangement of multiple qubits in logical qubits 1710 and 1720 that are targets for generating logical Bell states.

[0131] 17, logical qubit 1710 specifically includes four data qubits 1 to 4 arranged in a matrix of 2 rows and 2 columns. Logical qubit 1710 specifically includes an auxiliary qubit 9 for error correction Z measurement connected to data qubits 1 and 2. Logical qubit 1710 specifically includes an auxiliary qubit 10 for error correction Z measurement and merging processing connected to data qubits 3 and 4. Logical qubit 1710 specifically includes an auxiliary qubit 11 for error correction X measurement connected to data qubits 1 to 4.

[0132] 17, logical qubit 1720 specifically includes four data qubits 5 to 8 arranged in a matrix of 2 rows and 2 columns. Logical qubit 1720 specifically includes an auxiliary qubit 13 for error correction Z measurement connected to data qubits 7 and 8. Logical qubit 1720 specifically includes an auxiliary qubit 12 for error correction Z measurement and merging processing connected to data qubits 5 and 6. Logical qubit 1720 specifically includes an auxiliary qubit 14 for error correction X measurement connected to data qubits 5 to 8.

[0133] The arrangement of multiple qubits in logical qubits 1710 and 1720 is determined so as to minimize the number of pairs of ancillary qubits that are directly entangled. For example, in the example of Figure 17, the pair of ancillary qubits that are entangled is one of the pairs of ancillary qubits 10 and 12. Next, we move on to a description of Figure 18.

[0134] 18 shows quantum circuit 1800 in which information processing device 100 generates logical Bell states of logical quantum bits 1710 and 1720 and performs error correction. In FIG. 18, each horizontal line in quantum circuit 1800 represents a time axis corresponding to one of the quantum bits.

[0135] Information processing device 100 performs multiple quantum operations on quantum bits 1 to 14 in stages. For example, two or more quantum operations belonging to the same stage are executed in parallel. The thick lines in FIG. 18 represent quantum operations that are executed for error correction among the multiple quantum operations. Information processing device 100 acquires measurement results of data quantum bits 1 to 8 by performing multiple simulations in which multiple quantum operations are performed on quantum bits 1 to 14 in stages in accordance with quantum circuit 1800.

[0136] During the simulation, for example, the processing time for a one-qubit gate is assumed to be 5 ns. During the simulation, for example, the processing time for a two-qubit gate is assumed to be 20 ns. During the simulation, for example, the processing time for measurement is assumed to be 35 ns. During the simulation, for example, the processing time for state transfer is assumed to be 60 ns.

[0137] Here, quantum bits have the property that errors occur probabilistically. For example, at each stage of performing a quantum operation, the quantum bit has a probability p 1G , probability p 2G , or probability p M An error occurs at p. Furthermore, each time auxiliary qubits for merge processing are entangled, an error occurs in the qubit with probability p. Specifically, in quantum operation 1801 in FIG. 18, an error occurs in the qubit with probability p.

[0138] First, let us move on to the explanation of Figure 19, where p = 0.0 and the probability p 1G , probability p 2G , and probability p M An example of the accuracy of the measurement results of data qubits 1 to 8 when information processing device 100 performs simulations 10,000 times without taking this into consideration will be described.

[0139] 19 shows multiple values ​​that can be measured for data qubits 1 through 8, and the frequency with which each value occurs as a measurement result for data qubits 1 through 8. The multiple values ​​are, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no errors occur.

[0140] As shown in table 1900, no errors appear in the measurement results of data qubits 1 to 8, and the precision F (Fidelity) is 1.000±0.000.

[0141] Next, let us move on to the explanation of Figure 20, where p = 0.1 and the probability p 1G , probability p 2G , and probability p M An example of the accuracy of the measurement results of data qubits 1 to 8 when information processing device 100 performs simulations 10,000 times without taking this into consideration will be described.

[0142] 20 shows multiple values ​​that can be measured for data qubits 1 through 8, and the frequency with which each value occurs as a measurement result for data qubits 1 through 8. The multiple values ​​include, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no errors occur.

[0143] The multiple values ​​include, for example, 11110011, 00000011, 00001100, and 11111100. 11110011, 00000011, 00001100, and 11111100 are the values ​​in which the error occurred.

[0144] As shown in Table 2000, errors may appear in the measurement results of data qubits 1 to 8. The precision F (Fidelity) is 0.962±0.002.

[0145] Next, let us move on to the explanation of Figure 21, where p = 0.1 and the probability p 1G , probability p 2G , and probability p M Taking this into consideration, an example of the accuracy of the measurement results of data qubits 1 to 8 when information processing device 100 performs simulations 10,000 times will be described.

[0146] 21 shows multiple values ​​that may be measured for data qubits 1 through 8, and the frequency with which each value occurs as a measurement result for data qubits 1 through 8. The multiple values ​​include, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no errors occur.

[0147] The multiple values ​​include, for example, 11010000, 11110001, 00000100, 00100000, 00001110, 00000001, 11110011, and 11111100. 11010000, 11110001, 00000100, 00100000, 00001110, 00000001, 11110011, and 11111100 are values ​​in which errors occurred.

[0148] As shown in table 2100, errors may appear in the measurement results of data qubits 1 to 8. The precision F (Fidelity) is 0.778±0.004.

[0149] Next, an example of the accuracy of measurement results of data qubits in conventional methods will be described with reference to Figures 22 to 28. Specifically, an example of the accuracy of measurement results of data qubits will be shown for a case where a conventional computer generates logical Bell states of logical qubits 2210 and 2220 shown in Figure 22 and performs error correction.

[0150] 22 to 28 are explanatory diagrams showing an example of the accuracy of measurement results of data qubits. Specifically, Fig. 22 shows an example of an arrangement of multiple qubits in logical qubits 2210 and 2220 that are targets for generating logical Bell states.

[0151] As shown in FIG. 22 , logical qubit 2210 specifically includes four data qubits 1 to 4 arranged in a matrix of 2 rows and 2 columns. Logical qubit 2210 specifically includes an auxiliary qubit 9 for error correction Z measurement connected to data qubits 1 and 2. Logical qubit 2210 specifically includes auxiliary qubits 15 and 16 for error correction Z measurement connected to data qubits 3 and 4. Logical qubit 2210 specifically includes auxiliary qubit 10 for merging connected to data qubits 3 and 4. Logical qubit 2210 specifically includes auxiliary qubit 11 for error correction X measurement connected to data qubits 1 to 4.

[0152] As shown in FIG. 22, logical qubit 2220 specifically includes four data qubits 5 to 8 arranged in a matrix of 2 rows and 2 columns. Logical qubit 2220 specifically includes an auxiliary qubit 13 for error correction Z measurement connected to data qubits 7 and 8. Logical qubit 2220 specifically includes auxiliary qubits 17 and 18 for error correction Z measurement connected to data qubits 5 and 6. Logical qubit 2220 specifically includes an auxiliary qubit 12 for merging. Logical qubit 2220 specifically includes an auxiliary qubit 14 for error correction X measurement connected to data qubits 5 to 8. We now move on to the description of FIGS. 23 to 25.

[0153] 23 to 25 show quantum circuit 2300 in which a conventional computer generates logical Bell states of logical qubits 2210 and 2220 and performs error correction. In Fig. 23, each horizontal line in quantum circuit 2300 represents a time axis corresponding to one of the qubits.

[0154] A conventional computer performs multiple quantum operations on qubits 1 to 14 in stages. For example, two or more quantum operations belonging to the same stage are executed in parallel. The thick lines in FIGS. 23 to 25 represent quantum operations that are executed for error correction among the multiple quantum operations. The conventional computer acquires measurement results for data qubits 1 to 8 by performing multiple simulations in which multiple quantum operations are performed on qubits 1 to 14 in stages in accordance with quantum circuit 2300.

[0155] As mentioned above, quantum bits have the property that errors occur probabilistically. For example, at each stage of performing a quantum operation, a quantum bit has a probability p 1G , probability p 2G , or probability p M An error occurs at p. Furthermore, each time auxiliary qubits for merge processing are entangled, an error occurs in the qubit with probability p. Specifically, in quantum operations 2301 and 2302 in FIG. 23, an error occurs in the qubit with probability p.

[0156] First, let us move on to the explanation of Figure 26, where p = 0.0 and the probability p 1G , probability p 2G , and probability p M An example of the accuracy of the measurement results of data qubits 1 to 8 when a conventional computer performs a simulation 10,000 times without taking into account the above will be described.

[0157] 26 shows multiple values ​​that are measurement results of data qubits 1 to 8, and the frequency with which each value occurs as a measurement result of data qubits 1 to 8. The multiple values ​​are, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no errors occur.

[0158] As shown in table 2600, no errors appear in the measurement results of data qubits 1 to 8, and the precision F (Fidelity) is 1.000±0.000.

[0159] Next, let us move on to the explanation of Figure 27, where p = 0.1 and the probability p 1G , probability p 2G , and probability p M An example of the accuracy of the measurement results of data qubits 1 to 8 when a conventional computer performs a simulation 10,000 times without taking into account the above will be described.

[0160] 27 shows multiple values ​​that may be measured for data qubits 1 through 8, and the frequency with which each value occurs as a measurement result for data qubits 1 through 8. The multiple values ​​include, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no errors occur.

[0161] The multiple values ​​include, for example, 00100011, 11011100, 11101111, 00010000, 11100000, 00011111, 11100011, 11101100, 00011100, and 00010011. 00100011, 11011100, 11101111, 00010000, 11100000, 00011111, 11100011, 11101100, 00011100, and 00010011 are values ​​in which errors occurred.

[0162] As shown in table 2700, errors may appear in the measurement results of data qubits 1 to 8. The precision F (Fidelity) is 0.925±0.002.

[0163] Next, let us move on to the explanation of Figure 28, where p = 0.1 and the probability p 1G , probability p 2G , and probability p M Taking this into consideration, an example of the accuracy of the measurement results of data qubits 1 to 8 when a conventional computer performs a simulation 10,000 times will be described.

[0164] 28 shows multiple values ​​that may be measured for data qubits 1 through 8, and the frequency with which each value occurs as a measurement result for data qubits 1 through 8. The multiple values ​​include, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no errors occur.

[0165] The multiple values ​​include, for example, 00100011, 00101100, 11101111, 00011111, 11100000, 00010000, 11100011, 00010011, 11101100, and 00011100. 00100011, 00101100, 11101111, 00011111, 11100000, 00010000, 11100011, 00010011, 11101100, and 00011100 are values ​​in which errors occurred.

[0166] As shown in table 2800, errors may appear in the measurement results of data qubits 1 to 8. The precision F (Fidelity) is 0.670±0.005.

[0167] 17 to 21, the information processing device 100 can reduce the number of pairs of auxiliary qubits that are directly entangled, and can reduce the number of quantum operations that entangle the auxiliary qubits. Therefore, the information processing device 100 can reduce the number of times that an error can occur in a qubit with probability p. The information processing device 100 can easily prevent errors from occurring in the measurement results of data qubits 1 to 8 due to quantum operations that entangle the auxiliary qubits.

[0168] Furthermore, the information processing device 100 can reduce split processing, generate logical Bell states of the logical qubits 410 and 420, and perform error correction, thereby reducing processing time. Therefore, the information processing device 100 can reduce the number of stages in which quantum operations are performed. The information processing device 100 assigns a probability p 1G , probability p 2G , or probability p MThe information processing device 100 can reduce the number of times an error can occur in the measurement results of data qubits 1 to 8 due to the length of processing time. The information processing device 100 can reduce the number of gates forming the quantum circuit. The information processing device 100 can easily avoid the occurrence of error propagation.

[0169] 22 to 28, in the conventional method, the number of pairs of ancillary qubits that are directly entangled is 2. For this reason, in the conventional method, it is difficult to prevent errors from occurring in the measurement results of data qubits 1 to 8 due to quantum operations that entangle ancillary qubits.

[0170] Furthermore, conventional methods have the problem of increasing processing time because error correction is performed after generating the logical Bell states of logical qubits 410 and 420. For this reason, conventional methods have difficulty in preventing errors from occurring in the measurement results of data qubits 1 to 8 due to the long processing time.

[0171] In this way, compared to conventional techniques, information processing device 100 can more easily avoid situations in which errors occur in the measurement results of data qubits 1 to 8. As shown in Tables 1900, 2000, 2100 and Tables 2600, 2700, 2800, information processing device 100 can improve precision F (Fidelity) compared to conventional techniques.

[0172] In the above, the case where the information processing device 100 generates logical Bell states of two logical qubits each including four data qubits arranged in a matrix of 2 rows and 2 columns has been described, but the present invention is not limited to this. For example, the information processing device 100 may generate logical Bell states of N data qubits arranged in a matrix of N rows and N columns. 2 In some cases, it may be necessary to generate logical Bell states of two logical qubits each containing a data qubit.

[0173] Next, an example of generating logical Bell states of logical qubits 2910 and 2920, each of which includes nine data qubits arranged in a matrix of three rows and three columns, will be described with reference to FIGS.

[0174] Figures 29 and 30 are explanatory diagrams showing an example of generating logical Bell states for logical qubits 2910 and 2920. Specifically, Figure 29 shows an example of an arrangement of multiple qubits in logical qubits 2910 and 2920 for which logical Bell states are to be generated.

[0175] As shown in FIG. 29 , logical qubit 2910 exists, for example, at node A. Logical qubit 2910 specifically includes nine data qubits 1 to 9 arranged in a matrix of 3 rows and 3 columns. Logical qubit 2910 specifically includes an auxiliary qubit 19 for error correction Z measurement connected to data qubits 2, 3, 5, and 6. Logical qubit 2910 specifically includes an auxiliary qubit 20 for error correction Z measurement connected to data qubits 4, 5, 7, and 8. Logical qubit 2910 specifically includes an auxiliary qubit 21 for error correction Z measurement connected to data qubits 1 and 2.

[0176] Logical qubit 2910 specifically includes an auxiliary qubit 22 for error correction Z measurement and merging, connected to data qubits 8 and 9. Logical qubit 2910 specifically includes an auxiliary qubit 27 for error correction X measurement, connected to data qubits 1, 2, 4, and 5. Logical qubit 2910 specifically includes an auxiliary qubit 28 for error correction X measurement, connected to data qubits 5, 6, 8, and 9. Logical qubit 2910 specifically includes an auxiliary qubit 29 for error correction X measurement, connected to data qubits 4 and 7. Logical qubit 2910 specifically includes an auxiliary qubit 30 for error correction X measurement, connected to data qubits 3 and 6.

[0177] Logical qubit 2910 specifically includes an ancillary qubit 35 for merging, which connects to data qubits 7 and 8. Logical qubit 2910 specifically includes an ancillary qubit 36 ​​for merging, which connects to ancillary qubits 22 and 35. In this way, the arrangement of multiple qubits in logical qubit 2910 is determined so as to minimize the number of pairs of ancillary qubits that directly entangle.

[0178] 29 , logical qubit 2920 exists, for example, at node B. Logical qubit 2920 specifically includes nine data qubits 10 to 18 arranged in a matrix of three rows and three columns. Logical qubit 2920 specifically includes an auxiliary qubit 24 for error correction Z measurement connected to data qubits 14, 15, 17, and 18. Logical qubit 2920 specifically includes an auxiliary qubit 23 for error correction Z measurement connected to data qubits 10, 11, 13, and 14. Logical qubit 2920 specifically includes an auxiliary qubit 21 for error correction Z measurement connected to data qubits 16 and 17.

[0179] Logical qubit 2920 specifically includes an auxiliary qubit 25 for error correction Z measurement and merging, connected to data qubits 11 and 12. Logical qubit 2920 specifically includes an auxiliary qubit 32 for error correction X measurement, connected to data qubits 13, 14, 16, and 17. Logical qubit 2920 specifically includes an auxiliary qubit 31 for error correction X measurement, connected to data qubits 11, 12, 14, and 15. Logical qubit 2920 specifically includes an auxiliary qubit 33 for error correction X measurement, connected to data qubits 10 and 13. Logical qubit 2920 specifically includes an auxiliary qubit 34 for error correction X measurement, connected to data qubits 15 and 18.

[0180] Logical qubit 2920 specifically includes an ancillary qubit 37 for merging, which is connected to data qubits 10 and 11. Logical qubit 2920 specifically includes an ancillary qubit 38 for merging, which is connected to ancillary qubits 25 and 37. In this way, the arrangement of multiple qubits in logical qubit 2920 is determined so as to minimize the number of pairs of ancillary qubits that are directly entangled. For example, in the example of FIG. 29 , the pair of ancillary qubits that are entangled is one of the pairs of ancillary qubits 36 and 38. Next, we move on to the description of FIG. 30 .

[0181] Figure 30 shows quantum circuit 3000 that generates logical Bell states of logical quantum bits 2910 and 2920. In Figure 30, each horizontal line in quantum circuit 3000 represents a time axis corresponding to one of the quantum bits. In the example of Figure 30, specifically, quantum bits 7 to 12, 22, 25, and 35 to 38 of logical quantum bits 2910 and 2920 are shown.

[0182] Quantum bits 22, 25, and 35-38 are each in state |0〉. Information processing device 100 executes quantum state transfer 3001, which sets quantum bits 36 and 38 to states |00〉+|11〉, respectively. This enables information processing device 100 to entangle quantum bits 36 and 38.

[0183] Information processing device 100 executes controlled NOT gate 3002 with quantum bit 36 ​​as the control bit and quantum bit 22 as the target bit. Information processing device 100 executes controlled NOT gate 3002 with quantum bit 38 as the control bit and quantum bit 25 as the target bit.

[0184] Information processing device 100 executes controlled NOT gate 3003 with quantum bit 36 ​​as the control bit and quantum bit 35 as the target bit. Information processing device 100 executes controlled NOT gate 3003 with quantum bit 38 as the control bit and quantum bit 37 as the target bit.

[0185] Information processing device 100 executes controlled NOT gate 3004 with quantum bit 35 as the control bit and quantum bit 7 as the target bit. Information processing device 100 executes controlled NOT gate 3004 with quantum bit 37 as the control bit and quantum bit 10 as the target bit.

[0186] Information processing device 100 executes controlled NOT gate 3005 with quantum bit 35 as the control bit and quantum bit 8 as the target bit. Information processing device 100 executes controlled NOT gate 3005 with quantum bit 37 as the control bit and quantum bit 11 as the target bit. Information processing device 100 executes controlled NOT gate 3005 with quantum bit 22 as the control bit and quantum bit 9 as the target bit. Information processing device 100 executes controlled NOT gate 3005 with quantum bit 25 as the control bit and quantum bit 12 as the target bit.

[0187] Information processing device 100 executes Hadamard gate 3006 on quantum bits 22, 25, 35 to 38. Information processing device 100 executes logical Z gate 3007 if the product of the measurement results of quantum bits 22, 25, 35 to 38 is 1.

[0188] This allows information processing device 100 to generate the logical Bell states of logical qubits 2910 and 2920 without performing splitting. Specifically, information processing device 100 generates the logical Bell states of qubits 1 to 8 by dividing qubits 1 to 8 into logical Bell states |Φ L + 〉=|0 L A 〉|0 L B 〉+|1 L A 〉|1 L B >. Therefore, information processing device 100 can reduce the processing time required to generate the logical Bell states of logical qubits 2910 and 2920.

[0189] Next, the reason why the information processing device 100 does not need to perform split processing will be described with reference to Fig. 31 to Fig. 34. Specifically, first, the reason why split processing is performed using the conventional method will be described with reference to Fig. 31 and Fig. 32.

[0190] 31 and 32 are explanatory diagrams showing the reason for performing split processing. In the example of Fig. 31, for the sake of simplicity, a case will be described in which logical quantum bits 3110 and 3120 are merged with quantum bit 9 using a conventional method.

[0191] 31, logical qubit 3110 has an unentangled auxiliary qubit closer to logical qubit 3120 than data qubits 1 to 4. Similarly, logical qubit 3120 has an unentangled auxiliary qubit closer to logical qubit 3110 than data qubits 5 to 8. Thus, in logical qubits 3110 and 3120, an unentangled auxiliary qubit exists between data qubits 3 and 4 and data qubits 5 and 6.

[0192] The logical state of logical qubit 3110 is |0〉:|0 L A 〉=|0000〉+|1111〉. The logical state of logical qubit 3110 is |1〉:|1 L A 〉=|0011〉+|1100〉. The logical state of logical qubit 3120 is |0〉:|0 L B 〉=|0000〉+|1111〉. The logical state of logical qubit 3120 is |1〉:|1 L B >=|0011>+|1100>. The error-corrected state is a state expressed as the sum of the products of the above-mentioned logical states. For example, the error-corrected state is a state expressed by the following equation (1) or (2).

[0193]

number

[0194]

number

[0195] Next, we move on to the explanation of Fig. 32. Fig. 32 shows quantum circuit 3200 that generates logical Bell states of logical quantum bits 3110 and 3120. In Fig. 32, we will explain the changes in the quantum states of quantum bits 1 to 9 at each of the points (a) to (e) represented by the dotted lines in quantum circuit 3200.

[0196] At the time (a), the quantum states of quantum bits 1 to 9 are the quantum states expressed by the following formula (3). The first digit of the quantum state corresponds to quantum bit 9.

[0197]

number

[0198] At the time (b), the quantum states of quantum bits 1 to 9 are the quantum states expressed by the following formula (4).

[0199]

number

[0200] At time (c), the quantum states of quantum bits 1 to 9 are the quantum states expressed by the following formula (5).

[0201]

number

[0202] At time (d), the quantum states of quantum bits 1 to 9 are the quantum states expressed by the following formula (6).

[0203]

number

[0204] At time (e), the quantum states of quantum bits 1 to 9 are determined to be the quantum state expressed by the following formula (7) with a probability of 1 / 2 by observation.

[0205]

number

[0206] Thus, in the conventional method, the quantum states of qubits 1 to 8 in equation (7) above do not become error-corrected. In the conventional method, in logical qubits 3110 and 3120, there are unentangled auxiliary qubits between data qubits 3 and 4 and data qubits 5 and 6, so the quantum states of qubits 1 to 8 do not become error-corrected. Therefore, in the conventional method, split processing is performed. The conventional method has the problem of increasing the processing time required to generate the logical Bell states of logical qubits 3110 and 3120.

[0207] Next, the reason why the information processing device 100 does not need to perform split processing will be described with reference to FIGS.

[0208] 33 and 34 are explanatory diagrams showing why split processing is not necessary. In the example of Fig. 33, for simplicity of explanation, a case will be described in which information processing device 100 merges logical quantum bits 3310 and 3320 with quantum bit 9.

[0209] As shown in Figure 33, for logical quantum bit 3310, there are no unentangled auxiliary quantum bits closer to logical quantum bit 3320 than to data quantum bits 1 to 4. Similarly, for logical quantum bit 3320, there are no unentangled auxiliary quantum bits closer to logical quantum bit 3310 than to data quantum bits 5 to 8. Thus, for logical quantum bits 3310 and 3320, there are no unentangled auxiliary quantum bits between data quantum bits 3 and 4 and data quantum bits 5 and 6. Next, we move on to the description of Figure 34.

[0210] Figure 34 shows quantum circuit 3400 that generates logical Bell states of logical quantum bits 3310 and 3320. In Figure 34, the changes in the quantum states of quantum bits 1 to 9 at each of the points (a) to (e) indicated by the dotted lines in quantum circuit 3400 will be described.

[0211] At the time (a), the quantum states of quantum bits 1 to 9 are the quantum states expressed by the following formula (8). The first digit of the quantum state corresponds to quantum bit 9.

[0212]

number

[0213] At the time (b), the quantum states of quantum bits 1 to 9 are the quantum states expressed by the following formula (9).

[0214]

number

[0215] At time (c), the quantum states of quantum bits 1 to 9 are the quantum states expressed by the following formula (10).

[0216]

number

[0217] At the time (d), the quantum states of quantum bits 1 to 9 are the quantum states expressed by the following formula (11).

[0218]

number

[0219] At time (e), the quantum states of quantum bits 1 to 9 are determined to be the quantum state expressed by the following formula (12) with a probability of 1 / 2 by observation.

[0220]

number

[0221] In this way, information processing device 100 can make the quantum states of qubits 1 to 8 in equation (12) error-corrected. Information processing device 100 can entangle all auxiliary qubits between data qubits 3 and 4 and data qubits 5 and 6, making the quantum states of qubits 1 to 8 error-corrected. Therefore, information processing device 100 can avoid performing split processing. Information processing device 100 can reduce the processing time required to generate the logical Bell states of logical qubits 3310 and 3320.

[0222] As described above, according to information processing device 100, it is possible to generate a logical Bell state of two logical quantum bits by entangling all of the auxiliary quantum bits between the two logical quantum bits without using any data quantum bits. This allows information processing device 100 to avoid performing a split process, thereby reducing the processing time required to generate the logical Bell state of the two logical quantum bits.

[0223] According to the information processing device 100, when generating logical Bell states of two logical quantum bits, error correction of the data quantum bits can be performed using auxiliary quantum bits for error correction among the multiple quantum bits in each logical quantum bit. This allows the information processing device 100 to perform error correction while generating the logical Bell states of the two logical quantum bits, thereby reducing the time required to start error correction. The information processing device 100 can reduce the processing time required to complete generation of the logical Bell states of the two logical quantum bits and to complete error correction. The information processing device 100 can easily avoid an increase in the error rate that accompanies an increase in processing time.

[0224] The information processing device 100 can generate a logical Bell state of two logical qubits in which multiple qubits are arranged so as to minimize the number of entangled auxiliary qubits. The information processing device 100 can reduce the number of entanglements and can reduce the processing time required to generate the logical Bell state of two logical qubits. The information processing device 100 can easily avoid an increase in the error rate associated with entanglement.

[0225] According to information processing device 100, it is possible to generate a logical Bell state of two logical qubits in which one or more ancillary qubits serving as nodes are arranged in a binary tree shape with two or more data qubits as leaves and one directly entangled ancillary qubit as the root. This allows information processing device 100 to generate a logical Bell state of two logical qubits in which the number of entangled ancillary qubits is minimized.

[0226] Information processing device 100 can generate a logical Bell state of two logical qubits in which four data qubits are arranged in a two-row, two-column matrix and one auxiliary qubit is arranged directly connected to the two data qubits. This allows information processing device 100 to generate a logical Bell state of two logical qubits in which the number of entangled auxiliary qubits is minimized.

[0227] The information processing device 100 can generate a logical Bell state of two logical qubits in which nine data qubits are arranged in a matrix of three rows and three columns. Each logical qubit has three data qubits arranged on the side connected to the other logical qubit as leaves, and three ancillary qubits as nodes arranged in a binary tree with one ancillary qubit that is directly entangled as the root. This allows the information processing device 100 to generate a logical Bell state of two logical qubits that minimizes the number of ancillary qubits to be entangled.

[0228] The information processing method described in this embodiment can be realized by executing a prepared program on a computer such as a PC or a workstation. The information processing program described in this embodiment is recorded on a computer-readable recording medium and executed by being read from the recording medium by the computer. The recording medium may be a hard disk, a flexible disk, a CD (Compact Disc)-ROM, an MO (Magneto Optical disc), a DVD (Digital Versatile Disc), or the like. The information processing program described in this embodiment may also be distributed via a network such as the Internet.

[0229] The following additional notes are provided regarding the above-described embodiment.

[0230] (Supplementary Note 1) In an arrangement of a plurality of qubits including a plurality of data qubits and a plurality of auxiliary qubits in each of two logical qubits to be connected, all of the auxiliary qubits arranged on the side of the logical qubit that is connected to the other logical qubit relative to the data qubit are entangled between the two logical qubits without passing through the data qubit, thereby generating a logical Bell state of the two logical qubits. An information processing program that causes a computer to execute a process.

[0231] (Appendix 2) The generating process is 2. The information processing program of claim 1, wherein, when generating the logical Bell states of the two logical quantum bits, an auxiliary quantum bit for error correction is used among the plurality of quantum bits in each of the logical quantum bits to perform error correction on the data quantum bit.

[0232] (Appendix 3) The information processing program according to appendix 1 or 2, wherein each of the logical quantum bits is a logical quantum bit in which multiple quantum bits including multiple data quantum bits and multiple auxiliary quantum bits are arranged so that the number of entangled auxiliary quantum bits is minimized.

[0233] (Appendix 4) The information processing program according to appendix 3, wherein each of the logical quantum bits is a logical quantum bit in which two or more of the data quantum bits arranged on the side connecting to the other logical quantum bit are arranged as leaves, and one or more of the auxiliary quantum bits arranged as nodes are arranged in a binary tree shape with one of the auxiliary quantum bits directly entangled as the root.

[0234] (Appendix 5) The information processing program according to appendix 4, wherein each of the logical quantum bits is a logical quantum bit in which four of the data quantum bits are arranged in a matrix of two rows and two columns, and one of the auxiliary quantum bits is directly connected to two of the data quantum bits that are arranged on the side connecting to the other logical quantum bit.

[0235] (Supplementary Note 6) The information processing program according to Supplementary Note 4, wherein each of the logical quantum bits is a logical quantum bit in which nine of the data quantum bits are arranged in a matrix of three rows and three columns, and three of the data quantum bits arranged on the side connecting to the other logical quantum bit are arranged as leaves, and three of the auxiliary quantum bits are arranged as nodes in a binary tree shape with one of the auxiliary quantum bits directly entangled as the root.

[0236] (Supplementary Note 7) In an arrangement of a plurality of qubits including a plurality of data qubits and a plurality of auxiliary qubits in each of two logical qubits to be connected, all of the auxiliary qubits arranged on the side of the logical qubit that is connected to the other logical qubit relative to the data qubit are entangled between the two logical qubits without passing through the data qubit, thereby generating a logical Bell state of the two logical qubits. An information processing method characterized in that the processing is executed by a computer.

[0237] (Supplementary Note 8) In an arrangement of a plurality of qubits including a plurality of data qubits and a plurality of auxiliary qubits in each of two logical qubits to be connected, all of the auxiliary qubits arranged on the side of the logical qubit that is connected to the other logical qubit relative to the data qubit are entangled between the two logical qubits without passing through the data qubit, thereby generating a logical Bell state of the two logical qubits. An information processing device comprising a control unit. [Explanation of symbols]

[0238] 1~8, 10~18, 22, 25, 35~38 qubits 100 Information processing device 110 First logical qubit 120 Second logical qubit 200 Bus 201 CPU 202 memory 203 Network I / F 204 Recording Media I / F 205 Recording Media 206 Arithmetic unit I / F 207 Quantum computing device 210 Network 300 Storage section 301 Acquisition Department 302 Arithmetic section 303 Operation section 304 Output section 410,420,1110,1120,1710,1720,2210,2220,2910,2920,3110,3120,3310,3320 logical qubits 500,800,1200,1800,2300,3000,3200,3400 quantum circuit 501,802,1201,3001 Quantum State Transfer 502, 503, 505, 506, 803-807, 810-812, 1202, 1206, 1207, 1303, 1304, 1306, 1308, 3002-3005 Controlled NOT Gates 504,507,801,808,813,1203,1302,1309,3006 Hadamard Gate 508,809,814,1204,1301,1307,1310 Z measurement 509,1205 Z-Gate 3007 Logic Z Gate 1801,2301,2302 quantum computing 1900,2000,2100,2600,2700,2800 Table

Claims

1. In an arrangement of a plurality of qubits including a plurality of data qubits and a plurality of auxiliary qubits in each of two logical qubits to be connected, all of the auxiliary qubits arranged on the side of the logical qubit that is connected to the other logical qubit relative to the data qubit are entangled between the two logical qubits without passing through the data qubit, thereby generating a logical Bell state of the two logical qubits. An information processing program that causes a computer to execute a process.

2. The generating process includes:

2. The information processing program according to claim 1, wherein, when generating the logical Bell states of the two logical quantum bits, an auxiliary quantum bit for error correction is used among the plurality of quantum bits in each of the logical quantum bits to perform error correction on the data quantum bit.

3. 3. The information processing program according to claim 1, wherein each of the logical quantum bits is a logical quantum bit in which a plurality of quantum bits including a plurality of data quantum bits and a plurality of auxiliary quantum bits are arranged so that the number of the auxiliary quantum bits to be entangled is minimized.

4. 4. The information processing program according to claim 3, wherein each of the logical quantum bits is a logical quantum bit in which two or more of the data quantum bits arranged on the side connected to the other logical quantum bit are leaves, and one or more of the ancillary quantum bits are arranged as nodes in a binary tree shape with one of the ancillary quantum bits directly entangled as a root.

5. In an arrangement of a plurality of qubits including a plurality of data qubits and a plurality of auxiliary qubits in each of two logical qubits to be connected, all of the auxiliary qubits arranged on the side of the logical qubit that is connected to the other logical qubit relative to the data qubit are entangled between the two logical qubits without passing through the data qubit, thereby generating a logical Bell state of the two logical qubits. An information processing method characterized in that the processing is executed by a computer.

6. In an arrangement of a plurality of qubits including a plurality of data qubits and a plurality of auxiliary qubits in each of two logical qubits to be connected, all of the auxiliary qubits arranged on the side of the logical qubit that is connected to the other logical qubit relative to the data qubit are entangled between the two logical qubits without passing through the data qubit, thereby generating a logical Bell state of the two logical qubits. An information processing device comprising a control unit.

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