Semiconductor drive device and electric power conversion device

Abstract

A semiconductor drive device (10) comprises: a gate drive unit (B10) for applying a voltage to a gate terminal (G) of a semiconductor switching element (M1) on the basis of an on / off command signal; and a voltage clamp unit (20) that has a voltage drop generation circuit (21) between the output of the gate drive unit (B10) and the gate terminal (G), wherein the voltage clamp unit (20) has a control terminal (K3) for adjusting the voltage drop degree by the voltage drop generation circuit (21), and comprises a first capacitive element (22) that is connected between the control terminal (K3) and one point on the path from the output of the gate drive unit (B10) to the voltage clamp unit (20), a second capacitive element (23) that is connected between the control terminal (K3) and a reference potential (VC0), and a first electric current limiting element (24) that is connected in parallel with the first capacitive element (22) or the second capacitive element (23).

Description

Semiconductor drive device and power conversion device

[0001] The present disclosure relates to a semiconductor driving device and a power conversion device.

[0002] In a power conversion device, such as an inverter device, which includes a power conversion unit and a control unit that controls the power conversion unit, power conversion is achieved by the on / off operation of a semiconductor switching element in the power conversion unit. Such devices are used in a variety of power conversion devices, including those for electric vehicles such as hybrid vehicles, plug-in hybrid vehicles, electric vehicles, and fuel cell vehicles, as well as for electric railways, industrial applications, and consumer applications. Examples of semiconductor switching elements include voltage-driven semiconductor switching elements, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate-Bipolar-Transistors). Controlling such semiconductor switching elements requires a semiconductor driver. Generally, a driver for a voltage-driven semiconductor element controls the conduction state of the semiconductor switching element by applying a voltage between the gate terminal and a control reference terminal of the semiconductor switching element.

[0003] The semiconductor drive device is equipped with a short-circuit detection unit that immediately detects a short circuit when a semiconductor switching element enters an overcurrent state due to a short circuit in the current path of the power conversion unit, and a short-circuit protection unit that safely cuts off the conduction of the semiconductor switching element to protect it from a short circuit. This short-circuit protection function is an important function related to the system reliability of the power conversion device. Generally, it takes a few microseconds to 5 microseconds for the semiconductor drive device to detect a short circuit and provide protection, but the semiconductor switching element is designed to avoid destruction during that period due to its short-circuit tolerance. Generally, the short-circuit tolerance of a semiconductor switching element is about 10 microseconds.

[0004] On the other hand, due to the recent trend toward lower loss in semiconductor switching elements, there is a trend toward reducing short-circuit tolerance, which is in a trade-off relationship with low loss. Furthermore, the use of wide-bandgap semiconductors formed from semiconductor materials with wider bandgaps than silicon (Si), such as silicon carbide (SiC) and gallium nitride (GaN), is increasing, and short-circuit tolerance can sometimes be reduced to a few microseconds or less. Such a decrease in short-circuit tolerance must be compensated for by operating the short-circuit protection function of the semiconductor driver at high speed. However, there are physical limits to reducing the time required to distinguish between normal turn-on operation and turn-on operation during a short circuit, and the time required to safely interrupt short-circuit current.

[0005] One approach to this problem is to add a gate voltage clamp function to a semiconductor switching device that suppresses the transient gate voltage during turn-on operation below the gate voltage during steady-state on-state, thereby achieving both low loss and short-circuit resistance. This method aims to both suppress short-circuit current when a short circuit occurs during turn-on and reduce conduction loss during steady-state on-state. This method reduces the resistance value of the gate resistor to adjust the gate charging time constant by reducing the transient gate voltage during turn-on operation, thereby preventing an increase in switching loss. Furthermore, by increasing the gate voltage after a time when short-circuit protection operation is expected to be completed if turn-on occurs during a short circuit, conduction loss can be reduced while preventing short-circuit breakdown (see, for example, Patent Documents 1 and 2).

[0006] JP 2009-71956 A Japanese Patent No. 5392287 A

[0007] However, in the technology disclosed in Patent Document 1, the gate is driven by a low power supply voltage when turned on, and after turning on, a high gate voltage is achieved during steady-state on state by a high power supply voltage, which poses the problem of requiring multiple power supplies, resulting in a large circuit size and high costs.

[0008] In the method disclosed in Patent Document 2, which realizes voltage clamping by providing a discharge path between the gate terminal and the control reference terminal, current flows through the gate charge path and the branched discharge path, which increases the gate drive power, resulting in an increase in the size of the power supply and an increase in cost.

[0009] The present disclosure discloses a technology for solving the above-mentioned problems, and aims to provide a semiconductor driving device that can realize, at low cost, a gate voltage clamp function that suppresses the transient gate voltage during turn-on operation to a level lower than the gate voltage during steady-state on-state, and a power conversion device using the same.

[0010] The semiconductor driving device disclosed herein applies a voltage to a gate terminal of a semiconductor switching element through which a current flows from a first main terminal to a second main terminal, thereby driving the semiconductor switching element to be turned on and off, and includes: a gate driving unit that applies a voltage to the gate terminal based on an on / off command signal; and a voltage clamping unit having a voltage drop generation circuit that drops the voltage between the output of the gate driving unit and the gate terminal, wherein the voltage clamping unit has a control terminal through which the voltage drop generation circuit adjusts the degree of voltage drop, and includes: a first capacitance element connected between the control terminal and a point on a path from the output of the gate driving unit to the voltage clamping unit; a second capacitance element connected between the control terminal and a reference potential; and a first current limiting element connected in parallel with the first capacitance element or the second capacitance element.

[0011] According to the present disclosure, a voltage clamp unit for suppressing the transient gate voltage during turn-on operation to a value lower than the gate voltage during steady-state on-state has been realized with a simple configuration, making it possible to provide a semiconductor driving device that can suppress the gate voltage during turn-on operation at low cost, and a power conversion device using the same.

[0012] 2A is a block diagram showing the configuration of a semiconductor driving device according to a first embodiment. FIG. 2B is a schematic diagram showing the voltage and current waveforms of a semiconductor switching element in the semiconductor driving device according to the first embodiment, where FIG. 2A shows the waveforms during a normal turn-on operation, and FIG. 2B shows the waveforms during a turn-on operation when a short-circuit path is formed. FIG. 2B is a diagram showing a specific circuit configuration of the semiconductor driving device according to the first embodiment. FIG. 2C is a block diagram showing the configuration of a modified example of the semiconductor driving device according to the first embodiment. FIG. 2D is a diagram showing the specific circuit configuration of a modified example of the semiconductor driving device according to the first embodiment. FIG. 2E is a block diagram showing the configuration of a semiconductor driving device according to the second embodiment. FIG. 2F is a block diagram showing the configuration of a semiconductor driving device according to the third embodiment. FIG. 2G is a schematic diagram showing the signals of a short-circuit detection unit and the voltage and current waveforms of a semiconductor switching element in the semiconductor driving device according to the third embodiment. FIG. 2H is a block diagram showing the configuration of a semiconductor driving device according to the fourth embodiment. FIG. 2H is a block diagram showing the configuration of a semiconductor driving device according to the fifth embodiment. FIG. 2I is a block diagram showing the configuration of a semiconductor driving device according to the sixth embodiment. FIG. 2I is a block diagram showing the configuration of a semiconductor driving device according to the seventh embodiment. FIG. 2I is a schematic diagram showing the signals of a short-circuit detection unit and the voltage and current waveforms of a semiconductor switching element in a normal state in the semiconductor driving device according to the seventh embodiment. FIG. 2I is a schematic diagram showing the signals of a short-circuit detection unit and the voltage and current waveforms of a semiconductor switching element in a short-circuit state in the semiconductor driving device according to the seventh embodiment. Fig. 10 is a block diagram showing the configuration of a power conversion device according to embodiment 8. Fig. 11 is a block diagram showing the configuration of a power conversion device according to embodiment 9. Fig. 12 is a block diagram showing the configuration of a power conversion device according to embodiment 10. Fig. 13 is a diagram showing an example of the hardware configuration of a short circuit detection unit according to embodiments 3 to 7.

[0013] The present embodiment will be described below with reference to the drawings, in which the same reference numerals indicate the same or corresponding parts.

[0014] First Embodiment. A semiconductor driving device according to the first embodiment will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a semiconductor driving device 10A according to the first embodiment. In FIG. 1, a MOSFET is shown as an example of the semiconductor switching element M1 to be driven by the semiconductor driving device 10A. The semiconductor driving device 10A controls the conductive and non-conductive states of a current flowing from the drain terminal D, which is the first main terminal, of the semiconductor switching element M1 to the source terminal Sm, which is the second main terminal, by applying a gate voltage Vgs between the gate terminal G and a control reference terminal S (hereinafter referred to as the control source terminal S).

[0015] <Configuration of Semiconductor Driver 10A> In order to drive the gate of semiconductor switching element M1, semiconductor driver 10A is provided with a power supply PS consisting of a positive power supply having a potential VP and a negative power supply having a potential VN, and generates a positive potential to be applied during a period in which the gate is turned on and a negative potential to be applied during a period in which the gate is turned off on a control reference potential FG of control source terminal S. In this embodiment, a negative power supply is provided to prevent erroneous firing of the gate, which is a concern in large current applications, but a configuration without a negative power supply is also possible depending on the current capacity of semiconductor switching element M1.

[0016] Furthermore, the semiconductor driver 10A receives an on / off command signal SGD from a higher-level logic unit such as a microcomputer, which signals whether the MOSFET is conductive or non-conductive, and applies a preset voltage from the gate driver B10 to the gate of the semiconductor switching element M1 to perform on / off control. The gate driver B10 is configured as a buffer circuit, which amplifies the current and generates a predetermined voltage. In this example, the buffer circuit drives the positive side with a P-type MOSFET and the negative side with an N-type MOSFET, with the drain terminals of each MOSFET separated, but the configuration may also be such that an NPN transistor and a PNP transistor are used, respectively.

[0017] In this example, the semiconductor switching element M1 is turned on and off using a constant voltage drive via an on-gate resistor R10 and an off-gate resistor R11 to adjust the gate current in order to adjust its switching characteristics, but this embodiment is not limited to this and can be applied to various drive methods such as constant current drive or lamp drive that controls dVgs / dt to a constant value.

[0018] Since the on / off command signal SGD needs to be transmitted on a different potential from that of a higher-level logic unit such as a microcomputer that is the source of the signal, an insulating communication element such as a photocoupler, an optical conversion module, or an insulating gate driver IC (Integrated Circuit) is provided between the higher-level logic unit and the semiconductor drive device 10A, but is not shown here for the sake of simplicity. When a photocoupler or gate driver IC is used as the insulating communication element, it is common for the gate drive unit B10 to be built into it.

[0019] <Configuration of Voltage Clamping Unit 20> A feature of the semiconductor driving device 10A according to the first embodiment is that a voltage clamping unit 20 is provided in series between the gate driving unit B10 and the semiconductor switching element M1, the output voltage of the gate driving unit B10 is received at terminal K1 of a voltage drop generating circuit 21, and the voltage dropped by the voltage drop generating circuit 21 is applied to the gate terminal G via terminal K2. The voltage drop generating circuit 21 has a control terminal K3 for adjusting the degree of voltage drop, a first capacitance element 22 between the control terminal K3 and a point on the path from the gate driving unit B10 to the voltage clamping unit 20, a second capacitance element 23 between the control terminal K3 and the negative power supply potential VN, and a first current limiting element 24 connected in parallel with the first capacitance element 22.

[0020] In this example, the first capacitance element 22 is provided between the control terminal K3 and the output of the gate driver B10. The first capacitance element 22 and the second capacitance element 23 are capacitors, with the capacitance of the first capacitance element 22 being C1 and the capacitance of the second capacitance element 23 being C2. The first current limiting element 24 is a resistor, with its resistance being R1. In this embodiment, the reference potential VC0 connected to the second capacitance element 23 is the negative power supply potential VN of the semiconductor switching element M1. However, it may be the control reference potential FG or another constant potential generated based on the control reference potential FG or the control reference potential FG. The negative power supply potential VN and the positive power supply potential VP in FIG. 3 are gate drive power supplies generated based on the control reference potential FG, which is the potential of the control source terminal S, and are the voltages applied to the gate terminal G when turning off and on the semiconductor switching element M1, respectively.

[0021] <Operation of Voltage Clamp Unit 20> Next, the operating principle of the voltage clamp unit 20 will be described. When the gate driver B10 transitions from the OFF state to the ON state based on the ON / OFF command signal SGD, the impedance of the capacitor is transiently smaller than the resistance, so the potential VK3 of the control terminal K3 is determined by the capacitance ratio of the first capacitance element 22 to the second capacitance element 23, and satisfies the relationship C1(VP-VK3)=C2(VK3-VN). Here, if this capacitance ratio γ is defined as γ=C1 / C2, the potential VK3 of the control terminal K3 can be expressed as VK3=(γVP+VN) / (γ+1). If the potential VK3 of the control terminal K3 is greater than the gate threshold voltage Vth of the semiconductor switching element M1, the following relationship is obtained: γ>(Vth-VN) / (VP-Vth) (1). As described above, in the first embodiment, the reference potential VC0 connected to the second capacitance element 23 is set to the negative power supply potential VN of the semiconductor switching element M1, so VC0=VN, and equation (1) can be expressed as the following equation (2): γ>(Vth-VC0) / (VP-Vth) (2) It is obvious that the potential VK3 of the control terminal K3 is a potential less than the positive power supply potential VP.

[0022] The condition VK3>Vth, i.e., the condition that the potential VK3 of the control terminal K3 is greater than the gate threshold voltage Vth of the semiconductor switching element M1, means that the transient voltage clamp level of the voltage clamp unit 20 is greater than the gate threshold voltage Vth, and is the minimum required condition for realizing switching operation in applications with small load currents. On the other hand, when the load current is approximately the same as the rated current of the semiconductor switching element M1, a necessary condition for realizing switching operation with this load current is that the potential VK3 of the control terminal K3 is greater than the gate mirror voltage Vm that appears in the gate voltage waveform during the period when the drain-source voltage (drain voltage Vds) drops. In other words, the relationship expressed by the following equation (3) holds: γ>(Vm-VC0) / (VP-Vm) (3)

[0023] As described above, the capacitance ratio γ of the first capacitance element 22 to the second capacitance element 23 can be set to a small value within a range that satisfies at least formula (2), thereby effectively reducing the short-circuit current that occurs with the turn-on operation during a main circuit abnormality. Furthermore, in a system in which the load current is as large as the rated current of the elements, the capacitance ratio γ of the first capacitance element 22 to the second capacitance element 23 can be set to a small value within a range that satisfies formula (3).

[0024] After the potential VK3 of the control terminal K3 reaches a voltage determined by the γ of the capacitors of the first capacitance element 22 and the second capacitance element 23, the potential VK3 of the control terminal K3 gradually rises to the positive power supply potential VP due to the action of the first current limiting element 24. This makes it possible to reduce the conduction loss during steady-state on of the semiconductor switching element M1 to the same level as when the gate voltage is not clamped. The time constant for the rise in the potential VK3 of the control terminal K3 is determined by the combined capacitance of the capacitance C1 of the first capacitance element 22 and the capacitance C2 of the second capacitance element 23 and the resistance R1 of the first current limiting element 24. This time constant is sufficiently longer than the time required for the drain voltage Vds, which is the main voltage, and the drain current Id, which is the main current, of the semiconductor switching element M1 to transition so that the clamp voltage can be maintained during the switching operation period, and is also set to be equal to or less than the short-circuit withstand capability of the semiconductor switching element M1 to minimize an increase in conduction loss after turn-on.

[0025] <Effect of voltage clamp unit 20> Figure 2 is a schematic diagram of voltage and current waveforms of semiconductor switching element M1 in semiconductor drive device 10A according to embodiment 1. Figure 2A shows the waveforms during normal turn-on operation, and Figure 2B shows the waveforms during abnormal turn-on operation in which a short circuit path is formed. Note that the comparative example shows waveforms during turn-on operation in a semiconductor drive device that does not have a gate voltage clamp function.

[0026] 2A , the gate voltage clamp function of the voltage clamp unit 20 according to the first embodiment acts to reduce the gate drive voltage during the switching operation. That is, a potential that is lowered based on the potential VK3 of the control terminal K3, which is determined by the ratio γ between the capacitance C1 of the first capacitance element 22 and the capacitance C2 of the second capacitance element 23, is output to the terminal K2. The time constant for the gate voltage Vgs to rise from the gate mirror voltage Vm to the positive power supply potential VP after the switching operation is completed is set to be slower than that of the comparative example.

[0027] During the short circuit in FIG. 2B , the drain voltage Vds remains high due to the short circuit, and therefore, a mirror period does not occur in the gate voltage Vgs. Therefore, in the comparative example, the gate voltage Vgs rises to the positive power supply potential VP in a short period of time. As a result, the drain current Id increases rapidly and converges to a large saturation value corresponding to the gate voltage. On the other hand, in the semiconductor driver 10A according to the first embodiment, the voltage clamp unit 20 acts to reduce the gate drive voltage during the switching operation, as in the normal state, thereby gradualing the increase in the gate voltage Vgs. Therefore, the first embodiment can suppress the rapid increase in the drain current Id seen in the comparative example. This reduces short-circuit loss and relaxes the short-circuit protection delay specifications required for the semiconductor driver 10A. For example, if the semiconductor switching element M1 is made of a wide bandgap semiconductor with a strict short-circuit withstand capability of several hundred nanoseconds, conventionally, short circuits must be detected and protected within this short-circuit withstand time. This results in insufficient time for distinguishing between normal and abnormal conditions, increasing the risk of misdetecting normal switching as short-circuit switching. On the other hand, in the semiconductor driving device 10A according to the first embodiment, the time for short-circuit withstand can be extended according to the amount of reduction in the drain current Id, and therefore, the semiconductor switching element M1 can be protected while ensuring sufficient time for distinguishing between normal and abnormal states.

[0028] <Circuit Configuration Example 1 of Semiconductor Driver 10A> FIG. 3 shows a specific circuit configuration example 1 of the semiconductor driver 10A according to the first embodiment. The specific circuit configuration of the voltage drop generator circuit 21 in FIG. 1 is shown as a voltage drop generator circuit 21A. In FIG. 3, the voltage drop generator circuit 21A of the voltage clamp unit 20A is configured with an NPN transistor Q20A, which is a control switching element. In FIG. 3, the potential of a control terminal K3 connected to the base of the NPN transistor Q20A controls the current flowing from the collector to the emitter, i.e., the current flowing from the gate driver B10 to the gate terminal G. A protection diode D20A is provided between the base and emitter of the NPN transistor Q20A to prevent a reverse voltage exceeding the breakdown voltage from being applied when the semiconductor switching element M1 is turned off. In the case of the NPN transistor Q20A, even if its base potential rises to the positive power supply potential VP, the emitter potential remains lower than this potential by a base threshold voltage (e.g., approximately 0.7 V). For this reason, in this example, a second current limiting element R21 is provided to increase the potential of the gate G to the positive power supply potential VP. The second current limiting element R21 is a resistor here.

[0029] In the above example of the voltage drop generating circuit 21A, an NPN transistor Q20A is used as a control switching element, but this is not limiting. An N-type MOSFET may be used instead of the NPN transistor Q20A. Alternatively, a voltage regulator IC or the like may be used.

[0030] <Modification of semiconductor driving device 10A> Fig. 4 is a block diagram showing a modification of the semiconductor driving device 10A according to embodiment 1. Fig. 4 differs from Fig. 1 in that the first current limiting element 24 is provided in parallel with the second capacitance element 23.

[0031] <Circuit Configuration Example 2 of Semiconductor Driver 10A> FIG. 5 illustrates a specific circuit configuration example 2 of the semiconductor driver 10A according to the first embodiment, specifically a circuit configuration example of a variation of the semiconductor driver 10A according to the first embodiment of FIG. 4. A specific circuit configuration of the voltage drop generator circuit 21 in FIG. 4 is shown as a voltage drop generator circuit 21B. In FIG. 5, the voltage drop generator circuit 21B of the voltage clamp unit 20B is configured with a PNP transistor Q20B, which is a control switching element. In FIG. 5, a protection diode D20B is also provided between the base and emitter of the PNP transistor Q20B. When configured with the PNP transistor Q20B, the potential of the gate G can be raised to the positive power supply potential VP without using the second current limiting element R21 as in FIG. 3. However, if necessary, measures to prevent short-circuit current from flowing between the OFF-side switching element of the gate driver B10 and the PNP transistor Q20B, such as providing a dead time, may be required. The remaining configuration is similar to that of FIG. 3, and therefore detailed description thereof will be omitted.

[0032] In the above example of the voltage drop generating circuit 21B, a PNP transistor Q20B is used as a control switching element, but this is not limiting. A P-type MOSFET may be used instead of the PNP transistor Q20B. Furthermore, a voltage regulator IC or the like may be used, as in the case of configuration example 1 of FIG. 3 .

[0033] As described above, the semiconductor driver device of the first embodiment applies a voltage to the gate terminal of a semiconductor switching element through which a current flows from the drain terminal (first main terminal) to the source terminal (second main terminal), thereby driving the semiconductor switching element to turn on and off, the semiconductor driver device comprising: a gate driver that applies a voltage to the gate terminal based on an on / off command signal; and a voltage clamper having a voltage drop generator circuit that drops the voltage between the output of the gate driver and the gate terminal, the voltage clamper having a control terminal through which the voltage drop generator circuit adjusts the degree of voltage drop, a first capacitance element connected between a point on a path from the output of the gate driver to the voltage clamper and the control terminal, a second capacitance element connected between the control terminal and a reference potential, and a first current limiting element connected in parallel with the first capacitance element or the second capacitance element. This configuration realizes a voltage clamper that suppresses a transient gate voltage during a turn-on operation to be lower than a gate voltage during a steady-state on operation with a simple structure, a low-cost, low-loss configuration, and high-precision clamping of the gate voltage. This makes it possible to achieve both low loss and short-circuit resistance in the semiconductor switching element to be driven.

[0034] In addition, the potential of the control terminal of the voltage drop generating circuit can be generated by the first capacitive element, the second capacitive element, and the first current limiting element, thereby achieving high response and high accuracy. Furthermore, since the voltage drop generating circuit is configured with a control switching element, the current flowing toward the gate terminal can be easily adjusted, and it is also possible to drive the gate with a large current for a semiconductor switching element with a large current capacity.

[0035] Second Embodiment A semiconductor driver according to a second embodiment will now be described with reference to the drawings. FIG. 6 is a block diagram showing the configuration of a semiconductor driver 10B according to the second embodiment. The difference from FIG. 1 of the first embodiment is that in FIG. 6, the ON-side output and the OFF-side output of the gate driver B10 are shared. This configuration makes it possible to use general-purpose components to reduce the number of pins in the buffer circuit.

[0036] When the ON-side output and OFF-side output of the gate driver B10 are shared in this manner, in order to independently adjust the turn-on and turn-off characteristics of the semiconductor switching element M1, a gate resistor R12 common to both ON and OFF and an OFF-only gate resistor R13 connected in series with a gate rectifier element D10 (diode) are used, as shown in FIG. 6 . The gate resistor R12 is connected between the output of the gate driver B10 and the voltage clamping unit 20, and the series combination of the gate rectifier element D10 and the OFF-only gate resistor R13 is connected between the output of the gate driver B10 and the gate terminal G of the semiconductor switching element M1. The other configurations are the same as those in the first embodiment, and therefore description thereof will be omitted. In the second embodiment, the voltage drop generating circuit 21 may be configured using a controlled switching element such as an NPN transistor or an N-type MOSFET, or may be configured using a voltage regulator IC, as described in FIG. 3 . Furthermore, although the second embodiment illustrates an example in which the gate resistor R12 is connected between the output of the gate driver B10 and the voltage clamping unit 20, the gate resistor R12 may also be connected between the voltage clamping unit 20 and the gate terminal G.

[0037] As described above, according to the second embodiment, the same effects as those of the first embodiment can be achieved. Furthermore, it is possible to simplify the gate driver. Furthermore, since a current path during off-state is provided between the gate driver and the gate terminal and backflow is prevented by the gate rectifier diode, it is possible to pass a large off-gate current to the gate driver, as in the first embodiment, without affecting the turn-on characteristics.

[0038] Third Embodiment A semiconductor driving device according to a third embodiment will now be described with reference to the drawings. FIG. 7 is a block diagram showing the configuration of a semiconductor driving device 10C according to the third embodiment. To the configuration of FIG. 6 of the second embodiment, a short circuit detection unit 30 that detects a short circuit based on the drain voltage Vds and a unit that changes the potential VK3 of the control terminal K3 based on the status signal SST that is an output signal from the short circuit detection unit 30 are added. The other configurations are the same as those of the second embodiment, and a description thereof will be omitted. Note that the subject here is a short circuit that occurs in a main circuit including the semiconductor switching element M1.

[0039] The method of detecting a short circuit based on the drain voltage Vds is widely known as a method of detecting a non-saturated state by an overcurrent (Desat method), and since this technique is used here, a description of the configuration of the short circuit detection unit 30 will be omitted. Furthermore, the method of determining a short circuit based on the drain voltage Vds may be a method of determining using the voltage level itself, or a method of determining using a differential value of the voltage.

[0040] The voltage adjustment circuit 31 is the component that changes the potential VK3 of the control terminal K3 in response to the status signal SST. The voltage adjustment circuit 31 is composed of a rectifier D11, a first voltage limiting element Dz10, and a third current limiting element R14, which are connected in series between the control terminal K3 and the short-circuit detection unit 30. The status signal SST, which is the output of the short-circuit detection unit 30, has a logical polarity that outputs a high (Hi) level of the potential VP of the positive power supply when no short circuit is detected and the device is healthy, and outputs a low (Lo) level of the potential of the control reference potential FG when a short circuit is detected. Therefore, when a short circuit is detected by the short-circuit detection unit 30, the status signal SST goes low (Lo), and the potential VK3 of the control terminal K3 is clamped to the breakdown voltage Vz of the Zener diode, which is the first voltage limiting element Dz10. However, strictly speaking, it is necessary to take into consideration the forward voltage of the reverse diode, which is the rectifier element D11 that blocks the high (Hi) level voltage of the status signal SST, and the voltage drop due to the resistive voltage division between the resistor that is the third current limiting element R14 for the purpose of limiting inrush current and the resistor that is the first current limiting element 24, but these values ​​are small.

[0041] 8 is a schematic diagram showing the status signal SST of the short-circuit detection unit 30 and the voltage and current waveforms of the semiconductor switching element M1 of the semiconductor driving device 10C according to the third embodiment. Before time t0, the gate voltage Vgs of the semiconductor switching element M1 is at the on-state potential VP, and the drain current Id is equal to the load current Im. Here, if a short circuit occurs in the main circuit at time t0, the drain current Id increases by approximately ten times and the drain voltage Vds increases to near the power supply voltage, the short-circuit detection unit 30 detects the short circuit at time t1, and the status signal SST drops from high (Hi) to low (Lo). Accordingly, the gate voltage Vgs is lowered by the voltage clamp unit 20, significantly reducing the drain current Id, and current interruption begins at time t2.

[0042] At time t1, the voltage regulated by the voltage regulation circuit 31 is input to the voltage clamp unit 20 from the control terminal K3, and the gate voltage Vgs drops to a clamping voltage equal to or higher than the gate mirror voltage Vm. In this way, the period from time t1 to t2 is used as the clamping voltage period by lowering the gate voltage Vgs, thereby reducing the drain current Id and suppressing an increase in conduction loss. The clamping voltage determined by the first voltage clamping element Dz10 is determined so that the first surge voltage generated in the drain voltage Vds at time t1 due to the reduction in the drain current Id by the voltage clamp unit 20 is approximately equal to the second surge voltage generated in the drain voltage Vds at time t2 when the drain current starts to be blocked. This allows a large current due to a short circuit to be blocked in two roughly equal stages, thereby preventing the first surge voltage or the second surge voltage from becoming excessive.

[0043] On the other hand, the comparative example does not include the voltage clamp unit 20 and the configuration of controlling the gate voltage Vgs of the semiconductor switching element M1 by controlling the potential VK3 of the control terminal K3 when a short circuit is detected, as in the third embodiment, so the drain current Id that arrived at time t1 is maintained until the current is cut off at time t2. This could result in the semiconductor switching element M1 being instantly destroyed, or an excessive protection function would be required to prevent this.

[0044] In the third embodiment, even if a short circuit occurs while the gate of the semiconductor switching element M1 is on, the gate voltage is clamped with a simple configuration based on a signal that detects the short circuit, thereby significantly reducing the short-circuit current and preventing destruction of the semiconductor switching element M1 or extending the time until destruction.

[0045] As described above, embodiment 3 provides the same effects as embodiment 1. Furthermore, since the device is provided with a short-circuit detection circuit and a voltage adjustment circuit that adjusts the voltage at the control terminal of the voltage drop circuit, it is possible to significantly reduce the short-circuit current with high responsiveness even when a short circuit occurs while the gate of semiconductor switching element M1 is on, thereby suppressing an increase in conduction loss and contributing to preventing breakdown of semiconductor switching element M1.

[0046] Fourth Embodiment. A semiconductor driver according to the fourth embodiment will now be described with reference to the accompanying drawings. FIG. 9 is a block diagram showing the configuration of a semiconductor driver 10D according to the fourth embodiment. This embodiment differs from FIG. 7 of the third embodiment in that the voltage clamping unit 20 is configured such that the first current limiting element 24 is connected in parallel with the second capacitance element 23, as in FIG. 4 of the first embodiment. Accordingly, compared to FIG. 7, the logic of the output of the short-circuit detection unit 30 is inverted, and a signal inversion circuit INV1 is provided to match the logic of the status signal SST output by the semiconductor driver 10D. Furthermore, the polarity of the rectifying element D11 and the first voltage limiting element Dz10 are inverted and connected. The remaining configuration and operation are the same as those of the third embodiment, and therefore detailed description thereof will be omitted. In the fourth embodiment, the voltage drop generating circuit 21 may be configured using a controlled switching element such as a PNP transistor or a P-type MOSFET, or a voltage regulator IC, as described in FIG. 5.

[0047] As described above, the fourth embodiment provides the same effects as the third embodiment.

[0048] Fifth Embodiment. A semiconductor driver according to a fifth embodiment will now be described with reference to the drawings. FIG. 10 is a block diagram showing the configuration of a semiconductor driver 10E according to the fifth embodiment, which differs from FIG. 7 of the third embodiment in the method of detecting a short circuit. In FIG. 7 of the third embodiment, a short circuit is detected by detecting the drain voltage Vds of the semiconductor switching element M1. However, in the fifth embodiment, a short circuit is determined by detecting the current at the source terminal SS of a current detection element Ms1 connected in parallel to the semiconductor switching element M1. This current detection element Ms1 is formed by scaling the semiconductor switching element M1.

[0049] The configuration of the short-circuit detection unit 30 for determining a short circuit based on the current of the current detection element Ms1 may also be configured using a known method, and detailed description thereof will be omitted. In this embodiment, the short-circuit detection unit 30 may determine a short circuit by acquiring the current value Iss itself at the source terminal SS, or may determine a short circuit based on the rate of change dIss / dt of the current value or the integral value ∫Issdt. The other configurations and operations are the same as those of the third embodiment, and detailed description thereof will be omitted.

[0050] As described above, the fifth embodiment provides the same effects as the third embodiment.

[0051] Sixth Embodiment A semiconductor driving device according to a sixth embodiment will now be described with reference to the drawings. Fig. 11 is a block diagram showing the configuration of a semiconductor driving device 10F according to a fifth embodiment, which differs from Fig. 7 of the third embodiment in the method of detecting a short circuit. In the fifth embodiment, a short circuit is determined by detecting an electromotive voltage Lss·dIs / dt generated across a parasitic inductance Lss between the source terminal Sm, which is the second main terminal of the semiconductor switching element M1, and the control source terminal S.

[0052] The short circuit detection unit 30 that detects a short circuit based on the voltage of the parasitic inductance Lss can be configured by applying a known method, and detailed description thereof will be omitted. In this embodiment, the short circuit detection unit 30 also acquires the value Lss·dIs / dt of the electromotive voltage itself to determine a short circuit, and also acquires the integral value Lss·Is of the electromotive voltage, the differential value Lss·d ２ Is / dt２ Alternatively, a method of determining whether a short circuit has occurred may be used based on the pulse width. The other configurations and operations are the same as those of the third embodiment, and therefore detailed description thereof will be omitted.

[0053] As described above, the sixth embodiment provides the same effects as the third embodiment.

[0054] Seventh Embodiment A semiconductor driving device according to a seventh embodiment will now be described with reference to the drawings. Fig. 12 is a block diagram showing the configuration of a semiconductor driving device 10G according to the seventh embodiment, which differs from Fig. 7 of the third embodiment in that the short circuit detection unit 30 determines whether a short circuit has occurred based on the drain voltage Vds and gate voltage Vgs of the semiconductor switching element M1.

[0055] The short-circuit detection unit 30 of the semiconductor driver 10G according to the seventh embodiment includes an output determination unit 30A, first and second gate voltage determination units 30B and 30C for determining the gate voltage Vgs, and a logic synthesis unit (NAND circuit) 30D. When the gate voltage Vgs input to the first gate voltage determination unit 30B exceeds a first threshold VrefA, the output signal SOB goes high (Hi), starting the determination operation of the output determination unit 30A. When the input drain voltage Vds of the output determination unit 30A exceeds a third threshold VrefC, the output signal SOA goes high (Hi). When the input gate voltage Vgs of the second gate voltage determination unit 30C exceeds a second threshold VrefB that is greater than the first threshold VrefA, the output signal SOC goes high (Hi). The output signals SOA and SOC are input to the logic synthesis unit 30D, and the inverted logical product is generated as a status signal SST.

[0056] Here, the second threshold VrefB is a value equal to or greater than the gate mirror voltage Vm and less than the positive power supply voltage VP. The other configurations and operations are the same as those in the third embodiment, and therefore detailed description thereof will be omitted.

[0057] 13A and 13B are schematic diagrams showing the output signals and status signal SST of the short circuit detection unit 30 of the semiconductor driving device 10G according to embodiment 7, and the voltage and current waveforms of the semiconductor switching element. Fig. 13A shows the waveforms during a normal turn-on operation without a short circuit, and Fig. 13B shows the waveforms during an abnormal turn-on operation in which a short circuit path has been formed. The comparative example shows the behavior of the voltage and current of the semiconductor switching element in a semiconductor driving device that does not include the voltage clamp unit 20 or the short circuit detection unit 30 as in embodiment 7.

[0058] 13A , the output signal SOB of the first gate voltage determination unit 30B goes high (Hi) at time t11, causing the output signal SOA of the output determination unit 30A to go high (Hi), but goes low (Lo) at time t12 when the drain voltage Vds falls below the third threshold VrefC. Also, the second gate voltage determination unit 30C determines that the voltage is equal to or higher than the second threshold VrefB, causing the output signal SOC to go high (Hi) at time t13. Because time t13 is after time t12, the status signal SST, which is the inverse of the logical product of the output signals SOA and SOC, remains high (Hi).

[0059] 13B , the output signal SOB of the first gate voltage determination unit 30B goes high (Hi) at time t21, and the output signal SOA of the output determination unit 30A also goes high (Hi) (time t22). Thereafter, due to the short circuit, the drain voltage Vds does not fall below the third threshold VrefC, and the output signal SOA does not go low (Lo) but remains high (Hi). At time t23, the second gate voltage determination unit 30C determines that the voltage is equal to or greater than the second threshold VrefB. At this time, the output signal SOC goes high (Hi), and the status signal SST, which is the inverse of the logical product of the output signals SOA and SOC, drops from high (Hi) to low (Lo).

[0060] Typically, it takes a certain amount of time to determine whether the voltage is equal to or higher than a preset voltage or whether it is a high voltage, resulting in a delay in short-circuit determination. Therefore, even in this embodiment, a delay in the determination by the output determination unit 30A is a concern. However, according to the configuration of the seventh embodiment, the operation of the output determination unit 30A is enabled by the output signal determined by the first gate voltage determination unit 30B, which precedes the determination by the second gate voltage determination unit 30C, thereby minimizing the determination delay by the output determination unit 30A. Furthermore, by using a logical AND with the output signal SOC determined by the second gate voltage determination unit 30C, even if the output determination unit 30A erroneously detects a short, the status signal SST will not malfunction unless the second gate voltage determination unit 30C erroneously detects a short. This enables high-speed short-circuit detection, and makes it possible to protect the semiconductor switching element M1 from short circuits without requiring short-circuit protection specifications with excessive margins, even if the semiconductor switching element M1 is made of a wide bandgap semiconductor with strict short-circuit resistance.

[0061] As described above, according to the seventh embodiment, the same effects as those of the third embodiment can be achieved. Furthermore, high-speed short circuit detection becomes possible.

[0062] In the above example, the operation of the short circuit detection unit 30 was described when a short circuit occurs during turn-on. However, if a short circuit occurs during turn-on, the status signal SST can be switched and the gate voltage Vgs can be clamped in a similar manner. If a short circuit occurs after time t13 in FIG. 13A , the drain current Id exceeds the third threshold VrefC, causing the output signal SOA to go high (Hi). At this time, the output signal SOC is high (Hi), and the inversion of the logical product of the output signals SOA and SOC causes the status signal SST to drop from high (Hi) to low (Lo).

[0063] Eighth Embodiment A power conversion device according to an eighth embodiment will now be described with reference to the drawings. Fig. 14 is a block diagram showing the configuration of a power conversion device 100A according to the eighth embodiment. In Fig. 14, the power conversion device 100A is connected between a power supply 70 and a motor 80, which is a load, and includes a power converter 40 having a plurality of semiconductor switching elements 50, and a control device 90 that controls the power converter 40. The power supply 70 is a DC power supply, and the power conversion device 100A operates as an inverter that converts DC power into AC power and supplies it to the motor 80.

[0064] The control device 90 includes any one of the semiconductor driving devices 10A to 10G described above in the first to seventh embodiments. Since the semiconductor driving devices 10A to 10G are provided for each semiconductor switching element 50 of the power converter 40, the control device 90 is an assembly of the semiconductor driving devices 10A to 10G.

[0065] The power converter 40 is an inverter circuit provided with a smoothing capacitor 60 between DC buses and leg circuits 51 for each of the U, V, and W phases. The leg circuits 51 for each phase are configured by connecting upper and lower arms in series, each of which has a semiconductor switching element 50.

[0066] According to the eighth embodiment, the control device for a power converter includes any one of the semiconductor drive devices according to the first to seventh embodiments, and drives each semiconductor switching element in the power converter using the semiconductor drive device. The voltage clamp unit of the semiconductor drive device according to the first to seventh embodiments has a low-cost, low-power-loss configuration that does not require an additional power supply, and this configuration can clamp the gate voltage when the semiconductor switching element is turned on. As a result, even if one of the semiconductor switching elements in the power converter is turned off and destroyed, causing a short circuit in the main circuit when the other semiconductor switching element is turned on, the voltage clamp unit can suppress the current during the short circuit. Therefore, a highly reliable power converter can be obtained.

[0067] Furthermore, if a semiconductor driving device is equipped with a short circuit determination circuit like those of the semiconductor driving devices according to the third to seventh embodiments, the current in the event of a short circuit will be suppressed by the voltage clamp section even if a short circuit is detected during turn-on.

[0068] In the eighth embodiment, power converter 40 outputs two-level AC voltage, positive and negative, but may be an inverter capable of outputting multilevel voltages in which any number of semiconductor switching elements 50 are connected in series and parallel. In this case, power converter 40 also has a configuration including leg circuits 51 each including an upper arm and a lower arm connected in series, each arm including a semiconductor switching element 50. Furthermore, power converter 40 may be a converter device that converts AC power to DC power, or an inverter device capable of bidirectional output.

[0069] Ninth Embodiment A power conversion device according to a ninth embodiment will be described below with reference to the drawings. FIG. 15 is a block diagram showing the configuration of a power conversion device 100B according to the ninth embodiment. In FIG. 15, the power conversion device 100B is connected between a power supply 70 and a load 80A and includes a power converter 41 having a plurality of semiconductor switching elements 50, and a control device 90 that controls the power converter 40. The power supply 70 is a DC power supply, and the power conversion device 100B boosts the DC voltage and supplies it to the DC load 80A. It operates as a boost converter.

[0070] Similar to the eighth embodiment, the control device 90 includes any one of the semiconductor driving devices 10A to 10G described in the first to seventh embodiments. Since the semiconductor driving devices 10A to 10G are provided for each semiconductor switching element 50 of the power converter 41, the control device 90 is an assembly of the semiconductor driving devices 10A to 10G.

[0071] The power converter 41 includes an input-side smoothing capacitor 61, an output-side smoothing capacitor 62, a leg circuit 51A, and a boost reactor 63. The leg circuit 51A is configured by connecting an upper arm and a lower arm in series, each arm including a semiconductor switching element 50.

[0072] The ninth embodiment achieves the same effects as the eighth embodiment. That is, a control device for a power converter includes any one of the semiconductor driving devices according to the first to seventh embodiments, and drives each semiconductor switching element in the power converter using the semiconductor driving device. The voltage clamp unit of the semiconductor driving device according to the first to seventh embodiments has a low-cost, low-power-loss configuration that does not require an additional power supply. This configuration can clamp the gate voltage when the semiconductor switching element is turned on. As a result, even if one of the semiconductor switching elements in the power converter is destroyed during turn-off and a short circuit occurs in the main circuit when the other semiconductor switching element is turned on, the voltage clamp unit suppresses the current during the short circuit. Therefore, a highly reliable power converter can be obtained. Furthermore, if a semiconductor driving device includes a short-circuit determination circuit like the semiconductor driving devices according to the third to seventh embodiments, the voltage clamp unit suppresses the current during the short circuit even if a short circuit is detected during turn-on.

[0073] Although the ninth embodiment shows an example in which a boost converter is configured, the present invention can also be applied to a step-down converter or a step-up / step-down converter in which a boost converter and a step-down converter are combined.

[0074] Tenth Embodiment A power conversion device according to a tenth embodiment will now be described with reference to the drawings. Fig. 16 is a block diagram showing the configuration of a power conversion device 100C according to the tenth embodiment. In Fig. 16, the power conversion device 100C has a configuration in which the power converter 41 shown in Fig. 15 of the ninth embodiment is provided between the power converter 40 of the power conversion device 100A shown in Fig. 14 of the eighth embodiment and the power supply 70. However, the smoothing capacitor 62 on the output side is not necessary because the smoothing capacitor 60 of the power converter 40 is provided.

[0075] In this case, the power conversion device 100C boosts the DC voltage of the DC power supply 70 using the power converter 41, converts the boosted DC power into AC power using the power converter 40, and supplies it to the load, i.e., the motor 80. The power conversion device 100C operates as a boost inverter system, and is applied to, for example, an electric vehicle.

[0076] Similar to the eighth and ninth embodiments, the control device 90 includes any one of the semiconductor driving devices 10A to 10G described above in the first to seventh embodiments. Since the semiconductor driving devices 10A to 10G are provided for each of the power converters 40 and the semiconductor switching elements 50 of the power converters 41, the control device 90 is an assembly of the semiconductor driving devices 10A to 10G.

[0077] According to the tenth embodiment, the same effects as those of the eighth and ninth embodiments are achieved. That is, even if one of the semiconductor switching elements 50 of the power converter 40 or the power converter 41 is broken down during turn-off and a short circuit occurs in the power converter 40 or the power converter 41 during turn-on, the gate voltage of the other unbroken semiconductor switching element 50 can be clamped, and a highly reliable power conversion device 100C in which the current during the short circuit is suppressed can be obtained. Furthermore, the same effects as those of the eighth and ninth embodiments are achieved with respect to a short circuit during turn-on.

[0078] In the ninth embodiment, power converter 40 of power conversion device 100C may be an inverter capable of multilevel voltage output. Furthermore, power converter 41 of power conversion device 100C is not limited to a boost converter, and may be a buck converter or a buck-boost converter that combines a boost converter and a buck converter.

[0079] Other Embodiments (1) In the above-described embodiment, the semiconductor switching element 50 is described as a MOSFET, but this is not limiting. It may be an IGBT or other semiconductor switching element controlled by a control terminal such as a gate terminal.

[0080] (2) In the above-described embodiment, the semiconductor switching element 50 may be made of a wide bandgap semiconductor material having a wider bandgap than silicon, which can increase the switching speed of the semiconductor switching element 50. This also allows the boost reactor 63 in FIGS. 16 and 17 to be miniaturized. The wide bandgap semiconductor material may be any of silicon carbide (SiC), gallium nitride (GaN), gallium oxide-based materials, and diamond (C).

[0081] (3) An example of the configuration of the short circuit detection unit 30 of the semiconductor driving device according to the third to seventh embodiments is shown in FIG. 17 . As shown in FIG. 17 , the short circuit detection unit 30 includes, for example, a processor 1000 and a storage device 1100 as processing circuits. The processor 1000 may include a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), an IC, an FPGA (Field Programmable Gate Array), various logic circuits, various signal processing circuits, etc. Furthermore, a plurality of processors 1000 of the same type or different types may be provided, and each process may be shared and executed. The storage device 1100 includes a RAM (Random Access Memory) configured to be able to read and write data from the processor 1000, and a ROM (Read Only Memory) configured to be able to read data from the processor 1000. The processor 1000 executes a program input from the storage device 1100 such as a ROM.

[0082] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not illustrated are anticipated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0083] DESCRIPTION OF THE SYMBOLS 10A to 10G: semiconductor driving device, 20, 20A, 20B: voltage clamping section, 21, 21A, 21B: voltage drop generating circuit, 22: first capacitance element, 23: second capacitance element, 24: first current limiting element, 30: short circuit detection section, 30A: output determination section, 30B: first gate voltage determination section, 30C: second gate voltage determination section, 30D: logic synthesis section, 31: voltage adjustment circuit, M1, 50: semiconductor switching element, 40: power converter, 41: power converter, 51, 51A: leg circuit, 60 to 62: smoothing capacitor, 63: boost reactor, 70: power supply, 80: motor, 80A: load, 90: control device, 100A to 100C: power conversion device, VP: potential, VN: potential, FG: control reference potential, B10: gate driver, VC0: reference potential, R10: on-gate resistor, R11: off-gate resistor, R12: gate resistor, R13: gate resistor, R14: third current limiting element, D10: gate rectifier element, D11: rectifier element, Dz10: first voltage limiting element, Q20A: NPN transistor, Q20B: PNP transistor, R21: second current limiting element, SGD: on / off command signal, SST: status signal, 1000: processor, 1100: storage device.

Claims

1. A semiconductor drive device that applies a voltage to the gate terminal of a semiconductor switching element through which current flows from a first main terminal to a second main terminal to drive the on / off of the semiconductor switching element, comprising: a gate drive unit that applies a voltage to the gate terminal based on an on / off command signal; a voltage clamp unit having a voltage drop generation circuit that drops the voltage between the output of the gate drive unit and the gate terminal, wherein the voltage clamp unit has a control terminal for the voltage drop generation circuit to adjust the degree of voltage drop, a first capacitor element connected between a point on the path from the output of the gate drive unit to the voltage clamp unit and the control terminal, a second capacitor element connected between the control terminal and a reference potential, and a first current limiting element connected in parallel with the first capacitor element or the second capacitor element. A semiconductor drive device.

2. The semiconductor drive device according to claim 1, wherein the voltage drop generation circuit has a control switching element that controls the current flowing from the gate drive unit toward the gate terminal by the control terminal.

3. The voltage clamp unit includes a first terminal connected to the gate drive unit and a second terminal connected to the gate terminal, The semiconductor drive device according to claim 1, wherein a current path is provided between the first terminal and the second terminal and includes a first rectifying element that allows current to flow from the gate terminal to the gate drive unit.

4. The semiconductor drive device according to claim 2, wherein the voltage drop generation circuit includes a second current limiting element connected in parallel between the terminal on the gate drive unit side and the terminal on the gate terminal side of the control switching element.

5. The semiconductor drive device according to any one of claims 1 to 4, wherein when the gate drive unit turns on the semiconductor switching element, the following formula (1) is satisfied. γ>(Vth-VC0) / (VP-Vth)・・・Formula (1) where γ is the ratio of the capacitance C1 of the first capacitor element to the capacitance C2 of the second capacitor element (γ = C1 / C2), VP is the voltage applied to the gate terminal during the period when the semiconductor switching element is turned on, VC0 is the reference potential to which the second capacitor element is connected, Vth is the gate threshold voltage of the semiconductor switching element.

6. The semiconductor drive device according to any one of claims 1 to 4, wherein when the gate drive unit turns on the semiconductor switching element, the following formula (2) is satisfied. γ > (Vm - VC0) / (VP - Vm) ... Equation (2) However, γ is the ratio of the capacitance C1 of the first capacitive element to the capacitance C2 of the second capacitive element (γ = C1 / C2), VP is the voltage applied to the gate terminal during the period when the semiconductor switching element is on, VC0 is the reference potential to which the second capacitive element is connected, Vm is the gate mirror voltage of the semiconductor switching element.

7. A short-circuit detection unit that detects a short circuit in the current path flowing from the first main terminal to the second main terminal of the semiconductor switching element, and a voltage adjustment circuit that changes the potential of the control terminal based on the output of the short-circuit detection unit, When the short-circuit detection unit detects a short circuit, The potential of the control terminal is adjusted by the voltage adjustment circuit, and the voltage applied to the gate terminal is reduced to a limiting potential equal to or higher than the gate mirror voltage. The semiconductor drive device according to any one of Claims 1 to 4.

8. The short-circuit detection unit determines that a short circuit has been detected when the voltage of the first main terminal is greater than a preset value during the period when the semiconductor switching element is on. The semiconductor drive device according to Claim 7.

9. The short-circuit detection unit acquires a current value from a current detection element provided in the current path of the semiconductor switching element, and determines that a short circuit has been detected when the current value is greater than a preset value. The semiconductor drive device according to Claim 7.

10. The short-circuit detection unit acquires the potential difference between the potential of the second main terminal and the potential of a control reference terminal that is the reference for on / off driving of the semiconductor switching element and is provided branched from the second main terminal of the semiconductor switching element, and determines that a short circuit has been detected when the potential difference is greater than a preset value. The semiconductor drive device according to Claim 7.

11. The short-circuit detection unit, A first gate voltage determination unit that determines that the voltage of the gate terminal is equal to or higher than a first threshold value, A second gate voltage determination unit that determines that the voltage of the gate terminal is equal to or higher than a second threshold value that is greater than the first threshold value, A determination output unit that determines that the voltage of the first main terminal is equal to or higher than a third threshold value, and Based on the output of the first gate voltage determination unit, the determination operation of the determination output unit is enabled, and based on the logical product of the output of the second gate voltage determination unit and the output of the determination output unit, a short circuit of the semiconductor switching element is determined. The semiconductor drive device according to Claim 7.

12. The reference potential to which the second capacitance element is connected is any one of the potential of the second main terminal of the semiconductor switching element, the control reference potential that serves as a reference for on / off driving of the semiconductor switching element and is provided by branching from the second main terminal of the semiconductor switching element, the potential of the control reference terminal, and a fixed potential generated based on the potential of the second main terminal or the control reference terminal. The semiconductor drive device according to any one of Claims 1 to 4.

13. A power conversion device including: a power converter having at least one leg in which the semiconductor switching elements are connected in series; and a control device having the semiconductor drive device according to any one of Claims 1 to 4.

14. The power converter is any one of an inverter device that converts DC power into AC power, a boost converter device that boosts the voltage of DC power, a buck converter device that steps down the voltage of DC power, a converter device that converts AC power into DC power, a boost type inverter device including the boost converter device and the inverter device, and a buck type inverter device including the buck converter device and the inverter device. The power conversion device according to Claim 13.

15. The semiconductor switching element is formed of any one of wide bandgap semiconductors such as silicon carbide, gallium nitride, gallium oxide-based materials, or diamond. The power conversion device according to Claim 13.