Device having digital / analog conversion circuit

Abstract

A device 1 having a DA conversion circuit comprises at least: a processor 10P that outputs a DA conversion target value; a front stage circuit 10FNT that receives the DA conversion target value from the processor 10P and corrects and outputs the DA conversion target value in accordance with correction data; a body circuit 10BDY that includes one or more correction target DA converter elements and DA converts the corrected DA conversion target value; and an AD converter 10AD. The correction target DA converter element is a hybrid DA converter element that outputs, from an output terminal, an analog value obtained by adding an analog value outputted by a first-class circuit segment SEG1 assigned to a higher rank and an analog value outputted by a second-class circuit segment SEG2 assigned to a lower rank. The processor 10P: (A) acquires, as a calibration test for creating or updating the correction data, a plurality of test pairs each being a pair of a test input value and a test result value that have the following features, (A1) the test input value being a value inputted as the DA conversion target value to the body circuit with or without correction and (A2) the test result value being a value obtained by AD-converting the analog value outputted by inputting the test input value to the body circuit by the AD converter; and (B) updates the correction data on the basis of the plurality of test pairs in (A). The number of test pairs to be acquired during the calibration test is smaller than the N-th power of 2, and N is the number of bits indicating the resolution of the correction target DA converter element.

Description

Device having digital / analog conversion circuit

[0001] The present invention relates to a device having a digital / analog conversion circuit (hereinafter also referred to as a DA conversion circuit or a DA converter element), and for example to a device having a DA conversion circuit that can achieve high accuracy.

[0002] A technology for providing a high-precision DA conversion circuit is described, for example, in Patent Document 1. Patent Document 1 describes a technology for improving the precision of a DA conversion circuit by using an R-2R resistor DAC (digital-to-analog converter) element, an interpolation DAC element, and a sigma-delta modulator element. The document also describes the implementation of a calibration process (corresponding to the calibration test in the embodiments described below) to achieve high precision.

[0003] JP 2022-3830 A

[0004] The inventors have conducted research and found that the technology disclosed in Patent Document 1 has at least one of the following improvements.

[0005] It is expected that the conversion characteristics of a DA converter element (hereinafter simply referred to as a DA converter) may change due to dynamic changes in the temperature (environmental temperature) of a device that includes the DA converter. For this reason, calibration tests must be performed repeatedly, but the technology disclosed in Patent Document 1 leaves room for improvement in the calibration test time.

[0006] The target device to which the analog value output from the DA converter is supplied may be a device that requires a high voltage or a high current. In such devices, it is difficult to directly supply the output of the DA converter to the target device, and so an amplifier circuit is typically connected between the DA converter and the target device. The input / output characteristics of the amplifier circuit, such as the gain, fluctuate with temperature (environmental temperature), and therefore fluctuate over time. As a result, the analog value supplied to the target device also fluctuates over time. The technology described in Patent Document 1 leaves room for improvement in this regard.

[0007] SUMMARY OF THE INVENTION It is an object of the present invention to provide an apparatus that overcomes one or more of the above problems.

[0008] Other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009] A brief summary of a representative embodiment of the present invention will be given below.

[0010] That is, the device according to the embodiment includes at least a processor that outputs a value to be converted into an analog signal, a front-stage circuit that receives the value to be converted into an analog signal from the processor, corrects it in accordance with correction data, and outputs the corrected value to be converted into an analog signal, the main circuit including one or more DA converter elements that are to be corrected and performs DA conversion of the corrected DA conversion value, and an AD converter. Here, the DA converter elements to be corrected are hybrid DA converter elements that output from an output terminal an analog value obtained by adding together an analog value output by a first-type circuit segment that handles higher levels and an analog value output by a second-type circuit segment that handles lower levels. Furthermore, as a calibration test for creating or updating correction data, the processor: (A) acquires a plurality of test pairs, which are pairs of test input values ​​and test result values ​​having the following characteristics: (A1) the test input values ​​are values ​​to be input to the main circuit with or without correction as values ​​to be DA converted, and (A2) the test result values ​​are values ​​obtained by AD converting, by an AD converter, an analog value output by inputting the test input values ​​to the main circuit, and (B) updates the correction data based on the plurality of test pairs of (A), where the number of test pairs acquired during the calibration test period is smaller than 2 to the power N, and N is the number of bits indicating the resolution of the DA converter element to be corrected.

[0011] Another embodiment of the device includes a main circuit including one or more DA converter elements that converts a received main circuit input bit string, which is a bit string, into a main circuit output analog value, which is an analog value, and outputs the converted bit string; a processor that outputs a processor output bit string; a front-end circuit that receives the processor output bit string and outputs the main circuit input bit string; and an AD converter. Here, the front-end circuit corrects the processor output bit string based on correction data and outputs the main circuit input bit string, and the main circuit includes an amplifier circuit that amplifies the analog value output by the DA converter element and outputs it as a main circuit output analog value. Here, the processor: (A) acquires multiple pairs of test bit strings and test result bit strings having the following characteristics: (A1) the test bit string is a processor output bit string or a main circuit input bit string for a calibration test, and (A2) the test result bit string is acquired by converting the main circuit output analog value using an AD converter, and (B) updates the correction data based on the multiple pairs of (A).

[0012] To briefly explain the effect obtained by a representative embodiment of the invention disclosed in this application, it is possible to provide a device equipped with a highly accurate DA conversion circuit.

[0013] 1 is a block diagram showing the configuration of a device having a DA converter according to a first embodiment. FIG. 2 is a block diagram showing the configuration of a DA converter according to the first embodiment. FIG. 3 is a circuit diagram showing the configuration of a DA converter according to the first embodiment. FIG. 4 is a flowchart for operating the DA converter according to the first embodiment. FIG. 5 is a flowchart for explaining a calibration test according to the first embodiment. FIG. 6 is a diagram for explaining a calibration test according to the first embodiment. FIG. 7 is a diagram for explaining a correction amount according to the first embodiment. FIG. 8 is a block diagram showing the configuration of a bit string correction circuit according to the first embodiment. FIG. 9 is a block diagram showing the configuration of a DA converter according to a second embodiment. FIG. 10 is a diagram for explaining a bit string correction circuit according to the second embodiment. FIG. 11 is a block diagram showing the configuration of a charged particle beam device according to a fourth embodiment. FIG. 12 is a diagram showing formulas for explaining the embodiments. FIG. 13 is a block diagram showing the configuration of a DA converter according to a modified example of the second embodiment.

[0014] The following description of the embodiments will be given with reference to the drawings. Note that the embodiments described below do not limit the scope of the invention as claimed, and not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the invention.

[0015] (Embodiment 1) <Device Configuration> Fig. 1 is a block diagram showing the configuration of a device according to embodiment 1. In Fig. 1, reference numeral 1 indicates the device. The device 1 includes a processor 10P, a pre-stage circuit 10FNT, a main circuit 10BDY, and an analog-to-digital converter (hereinafter referred to as an AD converter) 10AD.

[0016] In FIG. 1 , OBJ represents a target device, and device 1 outputs an analog value to target device OBJ. Here, the target device OBJ is described as being external to device 1, but of course, target device OBJ may also be included in device 1. Target device OBJ is a device that operates when an analog value is provided from device 1. An example of target device OBJ will be described later, but this is not limiting. Broadly speaking, target device OBJ can also be considered a controlled device whose operation is controlled by an analog value from device 1, and target device OBJ can also be considered an amplifier circuit such as an operational amplifier. Note that, in this specification, a value represented in an analog manner (which at least refers to representing a value using a continuously changing (or causing) physical quantity such as voltage or current) is referred to as an analog value. Note that processes such as generating, outputting, inputting, transmitting, and receiving analog values ​​of physical entities (elements, circuits, devices) actually mean at least changing a continuously changing (or causing) physical quantity such as current or voltage.

[0017] In the following description, the pre-stage circuit 10FNT and the main circuit 10BDY shown in FIG. 1 may be collectively referred to as a DA conversion circuit.

[0018] <<Processor>> The processor 10P is a device that performs a predetermined process (control process in FIG. 1) to generate and transmit a digital value (bit string) of a value (hereinafter, sometimes referred to as a DA conversion target value) to be given to the object device OBJ after DA conversion via a circuit described later. In the following explanation, the bit string that the processor 10P generates and transmits as a result of the control process is referred to as a processor output bit string, and is illustrated as 10BTP in FIG. 1.

[0019] The processor 10P may be, for example, a device such as a CPU or GPU that performs a predetermined process by executing a program. However, the processor 10P may also be an FPGA or other IC as long as it can generate the aforementioned digital value (bit string) by performing the predetermined process. The processor 10P may be part of a component 10C, such as a motherboard or controller, along with volatile memory VOLMEM or non-volatile memory NVMEM (e.g., flash memory or HDD), or may be a computer. In addition, the device 1 itself may be a computer. The program(s) that implement the test process and control process executed by the processor 10P are stored in non-volatile memory NVMEM.

[0020] <<Main Circuit and Preceding Circuit>> The main circuit 10BDY is a circuit including one or more DA converters (correction target DA converters) 10DAC that convert the main circuit input bit string 10BTB into an analog main circuit output analog value 10ANG (A) and output it. Note that the value of the main circuit input bit string 10BTB output in accordance with the processor output bit string 10BTP having a DA conversion target value can also be said to have a "corrected DA conversion target value."

[0021] The pre-stage circuit 10FNT is a circuit that receives the processor output bit string 10BTP and outputs the main body input bit string 10BTB. The pre-stage circuit 10FNT includes a bit string correction circuit 10BCT that corrects the processor output bit string 10BTP based on correction data (correction data D in FIG. 1) and outputs the main body input bit string 10BTB. The correction data is stored in a memory (not shown) within the pre-stage circuit. This correction does not have to be performed all the time. For example, this correction is performed after a calibration test, which will be described later.

[0022] <<AD Converter>> The AD converter 10AD is an element used during a calibration test, which will be described later. During the calibration test, the AD converter 10AD converts the main body output analog value 10ANG into a bit string 10BTTR. In the following description, for ease of distinction, the bit string 10BTTR will be referred to as a test result bit string 10BTTR. Note that in the following description, the calibration test may be abbreviated to simply "test." Of course, the AD converter 10AD may also be used for purposes other than testing.

[0023] <<Test Purpose and Correction Purpose>> The calibration test process is performed by the processor 10P. This calibration test is performed to understand the conversion relationship (mainly the DA conversion relationship) between the input and output of the main circuit 10BDY due to changes in the characteristics of the main circuit 10BDY (e.g., due to environmental factors such as temperature). Based on the results of this test process, correction data used in the pre-stage circuit 10FNT is generated. Note that, although the characteristic changes focused on in the first embodiment are those of the DA converter 10DAC(A), characteristic changes of other elements may also be considered. For example, characteristic changes of the amplifier circuit AMP, which will be described later, may also be considered.

[0024] A typical purpose of correction based on understanding the conversion relationship is to improve the linearity between digital and analog. A 3-bit bit string (offset binary format or unsigned binary format) will be described as an example. If the bit string (1, 0, 0) indicated by the order of MSB, middle bit, and LSB outputs a current of 4 mA, then, in a highly linear DA converter, taking into account the meaning of each bit, the analog value output for the bit string (0, 1, 0) would ideally be 2 mA, and the analog value output for the bit string (0, 0, 1) would ideally be 1 mA.

[0025] However, if the characteristics of the circuit responsible for the intermediate bits in the DA converter change significantly, and only the bit string (0, 1, 0) outputs 3 mA, while the other outputs remain unchanged, the aforementioned linearity will be reduced. The correction performed by the pre-stage circuit 10FNT improves the reduced linearity by changing the bit string actually input to the DA converter 10DAC. Note that the target line for improvement does not need to be a line connecting the analog values ​​of the bit string (1, 0, 0) and the bit string (0, 0, 1); it can also be a line interpolated using the analog values ​​of the other two bit strings, or a line obtained using regression analysis.

[0026] In the first embodiment, a calibration test by the processor 10P acquires a plurality of pairs (hereinafter also referred to as test pairs) of test bit strings (sometimes referred to as test input values ​​in abstraction) and test result bit strings (sometimes referred to as test result values ​​in abstraction) having the following characteristics (A1) and (A2):

[0027] (A1) The test bit string is the processor output bit string or the main body input bit string for a calibration test. From another perspective, the test bit string may be considered to be a value to be input to the main body circuit with or without correction as the DA conversion target value.

[0028] (A2) The test result bit string is obtained by converting the main body output analog value using the AD converter. From another perspective, the test result bit string may be considered to be a value obtained by AD converting, using the AD converter, an analog signal output by inputting the test input value to the main body circuit.

[0029] Here, the conversion relationship between the digital value (bit string) and the analog value of the DA converter 10DAC(A) is obtained from the set of the plurality of test pairs or by processing the set.

[0030] In each of the embodiments, the number of pairs required for the test is reduced by taking into consideration the internal structure of the DA converter 10DAC(A) in order to shorten the test processing time. More specifically, the number of test pairs is reduced by taking into consideration the structure of the DA converter 10DAC(A) that generates an analog value as a converter by adding an analog value output by a first-type circuit segment SEG1 and an analog value output by a second-type circuit segment SEG2, as shown in FIG. 1 .

[0031] In the case of a hybrid DA converter that supports high-precision multi-bit input while minimizing the circuit size within the DA converter, a circuit segment designed for high precision (typically responsible for the MSB and a predetermined number of bits below the MSB) and a circuit segment designed for low-circuit implementation (typically responsible for the LSB and a predetermined number of bits above the LSB) are used in combination. Examples of such segments (type 1 circuit segment SEG1, type 2 circuit segment SEG2) include a thermometer type suitable for high precision and a weighted binary type (ladder type) suitable for low-circuit implementation. Taking a 3-bit hybrid DA converter (offset binary format or unsigned binary format) as an example, the high-precision circuit segment (hereinafter sometimes referred to as the high-precision circuit segment) is responsible for the MSB, and the circuit segment designed for low-circuit implementation (hereinafter sometimes referred to as the low-circuit implementation circuit segment) is responsible for the LSB and intermediate bits. Note that the above example is not intended to limit the technology of this specification to DA converters that handle inputs in offset binary format or unsigned binary format, and the technology of this specification can also be applied to other binary formats (e.g., two's complement binary format).

[0032] In the low-scale circuit segment, common elements are often used to output the analog values ​​of one bit string and another bit string. Taking the example of 3 bits, common elements within the low-scale circuit segment are used for both the bit string (x, 0, 1) and the bit string (x, 1, 1). Note that the MSB is abbreviated to x because it is assumed that it is the responsibility of the high-density implementation segment.

[0033] In the following embodiments, by acquiring one or more test pairs based on the relationship between each bit in the bit string and the elements used in the circuit segment, the test result bit string of another test pair can be accurately estimated, and this "another test pair" is then omitted. As a result, the number of test pairs in one calibration test is smaller than 2 to the power of "the number of bits in the test bit string." From another perspective, the number of test pairs acquired during the calibration test period is smaller than 2 to the power of N (where N is the number of bits indicating the resolution of the DA converter element to be corrected).

[0034] <<Main Circuit Options>> The main circuit 10BDY according to the first embodiment may include the following options.

[0035] <<<<Amplifier Circuit AMP>>> The amplifier circuit AMP amplifies the output of the DA converter 10DAC(A) when the output (output current or output voltage) of the DA converter 10DAC(A) is insufficient to operate the target device OBJ. Examples of the amplifier circuit AMP include an operational amplifier, an amplifier circuit using an operational amplifier, and an amplifier circuit using a transistor (including a field-effect transistor (FET)). The amplifier circuit AMP may use circuit elements (e.g., resistors) that may be affected by the operating environment (e.g., temperature). To compensate for such amplifier circuit fluctuations, the output 10ANG(B) of the amplifier circuit AMP may be converted by the AD converter 10AD instead of the main body output analog circuit 10ANG(A). If the DA converter 10DAC(A) outputs a current value that is changed as an analog value, the amplifier circuit AMP may amplify either the current value or the voltage value. When the DA converter 10DAC(A) changes and outputs a voltage value as an analog value, the amplifier circuit AMP may amplify the voltage value or the current value.

[0036] <<<<Attenuator>>> The output of the DA converter 10DAC(A) or the output of the amplifier circuit AMP may be input to the AD converter 10AD via an attenuator (not shown). The attenuator can limit the voltage or current input to the AD converter 10AD, preventing the AD converter 10AD from being damaged by high voltages or currents. Furthermore, even if the elements constituting the attenuator are affected by the operating environment, fluctuations in the attenuator can be corrected.

[0037] <<<DA Converter DAC(B)>>> The main circuit 10BDY may include an additional DA converter 10DAC(B). The DA converter 10DAC(B) is used, for example, when converting a number of bits exceeding the number of bits that can be input to the DA converter 10DAC(A) into an analog value. The elements required to add the DA converter 10DAC(B) include a division circuit 10SPT and a weighted addition circuit 10ADDW. The roles of each will be explained later. Note that the DA converter 10DAC(B) does not have to be a hybrid DA converter, nor does it have to be subject to correction by a calibration test. Conversely, the DA converter 10DAC(B) may be a hybrid DA converter, and may also be subject to correction by a calibration test.

[0038] <<<Switch 10SW>>> The switch 10SW switches whether the output of the DA converter 10DAC(A) is supplied to the target device OBJ or to the AD converter 10AD. In Figure 1, the state of the switch 10SW during a test, which will be described later, is shown by a solid line. In this state, the output of the DA converter 10DAC(A) is supplied to the AD converter 10AD. The switch 10SW is used when the main body output analog value 10ANG during a test, which will be described later, is not desirable for the target device OBJ.

[0039] The preceding circuit 10FNT may include the optional components described for the main circuit 10BDY instead of the main circuit 10BDY. For example, the preceding circuit 10FNT may include a dividing circuit 10SPT(B) instead of the dividing circuit 10SPT(A), which is an option for the main circuit 10BDY. Such an example occurs when the correction, which is at least a part of the role of the preceding circuit 10FNT, is improved by closely coordinating it with the DA conversion circuit.

[0040] It should be noted that component elements such as operational amplifiers are not necessarily required for addition, not just within the DA converter 10DAC(A). For example, adding current values ​​can be achieved by joining the wires from two current sources into one, and adding voltage values ​​can be achieved by directly connecting two voltage sources. In the following explanation, such a structure for addition may be referred to as an "adder circuit." In other words, an adder circuit may consist of only wires. In addition, a "circuit" may consist of only wires, without any elements.

[0041] The "wiring" between the processor 10P, the pre-stage circuit 10FNT, the main circuit 10BDY, and the AD converter 10AD may be wiring formed on a substrate, cables such as coaxial cables, optical cables, or communication cables, an on-chip wiring pattern within an IC, or virtually defined wiring within an FPGA. For example, a communication cable (e.g., a network communication cable) may be used for some or all of the connection between the processor 10P and the pre-stage circuit 10FNT. Therefore, the processor output bit string 10BTP may be transmitted in parallel over multiple wirings or may be serialized and transmitted as in a general communication method. In other words, the connections between the processor 10P, the pre-stage circuit 10FNT, the main circuit 10BDY, and the AD converter 10AD do not need to be directly connected only by wiring, and some components may be included between them. Examples of such components include photodiodes for optical communications, communication chips for communicating using network communications protocols (e.g., USB, PCI, Ethernet), timing adjustment and hold circuits (elements) commonly used in digital and analog circuits, and bandpass filter circuits (elements). When the output, input, transmission, and reception of bit strings are described in this specification, it is sufficient that the bit string can be output, input, transmitted, and received as a result, and it is not essential that the transmission maintains a "string" as in serial communications.

[0042] Furthermore, the components that make up the device 1 do not necessarily need to be integrated into a single housing, device, or board. In other words, each component may be realized as a separate housing, device, or board.

[0043] <Configuration Example of DA Converter 10DAC(A)> FIG. 2 is a block diagram showing the configuration of a DA converter according to the first embodiment. As shown in FIG. 2, the DA converter 10DAC(A) shown in FIG. 1 includes a main DA converter M_DAC, a sub DA converter S_DAC, a weighted addition circuit MS_ADDW, holding circuits M_HL and S_HL, and a division circuit 10SPT(B). Here, an example is described in which the division circuit 10SPT(B) is included in the DA converter 10DAC(A) in the main circuit 10BDY. However, as shown in FIG. 1, the division circuit 10SPT(B) may also be included in the pre-stage circuit 10FNT. Note that the following description uses as an example a DA converter that handles inputs in offset binary format or unsigned binary format. However, the technology described herein can also be applied to two's complement binary format (for example, by including a decoder circuit that performs binary format conversion within the DA converter 10DAC(A)).

[0044] 2 illustrates the case where the number of bits in the processor output bit string (input bit string) 10BTP supplied from the processor 10P to the pre-stage circuit 10FNT and the main circuit 10BDY is N. The N-bit input bit string 10BTP is divided by the dividing circuit 10SPT(B) into an upper input bit string Inp_U and a lower input bit string Inp_L. The relationship between the input bit string 10BTP and the upper input bit string Inp_U and the lower input bit string Inp_L is as follows: the number of bits K in the upper input bit string Inp_U + the number of bits M in the lower input bit string Inp_L = the number of bits N in the input bit string 10BTP. Furthermore, the dividing circuit 10SPT(B) extracts M-1 bits from the least significant bit (LSB) of the input bit string 10BTP as the lower input bit string Inp_L. Furthermore, in the input bit string 10BTP, K bits from the M bit to the most significant bit MSB are extracted as an upper input bit string Inp_U by the dividing circuit 10SPT(B).

[0045] The upper input bit string Inp_U is held in a holding circuit M_HL corresponding to the main DA converter M_DAC and supplied to the input of the main DA converter M_DAC. The lower input bit string Inp_L is held in a holding circuit S_HL corresponding to the sub DA converter S_DAC and supplied to the input of the sub DA converter S_DAC. The upper input bit string Inp_U is converted to a corresponding analog value by the main DA converter M_DAC, and the lower input bit string Inp_L is converted to a corresponding analog value by the sub DA converter S_DAC. The analog value obtained by the main DA converter M_DAC and the analog value obtained by the sub DA converter S_DAC are added by an adder circuit MS_ADDW and output as an analog value 10ANG (A) corresponding to the input bit string 10BTP.

[0046] Because the upper input bit string Inp_U is made up of bits on the most significant bit (MSB) side, the analog value output from the main DA converter M-DAC changes significantly (roughly) when the bits constituting the upper input bit string Inp_U change. In contrast, because the lower input bit string Inp_L is made up of bits on the least significant bit (LSB) side, the analog value output from the sub DA converter S_DAC changes slightly (finely) when the bits constituting the lower input bit string Inp_L change.

[0047] <<Configurations of DA Converters M_DAC, S_DAC, and Adder Circuit MS_ADDW>> Next, a specific example of the main DA converter M_DAC, sub DA converter S_DAC, and adder circuit MS_ADDW shown in Fig. 2 will be described. Fig. 3 is a circuit diagram showing the configuration of the DA converter according to the first embodiment.

[0048] In the first embodiment, the main DA converter M_DAC is configured by a thermometer-type DA converter (hereinafter referred to as M_DAC), and the sub DA converter S_DAC is configured by a weighted binary-type DA converter (hereinafter referred to as S_DAC). The thermometer-type DA converter M_DAC corresponds to the first-type circuit segment SEG1 shown in FIG. 1 , and the weighted binary-type DA converter S_DAC corresponds to the second-type circuit segment SEG2. Therefore, the DA converter 10DAC(A) is a segment-type DA converter that combines the thermometer-type DA converter (first-type circuit segment) M_DAC and the weighted binary-type DA converter (second-type circuit segment) S_DAC.

[0049] The input bit string from the division circuit 10SPT(B) is supplied to control circuits (hereinafter also referred to as decoders) M_DEC and S_DEC. That is, the upper input bit string Inp_U from the division circuit 10SPT(B) is supplied to the decoder M_DEC. The decoder M_DEC outputs a plurality of complementary signals UI+ and UI- according to the code of the supplied upper input bit string Inp_U. That is, the signal UI+ is set to high level for the number of bits corresponding to the number represented by the code of the upper input bit string Inp_U, and the remaining signals UI+ are set to low level. Note that the signal UI- is complementary (inverted) to its counterpart signal UI+, and is set to low level when its counterpart signal UI+ is high level.

[0050] The lower-order input bit string Inp_L from the division circuit 10SPT(B) is supplied to the decoder S_DEC. The decoder S_DEC outputs complementary signals UB_0+, UB_0- to UB_M-1+, and UB_M-1- corresponding to the code of the supplied lower-order input bit string Inp_L. The complementary signals UB_0+, UB_0- to UB_M-1+, and UB_M-1- correspond to bit 0 (least significant bit LSB) to bit M-1 that make up the lower-order input bit string Inp_L. For example, when bit 0 has a logical value of "1," the signal UB_0+ is at a high level (UB_0- is at a low level), and when bit 0 has a logical value of "0," the signal UB_0+ is at a low level (UB_0- is at a high level). Similarly, the remaining complementary signals UB_1+, UB_1- to UB_M-1+, UB_M-1- also go to high or low level according to the logical value of the corresponding bit in the lower input bit string Inp_L.

[0051] <<<Weighted Binary DA Converter>>> The weighted binary DA converter S_DAC includes binary unit circuits (binary circuits, second type circuits) UB_0 to UB_M-1, the number of which corresponds to the number M of bit strings that make up the lower input bit string Inp_L. The binary unit circuit UB_0 corresponds to the least significant bit LSB of the lower input bit string Inp_L, and the binary unit circuits UB_1 to UB_M-1 correspond to bits 1 to M-1 in the lower input bit string Inp_L.

[0052] The binary unit circuits UB_0 to UB_M-1 have similar configurations. To explain the configuration using the binary unit circuit UB_0 corresponding to the least significant bit LSB as an example, the binary unit circuit UB_0 comprises transistors Q2 and Q3 whose drains are connected to output lines Lo+ and Lo-, and a transistor Q4 connected between the common source of the transistors Q2 and Q3 and the ground line Ls. The transistors Q2 and Q3 are turned on and off by corresponding signals UB_0+ and UB_0- from the decoder S_DEC. A reference voltage Vref is supplied to the gate of the transistor Q4. When the reference voltage Vref is supplied to the transistor Q4, a predetermined constant current 2 ０ I ｌｓｂThe transistor Q4 included in the binary unit circuit UB_0 is set, for example, in size so as to generate a constant current corresponding to the least significant bit LSB. Therefore, when the signal UB_0+ is at a high level, for example, the transistor Q2 turns on, and a predetermined constant current 2 is supplied from the output line Lo+ to the ground line Ls via the transistor Q2. ０ I ｌｓｂ will be played.

[0053] The binary unit circuits UB_1 to UB_M-1 differ from the binary unit circuit UB_0 in that the size of the transistor Q4 is set so that the value of the constant current to be formed corresponds to bits 1 to M-1 of the lower input bit string Inp_L. For example, the transistor Q4 of the binary unit circuit UB_M-1 generates a constant current 2 corresponding to bit M-1 of the lower input bit string Inp_L. Ｍ－１ I ｌｓｂ is set to flow.

[0054] As a result, in the weighted binary DA converter S_DAC, a constant current corresponding to the bit in the lower input bit string Inp_L, which has a logical value of "1", flows from the output line Lo+ to the ground line Ls via the binary unit circuit corresponding to the bit. As a result, the lower input bit string Inp_L is converted into a corresponding current value.

[0055] <<<<Thermometer-Type DA Converter>>> The thermometer-type DA converter M_DAC has thermo unit circuits (thermometer circuits, first-type circuits) UI, the number of which corresponds to the number of bits K of the upper input bit string Inp_U. That is, the thermometer-type DA converter M_DAC uses the number of bits K as an exponent to calculate a power of 2 (2^ Ｋ The thermo unit circuits UI are connected in parallel between the output lines Lo+, Lo− and the ground line Ls.

[0056] These thermo unit circuits UI have the same configuration. As shown in Figure 3, each thermo unit circuit UI includes a transistor Q1 to which a reference voltage Vref is supplied, and transistors Q2 and Q3 that operate in a complementary manner.

[0057] The transistor Q1 functions as a constant current source that generates a predetermined constant current when a reference voltage Vref is supplied to the gate. The value of the generated constant current is the current 2 corresponding to the least significant bit M in the upper input bit string Inp_U. Ｍ I ｌｓｂ is.

[0058] In the thermometer-type DA converter M_DAC, the transistors Q2 in the thermo unit circuits UI whose number is represented by the code of the upper input bit string Inp_U are turned on, so that a current corresponding to the number represented by the upper input bit string Inp_U flows from the output line Lo+ to the ground line Ls. As a result, the upper input bit string Inp_U is also converted into a corresponding current value.

[0059] As shown in FIG. 3, the output lines Lo+ and Lo- are connected to a voltage Vd via a load resistor RL. That is, the load resistor RL is common to the thermometer-type DA converter M_DAC and the binary-type DA converter S_DAC. This causes the outputs of the thermometer-type DA converter M_DAC and the binary-type DA converter S_DAC to be added together. That is, the adder circuit MS_ADDW shown in FIGS. 1 and 2 is realized by the common output lines Lo+ and Lo- and the load resistor RL.

[0060] <<<<Handling Various Binary Format Inputs>>>> The above is a description of the hybrid DA converter 10DAC(A) assuming an offset binary format or an unsigned binary format. When handling an input in two's complement binary format, a decoder circuit that converts the input two's complement binary format into offset binary format inside the converter can be disposed between the divider circuit 10SPT(B) and the input terminal. Other implementations are also possible. For example, the divider circuit 10SPT(B) may receive a bit string in two's complement binary format, divide it into an upper input bit string Inp_U and a lower input bit string Inp_L, and output them in two's complement binary format. In this case, the decoder of each segment handles the two's complement binary format. Based on the above implementation examples, the divider circuit may be considered as a circuit that outputs a K-bit internal upper bit string and an M-bit internal lower bit string based on the input value from the input terminal and the binary format expected by the element.

[0061] <DA Converter Calibration Test> As mentioned above, linearity (INL) is one of the factors related to the accuracy of a DA converter. The linearity of the DA converter 10DAC(A) shown in FIG. 1 fluctuates depending on, for example, changes in environmental temperature. In the first embodiment, in order to improve the accuracy of the DA converter 10DAC(A), a calibration test is performed by the DA converter 10DAC(A) before it actually performs a conversion operation, and the input bit string of the DA converter 10DAC(A) is corrected in the pre-stage circuit 10FNT shown in FIG. 1 based on the correction amount obtained by the calibration test.

[0062] FIG. 4 is a flowchart illustrating the operation of the DA converter 10DAC(A) according to the first embodiment. In step S0, the DA converter 10DAC(A) begins operation. Then, during a calibration period CAL, the processor 10P (FIG. 1) executes steps S0 to S3 to perform a calibration test on the DA converter 10DAC(A). That is, in step S1, the processor 10P reads a test bit string from the test data, inputs the read test bit string to the DA converter 10DAC(A) as an input bit string, and measures the output of the DA converter. In step S2, the processor 10P generates a correction amount using the output of the DA converter 10DAC(A) measured in step S1 and the test bit string. Then, in step S3, the processor 10P determines whether measurements and correction amount generation using all test bit strings have been completed. If it is determined in step S3 that processing has not been completed for all test bit strings, the processor 10P returns to step S1. That is, during the calibration period CAL, the processor 10P repeatedly executes steps S1 to S3.

[0063] After the calibration test is completed, in step S4, the DA converter 10DAC(A) performs an actual DA conversion operation.

[0064] In order to suppress fluctuations in the accuracy of the DA conversion circuit due to changes in environmental temperature and improve accuracy, it is conceivable to increase the frequency of calibration tests. However, if the calibration period CAL is long, the frequency with which the actual DA conversion operation is performed will decrease. If the calibration period CAL is long, it is conceivable to divide the calibration period CAL into multiple periods and perform calibration tests in separate periods. However, in this case, the time at which the final correction is completed will be delayed, and accuracy will decrease until the correction is completed.

[0065] The test bit string has the same number of bits as the input bit string 10BTP that is actually input to the DA converter 10DAC(A), and generally, test bit strings corresponding to all code combinations of the input bit string 10BTP are prepared as test data. That is, as described above, in the case of an input bit string 10BTP with a bit number N (number of bits in the upper input bit string: K bits + number of bits in the lower input bit string: M bits), the test bit string is multiplied by a power of 2 (2^ Ｎ ) test bit strings are prepared as test data. In order to increase the resolution of the DA converter 10DAC(A), it is necessary to increase the number of bits in the input bit string, which poses the problem of lengthening the calibration period CAL.

[0066] <Test Data> In the first embodiment, in order to shorten the calibration period CAL, a test bit string is used that takes into consideration the structure of the DA converter 10DAC(A). Here, as described with reference to FIGS. 2 and 3, a case will be described as an example in which the DA converter 10DAC(A) is configured with a thermometer-type DA converter M_DAC and a weighted binary-type DA converter S_DAC.

[0067] <<Test Bit String of Weighted Binary DA Converter>> The relationship between the lower-order input bit string Inp_L input to the weighted binary DA converter S_DAC shown in FIG. 3 and the output of the DA converter is expressed by equation (1) shown in FIG. 12. In equation (1), D ０ ~D Ｍ－１ represents the bits that make up the lower input bit string Inp_L. That is, bit D ０ corresponds to the least significant bit LSB of the lower input bit string Inp_L, and D Ｍ－１ corresponds to the most significant bit in the lower input bit string Inp_L. ０ For example, the bit D ０ When the logic value of is "1", the decoder S_DEC outputs a high-level signal UB_0+. １~D Ｍ－１ Mobit D ０ When the logic value of a bit is "1", the decoder S_DEC sets the corresponding signals UB_1+ to UB_M-1+ to high level.

[0068] In addition, in formula (1), W ０ ~W Ｍ－１ indicates the value of the constant current generated by the constant current source (transistor Q4) in the binary unit circuits UB_0 to UB_M-1. For example, the current value W ０ indicates the value of the constant current formed by the transistor Q4 of the binary unit circuit UB_0.

[0069] As can be seen from equation (1), the current value S_DA output by the weighted binary DA converter S_DAC is a constant current value when the desired bit is set to a logical value of "1" in the lower input bit string Inp_L by setting the desired bit to a logical value of "1" and all other bits to a logical value of "0". ０ The logic value of bit D is set to "1" １ ~D Ｍ－１ If all the logical values ​​of bit D are set to "0", ０ can be measured as the current value S_DA output from the weighted binary DA converter S_DAC.

[0070] Furthermore, when multiple bits in the lower input bit string Inp_L have a logical value of "1", by combining (adding) the previously measured current value S_DA with the bits having a logical value of "1", it is possible to calculate the value of the constant current output from the DA converter S_DAC when multiple bits in the lower input bit string Inp_L have a logical value of "1". For example, when the bit D ０ and Bit D １ If both bits are logic "1" and all remaining bits are logic "0", then bit D ０ The current value S_DA measured in advance for bit D １By adding the current value S_DA measured in advance to the weighted binary DA converter S_DAC, the current value S_DA output from the weighted binary DA converter S_DAC can be calculated.

[0071] In other words, if the output of the weighted binary DA converter S_DAC is measured when only one bit in the lower input bit string Inp_L has the logical value "1", this measured value can be used to calculate the output of the weighted binary DA converter S_DAC when multiple bits in the lower input bit string Inp_L simultaneously have the logical value "1".

[0072] Considering the structure of this weighted binary DA converter, in the weighted binary DA converter S_DAC according to the first embodiment, the bit D ０ ~D Ｍ－１ A bit string of M bits is used, in which one of the bits is a logical value "1" and all other bits are a logical value "0".

[0073] Furthermore, the weighted binary DA converter S_DAC may have a DC offset DC_Offset. ０ ~D Ｍ－１ A test bit string in which all the logical values ​​of are set to "0" is also used. Therefore, the number of test bit strings for the weighted binary DA converter S_DAC according to the first embodiment is M+1.

[0074] <<Test bit string for thermometer-type DA converter>> In the thermometer-type DA converter M_DAC, the constant currents of the thermo unit circuits UI, the number of which corresponds to the number represented by the code of the input bit string, are added together to form the current value output from the thermometer-type DA converter M_DAC.

[0075] In the first embodiment, the test bit strings are the same as all codes that can be input to the thermometer-type DA converter M_DAC. That is, the number of test bit strings for the thermometer-type DA converter M_DAC is calculated by multiplying the number of bits K of the upper input bit string Inp_U by a power of 2 (2^ Ｋ )

[0076] As a result, during the calibration period CAL, the number of test bit sequences supplied to the DA converter 10DAC(A) (FIG. 2) according to the first embodiment is M+1, which is the number of test bit sequences for the weighted binary DA converter S_DAC, and 2^ Ｋ The sum of (M + 1 + 2^ Ｋ ), and the number of test bit sequences corresponding to all codes represented by the input bit sequence (2^ Ｎ For example, if the number of bits K of the upper input bit string Inp_U is 7, the number of bits M of the lower input bit string Inp_L is 7, and the number of bits N (=K+M) of the input bit string 10BTP is 14 (for an N-bit resolution), the number of test bit strings corresponding to all codes is 2^ １４ On the other hand, according to the first embodiment, the number of test bit strings is 7+1+2^ ７ =136. That is, during the calibration period CAL, the number of times that the test bit string is supplied to the DA converter 10DCA(A) and its output is measured can be significantly reduced to 136 times.

[0077] The test data for the thermometer-type DA converter M_DAC and the test data for the weighted binary-type DA converter S_DAC determined in this manner are stored in the non-volatile memory NVMEM or the volatile memory VOLMEM shown in FIG. 1 before the calibration test is performed.

[0078] <Calibration Test Operation> Fig. 5 is a flowchart for explaining the calibration test according to embodiment 1. Fig. 6 is a diagram for explaining the calibration test according to embodiment 1. The calibration test operation will be explained below with reference to Figs. 1, 2, 5 and 6.

[0079] 5, in step SC0, the processor 10P starts a calibration test. Here, an example is described in which the calibration test of the thermometer-type DA converter M_DAC (hereinafter also simply referred to as the DA converter M_DAC) is performed before the calibration test of the weighted binary-type DA converter S_DAC (hereinafter also simply referred to as the DA converter S_DAC), but the present invention is not limited to this. In other words, the calibration test of the DA converter S_DAC may be performed first.

[0080] In step SC1, the processor 10P reads a test bit string from the test data stored in the nonvolatile memory NVMEM or the volatile memory VOLMEM and inputs it as an upper input bit string Inp_U to the DA converter M_DAC constituting the DA converter 10DAC(A) via the pre-stage circuit 10FNT. At this time, the processor 10P inputs a bit string whose all logical values ​​are "0" (a lower input bit string of a predetermined value) as a lower input bit string Inp_L to the DA converter S_DAC constituting the DA converter 10DAC(A). The processor 10P also controls the switch 10SW (FIG. 1) so that the output of the DA converter 10DAC(A) is supplied to the AD converter 10AD.

[0081] As a result, the analog values ​​corresponding to the test bit string converted by the DA converter M_DAC are supplied to the AD converter 10AD, which converts them into a digital string corresponding to the supplied analog values ​​and supplies them to the processor 10P as the test result bit string 10BTTR (Figure 1).

[0082] In step SC2, the processor 10P compares the test bit string supplied to the DA converter M_DAC in step SC1 with the supplied test result bit string, and generates input / output characteristics of the DA converter M_DAC based on the test bit string. Based on the generated input / output characteristics, the processor 10P generates correction amounts so that the test result bit string matches the test bit string, and stores the correction amounts in the memory of the front-stage circuit 10FNT as correction data (correction data D in FIG. 1). At this time, the processor 10P stores the generated correction amounts so as to form a pair with the supplied test bit string.

[0083] Next, in step SC3, the processor 10P determines whether the test using all test bit sequences has been completed for the DA converter M_DAC. This is achieved by the processor 10P determining whether all test data to be supplied to the DA converter M_DAC has been read from the nonvolatile memory NVMEM or the volatile memory VOLMEMTHM. If the processor 10P determines that the test using all test bit sequences has not been completed, the processor 10P returns to step SC1, reads the test bit sequences that have not been read, and repeats steps SC1 to SC3.

[0084] The output voltage range represented by the input bit string Input input to the DA converter 10DAC(A) is divided into multiple blocks 1 to 128 by the code of the upper input bit string Inp_U input to the DA converter M_DAC, as shown in the table on the left side of FIG. 6 . The code of the upper input bit string Inp_U indicates a base voltage value specific to each block, while the code of the lower input bit string Inp_L indicates a voltage value common to all blocks. For example, if the upper input bit string Inp_U has a logical value of "0x8000," block 1 is identified, and this upper input bit string Inp_U indicates the base voltage VB1B of block 1. If the upper input bit string Inp_U has a logical value of "0x0000," block 65 is identified, and this upper input bit string Inp_U indicates the base voltage VB65B of block 65.

[0085] The analog value 10ANG(A) output from the DA converter 10DAC(A) after converting the input bit string is expressed by equation (2) shown in FIG. 12 . In equation (2), VB(i) represents the base voltage indicated by the upper input bit string Inp_U. As can be seen from equation (2), the analog value 10ANG(A) corresponding to the input bit string 10BTP is obtained by adding the common voltage value indicated by the code of the lower input bit string Inp_L to the base voltage value specified by the code of the upper input bit string Inp_U. Therefore, in step SC1, by inputting a predetermined value (all logical values ​​"0") as the lower input bit string Inp_L to the DA converter S_DAC, the upper input bit string Inp_U represents the base voltage VB(i) of the block indicated by the upper input bit string.

[0086] In FIG. 6 , the graph on the right shows the relationship between block number and base voltage. In the graph, the horizontal axis represents block number, and the vertical axis represents base voltage. Although not particularly limited, as can be seen from this graph, the DA converter 10DAC(A) according to embodiment 1 converts the input bit string 10BTP into positive and negative voltages with respect to ground voltage (0 V). Furthermore, the DC offset DC_Offset is set to the value when the base voltage is at block number 65, which corresponds to ground voltage (0 V), at which output noise is reduced. That is, the DC offset DC_Offset is the output value of the DA converter 10DAC(A) when a test bit string corresponding to the logical value "0x000" is supplied to the DA converter 10DAC(A). In other words, the lower input bit string Inp_L is set to a predetermined value (all logical values ​​are "0"), and the upper input bit string Inp_U is also set to a predetermined value (all logical values ​​are "0") to obtain the DC offset DC_Offset.

[0087] Next, a calibration test for the DA converter S_DAC will be described.

[0088] After step SC3, the processor 10P executes step SC4. In step SC4, the processor 10P reads a test bit string related to the DA converter S_DAC stored in the nonvolatile memory NVMEM or the volatile memory VOLMEM, and inputs it to the DA converter S_DAC as the lower input bit string Inp_L. At this time, the processor 10P inputs a bit string whose all logical values ​​are "0" (an upper input bit string of a predetermined value) as the upper input bit string Inp_U to the DA converter M_DAC. The processor 10P also controls the switch 10SW so that the output of the DA converter 10DAC(A) is supplied to the AD converter 10AD.

[0089] As a result, an analog value corresponding to the test bit string converted by the DA converter S_DAC is supplied to the AD converter 10AD, which converts it into a corresponding digital string and supplies it to the processor 10P as the test result bit string 10BTTR.

[0090] In step SC5, the processor 10P compares the test bit string supplied to the DA converter S_DAC in step SC3 with the supplied test result bit string, and generates input / output characteristics of the DA converter S_DAC based on the test bit string. Based on the generated input / output characteristics, the processor 10P generates correction amounts so that the test result bit string matches the test bit string, and stores the correction amounts in the memory of the front-stage circuit 10FNT as correction data (correction data D in FIG. 1). At this time, the processor 10P stores the generated correction amounts so as to form a pair with the supplied test bit string.

[0091] Next, in step SC6, the processor 10P determines whether testing of all test bit sequences has been completed for the DA converter S_DAC. This determination can be made, for example, in a manner similar to that of step SC3 described above. If the processor 10P determines in step SC6 that all test bit sequences have not been read, the processor 10P returns to step SC4, reads the test bit sequences that have not been read, and repeats steps SC4 to SC6.

[0092] After step SC6 is completed, the processor 10P completes the calibration test operation in step SC7.

[0093] Fig. 7 is a diagram for explaining the correction amounts according to the first embodiment. Fig. 7 shows an example of the correction amounts generated by the processor 10P by executing the calibration test described in Fig. 6 and stored as correction data (correction data D) in the pre-stage circuit 10FNT.

[0094] 7, THM_D corresponds to the DA converter M_DAC and indicates an area in which a plurality of correction amounts generated by executing steps SC1 to SC3 are stored, and BW_D corresponds to the DA converter S_DAC and indicates an area in which a plurality of correction amounts generated by executing steps SC4 to SC6 are stored. As shown in FIG. 7, the correction amount of the DC offset DC_Offset is stored in the area BW_D.

[0095] In the area THM_D, the column M_DAC_Code indicates an area where a test bit string corresponding to the upper input bit string Inp_U is stored, and the column THM_C indicates an area where a correction amount is stored. In FIG. 7 , the area THM_C stores the correction amount of the block number corresponding to the test bit string. In the area TMH_D, the test bit string and the correction amount are stored in pairs so as to correspond to each other. For example, the correction amount of block number 1 is stored in pair with the test bit string "0x8000" indicating block number 1.

[0096] In the area BW_D, the column S_DAC_Code indicates an area where a test bit string corresponding to the lower input bit string Inp_L is stored, and BW_C indicates an area where a correction amount for a bit number corresponding to the test bit string is stored. For example, the correction amount for bit 1 is stored as a pair with the test bit string "0x0001" in which only bit 1 has a logical value of "1." Note that a DC offset DC_Offset is stored as a pair as correction data corresponding to the test bit string "0x0000."

[0097] <Correction> Next, the correction performed in the front-stage circuit 10FNT will be described with reference to Fig. 8. Fig. 8 is a block diagram showing the configuration of a bit string correction circuit according to the first embodiment.

[0098] The bit string correction circuit 10BCT includes a table THM_T corresponding to the upper input bit string Inp_U, a table BW_T corresponding to the lower input bit string Inp_L, and adders ADD1 and ADD2.

[0099] The processor 10P transmits the test bit strings and the correction amounts of the block numbers stored in the area THM_D (FIG. 7) to the table THM_T, and transmits the test bit strings and the bit correction amounts stored in the area BW_D (FIG. 7) to the table BW_T. As a result, as shown in FIG. 8, the test bit strings corresponding to the upper input bit string Inp_U and the corresponding correction amounts are registered as pairs in the table THM_T, and the test bit strings corresponding to the lower input bit string Inp_L and the corresponding correction amounts are registered as pairs in the table BW_T.

[0100] The table THM_T is searched by the upper input bit string Inp_U of the input bit string 10BTP, and the table THM_T outputs a correction amount corresponding to the test bit string that matches the upper input bit string Inp_U. The output correction amount is supplied to the adder ADD1.

[0101] Furthermore, the table BW_T is searched by the lower input bit string Inp_L of the input bit string 10BTP. In this search, a test bit string is searched for in which the same bit number as the bit number with a logical value of "1" in the lower input bit string Inp_L is set to a logical value of "1". As a result of the search, a correction amount corresponding to the test bit string in which the logical value of the same bit number is set to "1" is output from the table BW_T. In the lower input bit string Inp_L of the input bit string 10BTP, multiple different bit numbers may simultaneously have a logical value of "1". In this case, multiple correction amounts are output from the table BW_T. To accommodate this, the correction amounts output from the table BW_T are digitally summed. The summed correction amount is supplied to the adder ADD1.

[0102] The adder ADD1 adds the correction amount from the table THM_T and the correction amount (sum of the correction amounts) from the table BW_T, and supplies the result to the adder ADD2. The adder ADD2 adds the input bit string 10BTP and the correction amount from the adder ADD1, and supplies the result to the input of the DA converter 10DAC(A).

[0103] As a result, the main input bit string 10BTB supplied to the DA converter 10DAC(A) is corrected by the pre-stage circuit 10FNT based on the correction amount determined in the calibration test. In other words, the input bit string input to the DA converter 10DAC(A) is corrected based on the input / output characteristics of the DA converter 10DAC(A), thereby improving accuracy.

[0104] Since the number of test bit strings used in the calibration test can be reduced, the calibration period CAL can be shortened, and therefore the interval between calibration tests can be shortened to accommodate fluctuations in the environmental temperature.

[0105] Furthermore, since the number of correction amounts to correspond to the lower input bit string Inp_L is the number of bits M+1 that constitute the lower input bit string Inp_L, it is possible to prevent the table BW_T and the area BW_D of the memory 100 from becoming large.

[0106] In the first embodiment, the bit string correction circuit 10BCT of the front-stage circuit 10FNT includes an adder, as shown in Fig. 8, but the adder may be omitted. This can be realized by, for example, registering in the tables THM_T and BW_T not only the correction amount but also a value obtained by adding the value indicated by the original processor output bit string 10BTP to the correction amount, and outputting the value obtained by correcting the processor output bit string from the bit string correction circuit 10BCT.

[0107] Furthermore, the DA converter 10DAC(A) may be configured with a plurality of DA converters, a plurality of dividing circuits, and a plurality of weighted addition circuits.

[0108] 4 and 5 show an example in which the test result bit string corresponding to the test bit string is measured and the process of generating a correction amount is repeated, but the method of generating the correction amount is not limited to this. For example, a target DA conversion relationship may be created by regression analysis (linear regression) to generate a correction amount. In other words, all measurements may be performed and then the correction amount may be generated.

[0109] In the first embodiment, an example in which correction data is created by a calibration test has been described, but the present invention is not limited to this. That is, for example, already created correction data may be updated by a calibration test. In this case, the preceding circuit performs correction based on the updated correction data. In the following description, both creation and updating of correction data may be referred to as updating of correction data.

[0110] In the first embodiment, the correction data is updated or the test input value is generated based on the relationship between the bit group contained in the bit string input to the DA converter 10DAC(A) and the first type circuit segment SEG1 and the second type circuit segment SEG2.

[0111] In addition, in the first embodiment, an example has been described in which uncorrected values ​​are used as the test input values ​​of the test pair, but this is not limiting. For example, a calibration test may be performed using already corrected values ​​as the test input values.

[0112] As shown in FIG. 2, the divided circuit 10SPT(B) outputs K internal upper bits (Inp_U) to the first-type circuit segment (M_DAC) and M internal lower bits (Inp_L) to the second-type circuit segment (S_DAC). The calibration test includes a type 1 test for determining the DA conversion characteristics of the first-type circuit segment (M_DAC) and a type 2 test for determining the DA conversion characteristics of the second-type circuit segment (S_DAC). In this case, the type 1 test input value used in the type 1 test is a value adjusted so that the internal lower-order bit sequence becomes the second fixed bit sequence (predetermined value input in step SC1), as shown in FIG. 5. The type 2 test input value used in the type 2 test is a value adjusted so that the internal upper-order bit sequence becomes the first fixed bit sequence (predetermined value input in step SC4), as shown in FIG. 5. This makes it possible to reduce the influence of the second type circuit segments during the first type test, and reduce the influence of the first type circuit segments during the second type test.

[0113] Furthermore, in the calibration test, an offset measurement test is performed to obtain an analog value independent of the values ​​of the internal upper bit string and the internal lower bit string, as shown in Fig. 6. In this case, the first fixed bit string and the second fixed bit string of "0x0000" are input to the first type circuit segment (M_DAC) and the second type circuit segment (S_DAC), as shown in Fig. 6.

[0114] The calibration test according to the first embodiment can be considered not to include a first reduced-target test using a first reduced-target test input value, where the internal upper bit sequence is a value other than the first fixed bit sequence (M_DAC in FIG. 5: predetermined value input) and the internal lower bit sequence is a value other than the second fixed bit sequence (S_DAC in FIG. 5: predetermined value input).

[0115] Furthermore, the calibration test according to the first embodiment can be considered to include a first reduced-target test using a first reduced-target test input value, where the internal upper bit sequence of the first reduced-target test input value is a value other than the first fixed bit sequence and the internal lower bit sequence is a value other than the second fixed bit sequence, and the number of test pairs used in the first reduced-target test is 2 to the power of N - (2 to the power of K + 2 to the power of M + 1).

[0116] 3, the decoder M_DEC can be considered as a selector that selects one of a plurality of first-type circuits UI. In this case, the selector supplies an active signal (high-level signal UI+) to the selected first-type circuit and an inactive signal (high-level signal UI-) to the unselected first-type circuits. Considering the active / inactive states of the first-type circuit and the second-type circuit shown in FIG. 3, updating of correction data or generation of test input values ​​is performed based on the relationship between the bit group included in the bit string input to the DA converter 10DAC(A) and the active / inactive states of the first-type circuit and the second-type circuit.

[0117] The number of test pairs obtained in the calibration test is equal to or greater than the total number of the first type circuits and the second type circuits described with reference to FIG.

[0118] In FIG. 8, table THM_T can be considered as a first table that manages the amount of correction resulting from the first type circuit segment, and table BW_T can be considered as a table that manages the amount of correction resulting from the second type circuit segment.

[0119] Although the example in which the processor output bit string 10BTP is used as the test bit string has been shown, the main body input bit string 10BTB may also be used as the test bit string.

[0120] (Embodiment 2) In embodiment 1, a device using one DA converter 10DAC(A) was described. In embodiment 2, a device using multiple DA converters will be described. That is, embodiment 2 describes a case in which the main circuit 10BDY includes an additional DA converter 10DAC(B) in addition to the DA converter 10DAC(A). By adding the DA converter 10DAC(B), it is possible to increase the number of bits that can be input to the DA converter. In this case, as described above, the main circuit 10BDY further includes a division circuit 10SPT(A) and a weighted addition circuit 10ADDW.

[0121] 9 is a block diagram showing the configuration of a device according to the second embodiment. In FIG. 9, a main circuit 10BDY and a front-stage circuit 10FNT according to the second embodiment are shown.

[0122] 9, the main circuit 10BDY includes a DA converter 10DAC(A), a DA converter 10DAC(B), and a weighted addition circuit 10ADDW. As shown in FIG. 2, the DA converter DAC(A) is configured with a division circuit, holding circuits M_HL and S_HL, a main DA converter M_DAC, a sub DA converter S_DAC, and an addition circuit MS_ADDW. In the DA converter DAC(A) according to the second embodiment, a division circuit 10SPT(B) provided in the main circuit 10BDY is used as the division circuit.

[0123] The outputs of the DA converters 10DAC(A) and 10DAC(B) are added by an adder circuit 10ADDW and supplied as an analog value to the amplifier circuit AMP or the AD converter 10AD via the switch 10SW ( FIG. 1 ). In the second embodiment, although not particularly limited, the adder circuit 10ADDW includes a gain amplifier 10M_GP to which the output from the DA converter 10DAC(A) is supplied, a gain amplifier 10S_GP to which the output from the DA converter 10DAC(B) is supplied, and an adder ADDW that adds the outputs of the gain amplifiers 10M_GP and 10S_GP and outputs the sum.

[0124] <Previous Stage Circuit> As shown in Fig. 9, the previous stage circuit 10FNT includes a bit string correction circuit 10BCT, a division circuit 10SPT(B), holding circuits 10M_HL and 10S_HL, and an adder ADD4. Note that in the first embodiment, the bit string correction circuit 10BCT mainly uses the adder ADD2 in Fig. 8 to add and output the processor output bit string 10BTP. On the other hand, in the second embodiment, as shown in Fig. 9, the bit string correction circuit 10BCT does not perform such addition. This is because the adder ADD4 performs a similar role.

[0125] The divided circuit 10SPT(B) is supplied with a processor output bit string 10BTP from the processor 10P. Although not particularly limited, the following description will be given taking as an example a case where the processor output bit string 10BTP is 32 bits. In other words, the processor 10P supplies a bit string to the preceding circuit 10FNT with 32 bits parallel in time as one bit string.

[0126] The dividing circuit 10SPT(B) divides the supplied 32-bit processor output bit string 10BTP into an upper bit string U_Input and a lower bit string L_Input. Here, the upper bit string U_Input is made up of 16 bits on the most significant bit (MSB) side of the processor output bit string 10BTP, and the lower bit string L_Input is made up of 16 bits on the least significant bit (LSB) side of the processor output bit string 10BTP. Of course, 32 bits and 16 bits are merely examples and are not limiting.

[0127] The upper bit string U_Input is held by a holding circuit 10M_HL and input to a DA converter 10DAC(A). Meanwhile, the lower bit string L_Input is held by a holding circuit 10S_HL and supplied to an adder ADD4. The output of the adder ADD4 is input to a DA converter 10DAC(B). The outputs of the DA converters 10DAC(A) and 10DAC(B) are added by a weighting addition circuit 10ADDW and output as, for example, an analog value 10ANG(A).

[0128] The bit string correction circuit 10BCT includes tables THM_T and BW_T and an adder ADD3. The table (first table) THM_T and the table (second table) BW_T are searched using the upper bit string U_Input, and the correction amount found by the search is added by the adder ADD3. The addition result of the adder ADD3 is supplied to the adder ADD4. Therefore, the adder ADD4 adds the correction amount from the bit string correction circuit 10BCT to the lower bit string L_Input. In other words, the lower bit string L_Input is corrected by the correction amount from the bit string correction circuit 10BCT.

[0129] The DA converter 10DAC(A) according to the second embodiment is configured by the segment type DA converter described with reference to Figures 2 and 3. That is, the DA converter 10DAC(A) includes a thermometer type DA converter M_DAC and a weighted binary type DA converter S_DAC.

[0130] In the second embodiment, correction is performed on the DA converter 10DAC(A), whose voltage varies greatly depending on the value of the input bit string. Therefore, during the calibration period CAL, a test bit string suitable for the configuration of the thermometer-type DA converter M_DAC and the weighted binary-type DA converter S_DAC that make up the DA converter 10DAC(A) is supplied to the DA converter 10DAC(A) from the processor 10P ( FIG. 1 ) as the upper bit string U_Input.

[0131] That is, in the same manner as described in the first embodiment, test data composed of a test bit string derived from the structure of the thermometer-type DA converter M_DAC that constitutes the DA converter 10DAC(A), and test data composed of a test bit string derived from the structure of the weighted binary-type DA converter S_DAC that constitutes the DA converter 10DAC(A) are prepared in advance.

[0132] Using the prepared test data, as described in the first embodiment, the processor 10P supplies the test bit string to the DA converter 10DAC(A) via the pre-stage circuit 10FNT, and generates correction amounts based on the test result bit string from the AD converter 10AD (FIG. 1) and the test bit string. The processor 10P then registers, among the generated correction amounts, the correction data related to the thermometer-type DA converter M_DAC in table THM_T, and the correction data related to the weighted binary-type DA converter S_DAC in table BW_T. As a result, the test bit strings and correction amounts are registered in the tables THM_T and BW_T of the bit string correction circuit 10BCT shown in FIG. 9, similar to the tables shown in FIG. 7.

[0133] The upper bit string U_Input is divided into an upper input bit string Inp_U for the thermometer type DA converter M_DAC that constitutes the DA converter 10DAC(A), and a lower input bit string Inp_L for the weighted binary type DA converter S_DAC that constitutes the DA converter 10DAC(A).

[0134] The table THM_T is searched by the divided upper input bit string Inp_U, and the table THM_T is searched by the divided lower input bit string Inp_L. The correction amounts found by searching in each table are added by an adder ADD3 and supplied to an adder ADD4.

[0135] FIG. 10 is a diagram illustrating a correction table according to the second embodiment. FIG. 10 is similar to FIG. 8 . The difference is that the upper bit string U_Input to be input to the DA converter 10DAC(A), which is the target of correction, is used to search the tables THM_T and BW_T. Another difference from FIG. 8 is that the correction amount found by the search is added by an adder ADD3 and then output to the adder ADD4 in FIG. 9 .

[0136] 9, the adder ADD4 adds the lower bit string L_Input to the correction amount output from the bit string correction circuit 10BCT, and the lower bit string corrected to correct the DA converter 10DAC(A) is input to the DA converter 10DAC(B). As a result, as in the first embodiment, it is possible to reduce the number of test bit strings and increase the frequency of calibration, thereby preventing large fluctuations in accuracy due to fluctuations in environmental temperature, etc. Furthermore, because the number of test bit strings is reduced, it is also possible to prevent the bit string correction circuit 10BCT from becoming larger.

[0137] 9, the DA converter 10DAC(B) is also configured as a segment type DA converter, but the DA converter 10DAC(B) does not have to be a segment type DA converter.

[0138] Third Embodiment In a third embodiment, the input path of the AD converter 10AD shown in FIG. 1 is changed. That is, in FIG. 1, the output of the amplifier circuit AMP is supplied to the AD converter 10AD via an attenuator. As a result, the analog value that has been made into a high voltage by the amplifier circuit 1403 is attenuated by the attenuator 1100 and supplied to the AD converter 1406, making it possible to prevent the AD converter 1406 from being destroyed by the high voltage.

[0139] In the third embodiment, during the calibration period CAL, a correction amount is generated based on the test bit string, which is an integration of the input / output characteristics of the DA converter DAC(A) and the input / output characteristics of the amplifier circuit AMP, and the generated correction amount is registered as a table in the bit string correction circuit 10BCT.

[0140] As a result, the bit string correction circuit 10BCT corrects the bit string input to the DA converter DAC(A) with a correction amount that takes into account the input / output characteristics of both the DA converter DAC(A) and the amplifier circuit AMP. As a result, it is possible to improve the accuracy of the analog value output from the amplifier circuit AMP. Of course, even when two DA converters 10DAC(A) and 10DAC(B) are used, as in the second embodiment, the input / output characteristics of the amplifier circuit AMP may be taken into account in a similar manner.

[0141] Fourth Embodiment In a fourth embodiment, a charged particle beam device will be described as an example of a device having a DA converter.

[0142] 11 is a schematic diagram showing the configuration of a charged particle beam apparatus according to embodiment 4. In embodiment 4, the charged particle beam apparatus is an electron microscope apparatus using an electron beam, but the present invention is not limited to this and may be, for example, an ion microscope apparatus using an ion beam.

[0143] 11, a charged particle beam device 1100 is shown. The charged particle beam device 1100 generally irradiates a sample 1117 with an electron beam (charged particle beam) B1 emitted from an electron gun (charged particle gun) 1106, and detects the amount of electrons (specifically, secondary electrons and backscattered electrons) B2 emitted from the sample 1117 with a detector 1114.

[0144] The charged particle beam device 1100 shown in Figure 11 includes a main body 1101, a control unit 1119, multiple power supply circuits 1103a, 1103b, 1103c, and 1103d, and an image processing unit 1118. The main body 1101 includes a housing 1104 and a sample chamber 1105. The housing 1104 houses an electron gun (charged particle gun) 1106, a condenser lens 1110, a reflector 1111, a deflector 1112, an objective lens 1113, a detector 1114, and a boost electrode 1115. The electron gun 1106 includes an electron source (charged particle source) 1107, an extraction electrode 1108, and an acceleration electrode 1109. The sample chamber 1105 houses a stage 1116 on which a sample 1117 is placed.

[0145] The housing 1104 is made of metal and is connected to a ground power supply Vs. The power supply circuit 1103a generates a negative acceleration voltage V0 and supplies it to the electron source 1107. The power supply circuit 1103b generates a positive extraction voltage based on the voltage (V0) of the electron source 1107 and supplies it to the extraction electrode 1108. The electron source 1107 emits an electron beam (charged particle beam) B1 using this extraction voltage. The acceleration electrode 1109 is connected to the ground power supply Vs. Accordingly, a positive acceleration voltage V0 is applied to the acceleration electrode 1109 when the electron source 1107 is used as the reference. The electron beam B1 emitted from the electron source 1107 is accelerated by this acceleration voltage V0.

[0146] The condenser lens 1110 focuses the electron beam B1 emitted from the electron gun 1106. The objective lens 1113 focuses the electron beam B1 so that it forms a minute spot on the sample 1117. At this time, the power supply circuit 1103d generates a positive boost voltage Vb and supplies it to a boost electrode 1115 installed near the condenser lens 1110. Accordingly, the electron beam B1 accelerated by the acceleration voltage V0 is further accelerated by the boost voltage Vb. This enables the electron beam B1 to have even higher resolution.

[0147] The deflector 1112 is a magnetic deflector or an electrostatic deflector, and deflects the electron beam B1 focused by the objective lens 1113, thereby scanning the electron beam B1 (i.e., a microscopic spot) irradiated on the sample 1117. The power supply circuit 1103c generates a negative returning voltage Vr and supplies it to the stage 1116. Accordingly, the electron beam B1 that has passed through the objective lens 1113 is decelerated by the returning voltage Vr. This makes it possible to reduce damage to the sample 1117.

[0148] The electron beam B1 is given energy of, for example, several tens of kV by the acceleration voltage V0 and the boost voltage Vb. The returning voltage Vr reduces the energy of the electron beam B1 to, for example, 1 kV or less. In this way, the energy of the electron beam B1 is determined appropriately by the power supply circuits 1103a to 1103d. However, the power supply circuit 1103d and the boost electrode 1115 may not be provided.

[0149] In response to irradiation with the electron beam B1, the sample 1117 emits electrons (specifically, secondary electrons, backscattered electrons) B2. The emitted electrons B2 are accelerated toward the electron source 1107 by the returning voltage Vr and the boost voltage Vb and collide with the reflector 1111. As a result, the reflector 1111 emits secondary electrons. The detector 1114 detects the amount of emitted secondary electrons.

[0150] The control unit 1119 is composed of, for example, a wiring board (control board) on which various ICs (Integrated Circuits) including processors and the like are mounted. The control unit 1119 controls the voltage values ​​of the power supply circuits 1103a to 1103d. The control unit 1119 also controls the deflector 1112, the objective lens 1113, and the like. The control unit 1119 also processes the output signal from the detector 1114 using a predetermined signal processing circuit. At this time, the control unit 1119 synchronizes the control signal to the deflector 1112 with the output signal from the detector 1114 to create original data for creating a secondary electron image of the scanned area. Note that the control unit 1119 does not necessarily need to be mounted entirely on a single board. The control unit 1119 may also include components included in a computer, such as volatile memory or non-volatile memory.

[0151] The image processing unit 1118 is configured, for example, by a computer such as a PC (Personal Computer) configured with various ICs including a processor, etc. The image processing unit 1118 acquires original data of the secondary electron image from the control unit 1119 and creates a secondary electron image based on the original data. The image processing unit 1118 also displays the created secondary electron image on a display, etc. The secondary electron image is an image in which the brightness varies depending on the amount of secondary electrons emitted at each position within the scanning area.

[0152] In the charged particle beam system 1100 according to the fourth embodiment, the control unit 1119 includes the pre-stage circuit 10FNT, the main circuit 10BDY, the AD converter 10AD, and the like described in the first to third embodiments. Here, an example will be described in which the main circuit 10BDY described in the second embodiment is used to control the deflector 1112, but the present invention is not limited to this, and the DA converter can be used to control various parts of the charged particle beam system 1100. It goes without saying that the DA converter used may be the one described in the first or third embodiment.

[0153] In FIG. 11 , 1120 denotes a DA conversion circuit. The DA conversion circuit 1120 includes the pre-stage circuit 10FNT shown in FIG. 9 , the main circuit 10BDY, and an amplifier circuit AMP (corresponding to the amplifier circuit AMP in FIG. 1 ) that amplifies the output of the main circuit 10BDY. The deflection signal Scn is input to the DA conversion circuit 1120 as an input bit string Input, which converts the deflection signal Scn to an analog value, which is then amplified by the amplifier circuit. The amplified analog value of the deflection signal Scn is applied to the deflector 1112. The DA conversion circuit 1120 may also include an AD converter 10AD and a processor 10P ( FIG. 1 ) used for calibration. In this case, the processor 10P may also be included in the control device 1119.

[0154] By linearly increasing (decreasing) the value of the deflection signal Scn over time, the analog value applied to the deflector 1112 also linearly increases (decreases), which changes the magnetic field or electric field generated by the deflector 1112, causing the electron beam B1 to move over the sample 1117.

[0155] If the linearity of the DA converter fluctuates due to, for example, fluctuations in the environmental temperature, the magnetic field or electric field generated by the deflector 1112 will also fluctuate due to fluctuations in the environmental temperature. As a result, the distance that the electron beam B1 travels on the sample 1117 will change, causing stretching and shrinking of the created secondary electron image. In particular, when the observation range is wide at low resolution, the stretching and shrinking of the image due to fluctuations in the environmental temperature becomes significant.

[0156] As described above, by performing calibration, a correction amount for the DA conversion circuit including the amplifier circuit is generated, the bit string input to the DA conversion circuit is corrected, and linearity is improved. Moreover, according to the embodiment, since the calibration period CAL can be shortened, even if the frequency of calibration is increased to deal with fluctuations in environmental temperature, it is possible to reduce the shortening of the time required to observe the sample using the charged particle beam device 1100. Of course, calibration may be performed multiple times rather than forming all the correction amounts in one go.

[0157] In FIG. 11 , only one pair of deflectors 1112 is shown because the housing 1104 is viewed from the side. However, two pairs of deflectors 1112 are provided in the housing 1104 to move the electron beam B1 in the X and Y directions (two directions that are substantially perpendicular to each other) on the sample 1117. Since the DA converter circuit 1120 supplies an analog signal to the pair of deflectors 1112 in accordance with the deflection signal Scn, the control unit 1119 is provided with two pairs of DA converter circuits 1119 corresponding to the two pairs of deflectors. In this case, a calibration test can be performed simultaneously on both pairs of DA converter circuits, thereby preventing the test time from becoming too long. Note that the characteristics of the two pairs of DA converter circuits are not necessarily identical, making it difficult to share correction data between the two pairs of DA converter circuits.

[0158] In the fourth embodiment, a charged particle beam device has been described as an example of a device having a DA converter, but the device 1 is not limited to this.

[0159] In the first and second embodiments, an example was shown in which two tables THM_T and BW_T are used as the bit string correction circuit 10BCT, but this is not limiting. For example, the bit string correction circuit 10BCT may be provided with one table (for convenience, referred to as U_TB). Using the examples of FIGS. 9 and 10, the bit string correction circuit 10BCT is provided with a table searched by the upper bit string U_Input. During the calibration period CAL, multiple test bit strings corresponding to all codes of the upper bit string U_Input are supplied to the DA converter 10DAC(A). That is, using the number of bits N (=16 bits) of the upper bit string U_Input as an exponent, 2^ Ｎ Test bit strings are prepared in advance. During the calibration period CAL, the processor 10P sequentially supplies the test bit strings to the DA converter 10DAC(A), which then compares them with the test result bits from the AD converter 10AD and generates a correction amount corresponding to the test bit string. The processor 10P registers the generated correction amount in the table U_TB. This results in the table U_TB being configured with the upper bit string U_Input corresponding to the test bit string and the correction amount.

[0160] When the DA converter 10DAC(A) is actually used, the upper bit string U_Input is converted into an analog value by the DA converter 10DAC(A) and supplied to the bit string correction circuit 10BCT. The upper bit string U_Input supplied to the bit string correction circuit 10BCT is used to search the table U_TB, where it is converted into a correction amount, which is added to the lower bit string L_Input, which is then converted into an analog value by the DA converter 10DAC(B), and added to the analog value from the DA converter 10DAC(A).

[0161] By configuring the bit string correction circuit 10BCT in this way, during the calibration period CAL, Ｎ Based on the test bit sequences, 2^ ＮHowever, it is possible to correct the input bit string of the DA converter 10DAC(B) by taking into account the input / output characteristics of the DA converter 10DAC(A) without taking into account the configuration of the DA converter 10DAC(A).

[0162] FIG. 13 shows a modification of the second embodiment shown in FIG. 9 , which includes one table as described above. Hereinafter, this modification will be referred to as a modification of the second embodiment. It should be noted that the configuration of FIG. 13 may also be applied to a bit string correction circuit 10BCT including two tables as shown in FIG. 8. In the first embodiment, the bit string correction circuit 10BCT mainly uses the adder ADD2 of FIG. 8 to add and output the processor output bit string 10BTP. On the other hand, in the second embodiment, as shown in FIG. 9, the bit string correction circuit 10BCT does not perform such addition. This is because the adder ADD4 performs a similar role. The explanation of the second embodiment may also be applied to this modification.

[0163] In the first to fourth embodiments, an example has been described in which, in a segment-type DA converter, the main DA converter M_DAC that converts the upper input bit string Inp_U is configured as a thermometer-type DA converter, and the sub DA converter S_DAC that converts the lower input bit string Inp_L is configured as a weighted binary DA converter, but this is not limitative. That is, the main DA converter M_DAC that converts the upper input bit string Inp_U may be configured as a weighted binary DA converter, and the sub DA converter S_DAC that converts the lower input bit string Inp_L may be configured as a thermometer-type DA converter.

[0164] In terms of binary format, endian, and encoding for communication, the bit string generated by the processor, the bit string output by the processor when generated, the bit string input / output by the preceding circuit, the bit string input to the main circuit, the bit string input to the DA converter, and the bit string inside the DA converter may be the same or different. For example, when a DA conversion target value is generated inside the processor, when the DA conversion target value is output from the processor 10P as the processor output bit string 10BTP, when the DA conversion target value corrected by the preceding circuit is output, and when the corrected DA conversion target value is input to the main circuit 10BDY or the DA converter 10DAC(A), each of these may be different (in terms of binary format, endian, and encoding for communication).

[0165] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0166] The following has been described in this specification. 1. A device comprising at least a processor that outputs a DA conversion target value; a front-stage circuit that receives the DA conversion target value from the processor, corrects it in accordance with correction data, and outputs it; a main circuit that includes one or more correction target DA converter elements and performs DA conversion of the corrected DA conversion target value; and an AD converter, wherein the correction target DA converter elements are hybrid DA converter elements that output from an output terminal an analog value obtained by adding an analog value output by a first type circuit segment responsible for a higher order and an analog value output by a second type circuit segment responsible for a lower order, and wherein as a calibration test for creating or updating the correction data, the processor: (A) acquires a plurality of test pairs that are pairs of test input values ​​and test result values ​​having the following characteristics: (A1) the test input values ​​are values ​​that are input to the main circuit as the DA conversion target value with or without correction, and (A2) the test result values ​​are values ​​obtained by AD converting, by the AD converter, an analog value output by inputting the test input values ​​to the main circuit, (B) updating the correction data based on the plurality of test pairs of (A), wherein the number of test pairs acquired during the calibration test period is smaller than the Nth power of 2, and N is the number of bits indicating the resolution of the DA converter element to be corrected.

[0167] It has also been explained that the device may be as follows: (B) The updating of the correction data or the generation of the test input value is performed based on the following for an input terminal bit string, which is a bit string input to the input terminal of the DA converter element to be corrected: a relationship between 0 and 1 of a bit group included in the input terminal bit string and the first type circuit segment and the second type circuit segment.

[0168] The explanation also relates to the device as follows: the DA converter element to be corrected includes a dividing circuit that outputs a K-bit internal upper bit sequence and an M-bit internal lower bit sequence based on an input value from an input terminal and a binary format expected as input by the element, the internal upper bit sequence is input to the first type circuit segment, and the internal lower bit sequence is input to the second type circuit segment, the calibration test includes a first type test for grasping the DA conversion characteristics of the first type circuit segment and a second type test for grasping the DA conversion characteristics of the second type circuit segment, a first type test input value used in the first type test is a value adjusted so that the internal lower bit sequence becomes a second fixed bit sequence after passing through the dividing circuit, and a second type test input value used in the second type test is a value adjusted so that the internal upper bit sequence becomes a first fixed bit sequence after passing through the dividing circuit.

[0169] It has also been explained that the device may be as follows: the calibration test further includes an offset measurement test for outputting an analog value independent of the value of the internal upper bit string and the value of the internal lower bit string, and the test input value used in the offset measurement test is a value adjusted so that the internal lower bit string becomes a second fixed bit string and the internal upper bit string becomes a first fixed bit string after passing through the dividing circuit.

[0170] It has also been explained that the device may be as follows: the calibration test does not include a first reduced-target test using a first reduced-target test input value, and the first reduced-target test input value is a value adjusted to have the following characteristics after passing through the divided circuit, the internal upper bit sequence is a value other than the first fixed bit sequence, and the internal lower bit sequence is a value other than the second fixed bit sequence.

[0171] It has also been explained that the device may be as follows: the calibration test includes a first reduced-target test using a first reduced-target test input value, the first reduced-target test input value is a value adjusted to have the following characteristics after passing through the divided circuit, the internal upper bit sequence is a value other than the first fixed bit sequence, and the internal lower bit sequence is a value other than the second fixed bit sequence, and the number of test pairs used in the first reduced-target test is 2 to the Nth power - (2 to the Kth power + 2 to the Mth power + 1).

[0172] It has also been explained that the device may be as follows: the DA converter element to be corrected has a dividing circuit that outputs an internal upper bit string of K bits and an internal lower bit string of M bits based on an input value from an input terminal and a binary format assumed as input by the element, the internal upper bit string is input to the first type circuit segment, and the internal lower bit string is input to the second type circuit segment, the first type circuit segment includes a plurality of first type circuits and a selector circuit, the selector circuit is a circuit that selects one of the first type circuits according to the internal upper bit string and outputs an active signal to the selected first type circuit and an inactive signal to unselected first type circuits, each of the first type circuits includes a circuit element for outputting an analog value corresponding to the weight of the internal upper bit string and the active signal or inactive signal, the second type circuit segment has a second type circuit corresponding to each bit of the internal lower bit string and is a segment that adds up the analog values ​​output by each second type circuit to obtain an output value for the segment, the first type circuit includes a circuit element for outputting an analog value according to the weight of the bit and whether the bit is active or inactive.

[0173] It has also been explained that the device may be as follows: (B) The updating of the correction data or the generation of the test input value is performed based on the following for an input terminal bit string, which is a bit string input to the correction DA converter element at an input terminal: a relationship between 0 / 1 of a bit group included in the input terminal bit string and active / inactive of the plurality of first type circuits and the plurality of second type circuits.

[0174] It has also been explained that the device may be as follows: The number of the test pairs acquired during the calibration test period is equal to or greater than the sum of the number of the first type circuits and the number of the second type circuits.

[0175] It has also been explained that the device may be as follows: the first type circuit segment is a thermometer type circuit segment, and the second type circuit segment is a binary type or ladder type circuit segment.

[0176] The device may also be configured as follows: the pre-stage circuit stores, as the correction data, a first table for managing correction amounts derived from the first type circuit segments and a second table for managing correction amounts derived from the second type circuit segments.

[0177] It has also been explained that the device may be as follows. the main circuit is a circuit that performs DA conversion of N+1 bits or more by using a sub DA converter element that handles lower bits in addition to the DA converter element to be corrected that handles higher bits, and the preceding circuit has: a dividing circuit or dividing wiring that receives the DA conversion target value and divides it into a higher DA conversion target value and a lower DA conversion target value for output; a correction circuit that outputs a correction amount obtained from the higher DA conversion target value and the correction data; and an adding circuit that adds the correction amount and the lower DA conversion target value to output the corrected lower DA conversion target value; the DA converter element to be corrected converts the higher DA conversion target value, and the additional DA converter element converts the corrected lower DA conversion target value; and the main circuit has a weighted addition circuit that performs weighted addition of an analog value output by the DA converter element to be corrected and an analog value output by the sub DA converter element, and outputs an analog value.

[0178] The device may also be as follows: the main circuit has a wiring for outputting the analog value output by the weighted addition circuit as the main circuit output analog value.

[0179] It has also been explained that the device may be as follows: The main circuit comprises: an amplifier circuit that amplifies the analog value output by the weighted addition circuit, and wiring that outputs the analog value amplified by the amplifier circuit as the main body output analog value.

[0180] It has also been explained that the device may be as follows: the pre-stage circuit includes: a correction circuit that receives the processor output bit string and outputs a correction amount bit string based on the correction data, and an adder circuit that adds the correction amount bit string and the processor output bit string and outputs the main input bit string.

[0181] It has also been explained that the device may be as follows: The pre-stage circuit includes: a correction circuit that receives the processor output bit string and outputs the main input bit string based on the correction data.

[0182] It has also been explained that the device may be the following: A charged particle beam device including: a charged particle source that generates a charged particle beam; a deflector that deflects the charged particle beam; and the device described above as a controller that controls the deflector.

[0183] This specification also describes the following: A device having at least a main circuit including one or more DA converter elements that converts a received main body input bit string, which is a bit string, into a main body output analog value, which is an analog value, and outputs the converted bit string; a processor that outputs a processor output bit string; a pre-stage circuit that receives the processor output bit string and outputs the main body input bit string; and an AD converter, wherein the pre-stage circuit corrects the processor output bit string based on correction data and outputs the main body input bit string, and the main body circuit includes an amplifier circuit that amplifies the analog value output by the DA converter element and outputs it as the main body output analog value, and the processor: (A) acquires a plurality of pairs of test bit strings and test result bit strings having the following characteristics: (A1) the test bit string is the processor output bit string or the main body input bit string for a calibration test, (A2) the test result bit string is acquired by converting the main body output analog value with the AD converter, and (B) updates the correction data based on the plurality of pairs of (A).

[0184] 1 Device 10AD AD converter 10ADDW Weighted addition circuit 10BCT Bit string correction circuit 10BDY Main circuit 10DAC (A), 10DAC (B) DA converter 10FNT Pre-stage circuit 10P Processor 10SPT (A), 10SPT (B) Dividing circuit 1100 Charged particle beam device Inp_L Lower input bit string Inp_U Upper input bit string L_Input Lower bit string M_DAC Main DA converter S_DAC Sub DA converter U_Input Upper bit string

Claims

1. A device having at least a processor that outputs a DA conversion target value; a front-stage circuit that receives the DA conversion target value from the processor and corrects it in accordance with correction data before outputting it; a main circuit that includes one or more correction target DA converter elements and performs DA conversion of the corrected DA conversion target value; and an AD converter, wherein the correction target DA converter elements are hybrid DA converter elements that output from an output terminal an analog value obtained by adding together an analog value output by a first type circuit segment responsible for a higher level and an analog value output by a second type circuit segment responsible for a lower level, and as a calibration test for creating or updating the correction data, the processor: (A) obtains a plurality of test pairs that are pairs of test input values ​​and test result values ​​having the following characteristics: (A1) the test input value is a value that is input to the main circuit as the DA conversion target value with or without correction, and (A2) the test result value is a value obtained by AD converting, by the AD converter, an analog value output by inputting the test input value to the main circuit, (B) updating the correction data based on the plurality of test pairs of (A), wherein the number of the test pairs acquired during the calibration test period is smaller than the Nth power of 2, and N is a number of bits indicating a resolution of the DA converter element to be corrected.

2. A device as claimed in claim 1, wherein (B) updating of the correction data or generation of the test input value is performed based on the following for an input terminal bit string, which is a bit string input to the input terminal of the DA converter element to be corrected: the relationship between the bit group of 0s and 1s contained in the input terminal bit string and the first type circuit segment and the second type circuit segment.

3. An apparatus as described in claim 1, wherein the DA converter element to be corrected has a division circuit which outputs an internal upper bit string of K bits and an internal lower bit string of M bits based on an input value from an input terminal and a binary format expected to be input by the element, the internal upper bit string being input to the first type circuit segment, and the internal lower bit string being input to the second type circuit segment, the calibration test including a first type test for grasping the DA conversion characteristics of the first type circuit segment and a second type test for grasping the DA conversion characteristics of the second type circuit segment, a first type test input value used in the first type test is a value adjusted so that the internal lower bit string becomes a second fixed bit string after passing through the division circuit, and a second type test input value used in the second type test is a value adjusted so that the internal upper bit string becomes a first fixed bit string after passing through the division circuit.

4. An apparatus according to claim 3, wherein the calibration test further includes an offset measurement test for outputting an analog value independent of the value of the internal upper bit string and the value of the internal lower bit string, and a test input value used in the offset measurement test is a value adjusted so that the internal lower bit string becomes a second fixed bit string and the internal upper bit string becomes a first fixed bit string after passing through the division circuit.

5. An apparatus according to claim 4, wherein the calibration test does not include a first reduced target test using a first reduced target test input value, and the first reduced target test input value is a value adjusted to have the following characteristics after passing through the divided circuit: the internal upper bit sequence is a value other than the first fixed bit sequence, and the internal lower bit sequence is a value other than the second fixed bit sequence.

6. An apparatus according to claim 4, wherein the calibration test includes a first reduced target test using a first reduced target test input value, the first reduced target test input value being a value adjusted to have the following characteristics after passing through the divided circuit, the internal upper bit sequence being a value other than the first fixed bit sequence, and the internal lower bit sequence being a value other than the second fixed bit sequence, and the number of test pairs used in the first reduced target test is 2 to the power of N - (2 to the power of K + 2 to the power of M + 1).

7. An apparatus according to claim 1, wherein the DA converter element to be corrected has a division circuit which outputs an internal upper bit string of K bits and an internal lower bit string of M bits based on an input value from an input terminal and a binary format assumed to be input by the element, the internal upper bit string being input to the first type circuit segment, and the internal lower bit string being input to the second type circuit segment, the first type circuit segment including a plurality of first type circuits and a selector circuit, the selector circuit being a circuit which selects one of the first type circuits in accordance with the internal upper bit string, outputs an active signal to the selected first type circuit, and outputs an inactive signal to unselected first type circuits, each of the first type circuits including a circuit element for outputting an analog value corresponding to the weight of the internal upper bit string and the active signal or inactive signal, and the second type circuit segment having a second type circuit corresponding to each bit of the internal lower bit string, and which is a segment which determines the output value for the segment by adding up the analog values ​​output by each second type circuit, the first type circuit includes a circuit element for outputting an analog value according to the weight of the bit and active / inactive state indicated by the bit.

8. An apparatus as claimed in claim 7, wherein (B) the updating of the correction data or the generation of the test input value is performed based on the following for an input terminal bit string, which is a bit string input to the input terminal of the correction DA converter element: the 0 / 1 of a bit group contained in the input terminal bit string and the active / inactive relationship of the plurality of first type circuits and the plurality of second type circuits.

9. The apparatus according to claim 8, wherein the number of said test pairs acquired during said calibration test period is equal to or greater than the sum of the number of said first type circuits and the number of said second type circuits.

10. The apparatus of claim 1, wherein the first type circuit segment is a thermometer type circuit segment, and the second type circuit segment is a binary type or ladder type circuit segment.

11. An apparatus according to claim 1, wherein the pre-stage circuit stores, as the correction data, a first table for managing the amount of correction derived from the first type circuit segment and a second table for managing the amount of correction derived from the second type circuit segment.

12. A device according to claim 1, wherein the main circuit is a circuit for performing DA conversion of N+1 bits or more by using a sub DA converter element responsible for lower bits in addition to the DA converter element to be corrected responsible for higher bits, and the front-stage circuit has: a division circuit or division wiring that receives the DA conversion target value and divides it into an upper DA conversion target value and a lower DA conversion target value for output; a correction circuit that outputs a correction amount obtained from the upper DA conversion target value and the correction data; and an addition circuit that adds the correction amount and the lower DA conversion target value to output the corrected lower DA conversion target value, wherein the DA converter element to be corrected has the upper DA conversion target value as a conversion target, and the additional DA converter element has the corrected lower DA conversion target value as a conversion target, and the main circuit has a weighted addition circuit that performs weighted addition of an analog value output by the DA converter element to be corrected and an analog value output by the sub DA converter element, An apparatus having the above configuration.

13. The device according to claim 9, wherein said main circuit has wiring for outputting the analog value output by said weighted addition circuit as said main circuit output analog value.

14. The device according to claim 9, wherein the main circuit comprises: an amplifier circuit that amplifies the analog value output by the weighted addition circuit; and wiring that outputs the analog value amplified by the amplifier circuit as the main circuit output analog value.

15. An apparatus according to claim 1, wherein the pre-stage circuit includes: a correction circuit that receives the processor output bit string and outputs a correction amount bit string based on the correction data; and an addition circuit that adds the correction amount bit string and the processor output bit string and outputs the main input bit string.

16. The apparatus according to claim 1, wherein the pre-stage circuitry includes: a correction circuit which receives the processor output bit string and outputs the main input bit string based on the correction data.

17. A charged particle beam device comprising: a charged particle source for generating a charged particle beam; a deflector for deflecting the charged particle beam; and a device according to any one of claims 1 to 16 as a controller for controlling the deflector.

18. An apparatus having at least a main circuit including one or more DA converter elements that converts a received bit string, which is a main body input bit string, into an analog value, which is a main body output analog value, and outputs it; a processor that outputs a processor output bit string; a front-stage circuit that receives the processor output bit string and outputs the main body input bit string; and an AD converter, wherein the front-stage circuit corrects the processor output bit string based on correction data and outputs the main body input bit string, and the main body circuit includes an amplifier circuit that amplifies the analog value output by the DA converter element and outputs it as the main body output analog value, wherein the processor: (A) obtains a plurality of pairs of test bit strings and test result bit strings having the following characteristics: (A1) the test bit string is the processor output bit string or the main body input bit string for a calibration test, (A2) the test result bit string is obtained by converting the main body output analog value with the AD converter, and (B) updates the correction data based on the plurality of pairs of (A).