Multilayer ceramic capacitor

Abstract

The present invention makes it possible to provide a multilayer ceramic capacitor having high reliability while achieving high capacity. In a multilayer ceramic capacitor (1), a laminate (2) has: an inner layer part (10) in which a plurality of first internal electrode layers (6a) and a plurality of second internal electrode layers (6b) face each other; and an outer layer part formed from a dielectric material. When the length in a direction parallel to the lamination direction (T) of the inner layer part (10) at the central position of the inner layer part (10) in the width direction (W) is defined as a first length, and when the length in the direction parallel to the lamination direction (T) of the inner layer part (10), at a position at which the length from a width-direction (W) end portion of the inner layer part (10) in a direction parallel to the other width-direction (W) end portion of the inner layer part (10) in the width direction (W) is 0.3-8.0% of the length of the inner layer part (10) in the width direction (W), is defined as a second length, the second length is longer than the first length.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] When manufacturing a multilayer ceramic capacitor, multiple dielectric sheets are prepared and stacked. In recent years, in order to achieve miniaturization and high capacitance in multilayer ceramic capacitors, the dielectric sheets have become thinner and more multilayered. Furthermore, in order to improve the durability of multilayered multilayer ceramic capacitors, Patent Document 1 discloses a technique of incorporating a glass component into external electrodes.

[0003] Japanese Patent Application Laid-Open No. 2001-267173

[0004] However, as the dielectric sheets become thinner and more multi-layered, durability may decrease, especially at the edges of the internal electrode layers. The following is an example of a decrease in durability: When manufacturing a multilayer ceramic capacitor, stacked dielectric sheets are pressed. This pressing process may thin the dielectric layers at the edges of the internal electrode layers. Meanwhile, at the edges of the internal electrode layers, the electric field strength is stronger than in other parts of the internal electrode layers due to the edge effect. This causes electric field concentration at the edges of the internal electrode layers where the dielectric layers are thin, resulting in dielectric breakdown.

[0005] This decrease in durability becomes a greater problem when an attempt is made to increase capacitance, because the thickness of the dielectric layer is made thinner to increase capacitance.

[0006] Therefore, an object of the present invention is to provide a multilayer ceramic capacitor that has high reliability while realizing high capacitance.

[0007] The multilayer ceramic capacitor of the present invention comprises a laminate having a plurality of laminated dielectric layers, a plurality of first internal electrode layers and a plurality of second internal electrode layers laminated on the dielectric layers, the laminate having a first main surface and a second main surface opposing each other in a lamination direction, a first end face and a second end face opposing each other in a length direction perpendicular to the lamination direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the lamination direction and the length direction, a first external electrode disposed on the first end face, and a second external electrode disposed on the second end face, The laminated laminated body has an inner layer portion in which a plurality of first internal electrode layers and the plurality of second internal electrode layers face each other, and an outer layer portion made of a dielectric material, and when the length of the inner layer portion in a direction parallel to the stacking direction at the center position in the width direction of the inner layer portion is defined as a first length, and the length of the inner layer portion in a direction parallel to the stacking direction at a position from an end of the inner layer portion in the width direction to another end of the inner layer portion in the width direction is defined as a second length, the second length is longer than the first length.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can easily improve the capacitance and reliability.

[0009] 5A is a perspective view of a multilayer ceramic capacitor according to the present embodiment; FIG. 5B is a cross-sectional view taken along line I-I in FIG. 1; FIG. 5C is a cross-sectional view taken along line II-II in FIG. 1; FIG. 5D is a cross-sectional view taken along line III-III in FIG. 1; FIG. 5E is a diagram showing a state in which conductive paste and step-reducing paste are printed on a dielectric sheet; FIG. 5F is a diagram showing two dielectric sheets 40 to be laminated; FIG. 5G is a cross-sectional view taken along line WW' in FIG. 5A;

[0010] An embodiment of the invention will be described with reference to FIG. 1. FIG. 1 is a perspective view of a multilayer ceramic capacitor 1 according to an embodiment of the present invention. (Laminate) The laminate 2 includes a plurality of laminated dielectric layers and a plurality of internal electrode layers. The shape of the laminate 2 is approximately a rectangular parallelepiped. In the laminate 2, the direction in which the dielectric layers and internal electrode layers are laminated is referred to as the lamination direction T. The direction perpendicular to the lamination direction T is referred to as the width direction W. The direction perpendicular to the lamination direction T and the width direction W is referred to as the length direction L.

[0011] Of the two surfaces of the laminate 2 that face each other in the stacking direction T, one surface is designated as the first main surface M1. The remaining surface is designated as the second main surface M2. Of the two surfaces of the laminate 2 that face each other in the width direction W, one surface is designated as the first side surface S1. The remaining surface is designated as the second side surface S2. Of the two surfaces of the laminate 2 that face each other in the length direction L, one surface is designated as the first end surface E1. The remaining surface is designated as the second end surface E2. The mounting surface of the multilayer ceramic capacitor 1 is the second main surface M2. The mounting surface refers to the surface that faces a wiring board when the multilayer ceramic capacitor 1 is mounted on a wiring board or the like.

[0012] Regarding the cross section of the laminate 2, the cross section taken along line I-I in Fig. 1 is defined as the LT cross section. Regarding the cross section of the laminate 2, the cross section taken along line II-II in Fig. 1 is defined as the WT cross section. Regarding the cross section of the laminate 2, the cross section taken along line III-III in Fig. 1 is defined as the LW cross section.

[0013] The corners and ridges of the laminate 2 are preferably rounded. A corner is a portion where three surfaces of the laminate 2 intersect. A ridge is a portion where two surfaces of the laminate 2 intersect. Concaves and recesses may be formed on some or all of the main surface, side surface, and end surface.

[0014] (Dielectric Layer) The total number of dielectric layers stacked in the laminate 2 is preferably 15 to 2000. The main material of the dielectric layers is a ceramic material. Examples of ceramic materials include BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３The ceramic material may be a dielectric ceramic in which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to the primary component.

[0015] The thickness of each dielectric layer is preferably 0.5 μm or more and 10 μm or less.

[0016] (Division of Laminate) The division of the laminate 2 in the longitudinal direction L will be described with reference to Figure 2. Figure 2 is a cross-sectional view taken along line II in Figure 1. The laminate 2 can be divided into a first main surface side outer layer portion OL1, an inner layer area IL, and a second main surface side outer layer portion OL2 in the stacking direction T. The first main surface side outer layer portion OL1, the inner layer area IL, and the second main surface side outer layer portion OL2 are arranged in this order from the first main surface M1 to the second main surface M2 in the stacking direction T.

[0017] The first outer layer portion OL1 is a portion between the first main surface M1 and the internal electrode layer closest to the first main surface M1. The internal layer range IL is a range where internal electrode layers face each other. The second outer layer portion OL2 is a portion between the second main surface M2 and the internal electrode layer closest to the second main surface M2.

[0018] The first main surface side outer layer portion OL1 is located on the first main surface M1 side of the laminate 2. The first main surface side outer layer portion OL1 is formed by an assembly of multiple dielectric layers located between the first main surface M1 and the internal electrode layer closest to the first main surface M1. The first main surface side outer layer portion OL1 is formed by multiple dielectric layers located between the first main surface M1 and the outermost surface of the inner layer range IL on the first main surface M1 side and an extension of that outermost surface.

[0019] The second main surface side outer layer portion OL2 is located on the second main surface M2 side of the laminate 2. The second main surface side outer layer portion OL2 is formed by an assembly of multiple dielectric layers located between the second main surface M2 and the internal electrode layer closest to the second main surface M2. The second main surface side outer layer portion OL2 is formed by multiple dielectric layers located between the second main surface M2 and the outermost surface of the inner layer range IL on the second main surface M2 side and an extension of that outermost surface.

[0020] The inner layer area IL is an area sandwiched between the first outer layer portion OL1 on the main surface side and the second outer layer portion OL2 on the main surface side.

[0021] Of the dielectric layers, the dielectric layers arranged in the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2 are referred to as outer dielectric layers 3. Of the dielectric layers, the dielectric layers arranged in the inner layer range IL are referred to as inner dielectric layers 4.

[0022] The following terms are used in describing length and position. The length in the length direction L is referred to as the length length. The length in the width direction W is referred to as the width length. The length in the stacking direction T is referred to as the stacking direction length. The position that is half the length of the length length is referred to as the center position in the length direction L. The center position in the length direction L is referred to as the center position in the length direction. The position that is half the length of the width length is referred to as the center position in the width direction W. The center position in the width direction W is referred to as the center position in the width direction. The position that is half the length of the stacking length is referred to as the center position in the stacking direction T. The center position in the stacking direction T is referred to as the center position in the stacking direction. The end portions in the length direction L are referred to as length direction end portions. The end portions in the width direction W are referred to as width direction end portions. The end portions in the stacking direction T are referred to as stacking direction end portions.

[0023] The size of the laminate 2 is not particularly limited. The length of the laminate in the longitudinal direction is preferably 0.2 mm or more and 10 mm or less. The length of the laminate 2 in the width direction is preferably 0.1 mm or more and 5 mm or less. The length of the laminate 2 in the stacking direction is preferably 0.1 mm or more and 5 mm or less.

[0024] (L Gap) The division of the laminate 2 in the longitudinal direction L will be described. The laminate 2 can be divided into a first end surface side outer layer portion LG1, a longitudinally facing portion LF, and a second end surface side outer layer portion LG2 in the longitudinal direction L. The first end surface side outer layer portion LG1, the longitudinally facing portion LF, and the second end surface side outer layer portion LG2 are arranged in this order in the longitudinal direction L from the first end surface E1 to the second end surface E2.

[0025] The longitudinal facing portion LF is a portion where the first internal electrode layer 6a and the second internal electrode layer 6b face each other in the stacking direction T. The first end face side outer layer portion LG1 is a portion between the longitudinal facing portion LF and the first end face E1. The second end face side outer layer portion LG2 is a portion between the longitudinal facing portion LF and the second end face E2. The longitudinal facing portion LF is a portion corresponding to the facing electrode portion of the internal electrode layer. The first end face side outer layer portion LG1 and the second end face side outer layer portion LG2 are portions corresponding to the lead electrode portions of the internal electrode layer. The first end face side outer layer portion LG1 and the second end face side outer layer portion LG2 are also referred to as L gaps.

[0026] The first end face side outer layer portion LG1 is located on the first end face E1 side, between the first end face E1 and the outermost surface of the end portion of the second internal electrode layer 6b on the first end face E1 side.

[0027] The second end face side outer layer portion LG2 is located on the second end face E2 side, between the second end face E2 and the outermost surface of the end portion of the first internal electrode layer 6 a on the second end face E2 side.

[0028] (W Gap) The division of the laminate 2 in the width direction W will be described with reference to Figure 3. Figure 3 is a cross-sectional view taken along line II-II in Figure 1. The laminate 2 can be divided into a first side surface outer layer portion WG1, a widthwise opposing portion WF, and a second side surface outer layer portion WG2 in the width direction W. The first side surface outer layer portion WG1, the widthwise opposing portion WF, and the second side surface outer layer portion WG2 are arranged in this order in the width direction W from the first side surface S1 to the second side surface S2.

[0029] The widthwise facing portion WF is a portion where the internal electrode layers face each other in the stacking direction T. The first side surface side outer layer portion WG1 is a portion between the widthwise facing portion WF and the first side surface S1. The second side surface side outer layer portion WG2 is a portion between the widthwise facing portion WF and the second side surface S2. The first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 are also referred to as W gaps.

[0030] The first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 are portions where no internal electrode layers exist in the stacking direction T. The first side surface side outer layer portion WG1 is located on the first side surface S1 side. The first side surface side outer layer portion WG1 is formed by a plurality of dielectric layers located between the first side surface S1 and the outermost surface of the widthwise opposing portion WF on the first side surface S1 side.

[0031] The second side surface outer layer portion WG2 is located on the second side surface S2 side and is formed of a plurality of dielectric layers located between the second side surface S2 and the outermost surface of the widthwise facing portion WF on the second side surface S2 side.

[0032] (Internal Electrode Layers) The internal electrode layers include a plurality of first internal electrode layers 6 a and a plurality of second internal electrode layers 6 b. The first internal electrode layers 6 a are internal electrode layers exposed at the first end face E1. The second internal electrode layers 6 b are internal electrode layers exposed at the second end face E2.

[0033] The first internal electrode layer 6a can be divided into a first opposing electrode portion 7a and a first lead electrode portion 8a. The first opposing electrode portion 7a is a portion facing the second internal electrode layer 6b. The first lead electrode portion 8a is a portion led from the first opposing electrode portion 7a to the first end face E1 of the laminate 2.

[0034] The first extension electrode 8a has an end portion on the first end face E1 side extended to the surface of the first end face E1 of the laminate 2. The end portion of the first extension electrode 8a extended to the first end face E1 forms an exposed portion at the first end face E1.

[0035] The second internal electrode layer 6b can be divided into a second opposing electrode portion 7b and a second lead electrode portion 8b. The second opposing electrode portion 7b is a portion facing the first internal electrode layer 6a. The second lead electrode portion 8b is a portion led out from the second opposing electrode portion 7b to the second end face E2 of the laminate 2.

[0036] The second extraction electrode 8b has an end portion on the second end face E2 side extended to the surface of the second end face E2 of the laminate 2. The end portion of the second extraction electrode 8b extended to the second end face E2 forms an exposed portion at the second end face E2.

[0037] The shapes of the first opposing electrode portion 7a and the second opposing electrode portion 7b are not particularly limited. The shapes of the first opposing electrode portion 7a and the second opposing electrode portion 7b are preferably rectangular. The corners of the first opposing electrode portion 7a and the second opposing electrode portion 7b may be rounded. The corners of the first opposing electrode portion 7a and the second opposing electrode portion 7b may be formed obliquely. Forming the corners obliquely means forming them in a tapered shape.

[0038] The shapes of the first extension electrode 8a and the second extension electrode 8b are not particularly limited. The shapes of the first extension electrode 8a and the second extension electrode 8b are preferably rectangular. The corners of the first extension electrode 8a and the second extension electrode 8b may be rounded. The corners of the first extension electrode 8a and the second extension electrode 8b may be formed obliquely. Forming the corners obliquely means forming them in a tapered shape.

[0039] The width of the first opposing electrode portion 7 a and the width of the first extension electrode portion 8 a may be the same, but either the width of the first opposing electrode portion 7 a or the width of the first extension electrode portion 8 a may be narrower than the remaining width.

[0040] The width of the second opposing electrode portion 7 b and the width of the second extension electrode portion 8 b may be the same, but either the width of the second opposing electrode portion 7 b or the width of the second extension electrode portion 8 b may be narrower than the remaining width.

[0041] The material of the first internal electrode layer 6a and the second internal electrode layer 6b can be an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0042] In the multilayer ceramic capacitor 1, capacitance is formed by the first opposing electrode portion 7a and the second opposing electrode portion 7b facing each other via the inner dielectric layer 4. This allows the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0043] The thickness of the first internal electrode layers 6a and the second internal electrode layers 6b is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 6a and the second internal electrode layers 6b is preferably 15 or more and 2000 or less.

[0044] (Reduction of Steps Near End Faces) A ​​second dielectric layer 5b is disposed in the multilayer ceramic capacitor 1. The second dielectric layer 5b is a dielectric layer disposed to make the length of the laminate 2 in the stacking direction nearly uniform.

[0045] The reduction of steps in the laminate 2 will be described with reference to Figure 2. It is preferable that the difference between the stacking direction length of the laminate 2 in the longitudinally facing portion LF and the stacking direction length of the laminate 2 in the first end face side outer layer portion LG1 is small. It is also preferable that the difference between the stacking direction length of the laminate 2 in the longitudinally facing portion LF and the stacking direction length of the laminate 2 in the second end face side outer layer portion LG2 is small.

[0046] However, in the inner layer range IL, the difference between the stacking direction length of the laminate 2 in the longitudinal facing portion LF and the stacking direction length of the laminate 2 in the first end face side outer layer portion LG1 tends to be large. In the inner layer range IL, the difference between the stacking direction length of the laminate 2 in the longitudinal facing portion LF and the stacking direction length of the laminate 2 in the second end face side outer layer portion LG2 tends to be small.

[0047] In the inner layer range IL, the inner dielectric layer 4, the first inner electrode layer 6a and the second inner electrode layer 6b are laminated in the longitudinally facing portion LF.

[0048] Only the inner dielectric layer 4 and the first internal electrode layer 6a are laminated on the first end face side external layer portion LG1. The second internal electrode layer 6b is not laminated on the first end face side external layer portion LG1.

[0049] Only the inner dielectric layer 4 and the second internal electrode layer 6b are laminated on the second end face side outer layer portion LG2. The first internal electrode layer 6a is not laminated on the second end face side outer layer portion LG2.

[0050] The longitudinally facing portion LF and the first and second end-side outer layer portions LG1 and LG2 are made of different laminated layers, which makes it easy for the longitudinally facing portion LF to have different stacking direction lengths from the first and second end-side outer layer portions LG1 and LG2.

[0051] In order to reduce the difference in the stacking direction length between the longitudinally facing portion LF and the first and second end surface side outer layer portions LG1 and LG2, an additional inner dielectric layer 4 is disposed in the first and second end surface side outer layer portions LG1 and LG2. This additional inner dielectric layer 4 is referred to as a second dielectric layer 5b. To distinguish it from the second dielectric layer 5b, the dielectric layers included in the laminate 2 other than the second dielectric layer 5b are referred to as first dielectric layers 5a.

[0052] The second dielectric layer 5b is disposed between the longitudinal end of the first internal electrode layer 6a and the second end face E2. The second dielectric layer 5b is disposed between the longitudinal end of the second internal electrode layer 6b and the first end face E1.

[0053] The main component of the second dielectric layer 5b is preferably the same as the main component of the first dielectric layer 5a, but the component of the second dielectric layer 5b is not limited thereto.

[0054] (Reduction of Steps Near the Side Surfaces) In the multilayer ceramic capacitor 1, the second dielectric layer 5b is also disposed near the side surfaces. This will be explained based on FIG. 3. It is preferable that the stacking direction length of the laminate 2 is uniform not only in the length direction L but also in the width direction W. In the inner layer range IL, the stacking direction length tends to differ in the width direction W between the widthwise opposing portion WF and the first and second side surface side outer layer portions WG1 and WG2, just as in the length direction L.

[0055] In the inner layer range IL, the inner dielectric layer 4, the first inner electrode layer 6a and the second inner electrode layer 6b are laminated in the widthwise facing portion WF.

[0056] The first and second side surface side outer layer portions WG1 and WG2 are not provided with the first and second internal electrode layers 6a and 6b, and only the internal dielectric layers 4 are provided with the first and second side surface side outer layer portions WG1 and WG2.

[0057] The widthwise facing portion WF and the first and second side surface side outer layer portions WG1 and WG2 are made of different laminated layers, which makes it easy for the laminated lengths to differ between the widthwise facing portion WF and the first and second side surface side outer layer portions WG1 and WG2.

[0058] In order to reduce the difference in the stacking direction length between the widthwise facing portion WF and the first and second side surface outer layer portions WG1 and WG2, an additional inner dielectric layer 4 is disposed in the first and second side surface outer layer portions WG1 and WG2. This additional inner dielectric layer 4 is the second dielectric layer 5b.

[0059] The second dielectric layer 5b is disposed between the first side surface S1 and the end portions of the first internal electrode layer 6a and the second internal electrode layer 6b on the side of the first side surface S1 in the width direction W. The second dielectric layer 5b is disposed between the second side surface S2 and the end portions of the first internal electrode layer 6a and the second internal electrode layer 6b on the side of the second side surface S2 in the width direction W.

[0060] (Inner layer portion) The portion where the first internal electrode layer 6a and the second internal electrode layer 6b face each other is referred to as the inner layer portion 10. The inner layer portion 10 is the portion where the lengthwise facing portion LF shown in FIG. 2 and the widthwise facing portion WF shown in FIG. 3 intersect with the inner layer range IL. The shape of the inner layer portion 10 is approximately a rectangular parallelepiped. In FIG. 2, the portion where the lengthwise facing portion LF and the inner layer range IL intersect is shown as the inner layer portion 10. In addition, in FIG. 3, the portion where the widthwise facing portion WF and the inner layer range IL intersect is shown as the inner layer portion 10.

[0061] (External Electrodes) The external electrodes will now be described. The external electrodes include a first external electrode 20a and a second external electrode 20b. The first external electrode 20a is connected to the first internal electrode layer 6a. The first external electrode 20a is arranged from the first end face E1 to a portion of the first main surface M1, a portion of the second main surface M2, and a portion of the first side surface S1 and a portion of the second side surface S2.

[0062] The second external electrode 20b is connected to the second internal electrode layer 6b and is disposed from the second end face E2 to a part of the first main surface M1, a part of the second main surface M2, a part of the first side surface S1, and a part of the second side surface S2.

[0063] The first external electrode 20a and the second external electrode 20b preferably have a base electrode layer and a plating layer. The base electrode layer may include at least one layer selected from a baked layer, a conductive resin layer, a thin film layer, etc. The conductive resin layer may be provided separately from the base electrode layer. An example will be described below in which a baked layer is provided as the base electrode layer and a conductive resin layer is provided separately from the base electrode layer.

[0064] The first external electrode 20a includes a first base electrode layer 21a, a first conductive resin layer 22a, a first lower plating layer 23a, and a first upper plating layer 24a. The second external electrode 20b includes a second base electrode layer 21b, a second conductive resin layer 22b, a second lower plating layer 23b, and a second upper plating layer 24b.

[0065] The first base electrode layer 21a and the second external electrode 20b are layers containing conductive metal and glass components. The first conductive resin layer 22a and the second conductive resin layer 22b do not contain metal components. The first conductive resin layer 22a and the second conductive resin layer 22b are formed of a thermosetting resin. The first lower plating layer 23a and the second lower plating layer 23b may be, for example, Ni plating layers. The first upper plating layer 24a and the second upper plating layer 24b may be, for example, Sn plating layers.

[0066] (Base Electrode Layer) The base electrode layer includes a first base electrode layer 21a and a second base electrode layer 21b. The first base electrode layer 21a is disposed from the first end face E1 to a portion of the first main surface M1 and a portion of the second main surface M2, as well as a portion of the first side surface S1 and a portion of the second side surface S2. The second base electrode layer 21b is disposed from the second end face E2 to a portion of the first main surface M1 and a portion of the second main surface M2, as well as a portion of the first side surface S1 and a portion of the second side surface S2.

[0067] The first and second base electrode layers 21a and 21b contain a conductive metal and a glass component. The conductive metal is, for example, at least one of Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component is, for example, at least one of B, Si, Ba, Mg, Al, Li, etc.

[0068] The first base electrode layer 21a and the second base electrode layer 21b may be formed in multiple layers. The first base electrode layer 21a and the second base electrode layer 21b may be formed by applying a conductive paste containing a glass component and a metal to the laminate and then baking it. This baking may be performed simultaneously with the baking of the internal electrode layers. This baking may be performed after the baking of the internal electrode layers.

[0069] When baking is performed simultaneously with the firing of the internal electrode layers and the dielectric layers, it is preferable to add a dielectric material to the conductive paste instead of the glass component. The first base electrode layer 21 a and the second base electrode layer 21 b are baked layers formed by baking.

[0070] The thickness of the first base electrode layer 21a located on the first end face E1 at the center in the stacking direction is preferably, for example, about 10 μm to 150 μm, and the thickness of the second base electrode layer 21b located on the second end face E2 at the center in the stacking direction is preferably, for example, about 10 μm to 150 μm.

[0071] When the first and second base electrode layers 21a and 21b are provided on the first and second main surfaces M1 and M2, and the first and second side surfaces S1 and S2, it is preferable that the thickness of the first and second base electrode layers 21a and 21b at the longitudinal center position of the first and second base electrode layers 21a and 21b located on the first and second main surfaces M1 and M2, and the first and second side surfaces S1 and S2 is, for example, approximately 5 μm or more and 50 μm or less.

[0072] When the base electrode layer is a thin film layer, the thin film layer can be formed by a thin film formation method such as a sputtering method or a vapor deposition method. The formed thin film layer is a layer in which metal particles are deposited. The formed thin film layer has a thickness of 1 μm or less.

[0073] (Conductive Resin Layer) A conductive resin layer is disposed on the base electrode layer. The conductive resin layer contains a resin component and a metal component. The conductive resin layer has a first conductive resin layer 22a and a second conductive resin layer 22b. The first conductive resin layer 22a and the second conductive resin layer 22b contain a thermosetting resin as a resin component. By containing a resin component, the first conductive resin layer 22a and the second conductive resin layer 22b are more flexible than the base electrode layer. The base electrode layer does not contain a resin component. The base electrode layer contains a plating film, a metal component, a glass component, etc. The base electrode layer is a fired product. For these reasons, the base electrode layer is not flexible.

[0074] The conductive resin layer functions as a buffer layer, so that when a bending stress is applied to the mounting substrate and this stress applies a physical impact to the multilayer ceramic capacitor 1, cracks are unlikely to occur in the multilayer ceramic capacitor 1. When an impact due to a thermal cycle is applied to the multilayer ceramic capacitor 1, cracks are unlikely to occur in the multilayer ceramic capacitor 1.

[0075] The thermosetting resin contained in the conductive resin layer may be any of various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these resins, epoxy resin is one of the most suitable resins because it has excellent heat resistance, moisture resistance, adhesion, etc.

[0076] The first conductive resin layer 22a is disposed on the first base electrode layer 21a. The first conductive resin layer 22a covers the first base electrode layer 21a. It is preferable that an end of the first conductive resin layer 22a contacts the laminate 2.

[0077] The second conductive resin layer 22b is disposed on the second base electrode layer 21b. The second conductive resin layer 22b covers the second base electrode layer 21b. It is preferable that an end of the second conductive resin layer 22b contacts the laminate 2.

[0078] The metal components contained in the first conductive resin layer 22a and the second conductive resin layer 22b can be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The metal components are preferably in the form of fillers. When the metal components are metal powders, metal powders whose surfaces are coated with Sn, Ni, or Cu can be used. When metal powders whose surfaces are coated with Sn, N, or Cu are used, the metal powders are preferably powders of Ag, Cu, Ni, Sn, Bi, or alloys thereof. The metal components particularly preferably contain Ag. Ag may be Ag alone. Ag may be an alloy containing Ag, or a metal powder whose surface is coated with Ag.

[0079] When using a metal powder whose surface is coated with Ag, it is preferable to use powder of Cu, Ni, Sn, Bi, or an alloy thereof as the metal powder. Using Ag as the metal filler has the following advantages: Ag has the lowest resistivity of all metals. Ag can form electrodes with low electrical resistance. Ag is a noble metal. Ag is resistant to oxidation. Ag can increase the resistance of the conductive resin layer. Using Ag as the metal filler allows the base metal to be made cheaper while maintaining the properties of Ag.

[0080] The shape of the metal filler contained in the first conductive resin layer 22 a and the second conductive resin layer 22 b is not particularly limited. The shape of the metal filler may be spherical, flat, or the like. The metal filler may be a mixture of spherical metal powder and flat metal powder.

[0081] The average particle size of the metal filler contained in the first conductive resin layer 22 a and the second conductive resin layer 22 b is not particularly limited. The average particle size of the metal filler can be, for example, 0.3 μm or more and 10 μm or less. The average particle size of the metal filler contained in the conductive resin layer can be calculated using a laser diffraction particle size measurement method (based on IOS 13320). This method of calculating the average particle size can be applied regardless of the shape of the filler.

[0082] The metal fillers contained in the first conductive resin layer 22 a and the second conductive resin layer 22 b make the conductive resin layers electrically conductive, and contact between the metal fillers forms a conductive path within the conductive resin layers.

[0083] The resin contained in the first conductive resin layer 22a and the second conductive resin layer 22b may be any of various known thermosetting resins, such as epoxy resin, phenoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin. Epoxy resin has excellent heat resistance, moisture resistance, and adhesion. Epoxy resin is one of the most suitable resins.

[0084] The first conductive resin layer 22 a and the second conductive resin layer 22 b preferably contain a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent can be any of various known compounds such as phenols, amines, acid anhydrides, imidazoles, active esters, and amide-imides.

[0085] The amount of metal contained in the first conductive resin layer 22 a is preferably 35 vmol% to 75 vmol% of the total volume of the first conductive resin layer 22 a, and the amount of metal contained in the second conductive resin layer 22 b is preferably 35 vmol% to 75 vmol% of the total volume of the second conductive resin layer 22 b.

[0086] The amount of resin contained in the first conductive resin layer 22 a is preferably 25 vmol% or more and 65 vmol% or less with respect to the total volume of the first conductive resin layer 22 a. The amount of resin contained in the second conductive resin layer 22 b is preferably 25 vmol% or more and 65 vmol% or less with respect to the total volume of the second conductive resin layer 22 b.

[0087] The thickness of the first conductive resin layer 22a or the second conductive resin layer 22b located on the first end face E1 or the second end face E2 at the center position in the stacking direction is preferably, for example, approximately 10 μm or more and 200 μm or less.

[0088] When the first conductive resin layer 22a and the second conductive resin layer 22b are provided on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2, the thickness of the conductive resin layer at the longitudinal center position of the first conductive resin layer 22a or the second conductive resin layer 22b located on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2 is preferably, for example, approximately 10 μm or more and 200 μm or less.

[0089] (Plating Layer) The plating layer will be described. The plating layer includes a lower plating layer and an upper plating layer. The plating layer includes two layers. The plating layer may be a single layer or multiple layers.

[0090] (Underlayer plating layer) The underlayer plating layer is disposed on the conductive resin layer. The underlayer plating layer covers at least a portion of the conductive resin layer. The underlayer plating layer includes a first underlayer plating layer 23a and a second underlayer plating layer 23b. The first underlayer plating layer 23a is disposed on the first conductive resin layer 22a. The second underlayer plating layer 23b is disposed on the second conductive resin layer 22b.

[0091] The first lower-layer plating layer 23 a and the second lower-layer plating layer 23 b may be Ni plating layers, which prevents the base electrode layer and the like from being eroded by solder when the multilayer ceramic capacitor 1 is mounted.

[0092] (Upper-layer plating layer) The upper-layer plating layer is disposed on the lower-layer plating layer. The upper-layer plating layer covers at least a portion of the lower-layer plating layer. The upper-layer plating layer includes a first upper-layer plating layer 24a and a second upper-layer plating layer 24b. The first upper-layer plating layer 24a is disposed on the first lower-layer plating layer 23a. The second upper-layer plating layer 24b is disposed on the second lower-layer plating layer 23b.

[0093] The first upper plating layer 24 a and the second upper plating layer 24 b can be Sn plating layers. Sn plating layers have good solder wettability. Therefore, using Sn plating layers for the upper plating layers makes it easier to mount the multilayer ceramic capacitor 1 on a substrate or the like.

[0094] The metals of the materials for the under-plating layer and the top-plating layer are not particularly limited, and the plating layers, including the under-plating layer and the top-plating layer, can be, for example, at least one of metals such as Cu, Ni, Ag, Pd, Au, and Sn, and alloys such as Ag—Pd alloys.

[0095] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less.

[0096] The base electrode layer may not be provided, and the external electrodes may be formed only with plating layers. The case where only plating layers are provided without providing a base electrode layer will be described.

[0097] The first external electrode 20a and the second external electrode 20b are formed directly on the surface of the laminate 2. The first external electrode 20a and the second external electrode 20b are plated layers. The multilayer ceramic capacitor 1 includes a plated layer electrically connected to the first internal electrode layer 6a or the second internal electrode layer 6b. Before forming the plated layer, a pretreatment can be performed. The pretreatment is, for example, disposing a catalyst on the surface of the laminate 2.

[0098] The plating layer preferably includes a lower-layer plating electrode and an upper-layer plating electrode. The lower-layer plating electrode is a plating electrode formed on the surface of the laminate 2. The upper-layer plating electrode is a plating electrode formed on the surface of the lower-layer plating electrode. The lower-layer plating electrode and the upper-layer plating electrode preferably include at least one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal.

[0099] The lower plated electrode is preferably formed using Ni, which has good solder barrier properties. The upper plated electrode is preferably formed using Sn or Au, which have good solder wettability.

[0100] When the first internal electrode layer and the second internal electrode layer are formed using Ni, it is preferable that the lower-layer plated electrode be formed using Cu. Cu has good bonding properties with Ni. The upper-layer plated electrode can be formed as needed. The first external electrode 20a and the second external electrode 20b may be formed only using the lower-layer plated electrode.

[0101] The outermost layer of the plating layer may be an upper-layer plating electrode. Another plating electrode may be formed on the surface of the upper-layer plating electrode. When the plating layer is disposed without providing a base electrode layer, the preferred thickness per plating layer is 1 μm or more and 15 μm or less. The plating layer preferably does not contain glass. The preferred metal ratio per unit volume of the plating layer is 99% by volume or more.

[0102] The size of the multilayer ceramic capacitor 1 is not particularly limited. The length in the longitudinal direction of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes is preferably 0.2 mm or more and 10 mm or less. The length in the lamination direction of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes is preferably 0.1 mm or more and 5 mm or less. The length in the width direction of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes is preferably 0.1 mm or more and 10 mm or less.

[0103] (Method for manufacturing a multilayer ceramic capacitor) A method for manufacturing the multilayer ceramic capacitor 1 will be described. (1) A conductive paste for the dielectric sheets and the internal electrode layers is prepared. The conductive paste for the dielectric sheets and the internal electrode layers contains a binder and a solvent. The binder and the solvent may be a known organic binder and organic solvent, etc.

[0104] (2) A conductive paste for the internal electrode layers is printed on the dielectric sheet in a predetermined pattern. The internal electrode layer pattern is formed by printing the conductive paste. The printing can be performed by, for example, screen printing or gravure printing.

[0105] (3) A predetermined number of dielectric sheets for the outer layer portion are stacked. No internal electrode layer pattern is printed on the dielectric sheets for the outer layer portion. Dielectric sheets on which internal electrode layer patterns are printed are stacked in order on the stacked dielectric sheets. Furthermore, a predetermined number of dielectric sheets for the outer layer portion are stacked on top of those. A laminated sheet is produced by stacking these sheets.

[0106] The second dielectric layer 5b will now be described. The second dielectric layer 5b is disposed to reduce steps in the laminate 2. The dielectric paste that becomes the second dielectric layer 5b is called a step-reducing paste.

[0107] The step-reducing paste is applied to the area around the internal electrode layer pattern on the dielectric sheet on which the internal electrode layer pattern is printed. The step-reducing paste is applied to the area where the internal electrode layer pattern is not formed. This is because the step-reducing paste is a paste used to eliminate the step between the internal electrode layer pattern and its surrounding area. The step-reducing paste can be applied so as to overlap the end of the internal electrode layer pattern. The overlap width can be, for example, about 50 μm. The step-reducing paste can be applied so as to form a gap between the internal electrode layer pattern and the step-reducing paste. The gap width can be, for example, 50 μm.

[0108] The step-reducing paste may be the same as the ceramic paste used when producing the dielectric sheet, or it may be different from the ceramic paste used when producing the dielectric sheet.

[0109] (4) The laminated sheets are pressed in the lamination direction to produce a laminated block. The pressing method can be isostatic pressing.

[0110] (5) The laminated block is cut to a predetermined size. This cutting process cuts out laminated chips. When cutting, the corners and ridges of the laminated chips may be rounded. The rounding process may be performed by barrel polishing.

[0111] (6) The laminated chip is fired. This firing produces a laminate. The firing temperature is preferably 900° C. or higher and 1200° C. The firing temperature can be changed depending on the materials of the dielectric and internal electrode layers.

[0112] External electrodes are provided on the laminate. (7) A conductive paste that will become the base electrodes is applied to both end surfaces of the laminate. The conductive paste contains a glass component and a metal. The application method can be, for example, a dipping method. After application, a baking process is performed. A base electrode layer is formed by this baking process. The preferred temperature for the baking process is 700°C or higher and 900°C or lower. The base electrode layer is a baked layer.

[0113] (8) A conductive resin layer is formed on the base electrode layer. A conductive resin paste is prepared. The conductive resin paste contains a resin component and a metal component. The conductive resin paste is applied to the base electrode layer. The application method can be a dipping method. After application, a heat treatment is performed. The heat treatment temperature is 200°C or higher and 550°C or lower. The resin is thermally cured by this heat treatment. This thermal curing forms a conductive electrode layer. The atmosphere during the heat treatment is preferably a nitrogen gas atmosphere. A preferred oxygen concentration is 100 ppm or lower. This oxygen concentration makes it difficult for the resin to scatter. This oxygen concentration makes it difficult for various metal components to oxidize.

[0114] (9) After forming the conductive resin layer, a Ni plating layer is formed on the surface of the conductive resin layer. This Ni plating layer becomes the first underlayer plating layer and the second underlayer plating layer. The Ni plating layer can be formed by electrolytic plating. A preferred plating method is barrel plating.

[0115] (10) A Sn plating layer is formed on the Ni plating layer. A first Sn plating layer is formed on the first Ni plating layer. A second Sn plating layer is formed on the second Ni plating layer. By forming the Sn plating layer, the wettability of the solder used for mounting can be improved when mounting the multilayer ceramic capacitor 1 on a substrate or the like. This makes it easier to mount the multilayer ceramic capacitor 1 on a substrate or the like. The Sn plating layer can be formed by electrolytic plating. A preferred plating method is barrel plating.

[0116] (Lamination Direction Length and Width Direction Length) The lengths of each portion of the inner layer portion 10 of the multilayer ceramic capacitor 1 will be described with reference to Fig. 4. 101 in Fig. 4 is a cross-sectional view taken along line III-III in Fig. 1. 101 in Fig. 4 is a WT cross-sectional view of the laminate 2 at the center position in the longitudinal direction of the laminate 2.

[0117] (Lamination Direction Length) The lamination direction length of the inner layer section 10 will be described. The width direction length of the inner layer section 10 is indicated by length D7. The width direction end of the inner layer section 10 is indicated by line W3. Half of length D7 is length D8. A position that is a length D8 away from width direction end W3 in the direction of the other width direction end of the inner layer section 10 in the width direction W is indicated by line W1. The position of line W1 is the center position in the width direction.

[0118] Length D9 is defined as a length equivalent to 0.3% to 8.0% of length D7. In other words, a position within the range of length D9 is a position where the length from an end of the width direction W of the inner layer section 10 in a direction parallel to another end of the width direction W of the inner layer section 10 in the width direction W is 0.3% to 8.0% of the length of the width direction W of the inner layer section 10. A position distanced by length D9 from the width direction end W3 toward the other width direction end of the inner layer section 10 in the width direction W is indicated by line W2. The position of line W2 is defined as the end-neighbor position W2 in the width direction W of the inner layer section 10. The end-neighbor position W2 in the width direction W is defined as the width direction end-neighbor position W2.

[0119] The length of the inner layer section 10 in the stacking direction at the widthwise center position W1 is defined as a first length D1. The length of the inner layer section 10 in the stacking direction at a widthwise end position W2 is defined as a second length D2. The length of the inner layer section 10 in the stacking direction at a widthwise end position W3 is defined as a third length D3.

[0120] (Lamination direction length at widthwise end positions) The second length D2 is longer than the first length D1. The lamination direction length of the inner layer section 10 is longer at the widthwise end positions W2 than at the widthwise center position W1.

[0121] The second length D2 is equal to or less than 102.6% of the first length D1. Alternatively, the second length D2 is longer than the first length D1, and the difference between the second length D2 and the first length D1 is equal to or less than 30 μm.

[0122] (Lamination direction length at widthwise end portions) The third length D3 is shorter than the first length D1. The lamination direction length of the inner layer portion 10 is shorter at the widthwise end portions W3 than at the widthwise center position W1.

[0123] To summarize the above, the stacking direction length of the inner layer portion 10 is such that the widthwise end vicinity position W2>the widthwise central position W1>the widthwise end position W3.

[0124] The width direction length of the inner layer section 10 will be described. The stacking direction length of the inner layer section 10 is indicated by D10. The stacking direction end of the inner layer section 10 is indicated by line T6. Half the length of length D10 is set to length D11. A position that is a length D11 away from the stacking direction end T6 in the direction of the other stacking direction end of the inner layer section 10 in the stacking direction T is indicated by line T4. The position of line T4 is the center position in the stacking direction.

[0125] A length equivalent to 10% to 40% of length D10 is defined as length D12. A position distanced by length D12 from stacking direction end T6 toward another stacking direction end of inner layer portion 10 in stacking direction T is indicated by line T5. The position of line T5 is defined as position T5 near the stacking direction end of inner layer portion 10.

[0126] The widthwise length of the inner layer section 10 at the center position T4 in the stacking direction is defined as a fourth length D4. The widthwise length of the inner layer section 10 at a position T5 near the end in the stacking direction is defined as a fifth length D5. The widthwise length of the inner layer section 10 at an end T6 in the stacking direction is defined as a sixth length D6.

[0127] The fifth length D5 is shorter than the fourth length D4. The width direction length of the inner layer section 10 is shorter at positions T5 near the stacking direction ends than at the length direction central position T4.

[0128] The fifth length D5 is equal to or greater than 97.5% and less than 100% of the fourth length D4, or the fifth length D5 is longer than the fourth length D4, and the difference between the fifth length D5 and the fourth length D4 is 30 μm or less.

[0129] The sixth length D6 is shorter than the fifth length D5. The width direction length of the inner layer section 10 is shorter at the end T6 in the stacking direction than at the position T5 near the end in the stacking direction.

[0130] To summarize the above, the width direction length of the inner layer portion 10 is such that the central position T4 in the stacking direction > the position near the end T5 in the stacking direction > the end T6 in the stacking direction.

[0131] (Protuberance) 102 in FIG. 4 is an enlarged view of a portion of the inner layer portion 10. As shown by the dashed-line box R1 in 102 in FIG. 4, at a widthwise end vicinity position W2, the first internal electrode layer 6a and the second internal electrode layer 6b protrude in the stacking direction T from the second main surface M2 toward the first main surface M1. For one internal electrode layer, a portion of the internal electrode layer located closer to the first main surface M1 at the widthwise end vicinity position W2 than at a position closer to the first main surface M1 in the stacking direction T at the widthwise center position W1 is referred to as a protuberance 30. The protuberance 30 is formed by the internal electrode layer overlapping the second dielectric layer 5b, for example. Due to the presence of the protuberance 30, the stacking direction length of the inner layer portion 10 at the widthwise end vicinity position W2 is longer than the stacking direction length at the widthwise center position W1.

[0132] (Dielectric Layers) The stacking direction length of each layer will be explained based on 102 in Figure 4. The stacking direction length of each layer indicates the thickness of each layer. The stacking direction length of the dielectric layers will be explained. The stacking direction length of the first dielectric layer 5a at the widthwise center position W1 is length D21. The stacking direction length of the second dielectric layer 5b at the widthwise end vicinity position W2 is length D22. The stacking direction length of the second dielectric layer 5b at the widthwise end W3 is length D23.

[0133] The length of the dielectric layer in the stacking direction is longer at a position W2 near the widthwise end than at a widthwise central position W11. The length D22 is longer than the length D21.

[0134] The length of the dielectric layer in the stacking direction is longer at the widthwise end W3 than at the position W2 near the widthwise end. Length D23 is longer than length D22.

[0135] (Internal electrode layer) The stacking direction length of the internal electrode layer will be described. The internal electrode layer will be described using the first internal electrode layer 6a as an example. The content described using the first internal electrode layer 6a as an example is also the same for the second internal electrode layer 6b. The stacking direction length at the widthwise center position W1 of the first internal electrode layer 6a is defined as length D24. The stacking direction length at the widthwise end vicinity position W2 of the first internal electrode layer 6a is defined as length D25. The stacking direction length at the widthwise end W3 of the first internal electrode layer 6a is defined as length D26.

[0136] The length in the lamination direction of the first internal electrode layer 6a is shorter at the widthwise end vicinity position W2 than at the widthwise central position W1. The length D25 is shorter than the length D24.

[0137] The length in the lamination direction of the first internal electrode layer 6a is shorter at the widthwise end W3 than at the position W2 near the widthwise end. The length D26 is shorter than the length D25.

[0138] (Element stacking direction length) One dielectric layer and one internal electrode layer in contact with this dielectric layer are combined to form one element. The sum of the stacking direction length of the dielectric layers included in one element and the stacking direction length of the internal electrode layers included in one element is the stacking direction length of the element. The stacking direction length of the element at the widthwise center position W1 is the sum of lengths D21 and D24. The stacking direction length of the element at the widthwise end vicinity position W2 is the sum of lengths D22 and D25. The stacking direction length of the element at the widthwise end W3 is the sum of lengths D23 and D26.

[0139] (Width-direction end vicinity position) The increase in length D22 of the dielectric layer from length D21 is greater than the decrease in length D25 of the internal electrode layer from length D24. Therefore, the stacking direction length of the element is longer at width-direction end vicinity position W2 than at width-direction center position W1. As a result, the stacking direction length of the inner layer portion 10 is longer at width-direction end vicinity position W2 than at width-direction center position W1.

[0140] (Width Direction Ends) The increase in length D23 of the dielectric layer from length D21 is smaller than the decrease in length D26 of the internal electrode layer from length D24. Therefore, the stacking direction length of the element is shorter at width direction end W3 than at width direction center position W1. As a result, the stacking direction length of the inner layer portion 10 is shorter at width direction end W3 than at width direction center position W1.

[0141] (Capacitance) In the multilayer ceramic capacitor 1, the second length D2 is longer than the first length D1, thereby increasing the capacitance of the multilayer ceramic capacitor 1. Increasing the lamination direction length of the inner layer portion 10 at the widthwise end vicinity position W2 allows the lamination direction length of the internal electrode layer included therein at the widthwise end vicinity position W2 to be increased. As the lamination direction length of the internal electrode layer increases, the capacitance increases. In the multilayer ceramic capacitor 1, the lamination direction length of the internal electrode layer does not suddenly decrease in two stages from the widthwise center position W1 to the widthwise end position W3, from the length D24 at the widthwise center position W1 to the length D26 at the widthwise end position W3. At the widthwise end vicinity position W2 between the widthwise center position W1 and the widthwise end position W3, the lamination direction length of the internal electrode layer becomes a length D25 that is longer than the length D26 at the widthwise end position W3. This is because the presence of the protrusion 30 increases the lamination direction length of the internal electrode layer at the widthwise end vicinity position W2.

[0142] The length in the lamination direction of the internal electrode layers is longer at the position W2 near the end in the width direction than at the end W3 in the width direction, so that the internal layer portion 10 can generate a larger capacitance.

[0143] By forming a portion where the length in the lamination direction of the internal electrode layers is long at the position W2 near the end in the width direction, it is possible to generate capacitance with high precision, thereby increasing the precision of the capacitance generated by the multilayer ceramic capacitor 1.

[0144] In the process of manufacturing the multilayer ceramic capacitor 1, the laminate sheet may be pressed in the stacking direction T. This pressing may cause the stacking direction length of the inner layer portion 10 at the widthwise end W3 to be shorter than that at the widthwise center position W1. If the stacking direction length of the inner layer portion 10 at the widthwise end W3 is shortened, the reliability of the multilayer ceramic capacitor 1 may be reduced. In order to prevent the stacking direction length of the inner layer portion 10 at the widthwise end W3 from becoming shorter, the stacking direction length of the inner layer portion 10 at the widthwise center position W1 may be increased. To increase the stacking direction length of the inner layer portion 10 at the widthwise center position W1, for example, it is possible to increase the stacking direction length of the dielectric layers. Increasing the stacking direction length of the dielectric layers causes a decrease in the capacitance of the multilayer ceramic capacitor 1.

[0145] In the multilayer ceramic capacitor 1, at the widthwise end-neighbor position W2, a portion is formed in which the lamination direction length of the inner layer portion 10 is longer than at the widthwise end W3. This prevents a decrease in the length of the inner layer portion 10 at the widthwise end W3. This eliminates the need to increase the lamination direction length of the inner layer portion 10 at the widthwise center position W1. This means that the lamination direction length of the dielectric layer does not need to be increased. This allows the multilayer ceramic capacitor 1 to increase its capacitance.

[0146] (Strength) In the multilayer ceramic capacitor 1, the second length D2 is longer than the first length D1, thereby improving the electrical strength of the multilayer ceramic capacitor 1. The multilayer ceramic capacitor 1 may be exposed to a strong electric field, particularly at its ends. When the multilayer ceramic capacitor 1 is exposed to a strong electric field, dielectric breakdown may occur in the multilayer ceramic capacitor 1. In the multilayer ceramic capacitor 1, the length of the dielectric layer in the stacking direction is longer at a position W2 near the widthwise end than at a central position W1 in the widthwise direction. Furthermore, the length of the dielectric layer in the stacking direction is longer at a widthwise end W3 than at a position W2 near the widthwise end.

[0147] Therefore, the multilayer ceramic capacitor 1 of the present disclosure has increased strength against electric fields, particularly at the ends.

[0148] The manufacturing method of the multilayer ceramic capacitor 1 will be described in more detail with reference to Figures 5A, 5B, and 6. The process of printing a predetermined pattern of conductive paste for internal electrode layers and the like on a dielectric sheet will be described. Figure 5A is a diagram showing a state in which conductive paste 42 for internal electrode layers and step-reducing paste 44 have been printed on the dielectric sheet. Figure 5A is a top view of a surface parallel to the length direction L and width direction W. Figure 5B is a diagram showing two dielectric sheets 40 to be laminated. Figure 6 is a cross-sectional view taken along the line W-W' of Figure 5A.

[0149] As shown in FIG. 5A , a conductive paste 42 for the internal electrode layers is printed in a predetermined pattern on a dielectric sheet. The dielectric sheet is not shown in FIG. 5A . The dielectric sheet 40 is shown in FIGS. 5B and 6 . In the internal electrode layer pattern shown in FIG. 5A , recessed portions 50 are provided at both widthwise ends near the center position in the longitudinal direction. The recessed portions 50 refer to portions where a part of the outline of the internal electrode layer pattern is cut out. The structure of the internal electrode layer pattern provided with the recessed portions 50 is also called a racket structure. However, the internal electrode layer pattern is not limited to this racket structure. The internal electrode layer pattern may also be a pattern without the recessed portions 50.

[0150] A step-reducing paste 44 is disposed around the pattern of the conductive paste 42 for the internal electrode layers. The step-reducing paste 44 is printed on the dielectric sheet 40 before the conductive paste 42 for the internal electrode layers is printed on the dielectric sheet 40.

[0151] The conductive paste 42 for the internal electrode layers is printed so that a portion of it overlaps the step reduction paste 44. The description will be made based on FIG. 6 . The width direction length of the portion where the conductive paste 42 for the internal electrode layers overlaps the conductive paste 44 is indicated by a length D31. The length D31 is called the overlap length. The length of the overlap length D31 can be determined as appropriate. The length of the overlap length D31 can be, for example, 50 μm.

[0152] 6 , the configuration in which the conductive paste 42 overlaps the step-reducing paste 44 means that the conductive paste 42 is formed after the step-reducing paste 44 is formed. When the conductive paste 42 is formed after the step-reducing paste 44 is formed, the positions of the ends of the internal electrode layers in the length direction L tend to be aligned in the subsequent laminate 2. This is because the step-reducing paste 44 acts as a dam for the conductive paste 42 when the conductive paste 42 is formed.

[0153] The order of forming the step-reducing paste 44 and the conductive paste 42 may be such that the conductive paste 42 is formed first, and then the step-reducing paste 44 is formed. Even with this order of formation, it is possible to obtain the multilayer ceramic capacitor 1 having the preferred first length D1 and second length D2.

[0154] The portion where the conductive paste 42 for the internal electrode layers overlaps the step-reducing paste 44 is referred to as an overlapping portion 46. This overlapping portion 46 becomes the protruding portion 30 in the inner layer portion 10, indicated by 102 in FIG.

[0155] The printing thicknesses of the step-reducing paste 44 and the conductive paste 42 for the internal electrode layers will now be described. Length D32 in FIG. 6 indicates the printing thickness of the step-reducing paste 44. Length D33 in FIG. 6 indicates the printing thickness of the conductive paste 42 for the internal electrode layers. Lengths D32 and D33 can be set as appropriate. The ratio of length D32 to length D33, i.e., D32 / D33, can be set to, for example, 0.5.

[0156] By appropriately setting the overlap length D31 and the value of D32 / D33, it is possible to form an inner layer portion 10 having a structure as shown in FIG.

[0157] The length in the width direction W of the inner layer portion 10 can be manufactured so that D6 < D5 < D4 by stacking the inner layer portion 10 loosely without any measures to prevent steps, and then using a rubber press to locally push the outer layer portion into the gap portion.

[0158] The lamination of the dielectric sheets 40 on which the conductive paste 42 for the internal electrode layers is printed will be described with reference to Fig. 5B. Two dielectric sheets 40 are shown in Fig. 5B to explain the lamination method. A predetermined number of the dielectric sheets 40 are sequentially laminated using the lamination method shown in Fig. 5B.

[0159] The dielectric sheets 40 are stacked such that every other sheet is shifted in the length direction L. Two consecutively stacked dielectric sheets 40 are referred to as a first dielectric sheet 40A and a second dielectric sheet 40B. The second dielectric sheet 40B is stacked on the first dielectric sheet 40A in a state where it is shifted in the length direction L by approximately half the length of the dielectric sheet 40 in the length direction L with respect to the first dielectric sheet 40A.

[0160] The laminate, in which a predetermined number of dielectric sheets 40 are stacked, is cut at predetermined locations. The cutting positions are indicated by lines L1 and L2 in Fig. 5B. After cutting, the cut pieces are fired to obtain the laminate 2.

[0161] In the state of the laminate 2, the conductive paste 42 for the internal electrode layers printed on the first dielectric sheet 40A becomes the first internal electrode layer 6a, while the conductive paste 42 for the internal electrode layers printed on the second dielectric sheet 40B becomes the second internal electrode layer 6b.

[0162] In order to form the recess 50 in the conductive paste 42 for the internal electrode layers, the starting points where the length in the width direction W decreases are defined as a first recess end 51 and a second recess end 52. The first recess end 51 and the second recess end 52 are located opposite each other in the width direction W. The line connecting the first recess end 51 and the second recess end 52 is indicated by line L3.

[0163] In the conductive paste 42 for the internal electrode layers, the ends in the length direction L are defined as a first square end 53 and a second square end 54. The first square end 53 and the second square end 54 are positioned opposite each other in the width direction W. The line connecting the first square end 53 and the second square end 54 is indicated by line L4.

[0164] In the multilayer ceramic capacitor 1 of this embodiment, when the first dielectric sheet 40A and the second dielectric sheet 40B are laminated, the lines L3 and L4 are not overlapped. The direction in which the line L3 is offset from the line L4 is the direction in which the line L3 does not overlap the conductive paste 42 for the internal electrode layers printed on the dielectric sheets 40 to be laminated. In the example shown in Figure 5B, the line L3 is offset in the direction in which the line L3 on the first dielectric sheet 40A does not overlap the conductive paste 42 for the internal electrode layers printed on the second dielectric sheet 40B. In Figure 5B, the length by which the lines L3 and L4 are offset is indicated as length D50.

[0165] In the multilayer ceramic capacitor 1 of this embodiment, the dielectric sheets 40 are laminated so that the lines L3 and L4 do not overlap. Therefore, in the laminate 2 after firing, the internal electrode layers are as follows. The internal electrode layers will be described below with reference to FIG. 5B, assuming that the conductive paste 42 for the internal electrode layers shown in FIG. 5B is formed into internal electrode layers by firing. In FIG. 5B, the symbols for the internal electrode layers are enclosed in parentheses.

[0166] In the multilayer ceramic capacitor 1 of this embodiment, despite the formation of the recessed portion 50, the first extension electrode portion 8a of the first end face side outer layer portion LG1 has a portion whose length in the width direction W is the same as that of the first opposing electrode portion 7a of the longitudinal opposing portion LF. The portion indicated by length D50 is the portion where the length in the width direction W of the first extension electrode portion 8a is the same as the length in the width direction W of the first opposing electrode portion 7a.

[0167] In Figure 5B, the length in the width direction W of the first opposing electrode portion 7a of the longitudinal opposing portion LF is indicated by length D51. The length in the width direction W of the first extension electrode portion 8a of the first end surface side outer layer portion LG1 is indicated by length D52 within the range indicated by D50. Regarding the length in the width direction W of the first extension electrode portion 8a of the first end surface side outer layer portion LG1, the length on line L1 is indicated by D53. Line L1 corresponds to the end face of the laminate 2. D52 is equal to D51. Furthermore, D53 is shorter than D51 and D52. This is due to the formation of the recessed portion 50.

[0168] The above-described configuration improves reliability near the boundary between the first end-side outer layer portion LG1 and the longitudinally opposing portion LF. Note that while the above description has been given using the first end-side outer layer portion LG1 as an example, the same applies to the second end-side outer layer portion LG2.

[0169] (Measurement Method) The length of each portion of the multilayer ceramic capacitor 1, the laminate 2, the inner layer portion 10, etc. can be measured with a micrometer or an optical microscope. For example, the multilayer ceramic capacitor 1 is polished to a desired position, such as the center position in the longitudinal direction. Then, the cross section exposed by polishing can be observed with an optical microscope or the like to measure the length.

[0170] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible.

[0171] For example, the step-reducing paste 44 may be printed on the dielectric sheet 40 after the conductive paste 42 for the internal electrode layers is printed on the dielectric sheet 40. The overlap between the conductive paste 42 for the internal electrode layers and the step-reducing paste 44 may be provided on the sides along the width direction W in addition to the sides along the length direction L in the outline of the internal electrode layer pattern.

[0172] <1> A multilayer ceramic capacitor having a plurality of laminated dielectric layers, a plurality of first internal electrode layers and a plurality of second internal electrode layers laminated on the dielectric layers, the laminate having first and second main surfaces opposing each other in a lamination direction, first end faces and second end faces opposing each other in a length direction perpendicular to the lamination direction, and first and second side faces opposing each other in a width direction perpendicular to the lamination direction and the length direction, a first external electrode disposed on the first end face, and a second external electrode disposed on the second end face, wherein the laminate has an inner layer portion where the plurality of first internal electrode layers and the plurality of second internal electrode layers face each other, and an outer layer portion made of a dielectric material, wherein a length of the inner layer portion in a direction parallel to the lamination direction at a center position in the width direction is defined as a first length, a multilayer ceramic capacitor, wherein when a length of the inner layer portion in a direction parallel to the stacking direction at a position where the length from an end of the inner layer portion in the width direction in a direction parallel to another end of the inner layer portion in the width direction is 0.3% to 8.0% of the length of the inner layer portion in the width direction is defined as a second length, the second length is longer than the first length.

[0173] <2> The multilayer ceramic capacitor according to <1>, wherein the second length is 102.6% or less of the first length.

[0174] <3> The multilayer ceramic capacitor according to <1>, wherein the second length is longer than the first length, and a difference between the second length and the first length is 30 μm or less.

[0175] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein when a length of the inner layer portion at the end in the width direction in a direction parallel to the stacking direction is defined as a third length, the third length is shorter than the first length.

[0176] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein a fourth length is a length of the inner layer portion in a direction parallel to the width direction at a central position in the stacking direction, and a fifth length is a length of the inner layer portion in a direction parallel to the width direction at a position where the length from an end of the inner layer portion in the stacking direction toward the central position in the stacking direction of the inner layer portion is 10% to 40% of the length of the inner layer portion in the stacking direction, and the fifth length is shorter than the fourth length.

[0177] <6> The multilayer ceramic capacitor according to <5>, wherein when a length of the inner layer portion at the end portion in the stacking direction in a direction parallel to the width direction of the inner layer portion is defined as a sixth length, the sixth length is shorter than the fifth length.

[0178] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein, in the first internal electrode layer and the second internal electrode layer, a portion disposed in the internal layer portion is defined as a counter electrode portion, and in the first internal electrode layer, a portion disposed between the internal layer portion and the first end face, and in the second internal electrode layer, a portion disposed between the internal layer portion and the second end face are defined as lead electrode portions, and the lead electrode portions have a portion whose length in the width direction is the same as the length in the width direction of the counter electrode portion.

[0179] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 Outer dielectric layer 4 Inner dielectric layer 5a First dielectric layer 5b Second dielectric layer 6a First internal electrode layer 6b Second internal electrode layer 10 Inner layer portion 20a First external electrode 20b Second external electrode 30 Protuberance 40 Dielectric sheet 42 Conductive paste for internal electrode layer 44 Step reduction paste 46 Overlap portion 50 Depression portion IL Inner layer range LF Lengthwise facing portion WF Widthwise facing portion

Claims

1. A laminate comprising a plurality of stacked dielectric layers, a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked on the dielectric layers, having a first main surface and a second main surface facing each other in the stacking direction, a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction, and a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction and the length direction, A first external electrode disposed on the first end face, A multilayer ceramic capacitor having a second external electrode disposed on the second end face, The laminated body is The inner layer portion in which the plurality of first internal electrode layers and the plurality of second internal electrode layers face each other, It has an outer layer made of a dielectric material, The length of the inner layer in the direction parallel to the stacking direction at the central position in the width direction of the inner layer is defined as the first length. When the length of the inner layer in the direction parallel to the stacking direction at a position where the length from the end of the inner layer in the width direction to another end of the inner layer in the width direction is 0.3% or more and 8.0% or less of the length of the inner layer in the width direction, is defined as the second length, The second length is longer than the first length. Multilayer ceramic capacitor.

2. The second length is 102.6% or less of the first length. The multilayer ceramic capacitor according to claim 1.

3. The second length is longer than the first length. The difference between the second length and the first length is 30 μm or less. The multilayer ceramic capacitor according to claim 1.

4. When the length of the inner layer portion at the end portion in the width direction, in a direction parallel to the stacking direction, is defined as the third length, The third length is shorter than the first length. The multilayer ceramic capacitor according to claim 1.

5. The length of the inner layer in the direction parallel to the width direction at the central position of the inner layer in the stacking direction is defined as the fourth length. When the length of the inner layer in the direction parallel to the width direction at a position where the length from the end of the inner layer in the stacking direction to the central position of the inner layer in the stacking direction is 10% or more and 40% or less of the length of the inner layer in the stacking direction is defined as the fifth length, The fifth length is shorter than the fourth length. A multilayer ceramic capacitor according to any one of claims 1 to 4.

6. When the length of the inner layer portion at the end in the stacking direction, in a direction parallel to the width direction of the inner layer portion, is defined as the sixth length, The sixth length is shorter than the fifth length. A multilayer ceramic capacitor according to any one of claims 1 to 4.

7. In the first internal electrode layer and the second internal electrode layer, the portion located in the inner layer is designated as the opposing electrode portion. When the portion of the first internal electrode layer located between the inner layer and the first end face, and the portion of the second internal electrode layer located between the inner layer and the second end face are defined as the extracted electrode portion, The length in the width direction of the first or second end face of the extraction electrode portion is shorter than the length in the width direction of the opposing electrode portion. The extraction electrode portion has a portion whose length in the width direction is the same as the length in the width direction of the opposing electrode portion. A multilayer ceramic capacitor according to any one of claims 1 to 4.