Semiconductor device, control circuit, control method, program, and storage medium

Abstract

Provided are a semiconductor device, a control circuit, a control method, a program, and a storage medium capable of reducing power consumption. The semiconductor device includes a normally-on first semiconductor element, a p-type MOSFET second semiconductor element, and a control circuit. The first semiconductor element includes a first source terminal, a first drain terminal, and a first gate terminal. The second semiconductor element includes a second source terminal electrically connected to the first source terminal, a second drain terminal, and a second gate terminal. In a first state in which the potential of the second source terminal is greater than or equal to the potential of the second drain terminal, the control circuit applies a first voltage to a connection point between the first source terminal and the second source terminal. In a second state in which the potential of the second source terminal is less than the potential of the second drain terminal, the control circuit applies a second voltage to the connection point. In the second state, the second voltage is smaller than the first voltage, and the absolute value of the difference between an applied voltage to the second gate terminal and the second voltage is larger than the absolute value of a threshold voltage of the second semiconductor element.

Description

Semiconductor device, control circuit, control method, program, and storage medium

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, a control circuit, a control method, a program, and a storage medium.

[0002] 2. Description of the Related Art There is a semiconductor device that includes a semiconductor element and a control circuit that controls the semiconductor element. There is a demand for a technology that can reduce the power consumption of the semiconductor device.

[0003] Patent No. 6966008

[0004] An object of the present invention is to provide a semiconductor device, a control circuit, a control method, a program, and a storage medium that are capable of reducing power consumption.

[0005] The semiconductor device according to the embodiment includes a first semiconductor element, a second semiconductor element, and a control circuit. The first semiconductor element includes a first source terminal, a first drain terminal, and a first gate terminal. The first semiconductor element is a normally-on type. The second semiconductor element includes a second source terminal, a second drain terminal, and a second gate terminal electrically connected to the first source terminal. The second semiconductor element is a p-type MOSFET. The control circuit is electrically connected to a connection point between the first source terminal and the second source terminal. In a first state in which the potential of the second source terminal is equal to or greater than the potential of the second drain terminal, the control circuit applies a first voltage to the connection point. In a second state in which the potential of the second source terminal is less than the potential of the second drain terminal, the control circuit applies a second voltage to the connection point. In the second state, the second voltage is smaller than the first voltage, and the absolute value of the difference between the voltage applied to the second gate terminal and the second voltage is greater than the absolute value of the threshold voltage of the second semiconductor element.

[0006] FIG. 1 is a schematic diagram showing the configuration of a semiconductor device according to an embodiment. FIG. 2 is a circuit diagram showing the configuration of an electric circuit according to an embodiment. FIG. 3 is a timing chart showing control of the electric circuit according to an embodiment. FIG. 4 is a schematic diagram showing current flow in the electric circuit according to an embodiment. FIG. 5 is a schematic diagram showing current flow in the electric circuit according to an embodiment. FIG. 6 is a schematic diagram showing current flow in the electric circuit according to an embodiment. FIG. 7 is a schematic diagram showing current flow in the electric circuit according to an embodiment. FIG. 8 is a graph showing characteristics of a first semiconductor element.

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those already described are designated by the same reference numerals, and detailed description will be omitted as appropriate.

[0008] 1 is a schematic diagram showing the configuration of a semiconductor device according to an embodiment. As shown in FIG. 1, the semiconductor device 1 according to the embodiment includes a first semiconductor element 10, a second semiconductor element 20, and a control circuit 30. The first semiconductor element is a normally-on semiconductor element (transistor). The second semiconductor element 20 is a p-type MOSFET.

[0009] The first semiconductor element 10 includes a first source terminal 11, a first drain terminal 12, and a first gate terminal 13. The second semiconductor element 20 includes a second source terminal 21, a second drain terminal 22, and a second gate terminal 23. The first source terminal 11 and the second source terminal 21 are electrically connected to each other. The potential of the first source terminal 11 is substantially the same as the potential of the second source terminal 21. The first semiconductor element 10 and the second semiconductor element 20 are cascode-connected.

[0010] The control circuit 30 is electrically connected to a connection point C between the first source terminal 11 and the second source terminal 21. The control circuit 30 is capable of controlling the potentials of the connection point C and the second gate terminal 23. The control circuit 30 is also electrically connected to the second source terminal 21 and the second drain terminal 22 by wirings L1 and L2, respectively, and is capable of detecting the potentials of the second source terminal 21 and the second drain terminal 22. The control circuit 30 includes a central processing unit (CPU), a memory, etc.

[0011] The first gate terminal 13 is electrically connected to a gate drive circuit 40 outside the semiconductor device 1. The potential of the first gate terminal 13 is controlled by the gate drive circuit 40.

[0012] The first semiconductor element 10 is a normally-on type. Therefore, when the negative voltage of the first gate terminal 13 relative to the first source terminal 11 is equal to or greater than the threshold, the first semiconductor element 10 is in an on state. When the negative voltage of the first gate terminal 13 relative to the first source terminal 11 is less than the threshold, the first semiconductor element 10 is in an off state. Note that, here, a negative voltage equal to or greater than the threshold refers to a state in which the negative voltage value is closer to zero than the threshold. For example, when the threshold is −12 V and the negative voltage of the first gate terminal 13 is in the range of −10 V to 0 V, the negative voltage is equal to or greater than the threshold.

[0013] The second semiconductor element 20 is a p-type MOSFET. Therefore, when the negative voltage of the second gate terminal 23 with respect to the second source terminal 21 is less than the threshold, the second semiconductor element 20 is in an on state. When the negative voltage of the second gate terminal 23 with respect to the second source terminal 21 is equal to or greater than the threshold, the second semiconductor element 20 is in an off state.

[0014] For example, a voltage is applied to the first drain terminal 12 from an external power supply. When both the first semiconductor element 10 and the second semiconductor element 20 are in an on state, a current flows through the first semiconductor element 10 and the second semiconductor element 20. When the first semiconductor element 10 is in an on state and the second semiconductor element 20 is in an off state, no current flows through the second semiconductor element 20, and the potential of the first source terminal 11 rises. The negative voltage of the first gate terminal 13 relative to the first source terminal 11 becomes less than the threshold, and the first semiconductor element 10 also becomes off. Thereafter, a first voltage greater than the absolute value of the threshold of the first semiconductor element 10 is applied to the connection point C via the control circuit 30, and the first semiconductor element 10 remains in the off state. Thereafter, the control circuit 30 causes the negative voltage of the second gate terminal 23 relative to the second source terminal 21 of the second semiconductor element 20 to become less than the threshold voltage of the second semiconductor element 20, thereby turning on the second semiconductor element 20. In this state, the first gate terminal 13 of the first semiconductor element 10 is controlled by the gate drive circuit 40, whereby the first semiconductor element 10 is switched on while the second semiconductor element 20 remains on. By switching the first semiconductor element 10, the flow of current in the semiconductor device 1 can be controlled.

[0015] The control circuit 30 can also determine between a first state in which the potential of the second source terminal 21 is equal to or greater than the potential of the second drain terminal 22, and a second state in which the potential of the second source terminal 21 is less than the potential of the second drain terminal 22. The first state is a state in which a current can flow from the first semiconductor element 10 to the second semiconductor element 20. The second state is a state in which a current can flow from the second semiconductor element 20 to the first semiconductor element 10. The second state occurs during reverse recovery after the second semiconductor element 20 is turned off.

[0016] In the first state, the control circuit 30 applies a first voltage to the connection point C. When the absolute value of the difference between the first voltage and the potential applied to the first gate terminal 13 by the gate drive circuit 40 is smaller than the absolute value of the threshold voltage of the first semiconductor element 10, the first semiconductor element 10 is in the ON state. When the absolute value of the difference between the first voltage and the voltage applied to the first gate terminal 13 by the gate drive circuit 40 is larger than the absolute value of the threshold voltage of the first semiconductor element 10, the first semiconductor element 10 is in the OFF state.

[0017] In the second state, the control circuit 30 applies a second voltage to the connection point C. The second voltage is smaller than the first voltage. At this time, the absolute value of the difference between the second voltage and the potential applied to the first gate terminal 13 by the gate drive circuit 40 is smaller than the absolute value of the threshold voltage of the first semiconductor element 10. Therefore, the first semiconductor element 10 is in the ON state. On the other hand, the absolute value of the difference between the second voltage and the voltage applied to the second gate terminal 23 by the control circuit 30 is greater than the absolute value of the threshold voltage of the second semiconductor element 20. Therefore, the second semiconductor element 20 is in the ON state. In the second state, a reverse current may flow through the first semiconductor element 10. For example, when the first semiconductor element 10 is turned off, a voltage drop that occurs in the first semiconductor element 10 when a current flows from the second semiconductor element 20 toward the first semiconductor element 10 is reduced by the first semiconductor element 10 temporarily being in the ON state.

[0018] FIG. 2 is a circuit diagram showing the configuration of an electric circuit according to an embodiment. The operation of the electric circuit using the semiconductor device according to the embodiment will be described in more detail below with reference to a specific example. The electric circuit 100 shown in FIG. 2 includes a semiconductor device 1a, a semiconductor device 1b, a coil 2, and a power supply 3. The configurations of the semiconductor devices 1a and 1b are the same as the configuration of the semiconductor device 1. The semiconductor device 1a includes a first semiconductor element 10a and a second semiconductor element 20a. The semiconductor device 1b includes a first semiconductor element 10b and a second semiconductor element 20b.

[0019] The semiconductor devices 1a, 1b, and power supply 3 are connected in series. The semiconductor device 1a is connected to the high-voltage side of the power supply 3. The semiconductor device 1b is connected to the low-voltage side of the power supply 3. The second drain terminal 22a of the second semiconductor element 20a of the semiconductor device 1a is electrically connected to the first drain terminal 12b of the first semiconductor element 10b of the semiconductor device 1b. The semiconductor device 1a and the coil 2 are connected in parallel. By controlling the respective operations of the first semiconductor element 10a, the first semiconductor element 10b, the second semiconductor element 20a, and the second semiconductor element 20b, current flows alternately through the semiconductor devices 1a and 1b.

[0020] The electric circuit 100 is applicable to a converter. Generally, in a converter, a first semiconductor element 10 a on a high voltage side and a first semiconductor element 10 b on a low voltage side are alternately turned on. In this example, in order to briefly explain the gist of the embodiment, an example will be described in which only the first semiconductor element 10 b on the low voltage side is turned on and off for switching.

[0021] Fig. 3 is a timing chart showing the control of the electric circuit according to the embodiment. Figs. 4 to 7 are schematic diagrams showing the flow of current in the electric circuit according to the embodiment. Note that Figs. 4 to 7 omit wiring for the control circuit 30a to detect the potential of the second source terminal 21a and the potential of the second drain terminal 22a, and wiring for the control circuit 30b to detect the potential of the second source terminal 21b and the potential of the second drain terminal 22b.

[0022] Regarding the symbols in the timing chart shown in FIG. 3 , as shown in FIG. 2 , GaN Vg1 represents the voltage applied to the first gate terminal 13a of the first semiconductor element 10a. GaN Vg2 represents the voltage applied to the first gate terminal 13b of the first semiconductor element 10b. Vn1 represents the voltage at the connection point Ca between the first source terminal 11a of the first semiconductor element 10a and the second source terminal 21a of the second semiconductor element 20a. Vdd1 is supplied to the control circuit 30a. The control circuit 30a controls the supplied Vdd1 and supplies Vn1 to the connection point Ca. Vn2 represents the voltage at the connection point Cb between the first source terminal 11b of the first semiconductor element 10b and the second source terminal 21b of the second semiconductor element 20b. Vdd2 is supplied to the control circuit 30b. The control circuit 30b controls the supplied Vdd2 and supplies Vn2 to the connection point Cb. Vg1 denotes a voltage applied to the second gate terminal 23a of the second semiconductor element 20a, and Vg2 denotes a voltage applied to the second gate terminal 23b of the second semiconductor element 20b.

[0023] 3, GaN Vg1, GaN Vg2, Vn1, and Vn2 are all 0 V. In this state, even if a high voltage is applied to Vdd3 (not shown) in FIG. 3, the second semiconductor elements 20a and 20b are in the off state, so the first semiconductor elements 10a and 10b are also in the off state, and no current flows through the electric circuit 100.

[0024] At timing t1, Vdd1 and Vdd2 are supplied to the control circuits 30a and 30b, and Vn1 and Vn2 begin to rise. At this time, the second semiconductor elements 20a and 20b are in the off state, so the first semiconductor elements 10a and 10b continue to be in the off state.

[0025] As Vn1 and Vn2 increase, Vn1 relative to GaN Vg1 and Vn2 relative to GaN Vg2 increase. Until then, the control circuits 30a and 30b apply the same voltage as Vn1 to Vg1 and the same voltage as Vn2 to Vg2. Then, from timing t2 to timing t3, the control circuits 30a and 30b increase the absolute values ​​of Vg1 relative to Vn1 and Vg2 relative to Vn2, respectively, above the absolute values ​​of the thresholds of the second semiconductor elements 20a and 20b. This causes the second semiconductor elements 20a and 20b to enter the ON state. Furthermore, between timing t1 and timing t3, Vn1 and Vn2 increase from 0 V to 15 V. 15 V is an example of a first voltage. GaN Vg1 relative to Vn1 and GaN Vg2 relative to Vn2 increase from 0 V to −15 V between timing t1 and timing t3, thereby switching the first semiconductor element 10a and the first semiconductor element 10b to the OFF state.

[0026] At timing t4, the GaN Vg2 increases from 0 V to 15 V. The GaN Vg2 relative to Vn2 increases from −15 V to 0 V. This switches the first semiconductor element 10b to the ON state. As the first semiconductor element 10b switches to the ON state, a current I1 flows through the coil 2, the first semiconductor element 10b, and the second semiconductor element 20b, as shown in FIG.

[0027] At timing t5, the GaN Vg2 decreases from 15 V to 0 V. The GaN Vg2 relative to Vn2 increases from 0 V to −15 V. This switches the first semiconductor element 10b to the off state. When the first semiconductor element 10b is turned off, the inductance component of the electric circuit 100 causes a current to flow from the second semiconductor element 20a to the first semiconductor element 10a.

[0028] At timing t6, Vn1 decreases from 15 V to 7 V. 7 V is an example of a second voltage. As a result, GaN Vg1 relative to Vn1 decreases from −15 V to −7 V. −7 V is greater than the threshold voltage of the second semiconductor element 20a. Therefore, the second semiconductor element 20a is in the ON state. Therefore, as shown in FIG. 5, a current I2 flows through the coil 2, the second semiconductor element 20a, and the first semiconductor element 10a.

[0029] At timing t7, Vn1 increases from 7 V to 15 V. GaN Vg1 relative to Vn1 also increases from −7 V to −15 V. At timing t8, GaN Vg2 increases from 0 V to 15 V. GaN Vg2 relative to Vn2 decreases from −15 V to 0 V. This switches the first semiconductor element 10b to the ON state. As the first semiconductor element 10b and the second semiconductor element 20b switch to the ON state, a current I3 flows from the power source 3 to the coil 2, the first semiconductor element 10b, and the second semiconductor element 20b, as shown in FIG. 6 .

[0030] After timing t8, the control from timing t4 to t7 is executed again. For example, at timing t8, similar to timing t4, current I3 flows through the coil 2, the first semiconductor element 10b, and the second semiconductor element 20b, as shown in Figure 6. At timing t10, similar to timing t6, current I4 flows through the coil 2, the second semiconductor element 20a, and the first semiconductor element 10a, as shown in Figure 7. Control similar to that from timing t4 to t7 may be repeated multiple times.

[0031] 3, from timing t8 to t17, the same control as that at timings t4 and t5 and the same control as that at timings t6 and t7 are repeated alternately. In addition, from timing t17 onwards, a termination operation is executed.

[0032] Specifically, in the termination operation, Vn1 and Vn2 decrease at timing t18. As a result, the voltage between Vn1 and Vg1, the voltage between Vn2 and Vg2, Vn1 relative to GaN Vg1, and Vn2 relative to GaN Vg2 decrease. Furthermore, from timing t18 to timing t19, the control circuits 30a and 30b respectively decrease the absolute values ​​of Vg1 relative to Vn1 and Vg2 relative to Vn2 to be less than the absolute values ​​of the thresholds of the second semiconductor elements 20a and 20b. The GaN Vg1 relative to Vn1 and the GaN Vg2 relative to Vn2 decrease from -15 V to 0 V between timing t19 and timing t20. This completes the series of operations of the electric circuit 100.

[0033] The advantages of the embodiment will be described. In the electric circuit 100, when the first semiconductor element 10b on the low-voltage side is turned on and then turned off, a period (dead time) is provided in which both the first semiconductor element 10a and the first semiconductor element 10b are in the off state. During this period, as shown in FIG. 5, a current I2 due to an inductance component flows through the first semiconductor element 10a. It is desirable that the power consumption due to the current I2 be small.

[0034] In the embodiment, the control circuit 30 changes the voltage at the connection point C between the first source terminal 11 and the second source terminal 21 according to the relationship between the potential of the second source terminal 21 and the potential of the second drain terminal 22. Specifically, the control circuit 30 applies a first voltage to the connection point C in a first state in which the potential of the second source terminal 21 is equal to or higher than the potential of the second drain terminal 22. The control circuit 30 applies a second voltage to the connection point C in a second state in which the potential of the second source terminal 21 is lower than the potential of the second drain terminal 22. In this second state, the second voltage is smaller than the first voltage. Furthermore, the absolute value of the difference between the voltage applied to the second gate terminal 23 and the second voltage is greater than the absolute value of the threshold voltage of the second semiconductor element 20.

[0035] FIG. 8 is a graph showing the characteristics of the first semiconductor element. In FIG. 8, the horizontal axis represents the voltage Vds of the first drain terminal 12 relative to the first source terminal 11. The vertical axis represents the current Id flowing through the first semiconductor element 10. FIG. 8 shows the relationship between the voltage Vds and the current Id when the current Id flows from the second semiconductor element 20 to the first semiconductor element 10. The solid line represents the relationship when the second voltage is applied to the connection point C in the second state. The dashed line represents the relationship when the first voltage is applied to the connection point C in the second state. From FIG. 8, it can be seen that the current Id increases as the voltage Vds increases. The product of the voltage Vds and the current Id corresponds to the power consumption. Therefore, reducing the voltage Vds is effective in reducing power consumption during dead time.

[0036] According to the embodiment, in a first state in which a current can flow from the second source terminal 21 to the second drain terminal 22, the control circuit 30 applies a relatively large first voltage to the connection point C. On the other hand, in a second state in which a current can flow from the second drain terminal 22 to the second source terminal 21, the control circuit 30 applies a relatively small second voltage to the connection point C. That is, in the dead time, a relatively small second voltage is applied to the connection point C. By applying the second voltage to the connection point C in the second state, the voltage Vds can be made smaller than when the first voltage is applied to the connection point C. For example, as shown in FIG. 8 , the voltage Vds can be made substantially zero. This reduces the power consumption of the first semiconductor element 10 during the dead time.

[0037] The determination of whether the semiconductor device 1 is in the first state or the second state may be performed by a processing circuit other than the control circuit 30, or may be performed by the control circuit 30. Preferably, the control circuit 30 performs the determination of whether the semiconductor device 1 is in the first state or the second state. By having the control circuit 30 determine the state, there is no need to provide a circuit separate from the control circuit 30. This allows the semiconductor device 1 to be made smaller.

[0038] For example, the control circuit 30 determines whether the device is in the first state or the second state by detecting the potential of the second source terminal 21 and the potential of the second drain terminal 22. Alternatively, the control circuit 30 may determine whether the device is in the first state or the second state by detecting the direction of the current in the second source terminal 21 or the second drain terminal 22. Any detected value may be used to determine whether the device is in the first state or the second state, as long as it can determine whether the device is in the first state or the second state.

[0039] The first semiconductor element 10 is preferably an element containing gallium nitride. Using an element using gallium nitride as the first semiconductor element 10 increases the breakdown voltage of the first semiconductor element 10 and reduces the on-resistance of the first semiconductor element 10. The second semiconductor element 20 is, for example, a p-type MOSFET using single crystal silicon.

[0040] The above operations by the control circuit 30 may be recorded as a program that can be executed by a computer on a magnetic disk (such as a flexible disk or hard disk), an optical disk (such as a CD-ROM, CD-R, CD-RW, DVD-ROM, DVD±R, DVD±RW), a semiconductor memory, or other non-transitory computer-readable storage medium.

[0041] For example, information recorded on a recording medium can be read by a computer (processing circuit). The recording medium may have any recording format (storage format). For example, the computer reads a program from the recording medium and causes a CPU to execute instructions written in the program based on the program. The computer may acquire (or read) the program via a network.

[0042] Embodiments of the present invention include the following features: (Feature 1) A semiconductor device comprising: a normally-on first semiconductor element including a first source terminal, a first drain terminal, and a first gate terminal; a second semiconductor element that is a p-type MOSFET including a second source terminal, a second drain terminal, and a second gate terminal electrically connected to the first source terminal; and a control circuit electrically connected to a connection point between the first source terminal and the second source terminal, the control circuit applying a first voltage to the connection point in a first state in which a potential of the second source terminal is equal to or higher than a potential of the second drain terminal, and applying a second voltage to the connection point in a second state in which a potential of the second source terminal is lower than a potential of the second drain terminal, the second voltage being smaller than the first voltage in the second state, and an absolute value of a difference between the voltage applied to the second gate terminal and the second voltage being greater than an absolute value of a threshold voltage of the second semiconductor element. (Feature 2) The semiconductor device according to Feature 1, wherein in the first state, an absolute value of a difference between the potential applied to the first gate terminal and the first voltage is smaller than an absolute value of a threshold voltage of the first semiconductor element, and in the second state, an absolute value of a difference between the voltage applied to the second gate terminal and the second voltage is greater than an absolute value of a threshold voltage of the first semiconductor element. (Feature 3) The semiconductor device according to Feature 1 or 2, wherein the control circuit is capable of detecting a potential of the second source terminal and a potential of the second drain terminal, and determines whether the state is the first state or the second state based on the detected potential of the second source terminal and the detected potential of the second drain terminal. (Feature 4) The semiconductor device according to any one of Features 1 to 3, wherein the control circuit is capable of detecting a direction of a current flowing through the second source terminal or the second drain terminal, and determines whether the state is the first state or the second state based on the detected direction. (Feature 5) The semiconductor device according to any one of Features 1 to 4, wherein the first semiconductor element includes gallium nitride.(Feature 6) A control circuit electrically connected to a connection point between a first source terminal of a normally-on first semiconductor element and a second source terminal of a second semiconductor element that is a p-type MOSFET, the control circuit applying a first voltage to the connection point when a potential of the second source terminal is equal to or higher than a potential of a second drain terminal of the second semiconductor element, and applying a second voltage to the connection point when a potential of the second source terminal is lower than a potential of the second drain terminal, the second voltage being lower than the first voltage, and an absolute value of a difference between the potential of the second drain terminal and the second voltage being higher than an absolute value of a threshold voltage of the second semiconductor element. (Feature 7) A control method for a semiconductor device including a normally-on first semiconductor element including a first source terminal and a first drain terminal, and a second semiconductor element which is a p-type MOSFET and includes a second source terminal electrically connected to the first source terminal and a second drain terminal, the control method comprising: applying a first voltage to a connection point between the first source terminal and the second source terminal when a potential of the second source terminal is equal to or higher than a potential of the second drain terminal; and applying a second voltage to the connection point when the potential of the second source terminal is lower than a potential of the second drain terminal, the second voltage being lower than the first voltage, and an absolute value of a difference between the potential of the second drain terminal and the second voltage being higher than an absolute value of a threshold voltage of the second semiconductor element. (Feature 8) A program for causing a computer to execute the control method according to Feature 7. (Feature 9) A storage medium having the program according to Feature 8 stored therein.

[0043] According to the embodiments described above, a semiconductor device, a control circuit, a control method for a semiconductor device, a program, and a storage medium that can reduce power consumption are provided.

[0044] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other.

[0045] 1, 1a, 1b: semiconductor device, 2: coil, 3: power supply, 10, 10a, 10b: first semiconductor element, 11, 11a, 11b: first source terminal, 12, 12a, 12b: first drain terminal, 13, 13a, 13b: first gate terminal, 20, 20a, 20b: second semiconductor element, 21, 21a, 21b: second source terminal, 22, 22a, 22b: second drain terminal, 23, 23a, 23b: second gate terminal, 30, 30a, 30b: control circuit, 40: gate drive circuit, 100: electric circuit, C, Ca, Cb: connection points, I1 to I4: current, L1, L2: wiring

Claims

1. A normally-on type first semiconductor element including a first source terminal, a first drain terminal, and a first gate terminal, A second semiconductor element which is a p-type MOSFET, including a second source terminal, a second drain terminal, and a second gate terminal electrically connected to the first source terminal, A control circuit electrically connected to the connection point between the first source terminal and the second source terminal, In the first state, where the potential of the second source terminal is greater than or equal to the potential of the second drain terminal, a first voltage is applied to the connection point. In the second state, where the potential of the second source terminal is less than the potential of the second drain terminal, a second voltage is applied to the connection point. In the second state, the second voltage is smaller than the first voltage, and the absolute value of the difference between the voltage applied to the second gate terminal and the second voltage is greater than the absolute value of the threshold voltage of the second semiconductor element, the control circuit, A semiconductor device equipped with the following features.

2. In the first state, the absolute value of the difference between the potential applied to the first gate terminal and the first voltage is smaller than the absolute value of the threshold voltage of the first semiconductor element. The semiconductor device according to claim 1, wherein in the second state, the absolute value of the difference between the voltage applied to the second gate terminal and the second voltage is greater than the absolute value of the threshold voltage of the second semiconductor element.

3. The semiconductor device according to claim 1 or 2, wherein the control circuit is capable of detecting the potential of the second source terminal and the potential of the second drain terminal, and determines the first state and the second state based on the detected potential of the second source terminal and the potential of the second drain terminal.

4. The semiconductor device according to claim 1 or 2, wherein the control circuit is capable of detecting the direction of the current flowing to the second source terminal or the second drain terminal, and determines the first state and the second state based on the detected direction.

5. The semiconductor device according to claim 1 or 2, wherein the first semiconductor element comprises gallium nitride.

6. A control circuit electrically connected to the connection point between the first source terminal of a normally-on type first semiconductor element and the second source terminal of a second semiconductor element which is a p-type MOSFET, If the potential of the second source terminal is greater than or equal to the potential of the second drain terminal of the second semiconductor element, a first voltage is applied to the connection point. If the potential of the second source terminal is less than the potential of the second drain terminal, a second voltage is applied to the connection point. The second voltage is lower than the first voltage. A control circuit in which the absolute value of the difference between the voltage applied to the second gate terminal of the second semiconductor element and the second voltage is higher than the absolute value of the threshold voltage of the second semiconductor element.

7. A normally-on type first semiconductor element including a first source terminal and a first drain terminal, A control method for a semiconductor device comprising a second semiconductor element which is a p-type MOSFET and includes a second source terminal electrically connected to the first source terminal and a second drain terminal, If the potential of the second source terminal is greater than or equal to the potential of the second drain terminal, a first voltage is applied to the connection point between the first source terminal and the second source terminal. If the potential of the second source terminal is less than the potential of the second drain terminal, a second voltage is applied to the connection point. A control method wherein the second voltage is lower than the first voltage, and the absolute value of the difference between the voltage applied to the second gate terminal of the second semiconductor element and the second voltage is higher than the absolute value of the threshold voltage of the second semiconductor element.

8. A program that causes a computer to execute the control method described in claim 7.

9. A storage medium storing the program described in claim 8.