Circuit for estimating the junction temperature of a power transistor and method for estimating the junction temperature of a power transistor

Abstract

To provide a temperature estimation circuit for a power transistor capable of correctly estimating a junction temperature even when a threshold voltage Vth varies.SOLUTION: A storage unit 8 stores data indicating the relationship between an inter-terminal voltage Vds_on, a current Id, a junction temperature Tj of a FET 1, and a fluctuation amount Vth_shift of a threshold voltage Vth of the FET 1 with respect to a plurality of gate drive voltages acquired in advance. A temperature estimation unit 7 estimates the junction temperature Tj dependent on the fluctuation amount Vth_shift corresponding to each gate drive voltage stored in the storage unit 8 according to the inter-terminal voltage Vds_on and the drain current Id detected when the gate of the FET1 is driven with a plurality of gate drive voltages, and sets the optimal value obtained by performing statistical processing on each junction temperature Tj estimated for each gate drive voltage Vgs as the final estimated junction temperature Tj.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a circuit and method for estimating the junction temperature of a power transistor.

Background Art

[0002] For power transistors used in inverters and the like, a circuit for detecting the junction temperature of the transistor is provided to detect abnormal heat generation due to overcurrent or the like. When the detected temperature reaches a predetermined temperature, the output of the inverter is restricted to protect the system including the power transistor. If the accuracy of this temperature detection is improved, the required margin for the thermal design of the power transistor can be reduced, and thus cost reduction and the like can be achieved.

[0003] As a technique for detecting the junction temperature, for example, as disclosed in Patent Documents 1 and 2, a method has been proposed in which the on-resistance Ron of a power device is estimated from the on-voltage Vds_on and the element current Id of a power transistor, and the junction temperature Tj is estimated using its temperature characteristics.

[0004] Here, the on-resistance Ron of a high-voltage vertical power device is composed of four resistance elements shown in Equation (1), and among these, the channel resistance Rch and the drift resistance Rd occupy most of it. Ron≒Rch+Rd+Rsub+ Rpackage …(1) Rsub: Substrate resistance, Rpackage: Resistance of mounting components The channel resistance Rch and the drift resistance Rd are expressed by Equation (2) and Equation (3), respectively.

[0005]

Equation

[0006] Here, although it depends on the device structure, generally both the threshold voltage Vth and the electron mobility μn_ch in the channel have negative temperature characteristics. In the practical range, for example, with a gate drive voltage Vgs of 20V, the temperature characteristics of the electron mobility μn_ch have a greater influence than the threshold voltage Vth. Therefore, the channel resistance Rch has positive temperature characteristics. On the other hand, since the electron mobility μn_d in the drift layer also has negative temperature characteristics, the drift resistance Rd also has positive temperature characteristics. Based on the above, conventional techniques focus on the temperature dependence of the on-resistance Ron and estimate the junction temperature Tj by detecting the on-resistance Ron. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Patent No. 6522232 [Patent Document 2] Patent No. 6885862 [Overview of the project] [Problems that the invention aims to solve]

[0008] For example, SiC (silicon carbide) MOSFETs, which have been increasingly put into practical use as power devices in recent years, have a problem in that the threshold voltage Vth fluctuates during use due to the charge trapping phenomenon at the gate oxide interface. As a result of this fluctuation, the channel resistance Rch fluctuates according to equation (2), and the temperature characteristics of the on-resistance Ron also fluctuate. Considering this fluctuation, it is difficult to correctly estimate the junction temperature Tj by simply detecting the on-resistance Ron, as in conventional techniques.

[0009] The present invention has been made in view of the above circumstances, and its object is to provide a temperature estimation circuit and method for a power transistor that can correctly estimate the junction temperature even when the threshold voltage Vth fluctuates. [Means for solving the problem]

[0010] According to the power transistor temperature estimation circuit described in claim 1, the voltage detection unit (3) detects the terminal voltage applied between the conductive terminals while the power transistor (1) is ON, and the current detection unit (4) detects the current flowing through the power transistor at the same timing as the voltage detection unit detects the voltage. A power transistor is a transistor used for switching over relatively large amounts of power, and is a general term for power MOSFETs, SiC MOSFETs, IGBTs, etc. The memory unit (8,23) stores data that has been acquired in advance, showing the relationship between terminal voltage, current, junction temperature of the power transistor, and the amount of fluctuation of the threshold voltage of the power transistor with respect to multiple gate drive voltages.

[0011] The temperature estimation unit (7,22) estimates the junction temperature, which is dependent on the fluctuation amount corresponding to each gate drive voltage and is stored in the memory unit, based on the terminal voltage detected by the voltage detection unit and the current detected by the current detection unit when the gate drive unit drives the gate of the power transistor with multiple gate drive voltages. The optimal value obtained by performing statistical processing on each junction temperature estimated for each of the multiple gate drive voltages is then set as the final estimated junction temperature.

[0012] With this configuration, when the gate of a power transistor is driven by multiple gate drive voltages, data indicating the fluctuation amount of the threshold voltage of the power transistor, corresponding to the terminal voltage and current obtained for each gate drive voltage, can be obtained from the storage unit. Since the fluctuation of the threshold voltage affects the fluctuation of the junction temperature, a data set of junction temperatures corresponding to the fluctuation amount of the threshold voltage obtained for each gate drive voltage can be obtained. The junction temperature is estimated by selecting the data with the closest values ​​from each data set and performing statistical processing on them to obtain the optimal value, which is then used as the final estimated junction temperature. Therefore, even if the threshold voltage fluctuates while the power transistor is in use, the junction temperature can be estimated with high accuracy.

[0013] According to the power transistor temperature estimation circuit described in claim 2, the on-resistance calculation unit (6) calculates the on-resistance of the power transistor according to the terminal voltage detected by the voltage detection unit and the current detected by the current detection unit. The data stored in the memory unit are characteristics of the on-resistance, junction temperature, and the amount of variation of the on-resistance corresponding to a plurality of gate drive voltages, and the temperature estimation unit estimates the junction temperature using the on-resistance calculated by the on-resistance calculation unit and the data stored in the memory unit. Since fluctuations in the threshold voltage affect fluctuations in the junction temperature by affecting fluctuations in the on-resistance, it is possible to estimate the junction temperature according to the amount of threshold voltage fluctuation for the on-resistance obtained for each gate drive voltage. Furthermore, the number of data parameters to be stored in the memory unit can be reduced by one.

[0014] According to the power transistor temperature estimation circuit described in claim 3, the on-resistance data stored in the memory unit is data obtained when the power transistor is operated by a gate drive voltage obtained by adding or subtracting a value including the fluctuation amount from each of a plurality of reference gate drive voltages for each junction temperature. This makes it possible to estimate the junction temperature with high accuracy based on data previously obtained for power transistors that are in a state without characteristic degradation before being used in the market. [Brief explanation of the drawing]

[0015] [Figure 1] In the first embodiment, a functional block diagram showing the configuration of the junction temperature estimation circuit is provided. [Figure 2] Circuit diagram showing the configuration of the voltage detection unit. [Figure 3] Waveform diagram showing the voltage applied to each input terminal of a differential amplifier. [Figure 4] Flowchart showing the main process [Figure 5] Flowchart showing the Tj,Vth_shift detection process [Figure 6] Image diagram of the 3D data map at Vgs=20V stored in the memory unit. [Figure 7]Image diagram of the three-dimensional data map at Vgs = 18V [Figure 8] Diagram showing the processing image corresponding to step S14 [Figure 9] Diagram showing the processing image corresponding to step S18 [Figure 10] Diagram showing the processing image corresponding to step S19 [Figure 11] Diagram showing the data table corresponding to FIG. 6 [Figure 12] Diagram showing the data table corresponding to FIG. 7 [Figure 13] Diagram showing the data group extracted in step S14 [Figure 14] Diagram showing the data group extracted in step S18 [Figure 15] Diagram explaining the process of step S19 [Figure 16] Diagram showing the data table when the reference of the gate drive voltage Vgs is set to five types [Figure 17] Diagram showing the on-resistance Ron with respect to five types of reference gate drive voltages Vgs in the range of the junction temperature Tj = -50°C to 200°C in 10°C increments [Figure 18] Diagram showing the plotted data shown in FIG. 17 [Figure 19] Functional block diagram showing the configuration of the junction temperature estimation circuit in the second embodiment [Figure 20] Flowchart showing the main process [Figure 21] Flowchart showing the Tj detection process

Mode for Carrying Out the Invention

[0016] (First Embodiment) As shown in Figure 1, the junction temperature estimation circuit of this embodiment estimates the junction temperature Tj of a power transistor, such as a SiC (silicon carbide) MOSFET 1. The gate drive unit 2, which drives the gate of FET 1, receives a PWM signal generated by a PWM signal generation unit (not shown) and a Vgs command as inputs. The gate drive unit 2 is configured to change the voltage applied to the gate of FET 1 according to the input Vgs command.

[0017] The drain and source terminals of FET1, which are conductive terminals, are connected to the respective input terminals of the voltage detection unit 3. A shunt resistor 4 is connected to the source of FET1, and both ends of the shunt resistor 4 are connected to the respective input terminals of the current detection unit 5. The voltage detection unit 3 detects the on-voltage Vds_on of FET1, and the current detection unit 5 detects the drain current Id of FET1. These on-voltage Vds_on and drain current Id are input to the Ron estimation unit 6.

[0018] Figure 2 shows a specific configuration example of the voltage detection unit 3. The input terminals INP and INM of the differential amplifier 11 are connected to the drain and source of the FET 1 via diodes 12P and 12M, respectively. In addition, current sources 13P and 13M are connected between the power supply VCC and the input terminals INP and INM, respectively. This prevents high voltages from being applied to the input terminals INP and INM, while allowing the on-voltage Vds_on to be detected by the differential amplifier 11, as shown in Figure 3.

[0019] The Ron estimation unit 6, which is the on-resistance calculation unit, estimates the on-resistance Ron of FET1 from the input on-voltage Vds_on and drain current Id, and outputs it to the temperature estimation unit 7. The temperature estimation unit 7 estimates the junction temperature Tj of FET1 based on the estimated on-resistance Ron and the Ron-Tj-Vth_shift data stored in the storage unit 8, which is a non-volatile memory. The storage unit 8 stores Ron-Tj-Vth_shift data that has been acquired in advance as follows.

[0020] Substituting equations (2) and (3) into equation (1) yields equation (4).

[0021]

number

[0022] A=Lch / (Wch×Cox), B=Ld / (q×Nd×Ad), C = Rsub + Rpackage, and these coefficients A to C do not depend on the junction temperature Tj.

[0023] The on-resistance Ron' when the threshold voltage Vth changes is given by equation (4). Equation (5) is obtained by considering the fluctuation amount Vth_shift.

[0024]

number

[0025] As shown in equation (5), the on-resistance Ron' when a certain gate drive voltage Vgs is applied when a certain fluctuation Vth_shift occurs is equal to the on-resistance Ron' when a gate drive voltage Vgs is applied minus a certain fluctuation Vth_shift when the actual fluctuation Vth_shift = 0V.

[0026] Here, two voltages, for example 20V and 18V, are selected as reference voltages for the gate drive voltage. The step size of the shift voltage, Vth_shift, is set to 0.1V. The gate drive voltage Vgs of FET1 is then varied within a range of ±1V from the reference voltage, and the junction temperature Tj of FET1 is varied in 20°C increments between 0°C and 200°C, for example, to measure the on-resistance Ron of FET1 for each measurement parameter. The measurement results of the on-resistance Ron for each measurement parameter are stored in the storage unit 8 as Ron-Tj-Vth_shift data. The stored data shows the dependence of the on-resistance Ron on the junction temperature Tj for Vth_shift = 1V to -1V when a gate drive voltage of 20V and 18V is applied. The above constitutes the junction temperature estimation circuit 9.

[0027] Figures 6 and 7 correspond to gate drive voltages Vgs = 20V and 18V, respectively. Figures 11 and 12 are tables showing the 3D data map of the Ron-Tj-Vth_shift data, with Figures 11 and 12 representing the individual data values.

[0028] Next, the operation of this embodiment will be explained. As shown in Figure 4, when power is supplied to the system and a command to start detecting the junction temperature Tj is input to the temperature estimation unit 7 (S1; YES), the Tj, Vth_shift detection process shown in Figure 5 is executed (S2). When a command to end the detection of the junction temperature Tj is input (S3; YES), the process is terminated.

[0029] As shown in Figure 5, the gate drive unit 2 sets the gate drive voltage Vgs = 20V according to the PWM signal (S11). The voltage detection unit 3 and current detection unit 4 detect the on-voltage Vds_on and drain current Id, respectively, while the FET1 is on (S12). The Ron estimation unit 6 calculates the on-resistance Ron of the FET1 by dividing the input on-voltage Vds_on by the drain current Id (S13).

[0030] Next, from the Ron-Tj-Vth_shift data obtained from the memory unit 8 when Vgs=20V, the Tj-Vth_shift data corresponding to the on-resistance Ron calculated in step S13 is extracted (S14). Then, the gate drive voltage Vgs is set to 18V (S15), and the same processing as in steps S12 to S14 is performed on that gate drive voltage Vgs (S16 to S18). Figures 8 and 9 show the processing image when the on-resistance Ron = 9.86mΩ when Vgs=20V is applied and the on-resistance Ron = 10.47mΩ when Vgs=18V is applied, and Figures 13 and 14 show the data extracted in steps S14 and S18.

[0031] Then, from the data extracted in steps S14 and S18, two values ​​that bring the junction temperatures Tj of both components closest are selected and statistically processed (S19). "Statistical processing" refers to, for example, the average value of both components, or, if three or more reference values ​​for the gate drive voltage Vgs are set, the median or mode of the three or more values ​​may also be used. Here, the average value is used. In Figure 15, the data from Figures 13 and 14 are arranged vertically, and the matching values ​​are selected by setting Tj = 112°C when Vth_shift = -0.5V, which minimizes the difference in junction temperatures Tj. Figure 10 shows the corresponding processing image.

[0032] As another example, Figure 16 shows the case where the gate drive voltage Vgs reference is set to five different values, and data for 12V, 14V, and 16V are added. In this case, the case where the difference between the maximum and minimum junction temperature Tj is smallest is still Vth_shift=-0.5V, but the values ​​are different: Tj=114℃ for Vgs=16V and Tj=116℃ for Vgs=12V. Average value: 113.2℃ Median: 112℃ Mode: 112℃ This is the result. While the computational load is lighter when using the median or mode, it is preferable to select the mean: 113.2°C as the optimal value.

[0033] In step S19, the shift voltage Vth_shift is also obtained by statistically processing the two closest values, but this is not used in this embodiment. The shift voltage Vth_shift is used in the second embodiment.

[0034] Furthermore, Figures 17 and 18 show the on-resistance Ron for each gate drive voltage Vgs, in 10°C increments within the junction temperature range Tj = -50°C to 200°C, when five different reference gate drive voltage Vgs are set as shown in Figure 16. For example, if the rated temperature is 0°C to 150°C, it is desirable to select a voltage higher than 16V as the reference gate drive voltage Vgs, where the temperature characteristic of the on-resistance Ron shows a positive value within this temperature range. The same applies to the rated current range. This allows the number of reference gate drive voltages Vgs to be limited to those with on-resistance Ron values ​​that are more approximate, thereby reducing the capacity of the memory unit 8.

[0035] As described above, according to this embodiment, in the temperature estimation circuit 9, the voltage detection unit 3 detects the terminal voltage Vds_on applied between the drain and source during the period when the FET1 is ON, and the current detection unit 4 detects the drain current Id flowing through the FET1 at the same timing as the voltage detection unit 3 detects the voltage. The storage unit 8 stores data that has been acquired in advance, showing the relationship between the terminal voltage Vds_on, current Id, junction temperature Tj of the FET1, and the amount of fluctuation Vth_shift of the threshold voltage Vth of the FET1 for multiple gate drive voltages.

[0036] The temperature estimation unit 7 estimates the junction temperature Tj, which is dependent on the fluctuation amount Vth_shift corresponding to each gate drive voltage and stored in the memory unit 8, based on the terminal voltage Vds_on and drain current Id detected when the gate drive unit 2 drives the gate of FET1 with multiple gate drive voltages. The optimal value obtained by performing statistical processing on each junction temperature Tj estimated for each gate drive voltage Vgs is then set as the final estimated junction temperature Tj. This allows for highly accurate estimation of the junction temperature Tj even if the threshold voltage Vth fluctuates while FET1 is in use.

[0037] Furthermore, the Ron estimation unit 6 calculates the on-resistance Ron of FET1 according to the terminal voltage Vds_on and the drain current Id. The data stored in the memory unit 8 is the characteristics of the on-resistance Ron, junction temperature Tj, and fluctuation amount Vth_shift according to multiple gate drive voltages, and the temperature estimation unit 7 estimates the junction temperature Tj using the on-resistance Ron calculated by the Ron estimation unit 6 and the data stored in the memory unit 8. This reduces the number of parameters in the data to be stored in the memory unit 8 by one.

[0038] Furthermore, the on-resistance Ron data stored in the memory unit 8 is set to data obtained when the FET1 is operated by adding or subtracting a value including the fluctuation amount Vth_shift from each of the multiple reference gate drive voltages Vgs to each junction temperature Tj. This allows the junction temperature Tj to be estimated with high accuracy based on data previously obtained for the FET1 in a state without characteristic degradation before being used in the market. In addition, since the multiple gate drive voltages are determined within a range where the temperature dependence of on-resistance Ron is always positive within the rated temperature and rated current of the FET1, the number of reference gate drive voltages Vgs can be limited to those that more closely approximate the value of on-resistance Ron, thereby reducing the capacity of the memory unit 8.

[0039] (Second Embodiment) In the following description, parts identical to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted, while the differences are described. As shown in Figure 19, the junction temperature estimation circuit 21 of the second embodiment includes a temperature estimation unit 22 and a storage unit 23, which replace the temperature estimation unit 7 and the storage unit 8.

[0040] Next, the operation of the second embodiment will be described. As shown in Figure 20, when steps S1 and S2 are executed, the temperature estimation unit 22 stores the shift voltage Vth_shift data obtained in step S2 in the storage unit 23 (S21). In addition, Ron-Tj data corresponding to the shift voltage Vth_shift stored in step S21 is created from the Ron-Tj-Vth_shift data at Vgs=20V obtained from the storage unit 23, and this is also stored in the storage unit 23 (S22). Then, after performing the Tj detection process (S23), the process moves to step S3.

[0041] In the Tj detection process shown in Figure 21, the same process as in steps S11 to S13 is performed (S31 to S33), and the junction temperature Tj is calculated from the Ron-Tj data stored in step S22 and the on-resistance Ron obtained in step S33 (S34).

[0042] As described above, according to the second embodiment, the temperature estimation unit 22 stores the estimated fluctuation amount Vth_shift and junction temperature Tj in the storage unit 23 at a predetermined estimation timing, and drives the gate drive unit 2 with a constant voltage until the fluctuation amount Vth_shift and junction temperature Tj estimated at the next estimation timing are stored in the storage unit 8. Then, data for the on-resistance Ron and junction temperature Tj corresponding to the fluctuation amount Vth_shift for a constant voltage are read from the storage unit 8, and the junction temperature Tj is estimated from the read data. This makes it possible to estimate the junction temperature Tj without increasing the losses generated in the FET1.

[0043] (Other embodiments) The configuration of the voltage detection unit is not limited to that shown in Figure 2. This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and concept of this disclosure. [Explanation of Symbols]

[0044] In the diagram, 1 is a SiC MOSFET, 2 is a gate drive unit, 3 is a voltage detection unit, 4 is a current detection unit, 6 is a Ron estimation unit, 7 is a temperature estimation unit, 8 is a memory unit, and 9 is a junction temperature estimation circuit.

Claims

1. A gate drive unit (2) that can change the voltage driving the gate of the power transistor (1), A voltage detection unit (3) detects the terminal voltage applied between the conductive terminals during the period when the power transistor is turned on, At the same time that the voltage detection unit detects the voltage, a current detection unit (4) detects the current flowing through the power transistor, A storage unit (8, 23) stores data that has been acquired in advance, showing the relationship between the terminal voltage, current, junction temperature of the power transistor, and the amount of fluctuation of the threshold voltage of the power transistor for multiple gate drive voltages, The system includes a temperature estimation unit (7, 22) that estimates the junction temperature using the terminal voltage detected by the voltage detection unit, the current detected by the current detection unit, and the data stored in the storage unit. The temperature estimation unit estimates the junction temperature, which depends on the amount of fluctuation corresponding to each gate drive voltage, in accordance with the terminal voltage detected by the voltage detection unit and the current detected by the current detection unit when the gate drive unit drives the gate with the plurality of gate drive voltages. A power transistor junction temperature estimation circuit that uses the optimal value obtained by performing statistical processing on each junction temperature estimated for multiple gate drive voltages as the final estimated junction temperature.

2. The system includes an on-resistance calculation unit (6) that calculates the on-resistance of the power transistor according to the terminal voltage detected by the voltage detection unit and the current detected by the current detection unit, The data stored in the memory unit is a characteristic of the on-resistance, junction temperature, and the amount of variation corresponding to the multiple gate drive voltages. The power transistor junction temperature estimation circuit according to claim 1, wherein the temperature estimation unit estimates the junction temperature using the on-resistance calculated by the on-resistance calculation unit and the data stored in the storage unit.

3. The power transistor junction temperature estimation circuit according to claim 2, wherein the on-resistance data stored in the memory unit is data obtained when the power transistor is operated by a gate drive voltage obtained by adding or subtracting a value including the fluctuation amount from each of a plurality of reference gate drive voltages for each junction temperature.

4. The temperature estimation unit (22) stores the amount of fluctuation estimated at a predetermined estimation timing in the storage unit (23). Until the amount of variation estimated at the next estimation timing is stored in the memory unit, the gate drive unit drives the gate with a constant voltage. A power transistor junction temperature estimation circuit according to claim 2, wherein on-resistance and junction temperature data corresponding to the amount of fluctuation for the constant voltage are read from the storage unit, and the junction temperature is estimated from the read data.

5. The junction temperature estimation circuit for a power transistor according to any one of claims 1 to 4, wherein the plurality of gate drive voltages are determined within a range in which the temperature dependence of the on-resistance is always positive within the rated temperature and rated current of the power transistor.

6. Data showing the relationship between the terminal voltage of a power transistor, the current flowing through the power transistor, the junction temperature of the power transistor, and the amount of variation of the threshold voltage of the power transistor for multiple gate drive voltages is acquired and stored in advance. When the power transistor is driven by the aforementioned multiple gate drive voltages, the terminal voltage applied between the conductive terminals and the current flowing through the power transistor are detected. A method for estimating the junction temperature of a power transistor, in which the junction temperature is estimated using the detected terminal voltage, the detected current, and pre-stored data, and the optimal value obtained by performing statistical processing on each junction temperature estimated for each of the multiple gate drive voltages is used as the final estimated junction temperature.

7. The on-resistance of the power transistor is calculated based on the detected terminal voltage and the detected current. The data to be stored in advance are the characteristics of the on-resistance, junction temperature, and the amount of variation corresponding to the multiple gate drive voltages. A method for estimating the junction temperature of a power transistor according to claim 6, wherein the junction temperature is estimated using the calculated on-resistance and pre-stored data.

8. The method for estimating the junction temperature of a power transistor according to claim 7, wherein the stored on-resistance data is data obtained when the power transistor is operated by a gate drive voltage obtained by adding or subtracting a value including the fluctuation amount from each of a plurality of reference gate drive voltages for each junction temperature.

9. The estimated amount of change at a predetermined estimated timing is stored, The power transistor is driven at a constant voltage until the amount of fluctuation estimated at the next estimation timing is newly stored. A method for estimating the junction temperature of a power transistor according to claim 7, comprising reading out on-resistance and junction temperature data corresponding to the amount of fluctuation stored for the constant voltage, and estimating the junction temperature from the read-out data.

10. The method for estimating the junction temperature of a power transistor according to any one of claims 6 to 9, wherein the plurality of gate drive voltages are determined within a range in which the temperature dependence of the on-resistance is always positive within the rated temperature and rated current of the power transistor.

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