Semiconductor device and method for manufacturing the same

Abstract

The present disclosure aims to provide a semiconductor device and a method for manufacturing the semiconductor device that can achieve both electric field relaxation by the SFP and reduction of Cds. The semiconductor device of the present disclosure includes a semiconductor substrate, a first semiconductor layer stacked on the upper surface of the semiconductor substrate, a second semiconductor layer stacked on the upper surface of the first semiconductor layer and having a band gap larger than that of the first semiconductor layer, a source electrode, a drain electrode, and a gate electrode formed on the upper surface of the second semiconductor layer, an insulating film covering the upper surface of the second semiconductor layer and the side and upper surfaces of the gate electrode, and a conductive SFP that is electrically connected to the source electrode and extends from the gate electrode to the drain electrode on the insulating film. The insulating film below the end of the SFP that extends toward the drain electrode is thinner than the insulating film below the portion of the SFP that is not the end.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] There is known a semiconductor device in which a source field plate (hereinafter referred to as SFP) having the same potential as the source electrode is provided between the gate electrode and the drain electrode. By providing the SFP, the electric field concentrated at the end of the gate electrode on the drain electrode side can be concentrated at the end of the SFP on the drain electrode side as well. This makes it possible to reduce the electric field between the gate and drain electrodes.

[0003] On the other hand, providing an SFP poses the problem of parasitic capacitance occurring between the two-dimensional electron gas (hereinafter referred to as 2DEG) surface of the semiconductor layer and the bottom surface of the SFP. Since one end of the 2DEG surface is connected to the drain electrode, the parasitic capacitance occurring between the 2DEG surface and the SFP is the parasitic capacitance between the drain and source electrodes (hereinafter referred to as Cds). Since Cds affects the power consumption and frequency characteristics of the semiconductor device, it is preferable that it is small. Cds is proportional to the area of ​​the bottom surface of the SFP and inversely proportional to the distance between the 2DEG surface and the bottom surface of the SFP.

[0004] From the viewpoint of electric field relaxation, it is advantageous to extend the SFP from the gate electrode side to the drain electrode side and concentrate the electric field on the drain electrode side of the SFP.

[0005] However, when the area of ​​the bottom surface of the SFP increases by extending the SFP, Cds increases. In other words, it is known that there is a trade-off between the electric field relaxation using the SFP and the reduction of the parasitic capacitance Cds.

[0006] From the viewpoint of overcoming the trade-off, Patent Document 1 discloses an SFP with a stepped bottom surface. In this case, the bottom surface of the SFP on the drain electrode side is made higher than the bottom surface on the gate electrode side. This allows the distance between the bottom surface on the drain electrode side and the 2DEG surface to be increased, so that the parasitic capacitance Cds can be reduced compared to a configuration with a flat bottom surface. Therefore, even if the SFP is extended to alleviate the electric field, the increase in Cds can be suppressed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2021 / 230283 Summary of the Invention [Problem to be solved by the invention]

[0008] In the SFP of Patent Document 1, the bottom surface on the drain electrode side is higher than the bottom surface on the gate electrode side, so that Cds is lower at the end of the SFP on the drain electrode side than at the end of the SFP on the gate electrode side. This means that the effect of concentrating the electric field at the end of the SFP on the drain electrode side is weakened. In other words, the method of Patent Document 1 sacrifices the effect of alleviating the electric field by the SFP in exchange for reducing the parasitic capacitance Cds.

[0009] In order to solve the above-mentioned problems, a first object of the present disclosure is to provide a semiconductor device capable of achieving both electric field relaxation by SFP and reduction in Cds.

[0010] In order to solve the above-mentioned problems, a second object of the present disclosure is to provide a manufacturing method for a semiconductor device that can achieve both electric field relaxation by SFP and reduction in Cds. [Means for solving the problem]

[0011] A first aspect of the present disclosure is a method for manufacturing a semiconductor device comprising: A semiconductor substrate; a first semiconductor layer laminated on an upper surface of the semiconductor substrate; a second semiconductor layer laminated on an upper surface of the first semiconductor layer and having a band gap larger than that of the first semiconductor layer; a source electrode and a drain electrode formed on an upper surface of the second semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; an insulating film covering an upper surface of the second semiconductor layer and a side surface and an upper surface of the gate electrode; a conductive source field plate electrically connected to the source electrode and extending from the gate electrode toward the drain electrode on the insulating film; having The insulating film under the end of the source field plate extending toward the drain electrode is thinner than the insulating film under the other portion of the source field plate. Ku, The insulating film is a first insulating film formed on an upper surface of the second semiconductor layer; a second insulating film covering an upper surface of the second semiconductor layer exposed from an opening formed in the first insulating film between the gate electrode and the drain electrode, an upper surface of the first insulating film, and side and upper surfaces of the gate electrode; having the edge of the source field plate overlies the opening. It is preferably a semiconductor device. The second aspect is A semiconductor substrate; a first semiconductor layer laminated on an upper surface of the semiconductor substrate; a second semiconductor layer laminated on an upper surface of the first semiconductor layer and having a band gap larger than that of the first semiconductor layer; a source electrode and a drain electrode formed on an upper surface of the second semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; an insulating film covering an upper surface of the second semiconductor layer and a side surface and an upper surface of the gate electrode; a conductive source field plate electrically connected to the source electrode and extending from the gate electrode toward the drain electrode on the insulating film; having the insulating film under an end of the source field plate extending toward the drain electrode is thinner than the insulating film under a portion other than the end of the source field plate; The second semiconductor layer underlying the end of the source field plate is preferably a semiconductor device that includes fluorine to reduce two-dimensional electron gas concentration. The third aspect is A semiconductor substrate; a first semiconductor layer laminated on an upper surface of the semiconductor substrate; a second semiconductor layer laminated on an upper surface of the first semiconductor layer and having a band gap larger than that of the first semiconductor layer; a source electrode and a drain electrode formed on an upper surface of the second semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; an insulating film covering an upper surface of the second semiconductor layer and a side surface and an upper surface of the gate electrode; a conductive source field plate electrically connected to the source electrode and extending from the gate electrode toward the drain electrode on the insulating film; having the insulating film under an end of the source field plate extending toward the drain electrode is thinner than the insulating film under a portion other than the end of the source field plate; a non-conductive block embedded between the insulating film and the source field plate; It is preferable that the block is in contact with the insulating film covering the side surface of the gate electrode on the drain electrode side, and is not in contact with the end portion of the source field plate.

[0012] Also, 4 The embodiment of the present invention is as follows: depositing a first semiconductor layer on an upper surface of a semiconductor substrate; laminating a second semiconductor layer having a larger band gap than the first semiconductor layer on an upper surface of the first semiconductor layer; forming a source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode on an upper surface of the second semiconductor layer; forming a first insulating film on an upper surface of the second semiconductor layer; forming an opening in the first insulating film between the gate electrode and the drain electrode to expose the second semiconductor layer; forming a second insulating film covering an upper surface of the second semiconductor layer exposed by the opening, an upper surface of the first insulating film, and a side surface and an upper surface of the gate electrode; forming a conductive source field plate connected to the source electrode, covering the side and upper surface of the gate electrode via the second insulating film, and extending from the gate electrode toward the drain electrode on the second insulating film; Including, In the method for manufacturing a semiconductor device, it is preferable that an end of the source field plate extending toward the drain electrode is located above the opening. Effect of the Invention

[0013] In the present disclosure, the insulating film under the end of the SFP on the drain electrode side is thinner than the insulating film under the other part of the SFP. This enhances the effect of concentrating the electric field at the end. Furthermore, in the other part of the SFP on the drain electrode side, the thickness of the insulating film is increased to reduce the parasitic capacitance Cds of the SFP as a whole. Therefore, it is possible to achieve both electric field relaxation by the SFP5 and reduction in Cds. [Brief description of the drawings]

[0014] [Figure 1] 11A and 11B are diagrams illustrating the relationship between a cross section of a semiconductor device according to a comparative example of the present disclosure and the electric field distribution. [Diagram 2] 11A and 11B are diagrams illustrating the relationship between a cross section of a semiconductor device according to a comparative example of the present disclosure and the electric field distribution. [Diagram 3] 1 is a model for simulating the maximum electric field strength in a semiconductor device according to a comparative example of the present disclosure. [Figure 4] 13 is a result of simulating the maximum electric field strength in a semiconductor device according to a comparative example of the present disclosure. [Diagram 5] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 6] FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 7] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 8] 11A to 11C are cross-sectional views illustrating a method for forming a second insulating film according to a third embodiment of the present disclosure. [Figure 9] FIG. 11 is a cross-sectional view showing a modified example of the semiconductor device according to the third embodiment of the present disclosure. [Figure 10] FIG. 11 is a cross-sectional view showing a modified example of the semiconductor device according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Before describing the present disclosure, a comparative example will be described. The same reference numerals are used for components common to or corresponding to the present disclosure. Here, differences from the present disclosure will be mainly described, and components common to or corresponding to the present disclosure will be described in the description of the present disclosure.

[0016] Comparative Example 1 is a diagram showing the relationship between the cross section of a semiconductor device 200 according to a comparative example of the present disclosure and the electric field distribution. The semiconductor device 200 differs from the present disclosure in that it does not have an SFP5. In the graph showing the electric field distribution, the vertical axis represents the electric field strength, and the horizontal axis corresponds to the position on the first insulating film 2 in the cross-sectional view. As described in the background art, in the absence of an SFP5, the electric field between the gate and drain electrodes is concentrated at the end of the gate electrode 4 on the drain electrode side.

[0017] FIG. 2 is a diagram showing the relationship between the cross section of a semiconductor device 300 according to a comparative example of the present disclosure and the electric field distribution. The semiconductor device 300 has a structure in which an SFP5 is added to the semiconductor device 200 of FIG. 1. However, the SFP5 of the semiconductor device 300 differs from the present disclosure in that the lower surface is flat. In the structure of FIG. 1 without the SFP5, the electric field is concentrated only at the end of the gate electrode 4 on the drain electrode side, but in this figure, it is also concentrated at the end of the SFP5 on the drain electrode side. In other words, the electric field between the gate electrode and the drain electrode is relaxed by providing the SFP5. In addition, by providing the SFP5, a part of the electric field lines (not shown) from the gate electrode 4 toward the 2DEG surface 12 can be directed toward the SFP5 side. Therefore, the effect of reducing the gate-drain electrode capacitance Cgd is also obtained.

[0018] 3 shows a model 400 for simulating the maximum electric field strength in a semiconductor device 300 according to a comparative example of the present disclosure. In the simulation, a model 400 was used that includes a semiconductor substrate 1, a gate electrode 4 formed on the semiconductor substrate 1, a second insulating film 3 covering the gate electrode 4 and the semiconductor substrate 1, and an SFP5 covering the gate electrode 4 via the second insulating film 3. It was also assumed that a source electrode (not shown) exists on the left side of the paper on the semiconductor substrate 1, and a drain electrode (not shown) exists on the right side of the paper. In the simulation, the relationship between the extension distance D when the SFP5 is extended from the end of the gate electrode 4 on the drain electrode side toward the drain electrode side and the maximum electric field strength in the semiconductor device 300 was calculated.

[0019] 4 shows the results of simulating the maximum electric field strength in the semiconductor device 300 according to the comparative example of the present disclosure. The horizontal axis is the extension distance D of the SFP5, and the vertical axis is the maximum electric field strength in the first semiconductor layer 6 when the semiconductor device 300 is operated as a transistor. The shorter the extension distance D, the higher the maximum electric field strength. This is because the electric fields concentrated at the end of the gate electrode 4 on the drain electrode side and the end of the SFP5 on the drain electrode side interfere with each other and strengthen each other. The longer the extension distance D, the weaker the interference and the lower the maximum electric field strength. In other words, from the viewpoint of electric field relaxation, it is advantageous to extend the SFP5 from the gate electrode 4 side to the drain electrode side as much as possible and concentrate the electric field at the end of the SFP5 on the drain electrode side.

[0020] The present disclosure Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0021] First embodiment 5 is a cross-sectional view showing a semiconductor device 100 according to the first embodiment of the present disclosure. A first semiconductor layer 6 and a second semiconductor layer 7 are laminated in this order on the upper surface of a semiconductor substrate 1.

[0022] The first semiconductor layer 6 is a GaN channel layer. The first semiconductor layer 6 is not limited to GaN, and may be made of a Group III nitride semiconductor such as InGaN, AlGaN, or AlInGaN.

[0023] The second semiconductor layer 7 is an AlGaN layer. The second semiconductor layer 7 is not limited to AlGaN, and may be composed of a group III nitride semiconductor such as GaN, InGaN, AlGaN, AlN, or AlInGaN. A heterobarrier is formed at the interface between the second semiconductor layer 7 and the first semiconductor layer 6. The second semiconductor layer 7 has a larger band gap than the first semiconductor layer 6, and a 2DEG surface 12 is formed on the first semiconductor layer 6 side near the interface.

[0024] A first insulating film 2 is formed on the upper surface of the second semiconductor layer 7. The first insulating film 2 is formed to suppress current collapse caused by the surface of the second semiconductor layer 7. The first insulating film 2 is, for example, SiO2 or SiN.

[0025] A buffer layer (for example, a single layer or multiple layers of a group III nitride semiconductor such as GaN, AlGaN, AlN, InGaN, or AlInGaN) may be laminated between the semiconductor substrate 1 and the first semiconductor layer 6.

[0026] A gate electrode 4 is formed on the upper surface of the second semiconductor layer 7, penetrating the first insulating film 2. The gate electrode 4 is formed between a source electrode and a drain electrode (both not shown) that are formed spaced apart from each other on the upper surface of the second semiconductor layer 7. Here, it is assumed that the source electrode is located on the left side of the paper, and the drain electrode is located on the right side of the paper. The first semiconductor layer 6 and the second semiconductor layer 7 extend in a range that includes the areas directly below the source electrode and the areas directly below the drain electrode. The 2DEG surface 12 is electrically connected to the source electrode and the drain electrode.

[0027] The material of the gate electrode 4 is, for example, Ni, TiN, Pt, Pd, Cu, Ta, TaN, W, WSi, Al, Au, Ti, etc. The gate electrode 4 does not necessarily have to penetrate the first insulating film 2. In other words, the gate electrode 4 may have a MIS (Metal-Insulator-Semiconductor) structure.

[0028] Between the gate electrode 4 and the drain electrode, an opening 8 is formed in the first insulating film 2 to expose the second semiconductor layer 7. The opening 8 is formed at a position separated from the gate electrode 4.

[0029] A second insulating film 3 is formed to cover the upper surface of the second semiconductor layer 7 exposed by the opening 8, the upper surface of the first insulating film 2, and the side and upper surfaces of the gate electrode 4. The second insulating film 3 is formed to insulate the gate electrode 4 from the SFP 5. The second insulating film 3 is recessed along the opening 8.

[0030] An SFP5 is formed covering the side and top surfaces of the gate electrode 4 via the second insulating film 3. The SFP5 extends from the gate electrode 4 side to the drain electrode side, and the end of the SFP5 extending to the drain electrode side is above the opening 8. Since the second insulating film 3 is recessed along the opening 8, the bottom surface of the SFP5 at the end on the drain electrode side is lower than the bottom surface at other positions. The SFP5 is made of a conductive material such as Ti or Al.

[0031] In this disclosure, the surface of the SFP 5 on the semiconductor substrate 1 side is referred to as the bottom surface of the SFP 5.

[0032] Here, the first insulating film 2 and the second insulating film 3 are regarded as an integral part, and are referred to as an insulating film 10. Since the first insulating film 2 is not present, the insulating film 10 under the end of the SFP5 on the drain electrode side is thinner than the insulating film 10 under the portion of the SFP5 other than the end. Therefore, the distance between the bottom surface of the SFP5 and the 2DEG surface 12 is shortest at the end on the drain electrode side. In other words, in the present disclosure, the parasitic capacitance Cds at the end on the drain electrode side of the SFP5 is locally increased, thereby enhancing the effect of concentrating the electric field at the end.

[0033] Furthermore, in the portion of the SFP5 that is not the end portion on the drain electrode side, the thickness of the lower second insulating film 3 is increased, thereby increasing the distance between the bottom surface of the SFP5 and the 2DEG surface 12. In this manner, in the present disclosure, the parasitic capacitance Cds is increased in the end portion on the drain electrode side of the SFP5, but by reducing the parasitic capacitance Cds in the portion that is not the end portion, the parasitic capacitance Cds of the SFP5 as a whole can be sufficiently reduced. Therefore, it is possible to achieve both electric field relaxation by the SFP5 and reduction in Cds.

[0034] The manufacturing method of the semiconductor device 100 of the present disclosure will be described below. First, a first semiconductor layer 6 is laminated on the upper surface of a semiconductor substrate 1. Further, a second semiconductor layer 7 having a larger band gap than the first semiconductor layer 6 is laminated on the upper surface of the first semiconductor layer 6. Further, a first insulating film 2 is formed on the upper surface of the second semiconductor layer 7 by a sputtering method or the like.

[0035] The first insulating film 2 is further processed to form an opening for the gate electrode 4 and expose the second semiconductor layer 7. An opening 8 is further formed in the first insulating film 2 between the position where the gate electrode 4 is to be formed and the position where the drain electrode is to be formed, exposing the second semiconductor layer 7. The gate electrode 4 is further formed on the upper surface of the second semiconductor layer 7 in the opening for the gate electrode. A source electrode and a drain electrode are further formed on the upper surface of the second semiconductor layer 7.

[0036] Furthermore, a second insulating film 3 is formed by a sputtering method or the like to cover the upper surface of the second semiconductor layer 7 exposed by the opening 8, the upper surface of the first insulating film 2, and the side and upper surfaces of the gate electrode 4. Furthermore, an SFP5 is formed that is connected to the source electrode, covers the side and upper surfaces of the gate electrode 4 via the second insulating film 3, and extends from the gate electrode 4 toward the drain electrode on the second insulating film 3. The SFP5 is formed so that the end of the SFP5 extending toward the drain electrode is above the opening 8.

[0037] The semiconductor device 100 of the present disclosure is advantageous in that it can be manufactured with almost no change to the manufacturing process of the semiconductor device 300 of the comparative example. Specifically, in the manufacture of the semiconductor device 300, the opening 8 is additionally formed when processing the first insulating film 2 to form an opening for the gate electrode 4, thereby obtaining the semiconductor device 100 of the present disclosure. As described above, the semiconductor device 100 of the present disclosure exhibits superior effects to the semiconductor device 300 of the comparative example in terms of electric field relaxation and Cds reduction.

[0038] Embodiment 2 Here, changes from the first embodiment will be described. Fig. 6 is a cross-sectional view showing a semiconductor device 100 according to a second embodiment of the present disclosure. In this embodiment, the second semiconductor layer 7 below the end portion on the drain electrode side of the SFP5 contains fluorine 11 for reducing the 2DEG concentration. This makes it possible to adjust the Cds at the end portion of the SFP5 so as to weaken it according to the characteristics of electric field relaxation and parasitic capacitance Cds required for the semiconductor device 100.

[0039] Fluorine 11 can be introduced into the second semiconductor layer 7 through the opening 8 by including it in an etching gas for forming the opening 8 in the first insulating film 2. From the viewpoint of minimizing the influence on the electrical characteristics of the semiconductor device 100, it is desirable to introduce fluorine 11 only into the second semiconductor layer 7 around the opening 8. However, when the opening 8 and the opening for the gate electrode 4 are simultaneously formed in the first insulating film 2 by a single etching, fluorine will also be introduced from the opening for the gate electrode 4. In that case, the fluorine introduced into the second semiconductor layer 7 through the opening for the gate electrode 4 may be removed by heat treatment.

[0040] Third embodiment Here, the changes from the first embodiment will be described. Fig. 7 is a cross-sectional view showing a semiconductor device 100 according to a third embodiment of the present disclosure. In the semiconductor device 100, the second insulating film 3 covering the side surface of the gate electrode 4 is extended toward the drain electrode side. The lower surface of the SFP5 can be made higher by the amount of extension, and the parasitic capacitance Cds can be reduced compared to the first embodiment.

[0041] FIG. 8 is a cross-sectional view showing a method for forming the second insulating film 3 according to the third embodiment of the present disclosure. The second insulating film 3 is isotropically grown on the upper surface of the second semiconductor layer 7 exposed by the opening 8, the upper surface of the first insulating film 2, and the side and upper surfaces of the gate electrode 4. As a result, the second insulating film 3 covering the gate electrode 4 is extended toward the drain electrode side. Furthermore, the second insulating film 3 is subjected to etching adjusted so that the etching rate in the depth direction is faster than the etching rate in the side direction. By such anisotropic etching, the second insulating film 3 can be processed to a desired thickness while leaving as much of the portion of the second insulating film 3 extended toward the drain electrode side as possible. The etching may be dry etching or wet etching.

[0042] It is not necessary to perform anisotropic etching on the second insulating film 3, and isotropic etching may be performed.

[0043] FIG. 9 is a cross-sectional view showing a modified example of the semiconductor device 100 according to the third embodiment of the present disclosure. A non-conductive block 9 is embedded between the second insulating film 3 and the SFP5. The block 9 contacts the second insulating film 3 covering the side surface of the gate electrode 4 on the drain electrode side, and extends from the gate electrode side to the drain electrode side. However, the block 9 does not contact the end of the SFP5 on the drain electrode side. This allows the lower surface of the SFP5 to be raised in the portion other than the end of the SFP5, and the same effect as in the third embodiment can be obtained. The thickness of the block 9 is not limited. The material of the block 9 is, for example, resin, but it may be non-conductive.

[0044] The present disclosure is not limited to the above-described embodiment, and various modifications can be made in the implementation stage without departing from the spirit of the present disclosure. Furthermore, the embodiments and modifications may be implemented in appropriate combination, and in that case, the combined effects can be obtained.

[0045] 10 is a cross-sectional view showing a modified example of the semiconductor device 100 of the present disclosure. The SFP5 does not necessarily need to cover the side and top surfaces of the gate electrode 4 via the second insulating film 3, and it is sufficient that the SFP5 extends from the end of the gate electrode 4 on the drain electrode side toward the drain electrode side. If the insulating film 10 under the end of the SFP5 extending toward the drain electrode is thinner than the insulating film 10 under the portion of the SFP5 other than the end, the effects described in the first to third embodiments can be obtained. [Explanation of symbols]

[0046] REFERENCE SIGNS LIST 1 semiconductor substrate, 2 first insulating film, 3 second insulating film, 4 gate electrode, 5 SFP, 6 first semiconductor layer, 7 second semiconductor layer, 8 opening, 9 block, 10 insulating film, 11 fluorine, 12 2DEG surface, 100 semiconductor device, 200 semiconductor device, 300 semiconductor device, 400 model

Claims

1. Semiconductor substrate and A first semiconductor layer stacked on the upper surface of the semiconductor substrate, A second semiconductor layer is stacked on the upper surface of the first semiconductor layer and has a larger band gap than the first semiconductor layer, A source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode are formed on the upper surface of the second semiconductor layer. An insulating film covering the upper surface of the second semiconductor layer and the side and upper surface of the gate electrode, A conductive source field plate is electrically connected to the source electrode and extends on the insulating film in the direction from the gate electrode to the drain electrode, It has, The insulating film located below the end of the source field plate extending in the direction of the drain electrode is thinner than the insulating film located below the portion of the source field plate that is not at that end. The insulating film is The first insulating film formed on the upper surface of the second semiconductor layer, Between the gate electrode and the drain electrode, the upper surface of the second semiconductor layer exposed through an opening formed in the first insulating film, the upper surface of the first insulating film, and the side and upper surfaces of the gate electrode are covered by the second insulating film, It has, A semiconductor device wherein the end of the source field plate is located above the opening.

2. The semiconductor device according to claim 1, wherein the source field plate covers the side and top surfaces of the gate electrode via the insulating film.

3. A semiconductor substrate and A first semiconductor layer stacked on the upper surface of the semiconductor substrate, A second semiconductor layer is stacked on the upper surface of the first semiconductor layer and has a larger band gap than the first semiconductor layer, A source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode are formed on the upper surface of the second semiconductor layer. An insulating film covering the upper surface of the second semiconductor layer and the side and upper surface of the gate electrode, A conductive source field plate is electrically connected to the source electrode and extends on the insulating film in the direction from the gate electrode to the drain electrode, It has, The insulating film located below the end of the source field plate extending in the direction of the drain electrode is thinner than the insulating film located below the portion of the source field plate that is not at that end. The second semiconductor layer located below the end of the source field plate is a semiconductor device containing fluorine for reducing the two-dimensional electron gas concentration.

4. The semiconductor device according to any one of claims 1 to 3, wherein the insulating film covering the side surface of the gate electrode extends in the direction of the drain electrode.

5. A semiconductor substrate and A first semiconductor layer stacked on the upper surface of the semiconductor substrate, A second semiconductor layer is stacked on the upper surface of the first semiconductor layer and has a larger band gap than the first semiconductor layer, A source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode are formed on the upper surface of the second semiconductor layer. An insulating film covering the upper surface of the second semiconductor layer and the side and upper surface of the gate electrode, A conductive source field plate is electrically connected to the source electrode and extends on the insulating film in the direction from the gate electrode to the drain electrode, It has, The insulating film located below the end of the source field plate extending in the direction of the drain electrode is thinner than the insulating film located below the portion of the source field plate that is not at that end. The present invention further comprises an insulated block embedded between the insulating film and the source field plate, The block is in contact with the insulating film covering the drain electrode side of the gate electrode, but does not contact the end of the source field plate.

6. A process of stacking a first semiconductor layer on the upper surface of a semiconductor substrate, A step of stacking a second semiconductor layer having a larger band gap than the first semiconductor layer on the upper surface of the first semiconductor layer, A step of forming a source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode on the upper surface of the second semiconductor layer, A step of forming a first insulating film on the upper surface of the second semiconductor layer, A step of forming an opening in the first insulating film between the gate electrode and the drain electrode and exposing the second semiconductor layer, A step of forming a second insulating film that covers the upper surface of the second semiconductor layer exposed by the opening, the upper surface of the first insulating film, and the side and upper surfaces of the gate electrode, A step of forming a conductive source field plate connected to the source electrode, covering the side and top surfaces of the gate electrode via the second insulating film, and extending on the second insulating film from the gate electrode toward the drain electrode, Includes, The end of the source field plate extending in the direction of the drain electrode is located above the opening in the method for manufacturing a semiconductor device.

7. The step of forming the two insulating films described above is: A step of isotropically growing the second insulating film on the upper surface of the second semiconductor layer exposed by the opening, the upper surface of the first insulating film, and the side and upper surfaces of the gate electrode, A step of etching the grown second insulating film, A method for manufacturing a semiconductor device according to claim 6, including the method described in claim 6.

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