Memory device including ferroelectric tunnel field-effect transistor and method of operating thereof

Abstract

According to one embodiment of the present invention, a method of operation of a memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to a plurality of source lines comprises: a step of applying a first voltage to a selected word line connected to a selected memory cell among a plurality of word lines; a step of applying a second voltage to a selected bit line connected to a selected memory cell among a plurality of bit lines; and a step of applying a ground voltage to a plurality of source lines, non-selected word lines among a plurality of word lines, and non-selected bit lines among a plurality of bit lines, wherein the first voltage is greater than the ground voltage and the second voltage is less than the ground voltage, and each of the plurality of memory cells includes a ferroelectric tunnel field-effect transistor (FeTFET) element.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory, and more specifically, to a memory device including a ferroelectric tunnel field-effect transistor and a method of operating the same. Background Technology

[0002] Ferroelectric tunnel field-effect transistor (FeTFET) devices can operate at low voltages (e.g., less than 5V), have scalability to various thicknesses of ferroelectric thin films, and have high compatibility with CMOS processes.

[0003] FeTFET devices include a ferroelectric thin film, and program operations or erase operations can be performed depending on the polarization direction of the ferroelectric thin film. When a program operation or erase operation is performed on a memory cell array including FeTFET devices, voltage may be applied to non-selected cells that do not intend to perform the program operation or erase operation, and when voltage is applied to non-selected cells, there is a problem of leakage current occurring. The problem to be solved

[0004] The objective of the present invention is to provide a ferroelectric tunnel field-effect transistor to which a voltage is applied for reducing leakage current, a memory device including the same, and a method of operating the same. means of solving the problem

[0005] According to one embodiment of the present invention, a method of operating a memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to a plurality of source lines comprises: a step of applying a first voltage to a selected word line connected to a selected memory cell among the plurality of word lines; a step of applying a second voltage to a selected bit line connected to a selected memory cell among the plurality of bit lines; and a step of applying a ground voltage to the plurality of source lines, non-selected word lines among the plurality of word lines, and non-selected bit lines among the plurality of bit lines, wherein the first voltage is greater than the ground voltage and the second voltage is less than the ground voltage, and each of the plurality of memory cells includes a ferroelectric tunnel field-effect transistor (FeTFET) element. Effects of the invention

[0006] According to the present invention, when a memory device including a ferroelectric tunnel field-effect transistor performs a program operation or an erase operation, leakage current caused by a non-selected cell that does not intend to perform the program operation or erase operation can be reduced. Brief explanation of the drawing

[0007] FIG. 1 is a block diagram illustrating a memory device according to an embodiment of the present invention. Figure 2 is a diagram showing the memory cell array of Figure 1. Figure 3 is a diagram showing the first FeTFET device of Figure 2. Figures 4a and 4b are diagrams illustrating the programming operation of an FeTFET device. FIGS. 5A and FIGS. 5B are drawings for explaining the programming operation of an FeTFET device according to an embodiment of the present invention. Figures 6a and 6b are diagrams illustrating the erasure operation of a FeTFET device. FIGS. 7a and 7b are drawings for explaining the erasure operation of a FeTFET device according to an embodiment of the present invention. FIGS. 8a and FIGS. 8b are flowcharts showing a method of operation of a memory device according to an embodiment of the present invention. FIGS. 9a and 9b are graphs showing the voltage and current characteristics of a cell to which a voltage is applied for a program operation or an erase operation according to an embodiment of the present invention. FIG. 10 is a graph showing the reduced leakage current according to an embodiment of the present invention. Specific details for implementing the invention

[0008] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

[0009] FIG. 1 is a block diagram illustrating a memory device according to an embodiment of the present invention. Referring to FIG. 1, the memory device (100) may include a memory cell array (110), a row decoder block (120), a column decoder block (130), a command / address buffer block (140), an address decoder block (150), a command decoder block (160), and a data input / output block (170).

[0010] A memory cell array (110) may include a plurality of memory cells. The plurality of memory cells may each be connected to word lines and bit lines. In one embodiment, each of the plurality of memory cells may be a Ferroelectric Tunnel Field-Effect Transistor (FeTFET) device.

[0011] The memory cell array (110) can be connected to a row decoder block (120) through multiple word lines and to a column decoder block (130) through multiple bit lines.

[0012] The row decoder block (120) can control multiple word lines according to the control of the address decoder block (150). For example, the row decoder block (120) can select or determine selected word lines among multiple word lines according to the control of the address decoder block (150).

[0013] The column decoder block (130) can control multiple bit lines according to the control of the address decoder block (150). In one embodiment, the column decoder block (130) can transmit data read from the memory cell array (110) to the data input / output block (170) through multiple bit lines. In one embodiment, the column decoder block (130) can transmit data to be written to the memory cell array (110) from the data input / output block (170) to the memory cell array (110).

[0014] The command / address buffer block (140) may be configured to receive a command / address from an external device (e.g., a memory controller or a register clock driver (RCD)) through command / address lines (CA) and to temporarily store or buffer the received signals.

[0015] The address decoder block (150) may be configured to receive an address signal (ADDR) from the command / address buffer block (140) and to decode the received address signal (ADDR). The address decoder block (150) may be configured to control the column decoder block (120) and the row decoder block (130) based on the decoding result.

[0016] The command decoder block (160) receives a command signal (CMD) from the command / address buffer block (140) and can decode the received command signal (CMD). The command decoder block (160) can control the components of the memory device (100) based on the decoding result. For example, if the command signal (CMD) received from the command / address buffer block (140) is a program command, the command decoder block (160) can control the operation of the data input / output block (170) so that the received data is written to the memory cell array (110) through the data lines (DQ). Alternatively, if the command signal (CMD) received from the command / address buffer block (140) is a read command, the command decoder block (160) can control the operation of the data input / output block (170) so that data stored in the memory cell array (110) is read out.

[0017] The data input / output block (170) may be configured to receive data from an external device (e.g., a memory controller) or to transmit data to an external device through data lines (DQ). The data input / output block (170) may read data from the memory cell array (110) or write data to the memory cell array (110) under the control of the command decoder block (160).

[0018] The memory device (100) and the components of the memory device (100) described above may be nonvolatile memory devices including nonvolatile memory devices such as FeTFET devices. To facilitate the explanation of embodiments of the present invention, the memory device (100) is described as being a FeTFET device.

[0019] Figure 2 is a diagram showing the memory cell array of Figure 1.

[0020] Referring to FIGS. 1 and 2, a memory cell array (110) may include a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of source lines (SL). For example, each of the plurality of memory cells may include a FeTFET device.

[0021] In one embodiment, the gate electrode of the first FeTFET device (FeTFET1) may be connected to the first word line (WL1), and a voltage may be applied to the gate electrode through the first word line (WL1). The source electrode of the first FeTFET device (FeTFET1) may be connected to the first source line (SL1), and a voltage may be applied to the source electrode through the first source line (SL1). The drain electrode of the first FeTFET device (FeTFET1) may be connected to the first bit line (BL1), and a voltage may be applied to the drain electrode through the first bit line (BL1). In the manner described above, other memory cells may also be connected to the word line, source line, and bit line, and a voltage may be applied to the memory cells.

[0022] Figure 3 is a diagram showing the first FeTFET device of Figure 2.

[0023] First, referring to FIGS. 1, 2, and 3, the structure of a first FeTFET device (FeTFET1) is illustrated. The first FeTFET device (FeTFET1) may include a semiconductor substrate (410), a source region (420), a source electrode (430), a drain region (440), a drain electrode (450), a channel region (460), a gate electrode (470), a ferroelectric layer (480), and a gate insulating layer (490).

[0024] The semiconductor substrate (410) may be a suitable semiconductor substrate, such as a semiconductor wafer, a silicon-on-insulator substrate, or a semiconductor layer formed on the semiconductor substrate. The semiconductor substrate (410) may be a silicon substrate, but the scope of the present disclosure is not limited thereto, and other semiconductor materials may be used for the semiconductor substrate (410).

[0025] In one embodiment, the semiconductor substrate (410) may include a source region (420), a drain region (440), and a channel region (460). The source region (420) and the drain region (440) may be formed apart by a certain distance, and the channel region (460) may be formed between the source region (420) and the drain region (440).

[0026] The source region (420) may have a first doping concentration. For example, the source region (420) may have a P+ type. The drain region (440) may have a second doping concentration. For example, the drain region (440) may have an N+ type.

[0027] In one embodiment, to improve the turn-on operation and bipolar (or ambipolar) phenomenon of the first FeTFET device (FeTFET1), the doping concentration of the source region (420) may be adjusted (or adjusted, changed) or the doping concentration of the drain region (440) may be adjusted.

[0028] In one embodiment, the source region (420) and the drain region (440) may be spaced apart along the first direction (D1). The source region (420) and the drain region (440) may extend along the opposite direction of the second direction (D2), which is perpendicular to the first direction (D1).

[0029] In one embodiment, the semiconductor substrate (410) may be formed as an intrinsic region that is undoped, or as a source region (420) with P-type impurities doped more weakly than the source region (420). Alternatively, the semiconductor substrate (410) may be formed as an intrinsic region that is undoped, or as a drain region (440) with N-type impurities doped more weakly than the drain region (N-region). That is, the semiconductor substrate (410) may be an intrinsic (i-type) silicon substrate.

[0030] The channel region (460) may be formed as an intrinsic region that is undoped, or as a P-type impurity less doped than the source region (420). Alternatively, the channel region (460) may be formed as an intrinsic region that is undoped, or as a drain region (440) that is undoped, or as a drain region.

[0031] In one embodiment, the source region (420), drain region (440), and channel region (460) may be formed using silicon (Si), as well as at least one of silicon-germanium (Si-Ge), germanium (Ge), carbon (C), indium phosphide (InP), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or a combination thereof.

[0032] The source electrode (430) may be placed on the upper surface of the source region (420). Voltage may be applied to the source electrode (430) by the source line (SL). The drain electrode (450) may be placed on the upper surface of the drain region (440). Voltage may be applied to the drain electrode (450) by the bit line (BL).

[0033] The gate electrode (470), the ferroelectric layer (480), and the gate insulating layer (490) may be disposed on the upper surface of the channel region (460). The gate insulating layer (490), the ferroelectric layer (480), and the gate electrode (470) may be formed by sequentially stacking on the upper surface of the channel region (460). The gate insulating layer (490) may cover a portion of the upper surface of the channel region (460). Voltage may be applied to the gate electrode (470) by a word line (WL).

[0034] In one embodiment, the ferroelectric layer (480) may be formed by including at least one of PZT (Pb(Zr,Ti)O3), SBT (SrBi2Ta2O9), SBTN (SrBi2(Ta,Nb)O9), BLT ((Bix,La1- x)4Ti3O12) and BST (BaxSr(1-x)TiO3), hafnium oxide (HfO2), hafnium oxide with silicon added (HfO2 / Si), hafnium oxide with aluminum added (HfO2 / Al), hafnium oxide with zirconium added (HfO2 / Zr), or a combination thereof.

[0035] In one embodiment, the polarization direction of the ferroelectric layer (480) may change based on the voltage applied to the gate electrode (470), the source electrode (430), and the drain electrode (450). The first FeTFET device (FeTFET1) may perform a programmed operation or an erased operation depending on the polarization direction of the ferroelectric layer (480). The polarization direction of the ferroelectric layer (480) shown in FIG. 3 may be random. For example, the polarization direction of the ferroelectric layer (480) shown in FIG. 3 may be formed from the gate electrode (470) to the channel region (460) or from the channel region (460) to the gate electrode (470). The polarization direction that changes based on the voltage applied to the gate electrode (470), the source electrode (430), and the drain electrode (450) will be described later with reference to FIG. 4a, FIG. 5a, FIG. 6a, and FIG. 7a.

[0036] The first FeTFET device (FeTFET1) illustrated in FIG. 3 may be planar, but the scope of the present invention is not limited thereto and may have various transistor structures. For example, various transistor structures may include FinFETs (Fin Field-Effect Transistors), GAA (Gate-All-Around) transistors, MBCFETs (Multi-Bridge Channel FETs), and stacked transistors (e.g., three-dimensional stacked transistors).

[0037] Figures 4a and 4b are diagrams illustrating the programming operation of an FeTFET device.

[0038] First, FIG. 4a shows the voltage conditions applied for the program operation of the FeTFET device. Referring to FIGS. 1 to 4a, the first FeTFET device (FeTFET1) can perform a program operation when a program voltage (VPGM) is applied. For example, if the difference between the voltage applied to the gate electrode (470) of the first FeTFET device (FeTFET1) and the voltage applied to the drain electrode (450) of the first FeTFET device (FeTFET1) is greater than or equal to the program voltage (VPGM), the first FeTFET device (FeTFET1) can perform a program operation. For example, if the difference between the voltage applied to the gate electrode (470) of the first FeTFET device (FeTFET1) and the voltage applied to the drain electrode (450) of the first FeTFET device (FeTFET1) is less than the program voltage (VPGM), the first FeTFET device (FeTFET1) may not be able to perform a program operation.

[0039] In one embodiment, for the program operation of the first FeTFET device (FeTFET1), a program voltage (VPGM) may be applied to the gate electrode (470), a ground voltage may be applied to the drain electrode (450), and a ground voltage may be applied to the source electrode (430). The program voltage (VPGM) applied to the gate electrode (470) may be a positive voltage. That is, a voltage may be applied to the first FeTFET device (FeTFET1) such that the difference between the voltage applied to the gate electrode (470) (e.g., program voltage (VPGM)) and the voltage applied to the drain electrode (450) (e.g., ground voltage) is greater than or equal to the program voltage (VPGM).

[0040] When a positive program voltage (VPGM) is applied to the gate electrode (470), the electron concentration in the channel region (460) may increase. For example, the electron concentration in the channel region (460) may increase due to the drain region (440). As the electron concentration in the channel region (460) increases, the polarization direction of the ferroelectric layer (480) may be formed in a third direction (D3). For example, the polarization direction of the ferroelectric layer (480) may be formed from the gate electrode (470) toward the channel region (460). As the polarization direction of the ferroelectric layer (480) is formed in the third direction (D3), the program operation of the first FeTFET device (FeTFET1) may be performed.

[0041] Next, FIG. 4b describes the programming operation of a memory cell array including a FeTFET device. Referring to FIGS. 1 through 4b, voltages for programming data into a select cell (MC_sel) can be applied to the select cell (MC_sel). The voltages for programming data into the select cell (MC_sel) may be the same as the voltages described with reference to FIG. 4a. For example, a program voltage (VPGM) may be applied to the select word line (WL1) of the select cell (MC_sel), a ground voltage (e.g., 0V) may be applied to the select bit line (BL1) of the select cell (MC_sel), and a ground voltage may be applied to the select source line (SL1) of the select cell (MC_sel).

[0042] Voltages to prevent data from being written to the non-selected cells (MC_unsel1~MC_unsel3) may be applied to the non-selected cells (MC_unsel1~MC_unsel3). For example, to program data to the selected cell (MC_sel), voltages to prevent data from being written to the non-selected cells (MC_unsel1~MC_unsel3) may be applied to the non-selected cells (MC_unsel1~MC_unsel3). For example, to prevent the first to third non-selected cells (MC_unsel1~MC_unsel3) from performing a programming operation, a voltage may be applied such that the difference between the voltage applied to the gate electrode (470) of the first to third non-selected cells (MC_unsel1~MC_unsel3) and the voltage applied to the drain electrode (450) is smaller than the programming voltage (VPGM).

[0043] In one embodiment, as the first non-select cell (MC_unsel1) shares the select word line (WL1) with the select cell (MC_sel), a program voltage (VPGM) may be applied to the first non-select cell (MC_unsel1). To prevent data from being written to the first non-select cell (MC_unsel1), a program prevention voltage (VPGM_INH) may be applied to the non-select bit lines (BL2~BLn) of the first non-select cell (MC_unsel1). A ground voltage may be applied to the non-select source lines (SL2~SLn) of the first non-select cell (MC_unsel1). For example, the difference between the program voltage (VPGM) applied to the unselected word lines (WL2~WLn) of the first unselected cell (MC_unsel1) and the program prevention voltage (VPGM_INH) applied to the unselected bit lines (BL2~BLn) of the first unselected cell (MC_unsel1) may have a value smaller than the program voltage (VPGM). Therefore, the program operation of the first unselected cell (MC_unsel1) may not be performed.

[0044] In one embodiment, as the second non-selection cell (MC_unsel2) shares the selection source line (SL1) and the selection bit line (BL1) with the selection cell (MC_sel), a ground voltage may be applied to the selection source line (SL1) of the second non-selection cell (MC_unsel2) and a ground voltage may be applied to the selection bit line (BL1) of the second non-selection cell (MC_unsel2). In this case, a ground voltage may be applied to the non-selection word lines (WL2~WLn) of the second non-selection cell (MC_unsel2). The difference between the voltage applied to the unselected word lines (WL2~WLn) of the second unselected cell (MC_unsel2) and the voltage applied to the unselected bit lines (BL2~BLn) of the second unselected cell (MC_unsel2) may be 0 or a very small value, and therefore, the program operation of the second unselected cell (MC_unsel2) may not be performed.

[0045] In one embodiment, as the third non-selection cell (MC_unsel3) shares the non-selection source lines (SL2~SLn) and non-selection bit lines (BL2~BLn) with the first non-selection cell (MC_unsel1), a ground voltage may be applied to the non-selection source lines (SL2~SLn) of the third non-selection cell (MC_unsel3), and a program prevention voltage (VPGM_INH) may be applied to the non-selection bit lines (BL2~BLn) of the second non-selection cell (MC_unsel3). Additionally, as the third non-selection cell (MC_unsel3) shares the non-selection word lines (WL2~WLn) with each of the cells among the second non-selection cells (MC_unsel2), a ground voltage may be applied to the non-selection word lines (WL2~WLn) of the third non-selection cell (MC_unsel3). In this case, the difference between the voltage applied to the unselected word lines (WL2~WLn) of the third unselected cell (MC_unsel3) and the voltage applied to the unselected bit lines (BL2~BLn) of the third unselected cell (MC_unsel3) may have the value of the program prevention voltage (VPGM_INH). The program prevention voltage (VPGM_INH) may be smaller than the size of the program voltage (VPGM), and thus the program operation of the third unselected cell (MC_unsel3) may not be performed.

[0046] In the conventional case, for the program operation of a memory cell array, voltage may be applied not only to the selected cell (MC_sel) but also to the unselected cells. For example, a program voltage (VPGM) may be applied to the selected word line (WL1) of the first unselected cell (MC_unsel1), and a program prevention voltage (VPGM_INH) may be applied to the unselected bit lines (BL2~BLn) of the first unselected cell (MC_unsel1) and the unselected bit lines (BL2~BLn) of the third unselected cell (MC_unsel3). In this case, leakage current may occur as unnecessary voltage is applied to the first and third unselected cells (MC_unsel1, MC_unsel3).

[0047] FIGS. 5A and FIGS. 5B are drawings for explaining the programming operation of an FeTFET device according to an embodiment of the present invention.

[0048] First, FIG. 5a shows the voltage conditions applied for the programmed operation of the FeTFET device according to the present invention.

[0049] Referring to FIGS. 1 to 3 and FIG. 5a, for a program operation of a first FeTFET device (FeTFET1) according to the present invention, a first voltage (V1) may be applied to a gate electrode (470), and a second voltage (V2) may be applied to a drain electrode (450). The first voltage (V1) may have a voltage value smaller than the program voltage (VPGM). The second voltage (V2) may have a voltage value obtained by subtracting the program voltage (VPGM) from the first voltage (V1). For example, the first voltage (V1) may have a value of half (VPGM) of the positive program voltage (VPGM), and the second voltage (V2) may have a value of half (-VPGM) of the negative program voltage (VPGM). However, the scope of the present disclosure is not limited thereto, and the voltage values ​​of the first voltage (V1) and the second voltage (V2) may have various combinations of voltage values ​​such that the voltage value obtained by subtracting the second voltage (V2) from the first voltage (V1) is the program voltage (VPGM).

[0050] According to the present invention, when a first voltage (V1) is applied to the gate electrode (470) and a second voltage (V2) is applied to the drain electrode (450), the energy band of the drain region (440) may rise, and as the energy band of the drain region (440) rises, the electron concentration of the channel region (460) may increase. As the electron concentration of the channel region (460) increases, the polarization direction of the ferroelectric layer (480) may be formed in a third direction (D3). For example, the polarization direction of the ferroelectric layer (480) may be formed from the gate electrode (470) toward the channel region (460). As the polarization direction of the ferroelectric layer (480) is formed in the third direction (D3), a program operation may be performed.

[0051] That is, the programming operation of the FeTFET device according to the prior art was performed based on the voltage applied to the gate electrode (470), but the programming operation of the FeTFET device according to the embodiment of the present invention can be performed based not only on the voltage applied to the gate electrode (470) but also on the voltage applied to the drain electrode (450).

[0052] Next, FIG. 5b illustrates the programming operation of a memory cell array including a FeTFET element according to an embodiment of the present invention.

[0053] Referring to FIGS. 1 to 3, FIG. 5a, and FIG. 5b, voltages for programming data into a select cell (MC_sel) may be applied to the select cell (MC_sel). The voltages for programming data into the select cell (MC_sel) may be the same as the voltages described with reference to FIG. 5a. For example, a first voltage (V1) may be applied to the select word line (WL1) of the select cell (MC_sel), a second voltage (V2) may be applied to the select bit line (BL1) of the select cell (MC_sel), and a ground voltage may be applied to the select source line (SL1) of the select cell (MC_sel). The difference between the first voltage (V1) applied to the select word line (WL1) of the select cell (MC_sel) and the second voltage (V2) applied to the select bit line (BL1) of the select cell (MC_sel) may have the magnitude of the program voltage (VPGM). For example, the first voltage (V1) may have a value of half of the positive program voltage (VPGM), and the second voltage (V2) may have a value of half of the negative program voltage (VPGM). However, the scope of the present disclosure is not limited thereto, and the voltage values ​​of the first voltage (V1) and the second voltage (V2) may have various combinations of voltage values ​​such that the voltage value obtained by subtracting the second voltage (V2) from the first voltage (V1) is the program voltage (VPGM).

[0054] Voltages to prevent data from being written to the non-selected cells (MC_unsel1~MC_unsel3) may be applied to the non-selected cells (MC_unsel1~MC_unsel3). For example, voltages to prevent data from being written to the non-selected cells (MC_unsel1~MC_unsel3) may be applied to prevent data from being written to the selected cell (MC_sel). For example, to prevent the first to third non-selected cells (MC_unsel1~MC_unsel3) from performing a programming operation, a voltage may be applied such that the difference between the voltage applied to the gate electrode (470) of the first to third non-selected cells (MC_unsel1~MC_unsel3) and the voltage applied to the drain electrode (450) is smaller than the programming voltage (VPGM).

[0055] In one embodiment, as the selection word line (WL1) of the first non-selection cell (MC_unsel1) shares the selection word line (WL1) with the selection cell (MC_sel), a first voltage (V1) may be applied to the selection word line (WL1) of the first non-selection cell (MC_unsel1). A ground voltage may be applied to the non-selection bit lines (BL2~BLn) of the first non-selection cell (MC_unsel1). A ground voltage may be applied to the non-selection source lines (SL2~SLn) of the first non-selection cell (MC_unsel1). The difference between the voltage applied to the selection word line (WL1) of the first non-selection cell (MC_unsel1) and the voltage applied to the non-selection bit lines (BL2~BLn) of the first non-selection cell (MC_unsel1) may have the magnitude of the first voltage (V1). That is, as the difference between the voltage applied to the selection word line (WL1) of the first non-select cell (MC_unsel1) and the voltage applied to the non-select bit lines (BL2~BLn) of the first non-select cell (MC_unsel1) has a first voltage (V1) value that is smaller than the program voltage (VPGM), the program operation may not be performed.

[0056] In one embodiment, as the second non-selection cell (MC_unsel2) shares the selection source line (SL1) and the selection bit line (BL1) with the selection cell (MC_sel), a ground voltage may be applied to the selection source line (SL1) of the second non-selection cell (MC_unsel2), and a second voltage (V2) may be applied to the selection bit line (BL1) of the second non-selection cell (MC_unsel2). A ground voltage may be applied to the non-selection word lines (WL2~WLn) of the second non-selection cell (MC_unsel1). In this case, the difference between the voltage applied to the non-selection word lines (WL2~WLn) of the second non-selection cell (MC_unsel2) and the voltage applied to the selection bit line (BL1) of the second non-selection cell (MC_unsel2) may have the magnitude of the second voltage (V2). That is, as the difference between the voltage applied to the unselected word lines (WL2~WLn) of the second unselected cell (MC_unsel2) and the voltage applied to the selection bit line (BL1) of the second unselected cell (MC_unsel2) is smaller than the program voltage (VPGM), the program operation may not be performed.

[0057] In one embodiment, as the third unselected cell (MC_unsel3) shares the unselected source lines (SL2~SLn) and unselected bit lines (BL2~BLn) with the first unselected cell (MC_unsel1), a ground voltage may be applied to the unselected source lines (SL2~SLn) of the third unselected cell (MC_unsel3), and a ground voltage may be applied to the unselected bit lines (BL2~BLn) of the third unselected cell (MC_unsel3). Additionally, as the third unselected cell (MC_unsel3) shares the unselected word lines (WL2~WLn) with each of the cells among the second unselected cells (MC_unsel2), a ground voltage may be applied to the unselected word lines (WL2~WLn) of the third unselected cell (MC_unsel3). In this case, the difference between the voltage applied to the unselected word lines (WL2~WLn) of the third unselected cell (MC_unsel3) and the voltage applied to the unselected bit lines (BL2~BLn) of the third unselected cell (MC_unsel3) may be zero or a very small voltage. That is, as the difference between the voltage applied to the unselected word lines (WL2~WLn) of the third unselected cell (MC_unsel3) and the voltage applied to the unselected bit lines (BL2~BLn) of the third unselected cell (MC_unsel3) is smaller than the program voltage (VPGM), the program operation may not be performed.

[0058] That is, in the case of a program operation of a memory cell array according to the present invention, the voltage applied to the non-selected cells can be reduced. For example, a ground voltage can be applied to the non-selected bit lines (BL2~BLn) of the first non-selected cell (MC_unsel1) instead of the program prevention voltage (VPGM_INH), and a ground voltage can be applied to the non-selected bit lines (BL2~BLn) of the third non-selected cell (MC_unsel3) that shares the non-selected bit lines (BL2~BLn) with the first non-selected cell (MC_unsel1). Accordingly, leakage current can be reduced by reducing the unnecessary voltage applied to the first and third non-selected cells (MC_unsel1, MC_unsel3).

[0059] Figures 6a and 6b are diagrams illustrating the erasure operation of a FeTFET device.

[0060] First, FIG. 6a shows the voltage conditions applied for the erase operation of the FeTFET device. Referring to FIGS. 1 to 3 and FIG. 6a, the first FeTFET device (FeTFET1) can perform an erase operation when an erase voltage (VERS) is applied. For example, if the difference between the voltage applied to the source electrode (430) of the first FeTFET device (FeTFET1) and the voltage applied to the gate electrode (470) of the first FeTFET device (FeTFET1) is greater than or equal to the erase voltage (VERS), the first FeTFET device (FeTFET1) can perform an erase operation. For example, if the difference between the voltage applied to the source electrode (430) of the first FeTFET device (FeTFET1) and the voltage applied to the gate electrode (470) of the first FeTFET device (FeTFET1) is smaller than the erase voltage (VERS), the first FeTFET device (FeTFET1) may not be able to perform the erase operation.

[0061] In one embodiment, for the erasure operation of the first FeTFET device (FeTFET1), a ground voltage may be applied to the source electrode (430), an erasure voltage (VERS) may be applied to the gate electrode (470), and a ground voltage may be applied to the drain electrode (450). The erasure voltage (VERS) applied to the gate electrode (470) may be a negative voltage. That is, a voltage may be applied to the first FeTFET device (FeTFET1) such that the difference between the voltage applied to the gate electrode (470) (e.g., erasure voltage (VERS)) and the voltage applied to the source electrode (430) (e.g., ground voltage) is greater than or equal to the erasure voltage (VERS).

[0062] When a negative voltage, such as an erase voltage (VERS), is applied to the gate electrode (470), the hole concentration in the channel region (460) may increase. For example, the hole concentration in the channel region (460) may increase due to the source region (420). As the hole concentration in the channel region (460) increases, the polarization direction of the ferroelectric layer (480) may be formed in a fourth direction (D4). For example, the polarization direction of the ferroelectric layer (480) may be formed from the channel region (460) to the gate electrode (470). As the polarization direction of the ferroelectric layer (480) is formed in the fourth direction (D4), an erase operation may be performed.

[0063] Next, FIG. 6b describes the programming operation of a memory cell array including a FeTFET device. Referring to FIGS. 1 through 3, FIG. 6a, and FIG. 6b, voltages for erasing data written to the select cell (MC_sel) can be applied to the select cell (MC_sel). The voltages for erasing data written to the select cell (MC_sel) may be the same as the voltages described with reference to FIG. 4b. For example, a ground voltage may be applied to the select source line (SL1) of the select cell (MC_sel), an erase voltage (VERS) may be applied to the select word line (WL1) of the select cell (MC_sel), and a ground voltage may be applied to the select bit line (BL1) of the select cell (MC_sel).

[0064] Voltages to prevent data written to the unselected cells (MC_unsel1~MC_unsel3) from being erased may be applied to the unselected cells (MC_unsel1~MC_unsel3). For example, to erase data written to the selected cell (MC_sel), voltages to prevent data written to the unselected cells (MC_unsel1~MC_unsel3) from being erased may be applied to the unselected cells (MC_unsel1~MC_unsel3). For example, a voltage may be applied such that the difference between the voltage applied to the gate electrode (470) of the first to third non-selection cells (MC_unsel1~MC_unsel3) and the voltage applied to the source electrode (430) of the first to third non-selection cells (MC_unsel1~MC_unsel3) is smaller than the erase voltage (VERS) so that the first to third non-selection cells (MC_unsel1~MC_unsel3) do not perform an erase operation.

[0065] In one embodiment, as the first non-select cell (MC_unsel1) shares the selection word line (WL1) with the selection cell (MC_sel), an erase voltage (VERS) may be applied to the selection word line (WL1) of the first non-select cell (MC_unsel1). To prevent data from being written to the first non-select cell (MC_unsel1), an erasure prevention voltage (VERS_INH) may be applied to the non-select source lines (SL2~SLn) of the first non-select cell (MC_unsel1). For example, the difference between the erase voltage (VERS) applied to the selection word line (WL1) of the first non-select cell (MC_unsel1) and the erasure prevention voltage (VERS_INH) applied to the non-select source lines (SL2~SLn) of the first non-select cell (MC_unsel1) may have a value smaller than the erase voltage (VERS). Therefore, the erasure operation of the first unselected cell (MC_unsel1) may not be performed.

[0066] In one embodiment, as the second non-selection cell (MC_unsel2) shares the selection source line (SL1) and the selection bit line (BL1) with the selection cell (MC_sel), a ground voltage may be applied to the selection source line (SL1) of the second non-selection cell (MC_unsel2) and a ground voltage may be applied to the selection bit line (BL1) of the second non-selection cell (MC_unsel2). In this case, a ground voltage may be applied to the non-selection word lines (WL2~WLn) of the second non-selection cell (MC_unsel2). The difference between the voltage applied to the unselected word lines (WL2~WLn) of the second unselected cell (MC_unsel2) and the voltage applied to the selected source line (SL1) of the second unselected cell (MC_unsel2) may be zero or a very small voltage, and thus, the erase operation of the second unselected cell (MC_unsel2) may not be performed.

[0067] In one embodiment, as the third unselected cell (MC_unsel3) shares the unselected source lines (SL2~SLn) and unselected bit lines (BL2~BLn) with the first unselected cell (MC_unsel1), an erasure prevention voltage (VERS_INH) may be applied to the unselected source lines (SL2~SLn) of the third unselected cell (MC_unsel3), and a ground voltage may be applied to the unselected bit lines (BL2~BLn) of the second unselected cell (MC_unsel3). Additionally, as the third unselected cell (MC_unsel3) shares the unselected word lines (WL2~WLn) of each of the cells in the second unselected cell (MC_unsel2), a ground voltage may be applied to the unselected word lines (WL2~WLn) of the third unselected cell (MC_unsel3). In this case, the difference between the voltage applied to the unselected word lines (WL2~WLn) of the third unselected cell (MC_unsel3) and the voltage applied to the unselected source lines (SL2~SLn) of the third unselected cell (MC_unsel3) may have the value of the erase prevention voltage (VERS_INH). The erase prevention voltage (VERS_INH) may be smaller than the magnitude of the erase voltage (VERS), and thus the erase operation of the third unselected cell (MC_unsel3) may not be performed.

[0068] In the conventional case, for the erase operation of a memory cell array, voltage may be applied not only to the selected cell (MC_sel) but also to the unselected cells. For example, an erase voltage (VERS) may be applied to the selected word line (WL1) of the first unselected cell (MC_unsel1), and an erase prevention voltage (VERS_INH) may be applied to the unselected source lines (BL2~BLn) of the first unselected cell (MC_unsel1) and the unselected source lines (BL2~BLn) of the third unselected cell (MC_unsel3). In this case, leakage current may occur as unnecessary voltage is applied to the first and third unselected cells (MC_unsel1, MC_unsel3).

[0069] FIGS. 7a and 7b are drawings for explaining the erasure operation of a FeTFET device according to an embodiment of the present invention.

[0070] First, FIG. 7a illustrates voltage conditions applied for the programmed operation of a FeTFET device according to the present invention. Referring to FIGS. 1 to 3 and FIG. 7a, for the erase operation of a first FeTFET device (FeTFET1) according to the present invention, a third voltage (V3) may be applied to the source electrode (430), a fourth voltage (V4) may be applied to the gate electrode (470), and a ground voltage may be applied to the drain electrode (450) of the first FeTFET device (FeTFET1). The third voltage (V3) may have a voltage value smaller than the erase voltage (VERS). The erase voltage (VERS) may be a negative voltage. The fourth voltage (V4) may have a voltage value obtained by subtracting the erase voltage (VERS) from the third voltage (V3). For example, the fourth voltage (V4) may have a value of half (VERS) of the erase voltage (VERS), and the fourth voltage (V4) may be a negative voltage. For example, the third voltage (V3) may have a value of half (VERS) of the erase voltage (VERS), and the third voltage (V3) may be a positive voltage. That is, the difference between the fourth voltage (V4) applied to the gate electrode (470) and the third voltage (V3) applied to the source electrode (430) may be the erase voltage (VERS). However, the scope of the present disclosure is not limited thereto, and the voltage values ​​of the third voltage (V3) and the fourth voltage (V4) may have various combinations of voltage values ​​such that the voltage value obtained by subtracting the third voltage value (V3) from the fourth voltage value (V4) is the erase voltage (VERS).

[0071] According to the present invention, when a third voltage (V3) is applied to the source electrode (430) and a fourth voltage (V4) is applied to the gate electrode (470), the energy band of the source region (420) may decrease, and as the energy band of the source region (420) decreases, the hole concentration of the channel region (460) may increase. As the hole concentration of the channel region (460) increases, the polarization direction of the ferroelectric layer (480) may be formed in the fourth direction (D4). For example, the polarization direction of the ferroelectric layer (480) may be formed from the channel region (460) toward the gate electrode (470). As the polarization direction of the ferroelectric layer (480) is formed in the fourth direction (D4), an erasure operation may be performed.

[0072] That is, the erasure operation of the FeTFET device according to the prior art was performed based on the voltage applied to the gate electrode (470), but the erasure operation of the FeTFET device according to the embodiment of the present invention can be performed based not only on the voltage applied to the gate electrode (470) but also on the voltage applied to the source electrode (430).

[0073] Next, FIG. 7b illustrates the erasure operation of a memory cell array including a FeTFET element according to an embodiment of the present invention.

[0074] Referring to FIGS. 1 to 3, FIG. 7a, and FIG. 7b, voltages for erasing data written to the select cell (MC_sel) may be applied to the select cell (MC_sel). The voltages for erasing data written to the select cell (MC_sel) may be the same as the voltages described with reference to FIG. 7a. For example, a third voltage (V3) may be applied to the select source line (SL1) of the select cell (MC_sel), a fourth voltage (V4) may be applied to the select word line (WL1) of the select cell (MC_sel), and a ground voltage may be applied to the select bit line (BL1) of the select cell (MC_sel). The difference between the fourth voltage (V4) applied to the selection word line (WL1) of the selection cell (MC_sel) and the third voltage (V3) applied to the selection source line (SL1) of the selection cell (MC_sel) may have the magnitude of the erase voltage (VERS). For example, the fourth voltage (V4) may have a value of half (VERS) of the erase voltage (VERS), and the fourth voltage (V4) may be a negative voltage. For example, the third voltage (V3) may have a value of half (VERS) of the erase voltage (VERS), and the third voltage (V3) may be a positive voltage. That is, the difference between the fourth voltage (V4) applied to the gate electrode (470) and the third voltage (V3) applied to the source electrode (430) may be the erase voltage (VERS). However, the scope of the present disclosure is not limited thereto, and the voltage values ​​of the third voltage (V3) and the fourth voltage (V4) may have various combinations of voltage values ​​such that the voltage value obtained by subtracting the third voltage value (V3) from the fourth voltage value (V4) is the erase voltage (VERS).

[0075] Voltages to prevent data written to the unselected cells (MC_unsel1~MC_unsel3) from being erased may be applied to the unselected cells (MC_unsel1~MC_unsel3). For example, to erase data written to the selected cell (MC_sel), voltages to prevent data written to the unselected cells (MC_unsel1~MC_unsel3) from being erased may be applied to the unselected cells (MC_unsel1~MC_unsel3). For example, a voltage may be applied such that the difference between the voltage applied to the gate electrode (470) of the first to third non-selection cells (MC_unsel1~MC_unsel3) and the voltage applied to the source electrode (430) of the first to third non-selection cells (MC_unsel1~MC_unsel3) is smaller than the erase voltage (VERS) so that the first to third non-selection cells (MC_unsel1~MC_unsel3) do not perform an erase operation.

[0076] In one embodiment, as the first non-selection cell (MC_unsel1) shares the selection word line (WL1) with the selection cell (MC_sel), a fourth voltage (V4) may be applied to the selection word line (WL1) of the first non-selection cell (MC_unsel1). A ground voltage may be applied to the non-selection bit lines (BL2~BLn) of the first non-selection cell (MC_unsel1). A ground voltage may be applied to the non-selection source lines (SL2~SLn) of the first non-selection cell (MC_unsel1). The difference between the voltage applied to the selection word line (WL1) of the first non-selection cell (MC_unsel1) and the voltage applied to the non-selection source lines (SL2~SLn) of the first non-selection cell (MC_unsel1) may have the magnitude of the fourth voltage (V4). That is, as the difference between the voltages applied to the unselected word lines (WL2~WLn) and unselected source lines (SL2~SLn) of the first unselected cell (MC_unsel1) is smaller than the erase voltage (VERS), the erase operation may not be performed.

[0077] In one embodiment, as the second non-selection cell (MC_unsel2) shares the selection source line (SL1) and the selection bit line (BL1) with the selection cell (MC_sel), a third voltage (V3) may be applied to the selection source line (SL1) of the second non-selection cell (MC_unsel2), and a ground voltage may be applied to the selection bit line (BL1) of the second non-selection cell (MC_unsel2). A ground voltage may be applied to the non-selection word lines (WL2~WLn) of the second non-selection cell (MC_unsel2). The difference between the voltage applied to the non-selection word lines (WL2~WLn) of the second non-selection cell (MC_unsel2) and the voltage applied to the non-selection source lines (SL2~SLn) of the second non-selection cell (MC_unsel2) may have the magnitude of the third voltage (V3). That is, as the difference between the voltage applied to the unselected word lines (WL2~WLn) and the selected source line (SL1) of the second unselected cell (MC_unsel2) is smaller than the erase voltage (VERS), the erase operation may not be performed.

[0078] In one embodiment, as the third unselected cell (MC_unsel3) shares the unselected source lines (SL2~SLn) and unselected bit lines (BL2~BLn) with the first unselected cell (MC_unsel1), a ground voltage may be applied to the unselected source lines (SL2~SLn) of the third unselected cell (MC_unsel3), and a ground voltage may be applied to the unselected bit lines (BL2~BLn) of the third unselected cell (MC_unsel3). Additionally, as the third unselected cell (MC_unsel3) shares the unselected word lines (WL2~WLn) with each of the cells among the second unselected cells (MC_unsel2), a ground voltage may be applied to the unselected word lines (WL2~WLn) of the third unselected cell (MC_unsel3). In this case, the difference between the voltage applied to the unselected word lines (WL2~WLn) of the third unselected cell (MC_unsel3) and the voltage applied to the unselected source lines (SL2~SLn) of the third unselected cell (MC_unsel3) may be zero or a very small voltage. That is, as the difference between the voltages applied to the unselected word lines (WL2~WLn) and unselected source lines (SL2~SLn) of the third unselected cell (MC_unsel2) is smaller than the erase voltage (VERS), the erase operation may not be performed.

[0079] That is, in the case of an erase operation of a memory cell array according to the present invention, the voltage applied to the unselected cells can be reduced. For example, a ground voltage can be applied to the unselected source lines (SL2~SLn) of the first unselected cell (MC_unsel1) instead of the erase prevention voltage (VERS_INH), and a ground voltage can be applied to the unselected bit lines (BL2~BLn) of the third unselected cell (MC_unsel3) that shares the unselected bit lines (BL2~BLn) with the first unselected cell (MC_unsel1). Accordingly, by reducing the unnecessary voltage applied to the first and third unselected cells (MC_unsel1, MC_unsel3), leakage current can be reduced.

[0080] FIGS. 8a and FIGS. 8b are flowcharts showing a method of operation of a memory device according to an embodiment of the present invention.

[0081] First, FIG. 8a illustrates a method of operation of a memory device that performs a program operation. Referring to FIGS. 1 to 3, FIGS. 5a, FIG. 5b, and FIG. 8a, in step S110a, a first voltage (V1) may be applied to the selection word line (WL1) of a selection cell (MC_sel). The first voltage (V1) may be smaller than the program voltage (VPGM). The program voltage (VPGM) may be a voltage that causes the program operation of the selection cell (MC_sel).

[0082] In step S120a, a second voltage (V2) may be applied to the select bit line (BL1) of the select cell (MC_sel). The second voltage (V2) may have a value obtained by subtracting the program voltage (VPGM) from the first voltage (V1). For example, the first voltage (V1) may have a value of half of the positive program voltage (VPGM), and the second voltage (V2) may have a value of half of the negative program voltage (VPGM). However, the scope of the present disclosure is not limited thereto, and the voltage values ​​of the first voltage (V1) and the second voltage (V2) may have various combinations of voltage values ​​such that the voltage value obtained by subtracting the second voltage (V2) from the first voltage (V1) is the program voltage (VPGM).

[0083] In step S130a, a ground voltage may be applied to the selection source line (SL1) of the selection cell (MC_sel), the non-selection source line (SL2~SLn) of the first non-selection cell (MC_unsel1), the non-selection bit line (BL1~BLn) of the first non-selection cell (MC_unsel1), and the non-selection word line (WL2~WLn) of the second non-selection cell (MC_unsel2).

[0084] Next, FIG. 8b illustrates a method of operation of a memory device that performs an erase operation. Referring to FIGS. 1 through 3, FIGS. 7a, FIG. 7b, and FIG. 8b, in step S110b, a third voltage (V3) may be applied to the selection source line (SL1) of the selection cell (MC_sel). The third voltage (V3) may be smaller than the erase voltage (VERS). The erase voltage (VERS) may be a voltage that causes the erase operation of the selection cell (MC_sel).

[0085] In step S120b, a fourth voltage (V4) may be applied to the selected word line (WL1) of the selected cell (MC_sel). The fourth voltage (V4) may have a value obtained by subtracting the erase voltage (VERS) from the third voltage (V3). For example, the fourth voltage (V4) may have a value of half (VERS) of the erase voltage (VERS), and the fourth voltage (V4) may be a negative voltage. For example, the third voltage (V3) may have a value of half (VERS) of the erase voltage (VERS), and the third voltage (V3) may be a positive voltage. That is, the difference between the fourth voltage (V4) applied to the gate electrode (470) and the third voltage (V3) applied to the source electrode (430) may be the erase voltage (VERS). However, the scope of the present disclosure is not limited thereto, and the voltage values ​​of the third voltage (V3) and the fourth voltage (V4) may have various combinations of voltage values ​​such that the voltage value obtained by subtracting the third voltage value (V3) from the fourth voltage value (V4) is the erase voltage (VERS).

[0086] In step S130b, a ground voltage may be applied to the selection bit line (BL1) of the selection cell (MC_sel), the non-selection source line (SL2~SLn) of the first non-selection cell (MC_unsel1), the non-selection bit line (BL1~BLn) of the first non-selection cell (MC_unsel1), and the non-selection word line (WL2~WLn) of the second non-selection cell (MC_unsel2).

[0087] FIGS. 9a and 9b are graphs showing the voltage and current characteristics of a cell to which a voltage is applied for a program operation or an erase operation according to an embodiment of the present invention.

[0088] First, referring to FIGS. 1 to 3, FIG. 5a, FIG. 7a, FIG. 8a, and FIG. 9a, the voltage and current characteristics of memory cells (e.g., a selected cell (MC_sel), a first unselected cell (MC_unsel1), and a second unselected cell (MC_unsel2)) to which voltage for program operation according to an embodiment of the present invention is applied are illustrated. In the case of FIG. 9a, the first and second unselected cells (MC_unsel1, MC_unsel2) are described as being in a state where data has been erased through an erase operation.

[0089] The select cell (MC_sel) can perform a program operation as the program voltage (VPGM) is applied. For example, the select cell (MC_sel) may have voltage and current characteristics corresponding to a program state.

[0090] On the other hand, the first and second non-selected cells (MC_unsel1, MC_unsel2) may not perform a program operation as voltages according to the present invention are applied so that a program operation is not performed. For example, the first and second non-selected cells (MC_unsel1, MC_unsel2) may have voltage and current characteristics corresponding to an erase state.

[0091] Next, referring to FIGS. 1 to 3, FIG. 5b, FIG. 7b, FIG. 8b, and FIG. 9b, the voltage and current characteristics of memory cells (e.g., a selected cell (MC_sel), a first unselected cell (MC_unsel1), and a second unselected cell (MC_unsel2)) to which a voltage for an erase operation according to an embodiment of the present invention is illustrated. In the case of FIG. 9b, the first and second unselected cells (MC_unsel1, MC_unsel2) are described as having data written through a program operation.

[0092] The select cell (MC_sel) can perform an erase operation as the erase voltage (VERS) is applied. For example, the select cell (MC_sel) may have voltage and current characteristics corresponding to the erase state.

[0093] On the other hand, the first and second non-selected cells (MC_unsel1, MC_unsel2) may not undergo an erasure operation as voltages according to the present invention are applied so that an erasure operation is not performed. For example, the first and second non-selected cells (MC_unsel1, MC_unsel2) may have voltage and current characteristics corresponding to a program state.

[0094] FIG. 10 is a graph showing a reduced leakage current according to an embodiment of the present invention. Referring to FIGS. 1 to 3, FIGS. 5a, FIGS. 5b, FIGS. 7a, FIGS. 7b, and FIG. 10, a graph of leakage current is shown for a case where a voltage is applied for a conventional program operation or erase operation (Conventional) and a case where a voltage is applied for a program operation or erase operation according to the present invention (Novel).

[0095] According to the present invention (Novel), as the size of the memory cell array (110) increases, the size of the total leakage current can be reduced compared to the conventional case (Conventional). That is, according to the present invention, the leakage current that occurs as the size of the memory cell array (110) increases can be effectively reduced.

[0096] The above description describes specific embodiments for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present invention will include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present invention should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this invention.

Claims

Claim 1 A method of operation of a memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of source lines connected to a plurality of memory cells, comprising: a step of applying a first voltage to a selected word line connected to a selected memory cell among the plurality of word lines; a step of applying a second voltage to a selected bit line connected to the selected memory cell among the plurality of bit lines; and a step of applying a ground voltage to the plurality of source lines, non-selected word lines among the plurality of word lines, and non-selected bit lines among the plurality of bit lines, wherein the first voltage is greater than the ground voltage and the second voltage is less than the ground voltage, and each of the plurality of memory cells includes a Ferroelectric Tunnel Field-Effect Transistor (FeTFET) element. Claim 2 A method of operation according to claim 1, wherein each of the plurality of memory cells comprises a ferroelectric tunnel field-effect transistor element including: a source region; a drain region; a channel region formed between the source region and the drain region; an insulating layer formed on the channel region; a ferroelectric layer formed on the insulating layer; and a gate formed on the ferroelectric layer. Claim 3 A method of operation according to claim 2, wherein the source region is connected to one of the plurality of source lines, the drain region is connected to one of the plurality of bit lines, and the gate is connected to one of the plurality of word lines. Claim 4 A method of operation according to claim 2, wherein the source region is of the P+ type and the drain region is of the N+ type. Claim 5 A method of operation in which, in claim 1, the first voltage and the second voltage are at the same level. Claim 6 A method of operation in which the polarization direction of the ferroelectric layer of the selected memory cell is aligned in a first direction by a first voltage applied to the selected word line and a second voltage applied to the selected bit line. Claim 7 A method of operation according to claim 6, further comprising: a step of applying a third voltage to the selected word line; a step of applying a fourth voltage to a selected source line connected to the selected memory cell among the plurality of source lines; and a step of applying a ground voltage to the plurality of bit lines, the non-selected word lines, and the non-selected source lines among the plurality of source lines. Claim 8 In claim 7, the method of operation in which the third voltage is lower than the ground voltage and the fourth voltage is higher than the ground voltage. Claim 9 In claim 7, a method of operation in which the polarization direction of the ferroelectric layer of the selected memory cell is aligned to a second direction opposite to the first direction by the third voltage and the fourth voltage. Claim 10 A method of operation in which the polarization direction of the ferroelectric layer of each of the non-selected memory cells among the plurality of memory cells is not changed.

Images