Stacked component array structure

Abstract

A structure having an array of electronic components positioned between two stacked printed circuit boards is disclosed. The electronic components of the array may be connected to the printed circuit boards through solder connections. Exemplary electronic components include capacitors. A related manufacturing method is disclosed, comprising the step of applying heat to a solder paste array on the printed circuit boards to form solid conductors electrically connected to the electronic components.

Description

Technology Field

[0001] This application claims priority to U.S. Provisional Application No. 63 / 127,018, filed on December 17, 2020, titled “Stacked PCBs Passive / Active Components Array Structure,” the disclosure of which is incorporated herein by reference in its entirety and for all purposes. Background Technology

[0002] The present disclosure relates generally to electronic technology, and more specifically to passive and / or active components (such as capacitors, inductors, resistors, and combinations thereof) within a format of arrays of electronic devices (such as integrated circuit chips).

[0003] Switching power supplies is a generally known process. One application of switching power supplies is converting an input voltage, for example, to a lower DC voltage to drive an Integrated Circuit (IC). Voltage Regulator Modules (VRMs) can be used to convert voltage received from a battery or other DC source to a lower voltage for use by the IC. At relatively low voltages, for example, less than 1 volt, high power requirements for ICs, for example, exceeding 500 watts, create challenges for VRMs. VRMs must supply relatively low DC voltages at hundreds of amperes. Typically, VRMs have space constraints but still include components (such as LC filters) to generate clean power at low voltages while handling high currents.

[0004] VRMs typically require significant capacitance to regulate their output DC voltage. It is difficult to include this significant capacitance within a small form factor device, for example, a small footprint. Previous capacitor arrays typically require a relatively large footprint, which limits the footprint size of the VRM. This disadvantage of previous capacitor arrays introduces problems similar to those of other electronic technologies that have both high capacitance requirements and small footprint requirements. means of solving the problem

[0005] The innovations described in the claims each have various aspects, and none of them are solely responsible for the desirable attributes. Without limiting the scope of the claims, some prominent features of the present disclosure will now be described briefly.

[0006] One aspect of the present disclosure is a stacked printed circuit board (PCB) electronic component array structure comprising a first PCB, a second PCB stacked together with the first PCB, and an electronic component array comprising a plurality of electronic components positioned between the first PCB and the second PCB. The plurality of electronic components are electrically coupled to the first PCB through first solder connections. The plurality of electronic components are electrically coupled to the second PCB through second solder connections.

[0007] The first sides of the plurality of electronic components can be electrically coupled to both the first PCB and the second PCB, and the second sides of the plurality of electronic components are electrically coupled to both the first PCB and the second PCB. The inner surface of the first PCB can be coupled to the plurality of electronic components of the electronic component array, and the inner surface of the second PCB can be coupled to the plurality of electronic components of the electronic component array. The structure may include a first ball grid array disposed on the outer surface of the first PCB; - the plurality of electronic components are electrically coupled to the first ball grid array through first vias within the first PCB - and a second ball grid array disposed on the outer surface of the second PCB - the plurality of electronic components are electrically coupled to the second first ball grid array through second vias within the second PCB.

[0008] The plurality of electronic components include a plurality of discrete passive elements. The plurality of discrete passive elements may include a first group of discrete passive elements electrically connected in series and a second group of discrete passive elements electrically connected in parallel. The plurality of electronic components may include a plurality of capacitors. The plurality of electronic components may include a plurality of active components.

[0009] Another aspect of the present disclosure is a stacked printed circuit board (PCB) capacitor array structure comprising a lower PCB, an upper PCB, and a plurality of capacitors located between the lower PCB and the upper PCB, and electrically coupled to both the lower PCB and the upper PCB.

[0010] A first plurality of solder connections can electrically connect the plurality of capacitors of the capacitor array to the upper PCB, and a second plurality of solder connections can electrically connect the plurality of capacitors of the capacitor array to the lower PCB. The first sides of the plurality of capacitors can be electrically connected to both the upper PCB and the lower PCB, and the second sides of the plurality of capacitors are electrically connected to both the upper PCB and the lower PCB.

[0011] The inner surface of the upper PCB can be coupled to the plurality of capacitors of the capacitor array, and the inner surface of the lower PCB can be coupled to the plurality of capacitors of the capacitor array. The structure may include a first ball grid array disposed on the outer surface of the upper PCB and a second ball grid array disposed on the outer surface of the lower PCB.

[0012] Another aspect of the present disclosure is a method for assembling a stacked printed circuit board (PCB) electronic component array. The method comprises: providing a first PCB having a first solder paste array thereon; positioning a plurality of electronic components of an electronic component array associated with the first PCB; positioning a second PCB associated with the plurality of electronic components such that a second solder paste array on the second PCB is aligned with the plurality of electronic components; and applying heat to convert the second solder paste array into second solid conductors electrically connected to the plurality of electronic components; wherein, after the step of applying heat to convert the second solder paste array, the electronic components are electrically connected to the first solid conductors on the first PCB and to the second solid conductors on the second PCB.

[0013] The above method may include the step of applying a first solder paste array on the surface of the first PCB prior to the step of providing the first PCB. The step of applying heat to convert the second solder paste array into second solid conductors may also convert the first solder paste array into the first solid conductors. The above method may include the step of applying heat to convert the first solder paste array into first solid conductors prior to the step of positioning the second PCB.

[0014] The step of applying heat to convert the first and second paste arrays into second solid conductors may include an induction press reflow process. The step of applying heat to convert the second solder paste array into second solid conductors may include a laser welding process.

[0015] The plurality of electronic components may include individual passive components. The individual passive components may include a plurality of capacitors. The method may electrically connect a first group of electronic components of the plurality of electronic components in series with each other. The method may electrically connect a second group of electronic components of the plurality of electronic components in parallel with each other.

[0016] The above method can electrically connect the first sides of the plurality of electronic components to both the first PCB and the second PCB. The above method can electrically connect the second sides of the plurality of electronic components to both the first PCB and the second PCB.

[0017] Another aspect of the present disclosure is a method for constructing a stacked printed circuit board (PCB) capacitor array comprising: applying a first solder paste array to an inner surface of a lower PCB; placing a plurality of capacitors of a capacitor array with the first solder paste array; applying a second solder paste array to an inner surface of an upper PCB, wherein the pattern of the first solder paste array corresponds to the capacitor array; placing the upper PCB with the capacitor array such that the second solder paste array of the upper PCB is aligned with the plurality of capacitors of the capacitor array; and applying heat to convert the first solder paste array and the second solder paste array into solid conductors.

[0018] The step of applying heat to convert the first solder paste array and the second solder paste array into solid conductors may include an induction press reflow process.

[0019] The step of applying heat to convert the first solder paste array and the second solder paste array into solid conductors may include a laser welding process.

[0020] Another aspect of the present disclosure is a method for constructing a stacked printed circuit board (PCB) capacitor array, comprising: applying a first solder paste array to an inner surface of a lower PCB; arranging a plurality of capacitors of a capacitor array in the solder paste array; applying heat to convert the first solder paste array into solid conductors, wherein the pattern of the solder paste array corresponds to the capacitor array; applying a second solder paste array to an inner surface of an upper PCB; arranging the upper PCB in the capacitor array such that the second solder paste array of the upper PCB is aligned with a plurality of capacitors of the capacitor array; and applying heat to convert the second solder paste array into solid conductors.

[0021] The step of applying heat to convert the first solder paste array and the second solder paste array into solid conductors may include an induction press reflow process.

[0022] The step of applying heat to convert the first solder paste array and the second solder paste array into solid conductors may include a laser welding process.

[0023] For the purpose of summarizing the disclosure, specific aspects, benefits, and novel features of the innovations have been described herein. It should be understood that not all of these benefits may necessarily be achieved according to any specific embodiment. Accordingly, the innovations may be implemented or performed in a manner that achieves or optimizes one benefit or group of benefits as taught herein, without necessarily achieving other benefits as taught or proposed herein. Brief explanation of the drawing

[0024] FIG. 1 is a block diagram illustrating a processing system comprising a plurality of multiple circuit board high-power voltage regulator modules (VRMs) configured according to the present disclosure. FIG. 2 is a block schematic diagram illustrating a multi-circuit board high-power VRM according to the present disclosure. FIG. 3a is a block schematic diagram illustrating the first capacitor circuit board of the multi-circuit board high-power VRM of FIG. 2. FIG. 3b is a block schematic diagram illustrating a second capacitor circuit board of a multi-circuit board high-power VRM of FIG. 2. FIG. 4 is a block schematic diagram illustrating cooling system components of a multi-circuit board high-power VRM according to the present disclosure. FIG. 5 is a transparent perspective view of a capacitor array interconnected by conductive structures according to the present disclosure. FIG. 6 is a partial side view of a part of a stacked printed circuit board (PCB) capacitor array structure according to the present disclosure. FIG. 7 is a plan view of an unassembled stacked PCB capacitor array structure according to the present disclosure. FIG. 8a is a partial side view of a stacked PCB capacitor array structure configured according to the present disclosure. FIG. 8b is a plan view of a stacked PCB capacitor array structure partially constructed according to the present disclosure. FIG. 9a is a partial side view of a lower PCB having a plurality of first solder paste pads and a first solder paste array formed thereon. FIG. 9b is a partial side view of the lower PCB of FIG. 9a while capacitors are mounted thereon according to the present disclosure. FIG. 10a is a flowchart illustrating a first embodiment of a stacked PCB capacitor array structure according to the present disclosure. FIGS. 10b and FIGS. 10c are partial side views of a stacked PCB capacitor array structure while configuring a configuration consistent with FIG. 10a. FIG. 11a is a flowchart illustrating a second embodiment of a stacked PCB capacitor array structure according to the present disclosure. FIGS. 11b, FIGS. 11c, and FIGS. 11d are partial side views of a stacked PCB capacitor array structure while configuring a configuration consistent with FIG. 11a. Specific details for implementing the invention

[0025] FIG. 1 is a block diagram illustrating a processing system comprising a plurality of multiple circuit board high-power voltage regulator modules (VRMs) configured according to the present disclosure. The processing system (100) of FIG. 1 includes a plurality of multiple circuit board high-power VRMs (102A, 102B, 102C, and 102D) configured according to the present disclosure and mounted on a substrate panel (104). The plurality of multiple circuit board high-power VRMs (102A, 102B, 102C, and 102D) are supplied by a DC supply voltage (108), for example, 40 volts, 48 ​​volts, or another relative voltage, and each of the plurality of integrated circuits (ICs) (106A, 106B, 106C, and 106D) respectively. The DC supply voltage (108) may be in the range of 40 to 60 volts in certain applications. In some embodiments, each of the multiple circuit board high-power VRMs (102A, 102B, 102C, and 102D) generates an output of approximately 0.8 volts and provides 600 watts of power or more to each of the multiple ICs (106A, 106B, 106C, and 106D). Thus, each of the multiple circuit board high-power VRMs (102A, 102B, 102C, and 102D) generates a current exceeding 100 amperes to the multiple ICs (106A, 106B, 106C, and 106D).

[0026] Since each of the multiple multi-circuit board high-power VRMs (102A, 102B, 102C, and 102D) generates an output of approximately 0.8 volts to each of the multiple ICs (106A, 106B, 106C, and 106D) and it is desirable for the footprint of the VRMs (102A to 102D) to be nearly identical to the footprint of the multiple ICs (106A to 106D), the footprint of the multiple VRMs (102A to 102D) is limited. In some embodiments, the footprint is approximately 3 centimeters × 3 centimeters, 4 centimeters × 4 centimeters, or other relatively small dimensions close to the cross section of the multiple ICs (106A, 106B, 106C, and 106D). However, to generate power at low voltage and high power, multiple VRMs (102A to 102D) typically include a relatively large number of individual components.

[0027] Accordingly, according to the present disclosure, a plurality of multi-circuit board high-power VRMs (102A, 102B, 102C, and 102D) comprise circuit boards disposed in both planes perpendicular to the substrate panel (104) and planes parallel to the substrate panel (104). An embodiment to be described with reference to FIGS. 2, FIGS. 3a, and FIGS. 3b comprises two circuit boards oriented perpendicularly to the substrate panel (104) and two circuit boards oriented parallel to the substrate panel (104). In this structure, the VRMs (102A, 102B, 102C, and 102D) extend over the substrate panel (104) in a direction perpendicular to the substrate panel. One or more of the VRMs (102A, 102B, 102C, and 102D) may be included and / or implemented in relation to any suitable principles and advantages discussed with reference to FIGS. 5 through 11d. For example, the VRM (102A) may include a capacitor array located between two stacked PCBs and soldered to the two stacked PCBs.

[0028] FIG. 2 is a block schematic diagram illustrating a multi-circuit board high-power VRM according to the present disclosure. The multi-circuit board high-power VRM (200) includes a first voltage rail circuit board (202A), a second voltage rail circuit board (202B), a first capacitor circuit board (216), and a second capacitor circuit board (218). These components are mounted on rails (212A and 212B) and on a top brace (213), for example, the rails (212A and 212B) are joined to a board panel (210) using screws. The second capacitor board (218) can be joined to the board panel (210) via solder balls, which may have a pitch of 1 mm. The electrical connection formed by the substrate panel (210) combines the first rail voltage and the second rail voltage to the die (214) mounted on the opposite side of the substrate panel (210).

[0029] A first voltage rail circuit board (202A) is oriented in a first plane and forms a first plurality of conductors therein (in a plurality of layers), and mounts a first plurality of VRM elements (206A), a first plurality of inductors (208A) coupled to the first plurality of VRM elements (206A), and a first plurality of capacitors (204A) thereon. The first voltage rail circuit board (202A) is configured to receive a first voltage and generate a first rail voltage. A second voltage rail circuit board (202B) is oriented in a second plane substantially parallel to the first plane and includes a second plurality of conductors formed therein (in a plurality of layers), and mounts a second plurality of VRM elements (206B), a second plurality of inductors (208B) coupled to the second plurality of VRM elements (206B), and a second plurality of capacitors (204B) thereon. The second voltage rail circuit board (202B) is configured to receive the second voltage and generate the second rail voltage. The first voltage and the second voltage can be received from a battery pack inside the electric vehicle.

[0030] A first capacitor circuit board (216) is oriented in a third plane substantially perpendicular to a first plane and forms a third plurality of conductors therein. The first capacitor circuit board mounts a third plurality of capacitors thereon. A second capacitor circuit board (218) is oriented in a fourth plane substantially parallel to a third plane and includes a fourth plurality of conductors formed therein and mounts a fourth plurality of capacitors thereon.

[0031] The multi-circuit board high-power VRM (200) further includes a fifth plurality of conductors (216A and 217A) that combine a first voltage rail circuit board (202A) with a first capacitor circuit board (216) and a second capacitor circuit board (218). The multi-circuit board high-power VRM (200) further includes a sixth plurality of conductors (216B and 217B) that combine a second voltage rail circuit board (202B) with a first capacitor circuit board (216) and a second capacitor circuit board (216). The illustrated high-power VRM further includes a seventh plurality of conductors (220 and 222) that combine a first capacitor circuit board (216) with a second capacitor circuit board (218).

[0032] FIG. 3a is a block schematic diagram illustrating a first capacitor circuit board of the multi-circuit board high-power VRM of FIG. 2. The first capacitor circuit board (216) includes a third plurality of capacitors (302A, 304A, 302B, and 304B). Note that capacitors (302A and 304A) are located on the first side of the first capacitor circuit board (216), and capacitors (302B and 304B) are located on the second side of the first capacitor circuit board (216). A fifth plurality of conductors (216A and 217A) are coupled to connectors (308) of the first capacitor circuit board (216). Additionally, a sixth plurality of conductors (216B and 217B) are coupled to connectors (306) of the first capacitor circuit board (216). The seventh plurality of conductors (220 and 222) are coupled to the connectors (310) of the first capacitor circuit board (216).

[0033] FIG. 3b is a block schematic diagram illustrating a second capacitor circuit board of the multi-circuit board high-power VRM of FIG. 2. The second capacitor circuit board (218) includes a fourth plurality of capacitors (352A, 354A, 352B, and 354B). Note that the capacitors (352A and 354A) are located on the first side of the second capacitor circuit board (218), and the capacitors (352B and 354B) are located on the second side of the second capacitor circuit board (218). A fifth plurality of conductors (216A and 217A) are coupled to the connectors (356) of the second capacitor circuit board (218). Additionally, a sixth plurality of conductors (216B and 217B) are coupled to the connectors (354) of the second capacitor circuit board (218). The seventh plurality of conductors (220 and 222) are coupled to the connectors (358) of the second capacitor circuit board (218).

[0034] Referring to both FIG. 3a and FIG. 3b, the fifth plurality of conductors (216A and 217A) are coupled to the first outer portion (312) of the first capacitor circuit board (216) and the first outer portion (362) of the second capacitor circuit board (218). Additionally, the sixth plurality of conductors (216B and 217B) are coupled to the second outer portion (314) of the first capacitor circuit board (216) and the second outer portion (364) of the second capacitor circuit board (218). Furthermore, the seventh plurality of conductors (220 and 222) are coupled between the central portion (316) of the first capacitor circuit board (216) and the central portion (366) of the second capacitor circuit board (318).

[0035] Still referring to both FIG. 3a and FIG. 3b, the third plurality of capacitors (302A, 304A, 302B, and 304B) are configured to filter medium to low frequency components of the first rail voltage and the second rail voltage, and the fourth plurality of capacitors (352A and 352B) are configured to filter high frequency components of the first rail voltage and the second rail voltage.

[0036] In the embodiments of FIG. 2, 3a and / or 3b, the input voltage received by the first voltage rail circuit board (202A) and the second voltage rail circuit board (202B) may be a 40 voltage having a 0.8-volt signal used for communication with them.

[0037] FIG. 4 is a block schematic diagram illustrating cooling system components of a multi-circuit board high-power VRM according to the present disclosure. The difference between the embodiment (200) of FIG. 2 and the embodiment (400) of FIG. 4 is the inclusion of cooling system components. A first plurality of VRM elements (206A), a first plurality of inductors (208A), a second plurality of VRM elements (206B), and a second plurality of inductors (208B) generate significant heat during operation. Therefore, the multi-circuit board high-power VRM includes a cooling system for cooling these components. A cooling system source / sink (402) is coupled to a pipe (404) to service a flow of coolant to cool the VRM elements (206A / 206B) and inductors (208A / 208B). The pipe (404) may include many segments. The piping (404) can be directly coupled to the VRM elements (206A / 206B) and inductors (208A / 208B) or thermally coupled to them by intermediate structures. The cooling system source / sink (402) can service the multi-circuit board high-power VRMs as illustrated in FIG. 1.

[0038] FIG. 5 is a transparent perspective view of a capacitor array interconnected by conductive structures according to the present disclosure. The view in FIG. 5 is part of a larger capacitor array comprising capacitors (502) that extend in two dimensions, x and y from a plane. The capacitors (502) are essentially individual elements organized within the xy plane. Each capacitor (502) has a first side and a second side within the xy plane. The capacitors (502) may be surface mount technology (SMT) capacitors in certain applications. Also illustrated in FIG. 5 are conductive strips (504, 506, 508, 510, 512, 514, 516, and 518). Also illustrated are a first group of capacitors (520) and a second group of capacitors (522). Conductive strips (504 and 508) electrically connect the first sides of the first group of capacitors (520), and conductive strips (506 and 510) electrically connect the second sides of the first group of capacitors (520). Likewise, conductive strips (512 and 516) electrically connect the first sides of the second group of capacitors (522), and conductive strips (514 and 518) electrically connect the second sides of the second group of capacitors (522). In addition to providing electrical connections, the conductive strips (504 to 506) may hold capacitors (502) in a suitable location in an array format. In other embodiments, non-conductive strips may only provide to hold capacitors (502) in a suitable location prior to assembly with sandwich-type PCBs, and in this case, do not serve as electrical connection(s).

[0039] FIG. 6 is a partial side view of a portion of a stacked printed circuit board (PCB) capacitor array structure according to the present disclosure. The section of FIG. 6 illustrates a single capacitor (502) sandwiched between an upper PCB (600) and a lower PCB (606). The PCBs (606 and 600) may be referred to as the first PCB and the second PCB. The PCBs (606 and 600) may implement PCBs associated with VRM. For example, the PCBs (606 and 600) may be implemented instead of the capacitor circuit boards (216 and 218) of FIG. 2 in certain applications. The capacitor (502) has a first side (614) that is electrically coupled to the upper PCB (600) via a conductive strip (504) and electrically coupled to the lower PCB (606) via a conductive strip (508). The capacitor (502) has a second side (616) that is electrically coupled to the upper PCB (600) through a conductive strip (506) and electrically coupled to the lower PCB (606) through a conductive strip (510). The upper PCB (600) includes vias (604 and 605) that connect the first side (614) and the second side (616) of the capacitor (502) to a ball grid array (610) and / or other components. The lower PCB (606) includes vias (608 and 609) that connect the first side (614) and the second side (616) of the capacitor (502) to a ball grid array (612) and / or other components.

[0040] FIG. 7 is a plan view of an unassembled stacked PCB capacitor array structure according to the present disclosure. The stacked capacitor array structure includes a lower PCB (600), an upper PCB (606), and a capacitor array having a plurality of capacitors (502) located between the lower PCB (600) and the upper PCB (606) and electrically coupled to both the upper PCB (600) and the lower PCB (606) when the configuration is completed. The stacked PCB capacitor array structure includes a first plurality of solder connections electrically connecting the plurality of capacitors of the capacitor array to the upper PCB and a second plurality of solder connections electrically connecting the plurality of capacitors of the capacitor array to the lower PCB. Prior to assembly / configuration, the first plurality of solder connections are an array of first solder paste pads (602) and the second plurality of solder connections are an array of second solder paste pads (608).

[0041] FIG. 8a is a partial side view of a stacked PCB capacitor array structure configured according to the present disclosure. FIG. 8b is a top view of a stacked PCB capacitor array structure partially configured according to the present disclosure. Referring to both FIG. 8a and FIG. 8b, a plurality of capacitors (502) are electrically coupled to both the upper PCB (600) through a first plurality of solder connections (602) and the lower PCB (606) through a second plurality of solder connections (608). Ball grid arrays (610 and 612) provide electrical connection paths to the stacked PCB capacitor array. As illustrated in FIG. 8a, the first sides of the plurality of capacitors (502) are electrically coupled to both the upper PCB (600) and the lower PCB (606), while the second sides of the plurality of capacitors (502) are electrically coupled to both the upper PCB (600) and the lower PCB (606). Additionally, as illustrated in FIG. 8a, the inner surface of the upper PCB (606) is coupled to a plurality of capacitors (502) of the capacitor array, and the inner surface of the lower PCB (606) is coupled to a plurality of capacitors (502) of the capacitor array. In the structure of FIG. 8a and FIG. 8b, the capacitors (502) include a first group of capacitors coupled in series with each other and a second group of capacitors coupled in series with each other.

[0042] FIG. 9a is a partial side view of a lower PCB (606) having a first solder paste array formed thereon and comprising a plurality of first solder paste pads (608). In some embodiments, a double solder mask (or higher-order solder mask) may be used to compensate for different thicknesses of the capacitors in the capacitor array. As is understood, the capacitor array has a large number of capacitors, and in some embodiments, will have capacitors of different sizes and values. Accordingly, if different capacitors of the capacitor array have different thicknesses, different thicknesses of the solder paste pads (608) may be utilized. The same structure may be used for the upper PCB (600), but may have differences to reflect different configurations of the capacitor array from the upper side.

[0043] FIG. 9b is a partial side view of the lower PCB of FIG. 9a while mounting capacitors thereon according to the present disclosure. A robot can be used to place the capacitors (502) of the capacitor array on the first solder paste array using XYZ positioning and vision. At this point, during configuration, the capacitors (502) are resting on the first solder paste array but are not fused thereto. Therefore, there must be sufficient friction between the solder paste pads (608) and the capacitors (502) to prevent relative motion between the solder paste pads (608) and the capacitors (502) during configuration.

[0044] FIG. 10a is a flowchart illustrating a first embodiment of a stacked PCB capacitor array structure according to the present disclosure. FIG. 10b and FIG. 10c are partial side views of a stacked PCB capacitor array structure while configuring a configuration consistent with FIG. 10a. Referring together to FIG. 10a, 10b and 10c, a method (1000) for configuring a stacked PCB capacitor array comprises the step of applying a first solder paste array having a plurality of first solder paste pads (608) to the inner surface of a lower PCB (606) (step (1002)). The method (1000) follows the step of applying a second solder paste array having a plurality of second solder paste pads to the inner surface of an upper PCB (600) (step (1004)). The method (1000) leads to the step of placing a plurality of capacitors (502) of a capacitor array on a first solder paste array of a lower PCB (606), and the pattern of the first solder paste array corresponds to the capacitor array (step (1006)). The method (1000) leads to the step of placing the upper PCB (600) on a capacitor array such that a second solder paste array of the upper PCB (600) is aligned with the plurality of capacitors of the capacitor array (step (1010)). The method (1000) leads to the step of applying heat to convert the first solder paste array and the second solder paste array into solid conductors (1014 and 1016), individually (step (1012)). An induction press reflow process or laser welding may be used to convert a first solder paste array on the upper PCB (600) into solid conductors to combine a capacitor array on the upper PCB (600) and to convert a second solder paste on the lower PCB (606) into solid conductors to combine a capacitor array on the lower PCB (606).

[0045] FIG. 11a is a flowchart illustrating a second embodiment of a stacked PCB capacitor array structure according to the present disclosure. FIG. 11b, FIG. 11c, and FIG. 11d are partial side views of a stacked PCB capacitor array structure while configuring a configuration consistent with FIG. 11a. Referring to all of FIG. 11a, FIG. 11b, FIG. 11c, and FIG. 11d, a method (1100) for configuring a stacked PCB capacitor array comprises the step of applying a first solder paste array having a plurality of first solder paste pads (608) to the inner surface of a lower PCB (606) (step (1102)). The method (1100) follows the step of applying a second solder paste array having a plurality of second solder paste pads to the inner surface of an upper PCB (600) (step (1104)). Method (1100) leads to the step of placing a plurality of capacitors (502) of a capacitor array on a first solder paste array of a lower PCB (606), and the pattern of the first solder paste array corresponds to the capacitor array (step (1006)). Method (1100) leads to the step of applying heat to convert the first solder paste array into solid conductors (1114) (step 1008). Method (1100) leads to the step of placing the upper PCB (600) on a capacitor array such that a second solder paste array of the upper PCB (600) is aligned with a plurality of capacitors of the capacitor array (step (1010)). Method (1100) leads to the step of applying heat to convert the second solder paste array into solid conductors (1116) (step (1012)). An induction press reflow process or laser welding can be used to convert solder paste onto the lower PCB (606) into solid conductors to bond a capacitor array to the lower PCB (606) and to convert solder paste onto the upper PCB (600) into solid conductors to bond a capacitor array to the upper PCB (600).Note that the solid conductors (1114) underwent two reflow processes in step (1012).

[0046] While the descriptions and drawings herein may relate to components located between the upper and lower PCBs, such components may be different (passive and / or active) components. For example, the components may be an array of individual inductors, or an array of both individual inductors and individual capacitors. Additionally, these components may be packaged components, for example, a package containing multiple capacitors, multiple inductors, a combination of capacitors and inductors, a combination of capacitors, inductors, and resistors, etc. In some applications, the electronic components may include active components, such as integrated circuit chips. Such integrated circuit chips may include transistors. Any suitable electronic components may be located between the PCBs according to any suitable principles and advantages disclosed herein. For example, any suitable combination of features discussed with reference to FIGS. 5 through 11d may be implemented in relation to any suitable electronic components instead of individual capacitors. Although the embodiments disclosed herein may relate to capacitors located between two PCBs, any suitable principles and advantages disclosed herein may be applied to arrays of electronic components located between various groups of two PCBs from a stack of three or more PCBs.

[0047] The above systems and methods have been described in general terms to aid in understanding the details of the preferred embodiments of the disclosure. Other preferred embodiments of the disclosure include applications for the described electric vehicles. In the description herein, many details, such as examples of parts and / or methods, are provided to provide a complete understanding of the embodiments disclosed herein. However, those skilled in the art will recognize that the embodiments may be implemented without one or more specific details, or with other devices, systems, assemblies, methods, parts, materials, parts, and / or the like. In other cases, well-known structures, materials, or operations are not specifically illustrated or described in detail to avoid obscuring aspects of the embodiments disclosed herein.

[0048] References throughout this specification to “one embodiment,” “an embodiment,” or “a specific embodiment” mean that a specific feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure and is not necessarily present in all embodiments. Accordingly, each appearance of the phrases “in one embodiment,” “in an embodiment,” or “in a specific embodiment” at various locations throughout this specification does not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics of any specific embodiment of this disclosure may be combined with one or more other embodiments in any suitable manner. It should be understood that other variations and modifications of the embodiments of this disclosure described and illustrated herein are possible in light of the teachings herein and should be considered part of the spirit and scope of this disclosure.

[0049] It will also be understood that one or more components depicted in the drawings / figures may be implemented in a more separated or integrated manner as useful for a particular application, or removed or rendered as if they do not work in specific cases.

[0050] Additionally, any signal arrows in the drawings / figure should be regarded merely as exemplary and not limiting, unless otherwise specifically stated. Furthermore, as used herein, the term "or" is generally intended to mean "and / or" unless otherwise indicated. Where terminology is foreseen as rendering the ability to separate or combine, combinations of parts or steps will also be considered as referred to.

[0051] As used herein in the description and throughout the following claims, "a," "an," and "the" include plural references unless the context clearly indicates otherwise. Also, as used herein in the description and throughout the following claims, the meaning of "in" includes "in" and "on" unless the context clearly indicates otherwise.

[0052] The foregoing description of the exemplified embodiments of the present disclosure, including those described in the summary, is not intended to be complete without limiting or omitting any of the inventions to the exact forms disclosed herein. Specific embodiments of the innovations and examples of the innovations are described herein merely for illustrative purposes, but various equivalent modifications are possible within the spirit and scope of the present disclosure as will be recognized and understood by those skilled in the art. As indicated, such modifications may be made to the embodiments disclosed in light of the foregoing description of the exemplified embodiments and may be included within the spirit and scope of the present disclosure.

[0053] Accordingly, although the present disclosure has been described herein with reference to specific embodiments, the scope of modifications, various changes, and substitutions are intended for the foregoing disclosure, and it will be understood that in some cases, some features of the embodiments may be used without departing from the scope and spirit of the disclosure and without the corresponding use of other features as described. Therefore, many modifications may be made to adapt specific situations or materials to the essential scope and spirit of the present disclosure. Although the disclosure is not limited to specific terms used within the following claims and / or specific embodiments disclosed as the best mode considered for carrying out the inventions, the inventions are intended to include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the inventions is to be determined by the appended claims.

Claims

Claim 1 A stacked printed circuit board (PCB) electronic component array structure comprising: a first PCB; a second PCB; an electronic component array including a plurality of electronic components positioned between the first PCB and the second PCB, wherein the plurality of electronic components are electrically connected to the first PCB through first solder connections and electrically connected to the second PCB through second solder connections, wherein one of the first solder connections electrically connects a group of electronic components among the plurality of electronic components to the first PCB, and one of the second solder connections electrically connects a group of electronic components among the plurality of electronic components to the second PCB. Claim 2 A stacked PCB electronic component array structure according to claim 1, wherein the first sides of the plurality of electronic components are electrically coupled to both the first PCB and the second PCB; and the second sides of the plurality of electronic components are electrically coupled to both the first PCB and the second PCB. Claim 3 In paragraph 2, the inner surface of the first PCB is coupled to the plurality of electronic components of the array of electronic components; and the inner surface of the first PCB is coupled to the plurality of electronic components of the array of electronic components, a stacked PCB electronic component array structure. Claim 4 A stacked PCB electronic component array structure according to claim 2, further comprising: a first ball grid array disposed on the outer surface of the first PCB; - the plurality of electronic components are electrically coupled to the first ball grid array through first vias within the first PCB; and a second ball grid array disposed on the outer surface of the second PCB; - the plurality of electronic components are electrically coupled to the second first ball grid array through second vias within the second PCB. Claim 5 In claim 1, the plurality of electronic components comprises a plurality of discrete passive elements, forming a stacked PCB electronic component array structure. Claim 6 In claim 5, the plurality of individual passive elements comprises a first group of individual passive elements electrically connected in series and a second group of individual passive elements electrically connected in parallel, forming a stacked PCB electronic component array structure. Claim 7 In claim 1, the plurality of electronic components comprises a plurality of capacitors, forming a stacked PCB electronic component array structure. Claim 8 In claim 1, the plurality of electronic components comprises a plurality of active components, forming a stacked PCB electronic component array structure. Claim 9 A method for assembling a stacked printed circuit board (PCB) electronic component array comprises: providing a first PCB having a first solder paste array thereon; positioning a plurality of electronic components of an electronic component array associated with the first PCB; positioning a second PCB associated with the plurality of electronic components such that a second solder paste array is aligned with the plurality of electronic components on the second PCB, wherein the first solder paste array on the first PCB corresponds to the electronic component array; and applying heat to convert the second solder paste array into a second solid conductor electrically connected to the plurality of electronic components. - The electronic components are electrically connected to first solid conductors on the first PCB and second solid conductors on the second PCB after the step of applying heat to convert the second solder paste array, wherein one of the first solid conductors electrically connects a group of electronic components among the plurality of electronic components to the first PCB, and one of the second solid conductors electrically connects a group of electronic components among the plurality of electronic components to the second PCB. Claim 10 A method according to claim 9, further comprising the step of applying the first solder paste array on the surface of the first PCB prior to the step of providing the first PCB. Claim 11 In claim 9, the step of applying heat to convert the second solder paste array into the second solid conductors also converts the first solder paste array into the first solid conductors, a method. Claim 12 A method according to claim 9, further comprising the step of applying heat to convert the first solder paste array into the first solid conductors prior to the step of positioning the second PCB. Claim 13 In claim 9, the step of applying heat to convert the second solder paste array into the second solid conductors comprises an induction press reflow process. Claim 14 In claim 9, the step of applying heat to convert the second solder paste array into the second solid conductors comprises a laser welding process. Claim 15 In claim 9, the method wherein the plurality of electronic components include individual passive components. Claim 16 In claim 9, the method wherein the plurality of electronic components include a plurality of capacitors. Claim 17 In claim 9, the method electrically connects a first group of the plurality of electronic components in series with each other. Claim 18 In paragraph 17, the method electrically connects a group of second electronic components of the plurality of electronic components in parallel with each other. Claim 19 In claim 9, the method electrically connects the first sides of the plurality of electronic components to both the first PCB and the second PCB. Claim 20 In claim 19, the method electrically connects the second sides of the plurality of electronic components to both the first PCB and the second PCB.

Images