Semiconductor devices and method of manufacturing the same

Abstract

A method for manufacturing a semiconductor device according to an embodiment of the present invention comprises the steps of: forming a stacked structure by alternately stacking gate layers and interlayer insulating layers on a substrate; and forming a channel structure that penetrates the stacked structure in a vertical direction, wherein the step of forming the channel structure comprises the steps of: etching the stacked structure to form an opening; forming a gate insulating layer that covers at least the side of the opening; forming a variable resistance material layer that contacts the gate insulating layer; performing a plasma treatment or annealing process on the variable resistance material layer to change the oxygen vacancy concentration in a portion of the variable resistance material layer; forming a core insulating pattern that covers the variable resistance material layer and fills at least a portion of the opening after performing the plasma treatment or the annealing process; and forming a pad pattern on the core insulating pattern.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a semiconductor device. Background Technology

[0003] In data storage systems that require data storage, there is a demand for semiconductor devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. The problem to be solved

[0005] One of the technical problems that the present invention aims to solve is to provide a method for manufacturing a semiconductor device with improved electrical characteristics and a simplified manufacturing process.

[0006] One of the technical problems that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and a simplified manufacturing process, and a data storage system including the same. means of solving the problem

[0008] A method for manufacturing a semiconductor device according to exemplary embodiments comprises the steps of: forming a stacked structure by alternately stacking gate layers and interlayer insulating layers on a substrate; and forming a channel structure that penetrates the stacked structure in a vertical direction, wherein the step of forming the channel structure may include: etching the stacked structure to form an opening; forming a gate insulating layer covering at least a side of the opening; forming a variable resistance material layer in contact with the gate insulating layer; performing a plasma treatment or annealing process on the variable resistance material layer to change the oxygen vacancy concentration in a portion of the variable resistance material layer; forming a core insulating pattern covering the variable resistance material layer and filling at least a portion of the opening after performing the plasma treatment or annealing process; and forming a pad pattern on the core insulating pattern.

[0009] A method for manufacturing a semiconductor device according to exemplary embodiments comprises the steps of: forming a stacked structure by alternately stacking gate layers and interlayer insulating layers on a substrate; and forming a channel structure that penetrates the stacked structure in a vertical direction, wherein the step of forming the channel structure may include: etching the stacked structure to form an opening; forming a gate insulating layer covering at least the side of the opening; forming a variable resistance material layer in contact with the gate insulating layer and comprising a first region and a second region; increasing or decreasing the oxygen vacancy concentration of either the first region and the second region; forming a core insulating pattern that fills at least a portion of the opening; and forming a pad pattern on the core insulating pattern.

[0010] A method for manufacturing a semiconductor device according to exemplary embodiments comprises the steps of: forming a stacked structure by alternately stacking gate layers and interlayer insulating layers on a substrate; and forming a channel structure penetrating the stacked structure in a vertical direction, wherein the step of forming the channel structure comprises: etching the stacked structure to form an opening; forming a gate insulating layer within the opening; forming a variable resistance material capping layer that fills the opening and contacts the gate insulating layer; etching a central region of the variable resistance material capping layer to remove the remaining portion while leaving a variable resistance material layer extending along the side of the gate insulating layer and having a predetermined thickness from the side of the gate insulating layer; performing a plasma treatment or annealing process on the remaining variable resistance material layer to change the oxygen vacancy concentration in a portion of the variable resistance material layer; and, after performing the plasma treatment or annealing process, forming a core insulating pattern that covers the variable resistance material layer and fills at least a portion of the opening. and may include the step of forming a pad pattern on the core insulation pattern.

[0011] A semiconductor device according to exemplary embodiments comprises: a substrate; gate electrodes stacked on the substrate spaced apart from each other in a vertical direction; and a channel structure disposed within an opening penetrating the gate electrodes in the vertical direction, wherein the channel structure comprises a core insulating pattern spaced apart from the side of the opening, a gate insulating layer in contact with the gate electrodes at the side of the opening, and a variable resistance material layer between the gate insulating layer and the core insulating pattern, wherein the variable resistance material layer comprises a channel region having a first concentration of oxygen vacancies and an information storage region having a second concentration of oxygen vacancies smaller than the first concentration, wherein the channel region is in contact with the gate insulating layer and extends along the side of the gate insulating layer, and the information storage region is in contact with the core insulating pattern and extends along the side of the core insulating pattern.

[0012] A data storage system according to exemplary embodiments comprises: a lower substrate, a lower structure including circuit elements on the lower substrate, and an upper structure on the lower structure; a semiconductor storage device including an input / output pad electrically connected to the circuit elements; and a controller electrically connected to the semiconductor storage device through the input / output pad and controlling the semiconductor storage device, wherein the upper structure comprises: an upper substrate; and gate electrodes stacked on the upper substrate spaced apart from each other in a vertical direction. The apparatus includes a channel structure disposed within an opening penetrating the gate electrodes in the vertical direction, wherein the channel structure comprises a core insulating pattern spaced apart from the side of the opening, a gate insulating layer in contact with the gate electrodes at the side of the opening, and a variable resistance material layer between the gate insulating layer and the core insulating pattern, wherein the variable resistance material layer comprises a channel region having oxygen vacancies at a first concentration and an information storage region having oxygen vacancies at a second concentration smaller than the first concentration, wherein the channel region is in contact with the gate insulating layer and extends along the side of the gate insulating layer, and the information storage region is in contact with the core insulating pattern and extends along the side of the core insulating pattern. Effects of the invention

[0014] A method for manufacturing a semiconductor device with improved electrical characteristics and a simplified manufacturing process can be provided by including a variable resistive material layer that comprises a channel region with a high oxygen vacancy concentration and an information storage region with a low oxygen vacancy concentration.

[0015] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0017] FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 3 is a magnified partial view of a portion of a semiconductor device according to exemplary embodiments. FIGS. 4a to 4d are graphs showing the oxygen vacancy concentration in a variable resistance material layer of a semiconductor device according to exemplary embodiments. FIG. 5a is a magnified partial view of a portion of a semiconductor device according to exemplary embodiments. FIG. 5b is a graph showing the oxygen vacancy concentration in a variable resistance material layer of a semiconductor device according to exemplary embodiments. FIGS. 6a and 6b are magnified partial views of a portion of a semiconductor device according to exemplary embodiments. FIGS. 7 to 9 are schematic cross-sectional views of semiconductor devices according to exemplary embodiments. FIGS. 10a to 11b are flowcharts for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. FIGS. 12 to 23 are schematic drawings for explaining a method of manufacturing a semiconductor device according to exemplary embodiments. FIG. 24 is a schematic diagram illustrating a data storage system including a semiconductor device according to exemplary embodiments. FIG. 25 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment. FIG. 26 is a cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment. Specific details for implementing the invention

[0018] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0020] FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments.

[0021] FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 2 shows a cross-section along the cutting line I-I' of FIG. 1.

[0022] FIG. 3 is a magnified partial view of a portion of a semiconductor device according to exemplary embodiments. FIG. 3 illustrates an enlarged view of region 'A' of FIG. 2.

[0024] Referring to FIGS. 1 to 3, a semiconductor device (100) may include a first structure (1) comprising a lower substrate (10) and a second structure (2) comprising an upper substrate (101). The second structure (2) may be disposed on the first structure (1). The first structure (1) is an area where a peripheral circuit area of ​​the semiconductor device (100) is disposed, and the peripheral circuit area may include a row decoder, a page buffer, and other peripheral circuits. The second structure (2) is an area where memory cells of the semiconductor device (100) are disposed, and may include gate electrodes (130) and channel structures (CH), etc.

[0026] The first structure (1) may include a lower substrate (10), element isolation layers (15s) defining an active region (15a) on the lower substrate (10), circuit elements (20) disposed on the substrate (10), a lower wiring structure (30) electrically connected to the circuit elements (20), and a lower insulating layer (40).

[0028] The lower substrate (10) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The lower substrate (10) may be provided as a bulk wafer or an epitaxial layer. The lower substrate (10) may be placed below the upper substrate (101). Device isolation layers (15s) are disposed within the lower substrate (10), and source / drain regions (22) containing impurities may be disposed in a part of the active region (15a).

[0029] The circuit elements (20) may each include a transistor comprising a source / drain region (22), a circuit gate dielectric layer (24), and a circuit gate electrode (26). The source / drain regions (22) may be placed on both sides of the circuit gate electrode (25) in the active region (15a). The circuit gate dielectric layer (24) may be placed between the active region (15a) and the circuit gate electrode (26). A spacer layer (28) may be placed on both sides of the circuit gate electrode (26). The circuit gate electrode (26) may include a material layer such as, for example, tungsten (W), titanium (Ti), tantalum (Ta), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), polysilicon, or a metal-semiconductor compound.

[0030] The lower wiring structure (30) may be electrically connected to the circuit elements (20). The lower wiring structure (30) may include lower contacts (32) and lower wiring (34). Some of the lower contacts (32) may extend in the Z direction and be connected to source / drain regions (22). The lower contacts (32) may electrically connect the lower wiring (34) placed at different levels to each other. The lower wiring structure (30) may include a conductive material, such as a metallic material such as tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), cobalt (Co), molybdenum (Mo), and ruthenium (Ru). A barrier layer made of a material such as tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), etc. may be disposed on the bottom surface and sides of the lower wiring structure (30). The number of layers and arrangement of the lower contact (32) and lower wiring (34) constituting the lower wiring structure (30) can be varied. At least some of the lower wiring (34) may include a pad layer to which a plurality of through-contact plugs extending downward from the second structure (2) are directly connected. The plurality of through-contact plugs may be arranged to pass through a separate through-region formed in the laminated structure (ST) of the second structure (2).

[0031] The lower insulating layer (40) may be disposed to cover the lower substrate (10), circuit elements (20), and lower wiring structure (30). The lower insulating layer (40) may be made of an insulating material such as silicon oxide or silicon nitride. The lower insulating layer (40) may be made of a plurality of insulating layers. The lower insulating layer (40) may include an etch stop layer formed of silicon nitride.

[0033] The second structure (2) may include an upper substrate (101) on the first structure (1), a stacked structure (ST) including gate electrodes (130) spaced apart and stacked on the upper substrate (101), first separation patterns (MS) penetrating the stacked structure (ST) and separating the gate electrodes (130), channel structures (CH) penetrating the stacked structure (ST), a second separation pattern (SS) separating the upper gate electrode (130U) among the gate electrodes (130) between the first separation patterns (MS), and bit lines (180) disposed on the stacked structure (ST). The second structure (2) may further include interlayer insulating layers (120) that are alternately stacked with the gate electrodes (130) and form part of the stacked structure (ST), contact plugs (170) between the channel structures (CH) and the bit lines (180), and upper insulating layers (191, 192).

[0035] The upper substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The upper substrate (101) may include a polysilicon layer having an N-type or P-type conductivity type, for example. The upper substrate (101) may include an impurity region in contact with a channel structure (CH).

[0037] Gate electrodes (130) may be stacked spaced apart in the Z direction on an upper substrate (101) and may form part of a stacked structure (ST). Gate electrodes (130) may extend in the X direction. The gate electrodes (130) may include a lower gate electrode (130L) forming the gate of a ground select transistor, memory gate electrodes (130M) forming a plurality of memory cells, and an upper gate electrode (130U) forming the gate of string select transistors. The number of memory gate electrodes (130M) forming the memory cells may be determined according to the capacity of the semiconductor device (100). According to embodiments, the gate electrodes (130U, 130L) forming the string select transistor and the ground select transistor may each be one or two or more.

[0038] Gate electrodes (130) are stacked vertically spaced apart on the upper substrate (101) and, although not illustrated, may extend to different lengths in the Y direction to form a stepped structure. Due to the stepped structure, the gate electrodes (130) may have pad regions that are exposed upwards, with the lower gate electrode (130) extending longer than the upper gate electrode (130), and gate contact plugs may be disposed on the pad regions to be connected to the gate electrodes (130). The gate contact plugs may be electrically connected to the circuit elements (20) of the first structure (1) through a through-contact plug that passes through a separate through-region disposed in the stacked structure (ST).

[0039] Gate electrodes (130) may be separated from each other in the Y direction by first separation patterns (MS) extending in the X direction. Gate electrodes (130) between a pair of first separation patterns (MS) may form a single memory block, but the scope of the memory block is not limited thereto. Each gate electrode (130) may include a first layer and a second layer. The first layer may cover the upper and lower surfaces of the second layer and may extend between the channel structures (CH) and the second layer. The first layer may include a high dielectric material such as aluminum oxide (AlO), and the second layer may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN). According to an embodiment, the gate electrodes (130) may include polysilicon or a metal-semiconductor compound.

[0041] Interlayer insulating layers (120) can be placed between gate electrodes (130) and can form a stacked structure (ST). The interlayer insulating layers (120) can also be placed such that they are spaced apart from each other in the Z direction and extend in the X direction, just like the gate electrodes (130). The interlayer insulating layers (120) may include an insulating material such as silicon oxide. Some of the interlayer insulating layers (120) may have different thicknesses. For example, the top interlayer insulating layer (120) may have a thicker thickness than the other interlayer insulating layers (120).

[0043] The first separation patterns (MS) may be arranged to penetrate the gate electrodes (130) of the stacked structure (ST) in the Z direction and extend along the X direction. Adjacent first separation patterns (MS) in the Y direction may be arranged parallel to each other. The first separation patterns (MS) may penetrate the entire gate electrodes (130) of the stacked structure (ST) in the Z direction and come into contact with the upper substrate (101). The first separation patterns (MS) may be formed of an insulating material, for example, silicon oxide. According to embodiments, each of the first separation patterns (MS) may include a core pattern that includes a conductive material and comes into contact with the upper substrate (101), and a separation insulating pattern that covers the side of the core pattern and includes an insulating material.

[0045] Channel structures (CH) can be spaced apart from each other to form rows and columns, each forming a single memory cell string as illustrated in FIG. 1. Channel structures (CH) can be arranged to form a grid pattern between the first separation patterns (MS) or arranged in a zigzag shape in one direction. Channel structures (CH) can be placed within an opening (OP) that penetrates the stacked structure (ST) in the Z direction. Channel structures (CH) have a columnar shape and can have inclined sides that become narrower as they approach the upper substrate (101) according to the aspect ratio.

[0046] Each of the channel structures (CH) may include a gate insulation layer (141), a variable resistive material layer (142), a core insulation pattern (145), and a pad pattern (149). The variable resistive material layer (142) may be formed annularly to cover or surround the outer surface of the core insulation pattern (145). The gate insulation layer (141) may be formed annularly to cover or surround the outer surface of the variable resistive material layer (142). The gate insulation layer (141), the variable resistive material layer (142), and the core insulation pattern (145) may be arranged sequentially from the side of the gate electrodes (130). For example, the gate insulating layer (141) may be in contact with the gate electrodes (130) on the side of the opening (OP), the core insulating pattern (145) may be spaced apart from the side of the opening (OP), and the variable resistance material layer (142) may be placed between the gate insulating layer (141) and the core insulating pattern (145).

[0047] A gate insulating layer (141) may be disposed between the gate electrodes (130) and the variable resistance material layer (142). The gate insulating layer (141) may extend along the side of the opening (OP). The gate insulating layer (141) may extend from a level lower than the lower gate electrode (130L) to a level higher than the upper gate electrode (130U). The upper surface of the gate insulating layer (141) may be substantially co-planar with the upper surface of the pad pattern (149). The gate insulating layer (141) may be formed of silicon oxide or nitrogen-doped silicon oxide.

[0048] The variable resistance material layer (142) covers the side and bottom surfaces of the core insulation pattern (145) and may be in contact with the upper substrate (101). The variable resistance material layer (142) is formed as a single layer comprising a transition metal oxide and may include regions with different concentrations of oxygen vacancies. For example, the variable resistance material layer (142) may include a first region (142a) having a first concentration of oxygen vacancies (corresponding to the 'channel region' of the memory cell transistor, referred to as the 'channel region' below) and a second region (142b) having a second concentration of oxygen vacancies different from the first concentration (corresponding to the 'information storage region' of the memory cell transistor, referred to as the 'information storage region' below). The second concentration may be less than the first concentration.

[0049] The concentration of oxygen vacancies in the channel region (142a) of the variable resistance material layer (142) may be greater than the concentration of oxygen vacancies in the information storage region (142b) of the variable resistance material layer (142). The channel region (142a) may be in contact with the gate insulation layer (141), and the information storage region (142b) may be in contact with the core insulation pattern (145). In the drawing, the line between the channel region (142a) and the information storage region (142b) is shown for convenience of explanation, but there may not be an interface between the channel region (142a) and the information storage region (142b). Since the channel region (142a) and the information storage region (142b) are regions formed of the same material, the resistance between them may be relatively smaller than the contact resistance caused by the interface formed between them when they are each formed of different materials.

[0050] The channel region (142a) of the variable resistance material layer (142) may be in contact with the upper substrate (101) from below. As the channel region (142a) of the variable resistance material layer (142) corresponds to the channel region of the memory cell transistor as described above, a separate channel layer is not placed between the variable resistance material layer (142) and the gate insulation layer (141). For example, the variable resistance material layer (142) may be in contact with the gate insulation layer (141) without the interposition of a polysilicon film between the variable resistance material layer (142) and the gate insulation layer (141). Alternatively, the channel region (142a) of the variable resistance material layer (142) may not contain polysilicon. The channel region (142a) of the variable resistance material layer (142) may be a region where a portion of the variable resistance material layer (142) has been treated with plasma treatment or annealing to increase the oxygen vacancy concentration. The annealing process may be a thermal annealing or a laser annealing process. Since the electrical properties of a portion of the variable resistance material layer (142) can be changed by post-processing so that it can be used as a channel region (142a) of a memory cell transistor, the process step of forming a separate channel layer containing a material different from the variable resistance material layer (142) may be omitted.

[0051] The information storage area (142b) of the variable resistance material layer (142) may be an area where a portion of the variable resistance material layer (142) has been treated with plasma or annealed to reduce the oxygen vacancy concentration.

[0052] The information storage region (142b) of the variable resistance material layer (142) may have different resistances depending on the set state and reset state during operation of the semiconductor device (100). For example, among the word lines (WL), the selected word line (WLa) may be turned OFF, and the unselected word lines (WLb1, WL1b2) may be turned ON. In this case, the current indicated by the reference numeral CP in FIG. 3 may flow sequentially along the channel region (141a) facing the first unselected word line (WLb1) located above the selected word line (WLa), the information storage region (142b) facing the selected word line (WLa), and the channel region (142a) facing the second unselected word line (WLb2) located below the selected word line (WLa). In FIG. 3, the dashed line indicated by the reference numeral CP may represent the current flow during program operation. For example, the current flow (CP) during program operation may flow along the channel area (142a) facing the first non-selected word line (WLb1), shift to the information storage area (142b) facing the selected word line (WLa), and then shift again to the channel area (142a) facing the second non-selected word line (WLb2) and flow along the channel area (142a). As current flows along the information storage area (142b) facing the selected word line (WLa), the resistance of the information storage area (142b) changes, and a part of the information storage area (142b) facing the selected word line (WLa) may become set. Due to this program operation, a portion of the information storage area (142b) facing the selected word line (WLa) may have its resistance locally lowered.

[0053] The erase operation, similar to the program operation described above, turns off the selected word line (WLa) and turns off the unselected word lines (WLb1, WLb2), but changes the magnetic field by causing current to flow in the opposite direction to the current flow during the program operation described above, thereby changing a part of the information storage area (142b) facing the selected word line (WLa) to a reset state. Due to the erase operation, the resistance of a part of the information storage area (142b) facing the selected word line (WLa) may increase locally.

[0054] For example, the variable resistance material layer (142) may include at least one of hafnium oxide (HfO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO), tin oxide (SnO), copper oxide (CuO), molybdenum oxide (MoO), hafnium-silicon oxide (HSO), hafnium-zinc oxide (HZO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), and indium-tin-zinc oxide (ITZO).

[0055] The core insulation pattern (145) may have a cylindrical shape extending in the vertical direction (Z). The core insulation pattern (145) may be placed in an area including the center of the channel structure (CH). The upper surface of the core insulation pattern (145) may be in contact with the pad pattern (149). The core insulation pattern (145) may be formed from at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0056] The pad pattern (149) is placed on the core insulation pattern (145) and can come into contact with the upper portion of the variable resistance material layer (142). The pad pattern (149) can electrically connect the variable resistance material layer (142) to the bit lines (180). The pad pattern (149) can be formed of doft polysilicon, for example, doft polysilicon having an N-type conductivity type.

[0058] The second separation pattern (SS) may extend in the X direction between the first separation patterns (MS). The second separation pattern (SS) may penetrate the upper gate electrode (130U) among the gate electrodes (130) in the Z direction and separate them from each other in the Y direction. However, the number of upper gate electrodes (130U) separated by the second separation pattern (SS) may vary in the embodiments. The upper gate electrodes (130U) separated by the second separation pattern (SS) may form different string selection lines. The second separation pattern (SS) may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0060] Contact plugs (170) may be placed between channel structures (CH) and bit lines (180). Contact plugs (170) may be connected to pad patterns (149). Contact plugs (170) may be connected to bit lines (180). Contact plugs (170) may penetrate in the Z direction at least one of the upper insulating layers (191, 192), for example, the first upper insulating layer (191) and the second upper insulating layer (192). According to embodiments, a plurality of studs connected to the contact plugs (170) may be further placed between one channel structure (CH) and one bit line (180).

[0061] The contact plugs (170) may include a conductive pattern and a barrier layer covering the side and bottom surfaces of the conductive pattern. The barrier layer may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The conductive pattern may include a metallic material, for example, at least one of tungsten (W), titanium (Ti), copper (Cu), cobalt (Co), aluminum (Al), and alloys thereof. According to embodiments, the contact plugs (170) may be formed with a plurality of plug structures.

[0063] Bitlines (180) can be extended in the Y direction on the stacked structure (ST) and channel structures (CH). Bitlines (180) can be electrically connected to circuit elements (20) of the first structure (1) through separate through-contact plugs. Bitlines (180) can be electrically connected to a variable resistance material layer (141).

[0064] Bitlines (180) may include a conductive pattern and a barrier layer covering the side and bottom surfaces of the conductive pattern. The barrier layer may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The conductive pattern may include a metallic material, for example, at least one of tungsten (W), titanium (Ti), copper (Cu), cobalt (Co), aluminum (Al), and alloys thereof.

[0066] Upper insulating layers (191, 192) may be disposed on a laminated structure (ST). The upper insulating layers (191, 192) may include a first upper insulating layer (191) and a second upper insulating layer (192) that are stacked sequentially on the laminated structure (ST). The upper insulating layers (191, 192) may be made of an insulating material such as silicon oxide.

[0068] FIGS. 4a to 4d are graphs showing the oxygen vacancy concentration in a variable resistance material layer of a semiconductor device according to exemplary embodiments.

[0069] Referring to FIG. 4a, the variable resistance material layer (142) may have an oxygen vacancy concentration that changes in a step structure. That is, the oxygen vacancy concentration in the width direction of the variable resistance material layer (142) may decrease in a step profile in the direction from the gate insulation layer (141) toward the core insulation pattern (145). For example, the channel region (142a) of the variable resistance material layer (142) may have oxygen vacancy at a first concentration (C1), and the information storage region (142b) of the variable resistance material layer (142) may have oxygen vacancy at a second concentration (C2) that is smaller than the first concentration (C1). The first concentration (C1) may be a constant concentration depending on the thickness change of the channel region (142a), and the second concentration (C2) may be a constant concentration depending on the thickness change of the information storage region (142b).

[0070] Referring to FIGS. 4b and 4c, the variable resistance material layer (142) may have a gradually changing oxygen vacancy concentration, and the oxygen vacancy concentration in the information storage region (142b) of the variable resistance material layer (142) may be smaller than the oxygen vacancy concentration in the channel region (142a) of the variable resistance material layer (142).

[0071] Referring to FIG. 4b, for example, the oxygen vacancy concentration in the channel region (142a) of the variable resistor material layer (142) may increase as it gets closer to the gate insulation layer (141), and the oxygen vacancy concentration in the information storage region (142b) may decrease as it gets closer to the core insulation pattern (145). For example, within the channel region (142a), the oxygen vacancy concentration in the portion of the channel region (142a) adjacent to the gate insulation layer (141) may be greater than the oxygen vacancy concentration in the portion of the channel region (142a) adjacent to the information storage region (142b). For example, within the information storage region (142b), the oxygen vacancy concentration in the portion of the information storage region (142b) adjacent to the channel region (142a) may be greater than the oxygen vacancy concentration in the portion of the information storage region (142b) adjacent to the core insulation pattern (145).

[0072] Referring to FIG. 4c, for example, the oxygen vacancy concentration in the channel region (142a) of the variable resistor material layer (142) may decrease as it gets closer to the gate insulation layer (141), and the oxygen vacancy concentration in the information storage region (142b) may increase as it gets closer to the core insulation pattern (145). For example, within the channel region (142a), the oxygen vacancy concentration in the portion of the channel region (142a) adjacent to the gate insulation layer (141) may be greater than the oxygen vacancy concentration in the portion of the channel region (142a) adjacent to the information storage region (142b). For example, within the information storage region (142b), the oxygen vacancy concentration in the portion of the information storage region (142b) adjacent to the channel region (142a) may be smaller than the oxygen vacancy concentration in the portion of the information storage region (142b) adjacent to the core insulation pattern (145).

[0073] Referring to FIG. 4d, the variable resistance material layer (142) may have an oxygen vacancy concentration that changes at a constant rate. For example, within the variable resistance material layer (142), the oxygen vacancy concentration may gradually decrease from the channel region (142a) to the information storage region (142b). Thus, the information storage region (142b) may have a lower oxygen vacancy concentration than the channel region (142a).

[0075] FIG. 5a is a magnified partial view of a portion of a semiconductor device according to exemplary embodiments.

[0076] FIG. 5b is a graph showing the oxygen vacancy concentration in a variable resistance material layer of a semiconductor device according to exemplary embodiments.

[0077] Referring to FIGS. 5a and 5b, the information storage region (142b) of the variable resistor layer (142) may include a first information storage region (142b1) adjacent to the channel region (142a) and a second information storage region (142b2) adjacent to the core insulation pattern (145). The first information storage region (142b1) may have oxygen vacancies of a second concentration (C2) that is smaller than the first concentration (C1) of the channel region (142a), and the second information storage region (142b2) may have oxygen vacancies of a third concentration (C3) that is smaller than the first concentration (C1) and larger than the second concentration (C2). In FIG. 5b, the variable resistance layer (142) is shown to have an oxygen vacancy concentration that changes in a step structure, but the variable resistance layer (142) may have an oxygen vacancy concentration that changes gradually as in FIG. 4b and FIG. 4c, or an oxygen vacancy concentration that changes in a constant manner as in FIG. 4d.

[0079] FIGS. 6a and 6b are magnified partial views of a portion of a semiconductor device according to exemplary embodiments. FIGS. 6a and 6b represent a region corresponding to the region marked 'B' in FIG. 2.

[0080] Referring to FIG. 6a, the channel structure (CHa) may further include an epitaxial layer (107). The epitaxial layer (107) is positioned to contact the upper substrate (101) at the bottom of the channel structure (CHa) and may be positioned adjacent to the side of at least one gate electrode (130). The epitaxial layer (107) may be positioned in a recessed area of ​​the upper substrate (101). The height of the upper surface of the epitaxial layer (107) may be higher than the upper surface of the lower gate electrode (130L) and lower than the lower surface of the gate electrode (130) above it, but is not limited to what is illustrated. The epitaxial layer (107) may be connected to a variable resistance material layer (142) through its upper surface. An insulating layer (109) may be further disposed between the epitaxial layer (107) and the lowest gate electrode (130L) adjacent to the epitaxial layer (107).

[0081] Referring to FIG. 6b, the semiconductor device (100) may further include a first horizontal conductive layer (102) disposed along the upper surface of an upper substrate (101) and a second horizontal conductive layer (103) extending along the upper surface of the first horizontal conductive layer (102). The first horizontal conductive layer (102) and the second horizontal conductive layer (103) may be disposed between the upper substrate (101) and the stacked structure (ST). At least some of the first horizontal conductive layer (102) and the second horizontal conductive layer (103) may be formed of polysilicon having an N-type conductivity. The first horizontal conductive layer (102) may penetrate the gate insulating layer (141) at the bottom of the channel structure (CHb) and come into contact with the side of the variable resistance material layer (142).

[0083] FIGS. 7 to 9 are schematic cross-sectional views of semiconductor devices according to exemplary embodiments.

[0084] Referring to FIG. 7, each of the gate electrodes (130) of the semiconductor device (100A) may include a first gate portion (131) adjacent to the channel structures (CH) and a second gate portion (132) adjacent to the first separation patterns (MS). The first gate portion (131) may surround the side of the channel structures (CH).

[0085] The first gate portion (131) may be formed of doft polysilicon, and the second gate portion (132) may be formed of a metal-semiconductor compound (e.g., WSi, or TiSi, etc.), a metal nitride (e.g., WN, or TiN, etc.), and / or a metal (e.g., W, etc.).

[0086] Each of the gate electrodes (130) includes first and second gate portions (131, 132), thereby improving the electrical characteristics of the gate electrodes (130). Accordingly, in the embodiment, a semiconductor device with improved electrical characteristics can be provided.

[0087] Referring to FIG. 8, in a semiconductor device (100B), the stacked structure (ST) of the second structure (2) includes a lower stacked structure and an upper stacked structure on the lower stacked structure, and each of the channel structures (CHc) may include a lower channel structure penetrating the lower stacked structure and an upper channel structure penetrating the upper stacked structure. The variable resistance material layer (142) of the first channel structure and the variable resistance material layer (142) of the second channel structure may have a connected form. In the connection area, the gate insulating layer (141) and the variable resistance material layer (142) may each be folded. For example, the side of the variable resistance material layer (142) may include a folded portion due to a difference in width in the connection area, and the side slope may change. This embodiment exemplarily illustrates the case where the stacked structure is a double stacked structure, and the present invention may also include an embodiment of a multi-stacked structure that is a double or more stack.

[0088] Referring to FIG. 9, the first structure (1) and the second structure (2) of the semiconductor device (100C) can be joined to each other through a bonding structure without a separate adhesive layer. The second structure (2) is shown by inverting the second structure (2) of the semiconductor device (100) of FIG. 2. The semiconductor device (100) may further include an upper bonding pad (165) and a lower bonding pad (65). The second structure (2) may further include a third upper insulating layer (193). The upper bonding pad (165) may be electrically connected to a bit line (180) through a separate upper bonding via (163), and the lower bonding pad (65) may be electrically connected to circuit elements (20) through a separate lower via (63). The lower bonding pad (65) and the upper bonding pad (165) may each comprise, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. The lower bonding pad (65) and the upper bonding pad (165) may function as bonding layers for joining the first structure (1) and the second structure (2). Additionally, the lower bonding pad (65) and the upper bonding pad (165) may provide an electrical connection path between the first structure (1) and the second structure (2). The lower bonding pad (65) and the upper bonding pad (165) may be joined by copper (Cu)-copper (Cu) bonding. In addition to the copper-copper bonding mentioned above, the first structure (1) and the second structure (2) may also be joined by dielectric-to-dielectric bonding. The dielectric-to-dielectric bonding may be, for example, a bonding by dielectric layers surrounding the upper bonding pad (165) and the lower bonding pad (65), forming a part of each of the third upper insulating layer (193) and the lower insulating layer (40).

[0090] FIGS. 10a to 11b are flowcharts for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments.

[0091] FIGS. 12 to 23 are schematic drawings for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.

[0093] Referring to FIG. 10a, FIG. 10b, and FIG. 12, a first structure (1) including circuit elements (20) and a lower wiring structure (30) is formed on a lower substrate (10), an upper substrate (101) is formed on the first structure (1), sacrificial layers (110) and interlayer insulating layers (120) are alternately stacked on the upper substrate (101) (S10), and openings (OP) penetrating the stacked structure of sacrificial layers (110) and interlayer insulating layers (120) can be formed (S21).

[0094] First, device isolation layers (15s) may be formed within the lower substrate (10), and a circuit gate dielectric layer (24) and a circuit gate electrode (26) may be sequentially formed on the active region (15a). The device isolation layers (10s) may be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer (24) may be formed of silicon oxide, and the circuit gate electrode (26) may be formed of at least one of polysilicon or a metal-semiconductor compound layer, but is not limited thereto. Next, a spacer layer (28) may be formed on both sidewalls of the circuit gate dielectric layer (24) and the circuit gate electrode (26), and source / drain regions (22) may be formed in the active region (15a). According to embodiments, the spacer layer (28) may be composed of a plurality of layers. The source / drain regions (22) may be formed by performing an ion implantation process.

[0095] The lower contacts (32) and lower wiring (34) of the lower wiring structure (30) can be formed by forming a portion of the lower insulating layer (40), then etching and removing a portion of it and burying a conductive material, or by depositing a conductive material, then patterning it, and filling the patterned area removed with a portion of the lower insulating layer (40).

[0096] The lower insulating layer (40) may be formed from a plurality of insulating layers. The lower insulating layer (40) may be formed so as to finally cover the circuit elements (20) and the lower insulating layer (30) by forming a portion of it in each step of forming the lower wiring structure (30) and forming a portion of it on the uppermost lower wiring (34).

[0097] The upper substrate (101) may be formed of, for example, polysilicon. The polysilicon forming the upper substrate (101) may contain impurities.

[0098] The sacrificial layers (110) may be layers in which a portion is replaced by gate electrodes (130) (see FIG. 2) through a subsequent process. The sacrificial layers (110) may be made of a material different from the interlayer insulating layers (120) and may be formed of a material that can be etched with etch selectivity with respect to the interlayer insulating layers (120) under specific etching conditions. For example, the interlayer insulating layer (120) may be made of at least one of silicon oxide and silicon nitride, and the sacrificial layers (110) may be made of a material different from the interlayer insulating layer (120) selected from silicon, silicon oxide, silicon carbide, and silicon nitride. The sacrificial layer (110) may be referred to as a 'gate layer,' and if the sacrificial layer (110) comprises polysilicon, the gate layer comprising polysilicon may function as a gate electrode, and the process of replacing the sacrificial layer (110) with a subsequent gate electrode (130) may be omitted. In the embodiments, the thicknesses of the interlayer insulation layers (120) may not all be the same. The thicknesses of the interlayer insulation layers (120) and the sacrificial layers (110), and the number of constituent films may vary from those illustrated. The sacrificial layers (110) and the interlayer insulation layers (120) may be stacked to form a pre-laminated structure. After forming the pre-laminated structure, second separation patterns (MS2) that penetrate a portion of the upper sacrificial layers (110) may be formed.

[0099] The above pre-laminated structure can be anisotropically etched to form openings (OP). Due to the height of the pre-laminated structure, the sides of the openings (OP) may be inclined with respect to the upper surface of the upper substrate (101).

[0101] Referring to FIG. 10b, FIG. 11a, FIG. 13a, and FIG. 14, a gate insulating layer (141) covering the sides of the openings (OP) can be formed (S22), and a variable resistance material layer (142P) can be formed (S23). Forming the variable resistance material layer (142P) (S23) may include forming a first variable resistance material layer (142_1) (S23A) and forming a second variable resistance material layer (142_2) on the first variable resistance material layer (142_1) (S23B).

[0102] The gate insulating layer (141) can be formed to conformally cover the side and bottom surfaces of the openings (OP). The gate insulating layer (141) can also be partially formed at a level higher than the top interlayer insulating layer (120). After partially opening the bottom of the gate insulating layer (141), a first variable resistance material layer (142_1) and a second variable resistance material layer (142_2) can be conformally formed. The first variable resistance material layer (142_1) contacts the upper substrate (101) and can also contact the gate insulating layer (141). The first variable resistance material layer (142_1) and the second variable resistance material layer (142_2) are formed from the same material and, for example, can be formed by performing an atomic layer deposition (ALD) process. The first variable resistance material layer (141_1) and the second variable resistance material layer (142_2) are shown as separate layers for convenience of explanation, but they can substantially be formed as a single layer (142P).

[0103] Referring to FIG. 10b, FIG. 11b, FIG. 13b, and FIG. 14, a gate insulating layer (141) covering the sides of the openings (OP) can be formed (S22), and a variable resistance material layer (142P) can be formed (S23). Forming the variable resistance material layer (142P) (S23) may include forming a variable resistance material capping layer (142') that fills the openings (OP) and contacts the gate insulating layer (141) (S23A'), and etching the variable resistance material capping layer (142') (S23B'). The gate insulating layer (141) can be formed to conformally cover the sides and bottom surfaces of the openings (OP). The gate insulating layer (141) can also be partially formed at a level higher than the top interlayer insulating layer (120). After partially opening the lower portion of the gate insulating layer (141), a variable resistance material capping layer (142') can be formed by performing, for example, a chemical vapor deposition (CVD) process or a sputtering process. The variable resistance material capping layer (142') fills the opening (OP) and can come into contact with the gate insulating layer (141) within the opening (OP). The central region of the variable resistance material capping layer (142') can be etched to remove the remaining portion, leaving a variable resistance material layer (142P) that extends along the side of the gate insulating layer (141) and has a predetermined thickness from the side of the gate insulating layer (141).

[0104] As shown in FIG. 13, a method for forming a variable resistance material layer (142P) before performing the following post-processing step may include the manufacturing steps of FIG. 13a and FIG. 14 as described above, or the manufacturing steps of FIG. 13b and FIG. 14.

[0106] Referring to FIG. 10b and FIG. 14, a plasma treatment process (PP) can be performed on a variable resistance material layer (142P) to change the oxygen vacancy concentration in a portion of the variable resistance material layer (142P) (S24), thereby forming a variable resistance material layer (142) including a channel region (142a) and an information storage region (142b). The plasma treatment process (PP) can be performed using a source gas including oxygen (O2), hydrogen (H2), silane (SiH4), or argon (Ar). For example, by performing the plasma treatment process (PP) using argon (Ar), the oxygen vacancy concentration in a portion of the surface of the variable resistance material layer (142P) can be reduced, thereby forming a structure in which the oxygen vacancy concentration in the channel region (142a) is relatively lower than the oxygen vacancy concentration in the information storage region (142b).

[0107] For example, instead of a plasma treatment process (PP), an annealing process may be performed to change the oxygen vacancy concentration in a portion of the variable resistance material layer (142P). For example, by performing an annealing process, the oxygen vacancy concentration in a portion of the surface of the variable resistance material layer (142P) may be reduced. The annealing process may be a thermal annealing process or a laser annealing process.

[0108] For example, referring together with FIG. 13a, before forming the first variable resistance material layer (142_1) and forming the second variable resistance material layer (142_2), a plasma treatment process (PP) or an annealing process may be performed on the first variable resistance material layer (142_1) to change the oxygen vacancy concentration. Afterward, after forming the second variable resistance material layer (142_2), an additional plasma treatment process (PP) or annealing process may or may not be performed.

[0109] The change in oxygen vacancy concentration along the width direction of the variable resistance material layer (142), i.e., the oxygen vacancy concentration profile or distribution, can be confirmed, for example, through X-ray Photoelectron Spectrometry (XPS) or Secondary Ion Mass Spectrometry (SIMS).

[0111] Referring to FIG. 10b and FIG. 16 through 19, a core insulation pattern (145) can be formed that covers a variable resistance material layer (142) and fills at least a portion of an opening (OP) (S25). Forming the core insulation pattern (145) (S25) may include forming a first core insulation layer (145A), partially removing the first core insulation layer (145A) and the variable resistance material layer (142) from the top, respectively, filling the opening (OP) with a second core insulation layer (145B), and partially removing the first and second core insulation layers (145A, 145B) from the top to form the core insulation pattern (145).

[0112] First, the first core insulating layer (145A) can be formed to conformally cover the inner surface of the variable resistance material layer (142) within the opening (OP). Next, the first core insulating layer (145A) and the variable resistance material layer (142) can each be partially removed from the top so that the height of their tops is lower than the top of the gate insulating layer (141). Next, the second core insulating layer (145B) can fill the unfilled space of the opening (OP). The interface between the second core insulating layer (145A) and the second core insulating layer (145B) may be visible depending on the process conditions, but may not be clearly distinguishable. Next, a flattening process can be performed to remove the portion of the second core insulating layer (145B) covering the top of the gate insulating layer (141). The first and second core insulation layers (145A, 145B) can be partially removed from the top to form a space within the opening (OP) for forming a subsequent pad pattern (149).

[0114] Referring to FIGS. 10a, FIGS. 10b, FIGS. 20, and FIGS. 21, a pad pattern (149) can be formed on a core insulation pattern (145) (S26). Forming the pad pattern (149) (S26) may include forming a capping material layer (149P) on the core insulation pattern (145) and performing a flattening process to remove a portion of the capping material layer (149P) placed on top of the gate insulation layer (141). During the flattening process, a portion of the gate insulation layer (141) on the top interlayer insulation layer (120) may also be removed. This allows channel structures (CH) penetrating the pre-stacking structure to be formed (S20).

[0116] Referring to FIG. 22, separation openings (T) can be formed penetrating the sacrificial layers (110) and the interlayer insulation layers (120), and horizontal openings (LT) can be formed by removing the sacrificial layers (110) through the separation openings (T).

[0117] First, a channel structure (CH) can be formed, and then a first upper insulating layer (191) can be formed on the channel structure (CH). Separation openings (T) can be formed by using a photolithography process to form a mask layer and anisotropically etching the first upper insulating layer (191), sacrificial layers (110), and interlayer insulating layers (120). The separation openings (T) can be formed in the shape of a trench extending in the X direction and can expose the upper substrate (101) at the bottom.

[0118] Next, the sacrificial layers (110) can be selectively removed from the interlayer insulation layers (120) and the first upper insulation layer (191) through the separation openings (T). Accordingly, a plurality of horizontal openings (LT) can be formed between the interlayer insulation layers (120).

[0120] Referring to FIG. 10a and FIG. 23, gate electrodes (130) can be formed in horizontal openings (LT) and first separation patterns (MS) can be formed in separation openings (T) (S30).

[0121] First, gate electrodes (130) can be formed by filling horizontal openings (LT) formed by removing sacrificial layers (110) through separation openings (T) with a conductive material. In this way, a stacked structure (ST) can be formed in which interlayer insulating layers (120) and gate electrodes (130) are alternately stacked. Forming the gate electrodes (130) may include forming a first layer and a second layer in sequence.

[0122] Next, first separation patterns (MS) can be formed by filling the separation openings (T) with an insulating material. According to embodiments, a separation insulating pattern containing an insulating material and a conductive core pattern containing a conductive material may be formed sequentially within the separation openings (T). The conductive core pattern may be formed to be spaced apart from the gate electrodes (130) and to be in contact with the upper substrate (101).

[0123] Next, a second upper insulating layer (192) is formed, and contact plugs (170) and bit lines (180) are formed (S40) to manufacture the semiconductor device (100) of FIGS. 1 to 3.

[0125] FIG. 24 is a schematic diagram illustrating a data storage system including a semiconductor device according to exemplary embodiments.

[0126] Referring to FIG. 24, the data storage system (1000) may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The data storage system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (1100). For example, the data storage system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising one or more semiconductor devices (1100).

[0127] The semiconductor device (1100) may be a non-volatile memory device, for example, a NAND flash memory device described above with reference to FIGS. 1 through 9. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). In exemplary embodiments, the first structure (1100F) may be placed next to the second structure (1100S). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure comprising a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

[0129] In the second structure (1100S), each memory cell string (CSTR) may include lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0130] In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The gate lower lines (LL1, LL2) may each be the gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT), and the gate upper lines (UL1, UL2) may each be the gate electrodes of the upper transistors (UT1, UT2).

[0131] In exemplary embodiments, the lower transistors (LT1, LT2) may include a lower erase control transistor (LT1) and a ground select transistor (LT2) connected in series. The upper transistors (UT1, UT2) may include a string select transistor (UT1) and an upper erase control transistor (UT2) connected in series. At least one of the lower erase control transistor (LT1) and the upper erase control transistor (UT1) may be used for an erase operation to delete data stored in memory cell transistors (MCTs) using the GIDL phenomenon.

[0132] The common source line (CSL), the first and second gate lower lines (LL1, LL2), the word lines (WL), and the first and second gate upper lines (UL1, UL2) can be electrically connected to the decoder circuit (1110) through first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S). The bit lines (BL) can be electrically connected to the page buffer (1120) through second connecting wires (1125) extending from the first structure (1100F) to the second structure (1100S).

[0133] In the first structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit (1110) and the page buffer (1120) can be controlled by the logic circuit (1130). The semiconductor device (1000) can communicate with the controller (1200) through an input / output pad (1101) that is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0135] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to embodiments, the data storage system (1000) may include a plurality of semiconductor devices (1100), and in this case, the controller (1200) may control the plurality of semiconductor devices (1000).

[0136] The processor (1210) can control the overall operation of the data storage system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the semiconductor device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the semiconductor device (1100). Through the NAND interface (1221), control commands for controlling the semiconductor device (1100), data to be written to the memory cell transistors (MCT) of the semiconductor device (1100), data to be read from the memory cell transistors (MCT) of the semiconductor device (1100), etc., can be transmitted. The host interface (1230) can provide communication functions between the data storage system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the semiconductor device (1100) in response to the control command.

[0138] FIG. 25 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment.

[0139] Referring to FIG. 25, a data storage system (2000) according to an exemplary embodiment of the present invention may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor package (2003) and the DRAM (2004) may be connected to the controller (2002) by wiring patterns (2005) formed on the main board (2001).

[0140] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the data storage system (2000) and the external host. In exemplary embodiments, the data storage system (2000) may communicate with the external host according to any one of the interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In exemplary embodiments, the data storage system (2000) may operate by power supplied from the external host through the connector (2006). The data storage system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a semiconductor package (2003).

[0141] The controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the data storage system (2000).

[0142] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the data storage system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the DRAM (2004) is included in the data storage system (2000), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0144] A semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), semiconductor chips (2200) on the package substrate (2100), adhesive layers (2300) disposed on the lower surface of each of the semiconductor chips (2200), a connecting structure (2400) electrically connecting the semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0145] The package substrate (2100) may be a printed circuit board including package upper pads (2130). Each semiconductor chip (2200) may include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 22. Each of the semiconductor chips (2200) may include gate stacking structures (3210) and channel structures (3220). Each of the semiconductor chips (2200) may include the semiconductor device described above with reference to FIGS. 1 through 9.

[0146] In exemplary embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pads (2130). Accordingly, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (2130) of the package substrate (2100). According to embodiments, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0147] In exemplary embodiments, the controller (2002) and the semiconductor chips (2200) may be included in a single package. In an exemplary embodiment, the controller (2002) and the semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0149] FIG. 26 is a schematic cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 26 illustrates an exemplary embodiment of the semiconductor package (2003) of FIG. 25 and conceptually shows a region of the semiconductor package (2003) of FIG. 25 cut along the cutting line Ⅱ-±.

[0150] Referring to FIG. 26, in a semiconductor package (2003), the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body portion (2120), package upper pads (2130) disposed on the upper surface of the package substrate body portion (2120) (see FIG. 25), lower pads (2125) disposed on the lower surface of the package substrate body portion (2120) or exposed through the lower surface, and internal wiring (2135) electrically connecting the upper pads (2130) and the lower pads (2125) inside the package substrate body portion (2120). The upper pads (2130) may be electrically connected to connection structures (2400). The lower pads (2125) can be connected to the wiring patterns (2005) of the main board (2010) of the data storage system (2000) through conductive connections (2800) as shown in FIG. 25.

[0152] Each of the semiconductor chips (2200) may include a semiconductor substrate (3010) and a first structure (3100) and a second structure (3200) that are sequentially stacked on the semiconductor substrate (3010). The first structure (3100) may include a peripheral circuit region including peripheral wiring (3110). The second structure (3200) may include a common source line (3205), a gate stacking structure (3210) on the common source line (3205), channel structures (3220) penetrating the gate stacking structure (3210) and separation regions (3230), bit lines (3240) electrically connected to the memory channel structures (3220), and gate contact plugs electrically connected to the word lines (WL) (see FIG. 24) of the gate stacking structure (3210). As described above with reference to FIGS. 1 to 9, each of the semiconductor chips (2200) may include a lower substrate (10), an upper substrate (101), gate electrodes (130), a channel structure (CH) including a variable resistance material layer (142), a first separation pattern (MS), a second separation pattern (SS), and a bit line (180).

[0153] Each of the semiconductor chips (2200) may include a through-wire (3245) that is electrically connected to the peripheral wiring (3110) of the first structure (3100) and extends into the second structure (3200). The through-wire (3245) may be positioned outside the gate stack structure (3210) and may be further positioned to penetrate the gate stack structure (3210). Each of the semiconductor chips (2200) may further include an input / output pad (2210) (see FIG. 23) that is electrically connected to the peripheral wiring (3110) of the first structure (3100).

[0155] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, changes, and combinations of embodiments may be made by those skilled in the art without departing from the technical spirit of the invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0157] CH: Channel structure MS: First separation pattern SS: Second separation pattern ST: Laminated structure 10: Lower substrate 20: Circuit element 30: Lower wiring structure 40: Lower insulation layer 100: Semiconductor device 101: Upper substrate 110: Sacrificial layer 120: Interlayer insulation layer 130: Gate electrode 141: Gate insulation layer 142: Variable resistor material layer 145: Core insulation pattern 149: Pad pattern 170: Contact plug 180: Bitline 191, 192: Upper insulation layer

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: a step of forming a stacked structure by alternately stacking gate layers and interlayer insulating layers on a substrate; and a step of forming a channel structure penetrating the stacked structure in a vertical direction, wherein the step of forming the channel structure comprises: a step of etching the stacked structure to form an opening; a step of forming a gate insulating layer covering at least a side of the opening; a step of forming a variable resistance material layer in contact with the gate insulating layer; a step of performing a plasma treatment or annealing process on the variable resistance material layer to change the oxygen vacancy concentration of a portion of the variable resistance material layer; a step of forming a core insulating pattern covering the variable resistance material layer and filling at least a portion of the opening after performing the plasma treatment or annealing process; and a step of forming a pad pattern on the core insulating pattern, wherein the variable resistance material layer is formed by the plasma treatment or annealing process to include a channel region containing oxygen vacancies at a first concentration and an information storage region containing oxygen vacancies at a second concentration smaller than the first concentration. Claim 2 delete Claim 3 A method for manufacturing a semiconductor device according to claim 1, wherein the channel region of the variable resistance material layer is formed to be in contact with the gate insulation layer and extend along the side of the gate insulation layer, and the information storage region of the variable resistance material layer is formed to be in contact with the core insulation pattern and extend along the side of the core insulation pattern. Claim 4 A method for manufacturing a semiconductor device according to claim 1, wherein the information storage region of the variable resistance material layer is formed further from the side of the opening than the channel region. Claim 5 A method for manufacturing a semiconductor device according to claim 1, wherein the variable resistance material layer is formed of a transition metal oxide. Claim 6 A method for manufacturing a semiconductor device according to claim 1, wherein the variable resistance material layer is formed of at least one of hafnium oxide (HfO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO), tin oxide (SnO), copper oxide (CuO), molybdenum oxide (MoO), hafnium-silicon oxide (HSO), hafnium-zinc oxide (HZO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), and indium-tin-zinc oxide (ITZO). Claim 7 A method for manufacturing a semiconductor device comprising: a step of forming a stacked structure by alternately stacking gate layers and interlayer insulating layers on a substrate; and a step of forming a channel structure penetrating the stacked structure in a vertical direction, wherein the step of forming the channel structure comprises: a step of etching the stacked structure to form an opening; a step of forming a gate insulating layer covering at least the side of the opening; a step of forming a variable resistance material layer in contact with the gate insulating layer and comprising a first region and a second region; a step of increasing or decreasing the oxygen vacancy concentration of either the first region and the second region; a step of forming a core insulating pattern that fills at least a portion of the opening; and a step of forming a pad pattern on the core insulating pattern, wherein the step of increasing or decreasing the oxygen vacancy concentration of either the first region and the second region comprises a step of lowering the oxygen vacancy concentration of the second region to a lower oxygen vacancy concentration of the first region. Claim 8 A method for manufacturing a semiconductor device according to claim 7, wherein the variable resistance material layer is formed of a transition metal oxide. Claim 9 A method for manufacturing a semiconductor device according to claim 7, wherein the first region is in contact with the gate insulating layer and the second region is in contact with the core insulating pattern. Claim 10 A method for manufacturing a semiconductor device comprising: a step of forming a stacked structure by alternately stacking gate layers and interlayer insulating layers on a substrate; and a step of forming a channel structure penetrating the stacked structure in a vertical direction, wherein the step of forming the channel structure comprises: a step of etching the stacked structure to form an opening; a step of forming a gate insulating layer within the opening; a step of forming a variable resistance material capping layer that fills the opening and contacts the gate insulating layer; a step of etching a central region of the variable resistance material capping layer to remove the remaining portion while leaving a variable resistance material layer extending along the side of the gate insulating layer and having a predetermined thickness from the side of the gate insulating layer; a step of performing a plasma treatment or annealing process on the remaining variable resistance material layer to change the oxygen vacancy concentration in a portion of the variable resistance material layer; a step of forming a core insulating pattern that covers the variable resistance material layer and fills at least a portion of the opening after performing the plasma treatment or the annealing process; and a step of forming a pad pattern on the core insulating pattern.

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