Semiconductor device including fixed charge layer and method of forming the same

Abstract

A semiconductor device comprises a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately and repeatedly stacked. A channel structure is disposed penetrating the stacked structure. The channel structure comprises a channel layer; and an information storage pattern between the channel layer and the plurality of electrode layers. The information storage pattern comprises a tunnel insulating layer between the channel layer and the plurality of electrode layers; a charge storage layer between the tunnel insulating layer and the plurality of electrode layers; and a blocking layer between the charge storage layer and the plurality of electrode layers. The blocking layer comprises one or more sub-blocking layers having an oxide of a first element; and one or more fixed charge layers. Each of the one or more fixed charge layers comprises an oxide of a second element and a third element doped into the oxide of the second element. The proportion of the third element within the one or more fixed charge layers is 0.5 wt% to 5 wt%.

Description

Technology Field

[0001] The invention relates to a semiconductor device having a fixed charge layer and a method for forming the same. Background Technology

[0002] A technology employing a blocking layer is used to achieve high integration of non-volatile memory devices, such as flash memory. For example, a non-volatile memory device can be implemented using an information storage pattern having a charge storage layer between a tunnel insulating layer and a blocking layer. The composition of the blocking layer has a significant impact on the electrical characteristics and reliability of the non-volatile memory device. The problem to be solved

[0003] The objective according to embodiments of the technical concept of the present invention is to provide semiconductor devices having excellent electrical characteristics and a method for forming the same. means of solving the problem

[0004] A semiconductor device according to embodiments of the technical concept of the present invention comprises a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately and repeatedly stacked. A channel structure is disposed penetrating the stacked structure. The channel structure comprises a channel layer; and an information storage pattern between the channel layer and the plurality of electrode layers. The information storage pattern comprises a tunnel insulating layer between the channel layer and the plurality of electrode layers; a charge storage layer between the tunnel insulating layer and the plurality of electrode layers; and a blocking layer between the charge storage layer and the plurality of electrode layers. The blocking layer comprises one or more sub-blocking layers having an oxide of a first element; and one or more fixed charge layers. Each of the one or more fixed charge layers comprises an oxide of a second element and a third element doped into the oxide of the second element. The proportion of the third element within the one or more fixed charge layers is 0.5 wt% to 5 wt%. Effects of the invention

[0005] According to embodiments of the technical concept of the present invention, a blocking layer having one or more sub-blocking layers and one or more fixed charge layers is provided. The one or more sub-blocking layers comprise an oxide of a first element. The one or more fixed charge layers comprise an oxide of a second element and a third element doped into the oxide of the second element. Semiconductor devices having excellent electrical characteristics and a method for forming the same may be provided. Brief explanation of the drawing

[0006] FIGS. 1 to 13 are cross-sectional views for explaining semiconductor devices according to embodiments of the technical concept of the present invention. FIGS. 14 to 24 are cross-sectional views for explaining methods for forming semiconductor devices according to embodiments of the technical concept of the present invention. Specific details for implementing the invention

[0007] FIGS. 1 to 13 are cross-sectional views for illustrating semiconductor devices according to embodiments of the technical concept of the present invention. In one embodiment, FIGS. 1 to 11 may be cross-sectional views corresponding to part (8) of FIG. 12. In one embodiment, semiconductor devices according to embodiments of the technical concept of the present invention may include non-volatile memory such as VNAND or 3D flash memory. Semiconductor devices according to embodiments of the technical concept of the present invention may be interpreted as including a Cell On Peripheral (COP) structure.

[0008] Referring to FIG. 1, semiconductor devices according to embodiments of the technical concept of the present invention may include a plurality of first insulating layers (62), a plurality of first electrode layers (64), and a channel structure (110). The plurality of first insulating layers (62) and the plurality of first electrode layers (64) may be stacked alternately and repeatedly. The channel structure (110) may penetrate the plurality of first insulating layers (62) and the plurality of first electrode layers (64).

[0009] Each of the plurality of first electrode layers (64) may include an electrode conductive layer (64C) and a barrier layer (64B). The barrier layer (64B) may cover the upper surface, lower surface, and side surface of the electrode conductive layer (64C). The electrode conductive layer (64C) and the barrier layer (64B) may include a conductive material such as a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, polysilicon, amorphous silicon, a single-crystal silicon, or a combination thereof. In one embodiment, the barrier layer (64B) may include Ti, TiN, Ta, TaN, or a combination thereof. The electrode conductive layer (64C) may include W, WN, Ti, TiN, Ta, TaN, Co, Ni, Ru, Pt, polysilicon, conductive carbon, or a combination thereof.

[0010] The channel structure (110) may include an information storage pattern (120), a channel layer (131), and a core pattern (135). The channel layer (131) may surround the outer side of the core pattern (135). The information storage pattern (120) may surround the outer side of the channel layer (131) and the core pattern (135). The channel layer (131) may be interposed between the information storage pattern (120) and the core pattern (135). The information storage pattern (120) may be disposed between the plurality of first electrode layers (64) and the channel layer (131). The information storage pattern (120) may be in contact with the plurality of first electrode layers (64).

[0011] The information storage pattern (120) may include a blocking layer (121), a charge storage layer (128), and a tunnel insulating layer (129). The tunnel insulating layer (129) may surround the outer side of the channel layer (131). The charge storage layer (128) may surround the outer side of the tunnel insulating layer (129). The blocking layer (121) may surround the outer side of the charge storage layer (128). The charge storage layer (128) may be disposed between the tunnel insulating layer (129) and the blocking layer (121). The electrical equivalent thickness of the blocking layer (121) may be greater than the electrical equivalent thickness of the tunnel insulating layer (129). The thickness of the blocking layer (121) may be 0.5 nm to 50 nm (nanometers).

[0012] The blocking layer (121) may include one or more sub-blocking layers (122, 124, 126) and one or more fixed charge layers (123, 125).

[0013] Each of the one or more sub-blocking layers (122, 124, 126) may comprise an oxide of a first element. The first element may comprise Si, Al, or a combination thereof. For example, each of the one or more sub-blocking layers (122, 124, 126) may comprise silicon oxide, aluminum oxide, aluminum silicate, or a combination thereof.

[0014] Each of the one or more fixed charge layers (123, 125) may comprise an oxide of a second element and a third element doped into the oxide of the second element. The second element may comprise Si, Al, or a combination thereof. The second element may be the same as the first element, or the second element may be different from the first element. The third element may be different from the second element. The third element may comprise Al, Hf, Ti, Y, Li, Na, Mg, K, Ca, Cr, Mn, Fe, Zr, Mo, Pd, Au, Ta, Pb, Sn, In, Si, B, C, N, P, F, S, Se, Br, I, or a combination thereof. For example, each of the one or more fixed charge layers (123, 125) may comprise silicon oxide doped with the third element, aluminum oxide doped with the third element, aluminum silicate doped with the third element, or a combination thereof. In one embodiment, the proportion of the third element within the one or more fixed charge layers (123, 125) may be 0.5 wt% to 5 wt%. In one embodiment, the proportion of the third element within the one or more fixed charge layers (123, 125) may be 1 wt% or less.

[0015] In one embodiment, the blocking layer (121) may include a first sub-blocking layer (122), a first fixed charge layer (123), a second sub-blocking layer (124), a second fixed charge layer (125), and a third sub-blocking layer (126). The third sub-blocking layer (126) may surround the outside of the charge storage layer (128). The second fixed charge layer (125) may surround the outside of the third sub-blocking layer (126). The second sub-blocking layer (124) may surround the outside of the second fixed charge layer (125). The first fixed charge layer (123) may surround the outside of the second sub-blocking layer (124). The first sub-blocking layer (122) may surround the outer side of the first fixed charge layer (123). The first sub-blocking layer (122) may be in contact with the plurality of first insulating layers (62) and the plurality of first electrode layers (64).

[0016] The thickness of the first sub-blocking layer (122) may be 0.1 nm to 50 nm (nanometers). The first fixed charge layer (123) may be thinner than the first sub-blocking layer (122) or the second sub-blocking layer (124). The thickness of the first fixed charge layer (123) may be 0.01 nm to 5 nm. The second sub-blocking layer (124) may be thicker than the first sub-blocking layer (122). The thickness of the second sub-blocking layer (124) may be 0.1 nm to 50 nm (nanometers). The second fixed charge layer (125) may be thinner than the second sub-blocking layer (124) or the third sub-blocking layer (126). The thickness of the second fixed charge layer (125) may be 0.01 nm to 5 nm. The third sub-blocking layer (126) may be thinner than the second sub-blocking layer (124). The thickness of the third sub-blocking layer (126) may be 0.1 nm to 50 nm.

[0017] Referring to FIG. 2, the blocking layer (121) may include a first sub-blocking layer (122), a first fixed charge layer (123), a second sub-blocking layer (124), a second fixed charge layer (125), and a third sub-blocking layer (126). Each of the first sub-blocking layer (122), the second sub-blocking layer (124), and the third sub-blocking layer (126) may have substantially the same thickness. Each of the first fixed charge layer (123) and the second fixed charge layer (125) may have substantially the same thickness. Each of the first fixed charge layer (123) and the second fixed charge layer (125) may have a thickness smaller than each of the first sub-blocking layer (122), the second sub-blocking layer (124), and the third sub-blocking layer (126).

[0018] Referring to FIG. 3, the blocking layer (121) may include a first fixed charge layer (123), a second sub-blocking layer (124), a second fixed charge layer (125), a third sub-blocking layer (126), and a third fixed charge layer (127). The third fixed charge layer (127) may include a configuration similar to the first fixed charge layer (123) and the second fixed charge layer (125). For example, the third fixed charge layer (127) may include a material substantially identical to the first fixed charge layer (123) and the second fixed charge layer (125).

[0019] The third fixed charge layer (127) may surround the outer side of the charge storage layer (128). The third fixed charge layer (127) may be in contact with the charge storage layer (128). The third sub-blocking layer (126) may surround the outer side of the third fixed charge layer (127). The second fixed charge layer (125) may surround the outer side of the third sub-blocking layer (126). The second sub-blocking layer (124) may surround the outer side of the second fixed charge layer (125). The first fixed charge layer (123) may surround the outer side of the second sub-blocking layer (124). The first fixed charge layer (123) may be in contact with a plurality of first insulating layers (62) and a plurality of first electrode layers (64).

[0020] Referring to FIG. 4, the blocking layer (121) may include a first fixed charge layer (123), a second sub-blocking layer (124), a second fixed charge layer (125), and a third sub-blocking layer (126). The third sub-blocking layer (126) may surround the outside of the charge storage layer (128). The second fixed charge layer (125) may surround the outside of the third sub-blocking layer (126). The second sub-blocking layer (124) may surround the outside of the second fixed charge layer (125). The first fixed charge layer (123) may surround the outside of the second sub-blocking layer (124). The first fixed charge layer (123) may be in contact with a plurality of first insulating layers (62) and a plurality of first electrode layers (64).

[0021] Referring to FIG. 5, the blocking layer (121) may include a first sub-blocking layer (122), a first fixed charge layer (123), a second sub-blocking layer (124), and a second fixed charge layer (125). The second fixed charge layer (125) may surround the outside of the charge storage layer (128). The second fixed charge layer (125) may be in contact with the charge storage layer (128). The second sub-blocking layer (124) may surround the outside of the second fixed charge layer (125). The first fixed charge layer (123) may surround the outside of the second sub-blocking layer (124). The first sub-blocking layer (122) may surround the outside of the first fixed charge layer (123). The first sub-blocking layer (122) may be in contact with a plurality of first insulating layers (62) and a plurality of first electrode layers (64).

[0022] Referring to FIG. 6, the blocking layer (121) may include a first sub-blocking layer (122), a first fixed charge layer (123), and a second sub-blocking layer (124). The second sub-blocking layer (124) may surround the outside of the charge storage layer (128). The second sub-blocking layer (124) may be in contact with the charge storage layer (128). The first fixed charge layer (123) may surround the outside of the second sub-blocking layer (124). The first sub-blocking layer (122) may surround the outside of the first fixed charge layer (123). The first sub-blocking layer (122) may be in contact with a plurality of first insulating layers (62) and a plurality of first electrode layers (64).

[0023] Referring to FIG. 7, the blocking layer (121) may include a first fixed charge layer (123), a second sub-blocking layer (124), and a second fixed charge layer (125). The second fixed charge layer (125) may surround the outside of the charge storage layer (128). The second fixed charge layer (125) may be in contact with the charge storage layer (128). The second sub-blocking layer (124) may surround the outside of the second fixed charge layer (125). The first fixed charge layer (123) may surround the outside of the second sub-blocking layer (124). The first fixed charge layer (123) may be in contact with a plurality of first insulating layers (62) and a plurality of first electrode layers (64).

[0024] Referring to FIG. 8, the blocking layer (121) may include a first fixed charge layer (123) and a second sub-blocking layer (124). The second sub-blocking layer (124) may surround the outside of the charge storage layer (128). The second sub-blocking layer (124) may be in contact with the charge storage layer (128). The first fixed charge layer (123) may surround the outside of the second sub-blocking layer (124). The first fixed charge layer (123) may be in contact with a plurality of first insulating layers (62) and a plurality of first electrode layers (64).

[0025] Referring to FIG. 9, the blocking layer (121) may include a second sub-blocking layer (124) and a second fixed charge layer (125). The second fixed charge layer (125) may surround the outside of the charge storage layer (128). The second fixed charge layer (125) may be in contact with the charge storage layer (128). The second sub-blocking layer (124) may surround the outside of the second fixed charge layer (125). The second sub-blocking layer (124) may be in contact with a plurality of first insulating layers (62) and a plurality of first electrode layers (64).

[0026] Referring to FIG. 10, an additional blocking layer (67) may be formed between a plurality of first electrode layers (64) and a blocking layer (121). The additional blocking layer (67) may extend between the plurality of first electrode layers (64) and the plurality of first insulating layers (62). The additional blocking layer (67) may include an oxide of the first element.

[0027] Referring to FIG. 11, the tunnel insulating layer (129) may include one or more sub-tunnel insulating layers (129A, 129B) and at least one tunnel fixed charge layer (129F). The blocking layer (121) may include one or more sub-blocking layers (122, 124, 126) and one or more fixed charge layers (123, 125). The blocking layer (121) may include a configuration similar to that described with reference to FIG. 1 through 10.

[0028] Each of the one or more sub-tunnel insulating layers (129A, 129B) may comprise an oxide of a first element. The first element may comprise Si, Al, or a combination thereof. For example, each of the one or more sub-tunnel insulating layers (129A, 129B) may comprise silicon oxide, aluminum oxide, aluminum silicate, or a combination thereof.

[0029] The at least one tunnel fixed charge layer (129F) may comprise an oxide of a second element and a third element doped into the oxide of the second element. The second element may comprise Si, Al, or a combination thereof. The second element may be the same as the first element, or the second element may be different from the first element. The third element may be different from the second element. The third element may comprise Al, Hf, Ti, Y, Li, Na, Mg, K, Ca, Cr, Mn, Fe, Zr, Mo, Pd, Au, Ta, Pb, Sn, In, Si, B, C, N, P, F, S, Se, Br, I, or a combination thereof. For example, the at least one tunnel fixed charge layer (129F) may comprise silicon oxide doped with the third element, aluminum oxide doped with the third element, aluminum silicate doped with the third element, or a combination thereof. In one embodiment, the proportion of the third element within the at least one tunnel fixed charge layer (129F) may be 0.5 wt% to 5 wt%. In one embodiment, the proportion of the third element within the at least one tunnel fixed charge layer (129F) may be 1 wt% or less.

[0030] In one embodiment, the tunnel insulating layer (129) may include a first sub-tunnel insulating layer (129A), a second sub-tunnel insulating layer (129B), and at least one tunnel fixed charge layer (129F). The at least one tunnel fixed charge layer (129F) may be formed between the first sub-tunnel insulating layer (129A) and the second sub-tunnel insulating layer (129B). The at least one tunnel fixed charge layer (129F) may be thinner than the first sub-tunnel insulating layer (129A) or the second sub-tunnel insulating layer (129B).

[0031] Referring to FIG. 12, a semiconductor device according to embodiments of the technical concept of the present invention may include a lower structure (20), a horizontal wiring layer (40), a first stacked structure (60), a second stacked structure (70), a plurality of separated insulation patterns (91), a first upper insulation layer (93), a second upper insulation layer (94), a plurality of bit plugs (97), a plurality of bit lines (98), and a plurality of channel structures (110).

[0032] The above lower structure (20) may include a substrate (21), a device isolation layer (23), a plurality of transistors (25), a plurality of lower wirings (27), a first lower insulating layer (31), a second lower insulating layer (33), and a third lower insulating layer (35).

[0033] The horizontal wiring layer (40) may include a horizontal conductive layer (41), a sealing conductive layer (45), and a support (47). The horizontal conductive layer (41) may correspond to a common source line.

[0034] Each of the first laminated structure (60) and the second laminated structure (70) may include a plurality of first insulating layers (62) and a plurality of first electrode layers (64). The plurality of first insulating layers (62) and the plurality of first electrode layers (64) may be alternately and repeatedly laminated on the horizontal wiring layer (40). Some of the plurality of first electrode layers (64) may correspond to word lines and some of the others may correspond to selection lines.

[0035] Each of the plurality of channel structures (110) may include an information storage pattern (120), a channel layer (131), a core pattern (135), and a bit pad (138). The information storage pattern (120) may include a configuration similar to that described with reference to FIGS. 1 to 11.

[0036] Each of the plurality of channel structures (110) may extend into the horizontal wiring layer (40) by penetrating the second stacked structure (70) and the first stacked structure (60). In one embodiment, each of the plurality of channel structures (110) may extend into the horizontal conductive layer (41) by penetrating the plurality of first insulating layers (62), the plurality of first electrode layers (64), the support (47), and the sealing conductive layer (45).

[0037] Referring to FIG. 13, the horizontal wiring layer (40) may include a horizontal conductive layer (41). The horizontal conductive layer (41) may correspond to a common source line. The horizontal conductive layer (41) may include a first horizontal conductive layer (41A) and a second horizontal conductive layer (41B) on the first horizontal conductive layer (41A). Each of the plurality of channel structures (110) may extend into the horizontal wiring layer (40) by penetrating the second stacked structure (70) and the first stacked structure (60). In one embodiment, each of the plurality of channel structures (110) may extend into the second horizontal conductive layer (41B) by penetrating the plurality of first insulating layers (62) and the plurality of first electrode layers (64).

[0038] Each of the plurality of channel structures (110) may include an information storage pattern (120), a channel layer (131), a core pattern (135), and a bit pad (138). The information storage pattern (120) may include a configuration similar to that described with reference to FIGS. 1 to 11. The channel layer (131) may penetrate the lower part of the information storage pattern (120) and come into contact with the second horizontal conductive layer (41B).

[0039] FIGS. 14 to 24 are cross-sectional views for explaining methods for forming semiconductor devices according to embodiments of the technical concept of the present invention. FIGS. 16 to 23 may be cross-sectional views corresponding to part (8) of FIG. 15.

[0040] Referring to FIG. 14, semiconductor device formation methods according to embodiments of the technical concept of the present invention may include providing a substructure (20). The substructure (20) may include a substrate (21), a device isolation layer (23), a plurality of transistors (25), a plurality of lower wirings (27), a first lower insulating layer (31), a second lower insulating layer (33), and a third lower insulating layer (35).

[0041] The substrate (21) may include a semiconductor substrate such as a silicon wafer or an SOI (Silicon On Insulator) wafer. The device isolation layer (23) may be formed within the substrate (21) using a trench isolation method.

[0042] The plurality of transistors (25) may be formed in various ways inside the substrate (21) and / or on the substrate (21). The plurality of transistors (25) may be planar transistors, finFETs (fin Field Effect Transistors), or MBCFETs. ® It may include a multi-bridge channel transistor, a nanowire transistor, a vertical transistor, a recess channel transistor, a 3-D transistor, or a combination thereof.

[0043] A first lower insulating layer (31) covering the device isolation layer (23) and the plurality of transistors (25) may be formed on the substrate (21). The plurality of lower wirings (27) may be formed within the first lower insulating layer (31). The plurality of lower wirings (27) may include conductive patterns such as a plurality of horizontal wirings, a plurality of vertical wirings, and a plurality of connection pads. Some of the plurality of lower wirings (27) may be connected to a corresponding one of the plurality of transistors (25). The plurality of transistors (25) and the plurality of lower wirings (27) may form a peripheral circuit.

[0044] A second lower insulating layer (33) covering the first lower insulating layer (31) and the plurality of lower wirings (27) may be formed. A third lower insulating layer (35) may be formed on the second lower insulating layer (33). The second lower insulating layer (33) may include a material having an etching selectivity ratio with respect to the third lower insulating layer (35). The second lower insulating layer (33) may correspond to an etching stop layer.

[0045] Each of the above-mentioned device isolation layer (23), the above-mentioned first lower insulation layer (31), the above-mentioned second lower insulation layer (33), and the above-mentioned third lower insulation layer (35) may comprise a single layer or a multi-layer. Each of the above-mentioned device isolation layer (23), the above-mentioned first lower insulation layer (31), the above-mentioned second lower insulation layer (33), and the above-mentioned third lower insulation layer (35) may comprise at least two selected from the group consisting of Si, O, N, C, B, and H. Each of the above-mentioned device isolation layer (23), the above-mentioned first lower insulation layer (31), the above-mentioned second lower insulation layer (33), and the above-mentioned third lower insulation layer (35) may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), low-k dielectrics, high-k dielectrics, or a combination thereof. In one embodiment, the second lower insulating layer (33) may include silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), or a combination thereof. The first lower insulating layer (31) and the third lower insulating layer (35) may include silicon oxide.

[0046] The plurality of lower wires (27) may comprise a single layer or multiple layers. The plurality of lower wires (27) may comprise a conductive material such as metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, amorphous silicon, single-crystal silicon, or a combination thereof.

[0047] A horizontal wiring layer (40) may be formed on the lower structure (20). The horizontal wiring layer (40) may include a horizontal conductive layer (41), a horizontal mold layer (43), and a support (47).

[0048] The horizontal conductive layer (41) may comprise a single layer or multiple layers. The horizontal conductive layer (41) may comprise a conductive material such as a metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, amorphous silicon, single-crystal silicon, or a combination thereof. In one embodiment, the horizontal conductive layer (41) may comprise a conductive layer such as a polysilicon layer having N-type impurities or a single-crystal semiconductor layer having N-type impurities.

[0049] The horizontal mold layer (43) may be formed on the horizontal conductive layer (41). The horizontal mold layer (43) may include a single layer or multiple layers. For example, the horizontal mold layer (43) may include a pair of silicon oxide layers and a silicon nitride layer formed between the pair of silicon oxide layers. The support (47) may be formed on the horizontal mold layer (43). In one embodiment, the support (47) may include polysilicon.

[0050] A first preliminary stack structure (60T) and a second preliminary stack structure (70T) on the first preliminary stack structure (60T) may be formed on the horizontal wiring layer (40). Each of the first preliminary stack structure (60T) and the second preliminary stack structure (70T) may include a plurality of first insulating layers (62) and a plurality of first mold layers (63) that are alternately and repeatedly stacked.

[0051] The plurality of first mold layers (63) may include a material having an etching selectivity ratio with respect to the plurality of first insulating layers (62). In one embodiment, the plurality of first insulating layers (62) may include silicon oxide, and the plurality of first mold layers (63) may include silicon nitride.

[0052] A plurality of channel holes (110H) may be formed extending within the horizontal wiring layer (40) through the second pre-laminated structure (70T) and the first pre-laminated structure (60T). Each of the plurality of channel holes (110H) may extend within the horizontal conductive layer (41) through the second pre-laminated structure (70T), the first pre-laminated structure (60T), the support (47), and the horizontal mold layer (43). The sides of the plurality of first mold layers (63), the support (47), and the horizontal mold layer (43) may be exposed on the side walls of the plurality of channel holes (110H).

[0053] Referring to FIG. 15, a plurality of channel structures (110) may be formed within the plurality of channel holes (110H). Each of the plurality of channel structures (110) may include an information storage pattern (120), a channel layer (131), a core pattern (135), and a bit pad (138).

[0054] The channel layer (131) may surround the outer and bottom of the core pattern (135). The information storage pattern (120) may surround the outer and bottom of the channel layer (131). Forming the information storage pattern (120), the channel layer (131), and the core pattern (135) will be described with reference to FIGS. 16 to 23.

[0055] The bit pad (138) may be formed on the information storage pattern (120), the channel layer (131), and the core pattern (135). The bit pad (138) may be in contact with the channel layer (131). The bit pad (138) may include a conductive material such as polysilicon, amorphous silicon, single-crystal silicon, metal, metal nitride, metal oxide, metal silicide, conductive carbon, or a combination thereof.

[0056] Referring to FIGS. 15 and 16, forming the plurality of channel structures (110) may include forming a first sub-blocking layer (122) within the channel hole (110H). The first sub-blocking layer (122) may conformally cover the inner wall of the channel hole (110H). The first sub-blocking layer (122) may be in contact with the sides of the plurality of first insulating layers (62) and the plurality of first mold layers (63). The first sub-blocking layer (122) may include an oxide of a first element. The first element may include Si, Al, or a combination thereof. For example, the first sub-blocking layer (122) may include silicon oxide, aluminum oxide, aluminum silicate, or a combination thereof. The thickness of the first sub-blocking layer (122) may be 0.1 nm to 50 nm (nanometers).

[0057] In one embodiment, the first sub-blocking layer (122) may be formed using an atomic layer deposition (ALD) method. The first sub-blocking layer (122) may be formed using HCD, DCS, BTBAS, DS, MS, TCS, TDMAS, DIPAS, AlCl3, TMA, TDMAA, O, O2, O3, H2O, N2O, NO2, or a combination thereof.

[0058] Referring to FIGS. 15 and 17, a first fixed charge layer (123) may be formed on the first sub-blocking layer (122). The first fixed charge layer (123) may conformally cover the inner wall of the channel hole (110H).

[0059] The first fixed charge layer (123) may include an oxide of a second element and a third element doped into the oxide of the second element. The second element may include Si, Al, or a combination thereof. The second element may be the same as the first element, or the second element may be different from the first element. The third element may be different from the second element. The third element may include Al, Hf, Ti, Y, Li, Na, Mg, K, Ca, Cr, Mn, Fe, Zr, Mo, Pd, Au, Ta, Pb, Sn, In, Si, B, C, N, P, F, S, Se, Br, I, or a combination thereof. For example, the first fixed charge layer (123) may include silicon oxide doped with the third element, aluminum oxide doped with the third element, aluminum silicate doped with the third element, or a combination thereof.

[0060] In one embodiment, the first fixed charge layer (123) may be thinner than the first sub-blocking layer (122). The thickness of the first fixed charge layer (123) may be 0.01 nm to 5 nm (nanometers). The proportion of the third element within the first fixed charge layer (123) may be 0.5 wt% to 5 wt%. In one embodiment, the proportion of the third element within the first fixed charge layer (123) may be 1 wt% or less.

[0061] In one embodiment, the first fixed charge layer (123) can be formed using an atomic layer deposition (ALD) method.

[0062] Referring to FIGS. 15 and 18, a second sub-blocking layer (124) may be formed on the first fixed charge layer (123). The second sub-blocking layer (124) may conformally cover the inner wall of the channel hole (110H). The second sub-blocking layer (124) may be formed in a manner similar to the first sub-blocking layer (122). The second sub-blocking layer (124) may include an oxide of the first element. In one embodiment, the second sub-blocking layer (124) may be thicker than the first sub-blocking layer (122). The thickness of the second sub-blocking layer (124) may be 0.1 nm to 50 nm (nanometers).

[0063] Referring to FIGS. 15 and 19, a second fixed charge layer (125) and a third sub-blocking layer (126) may be formed sequentially on the second sub-blocking layer (124). Each of the second fixed charge layer (125) and the third sub-blocking layer (126) may conformally cover the inner wall of the channel hole (110H). In one embodiment, the first sub-blocking layer (122), the first fixed charge layer (123), the second sub-blocking layer (124), the second fixed charge layer (125), and the third sub-blocking layer (126) may form a blocking layer (121).

[0064] The second fixed charge layer (125) may be formed in a manner similar to the first fixed charge layer (123). The second fixed charge layer (125) may include an oxide of the second element and the third element doped into the oxide of the second element. In one embodiment, the second fixed charge layer (125) may be thinner than the second sub-blocking layer (124). The thickness of the second fixed charge layer (125) may be 0.01 nm to 5 nm (nanometers). The proportion of the third element within the second fixed charge layer (125) may be 0.5 wt% to 5 wt%. In one embodiment, the proportion of the third element within the second fixed charge layer (125) may be 1 wt% or less.

[0065] The third sub-blocking layer (126) may be formed in a manner similar to the second sub-blocking layer (124) or the first sub-blocking layer (122). The third sub-blocking layer (126) may include an oxide of the first element. In one embodiment, the third sub-blocking layer (126) may be thinner than the second sub-blocking layer (124). The thickness of the third sub-blocking layer (126) may be 0.1 nm to 50 nm (nanometers).

[0066] Referring to FIGS. 15 and 20, a charge storage layer (128) may be formed on the blocking layer (121). The charge storage layer (128) may conformally cover the inner wall of the channel hole (110H). In one embodiment, the charge storage layer (128) may include a nitride such as silicon nitride, silicon oxynitride, or a combination thereof.

[0067] Referring to FIGS. 15 and 21, a tunnel insulating layer (129) may be formed on the charge storage layer (128). The tunnel insulating layer (129) may conformally cover the inner wall of the channel hole (110H). The blocking layer (121), the charge storage layer (128), and the tunnel insulating layer (129) may form the information storage pattern (120). In one embodiment, the tunnel insulating layer (129) may include an oxide such as silicon oxide.

[0068] Referring to FIGS. 15 and 22, the channel layer (131) may be formed on the tunnel insulating layer (129). The channel layer (131) may conformally cover the inner wall of the channel hole (110H). The channel layer (131) may include a semiconductor such as polysilicon, amorphous silicon, single-crystal silicon, or a combination thereof.

[0069] Referring to FIGS. 15 and 23, the core pattern (135) may be formed on the channel layer (131). The core pattern (135) may fill the interior of the channel hole (110H). The core pattern (135) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0070] Referring to FIG. 24, a first upper insulating layer (93) may be formed on the second pre-laminated structure (70T). A plurality of separation trenches (91T) may be formed extending within the horizontal wiring layer (40) through the first upper insulating layer (93), the second pre-laminated structure (70T), and the first pre-laminated structure (60T).

[0071] The horizontal mold layer (43) can be removed and a sealing conductive layer (45) can be formed. The sealing conductive layer (45) can penetrate the side of the information storage pattern (120) and come into contact with the channel layer (131). The sealing conductive layer (45) may include a conductive material such as a metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, amorphous silicon, single-crystal silicon, or a combination thereof. In one embodiment, the sealing conductive layer (45) may include a polysilicon layer.

[0072] The plurality of first mold layers (63) can be removed and a plurality of first electrode layers (64) can be formed. The plurality of first insulating layers (62) and the plurality of first electrode layers (64) can form a first laminated structure (60) and a second laminated structure (70). Each of the plurality of first electrode layers (64) may include a single layer or a multi-layer. Each of the plurality of first electrode layers (64) may include a conductive material such as a metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, amorphous silicon, single-crystal silicon, or a combination thereof.

[0073] A plurality of separation insulating layers (91) may be formed within the plurality of separation trenches (91T). Each of the first upper insulating layer (93) and the plurality of separation insulating layers (91) may comprise a single layer or a multi-layer. Each of the first upper insulating layer (93) and the plurality of separation insulating layers (91) may comprise at least two selected from the group consisting of Si, O, N, C, B, and H. Each of the first upper insulating layer (93) and the plurality of separation insulating layers (91) may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), low-K dielectric, high-K dielectric, or a combination thereof.

[0074] Referring once again to FIG. 12, a second upper insulating layer (94) may be formed on the first upper insulating layer (93). A plurality of bit plugs (97) may be formed that penetrate the second upper insulating layer (94) and the first upper insulating layer (93) and are in contact with the plurality of channel structures (110). Each of the plurality of bit plugs (97) may be in contact with the plurality of bit pads (138). A plurality of bit lines (98) that are in contact with the plurality of bit plugs (97) may be formed on the second upper insulating layer (94).

[0075] The second upper insulating layer (94) may comprise a single layer or multiple layers. The second upper insulating layer (94) may comprise at least two selected from the group consisting of Si, O, N, C, B, and H. The second upper insulating layer (94) may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), low-K dielectric, high-K dielectric, or a combination thereof.

[0076] Each of the plurality of bit plugs (97) and the plurality of bit lines (98) may comprise a single layer or a multi-layer. Each of the plurality of bit plugs (97) and the plurality of bit lines (98) may comprise a conductive material such as a metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, amorphous silicon, single-crystal silicon, or a combination thereof.

[0077] Although embodiments according to the technical concept of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. The embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0078] 20: Substructure 21: Substrate 23: Device isolation layer 25: Transistor 27: Lower wiring 31: First lower insulating layer 33: Second lower insulating layer 35: Third lower insulation layer 40: Horizontal wiring layer 41: Horizontal conductive layer 45: Sealing conductive layer 47: Support 60, 70: Laminated structure 62: First insulating layer 64: First electrode layer 64B: Barrier layer 64C: Electrode conductive layer 67: Additional blocking layer 91: Separation insulation pattern 93: First upper insulating layer 94: Second upper insulating layer 97: Bit Plug 98: Bit Line 110: Channel structure 120: Information storage pattern 121: Blocking layer 122, 124, 126: Sub-Blocking Layer 123, 125, 127: Fixed Charge Layer 128: Charge storage layer 129: Tunnel insulation layer 131: Channel Layer 135: Core Pattern 138: Beat Pad

Claims

Claim 1 A stacked structure comprising a plurality of insulating layers and a plurality of electrode layers alternately and repeatedly stacked; and a channel structure penetrating the stacked structure, wherein the channel structure comprises a channel layer; and an information storage pattern between the channel layer and the plurality of electrode layers, wherein the information storage pattern comprises a tunnel insulating layer between the channel layer and the plurality of electrode layers; a charge storage layer between the tunnel insulating layer and the plurality of electrode layers; and a blocking layer between the charge storage layer and the plurality of electrode layers, wherein the blocking layer comprises one or a plurality of sub-blocking layers having an oxide of a first element; A semiconductor device comprising one or more fixed charge layers, wherein each of the one or more fixed charge layers comprises an oxide of a second element and a third element doped into the oxide of the second element, and the ratio of the third element within the one or more fixed charge layers is 0.5 wt% to 5 wt%, and the blocking layer comprises a first sub-blocking layer adjacent to the plurality of electrode layers; a second sub-blocking layer adjacent to the charge storage layer; and a first fixed charge layer between the first sub-blocking layer and the second sub-blocking layer, wherein the thickness of the first fixed charge layer is smaller than the thickness of the first sub-blocking layer or the second sub-blocking layer, and the blocking layer further comprises a second fixed charge layer disposed between the plurality of electrode layers and the first sub-blocking layer, or disposed between the charge storage layer and the second sub-blocking layer. Claim 2 In claim 1, the first element comprises Si, Al, or a combination thereof, the second element comprises Si, Al, or a combination thereof, and the third element comprises Al, Hf, Ti, Y, Li, Na, Mg, K, Ca, Cr, Mn, Fe, Zr, Mo, Pd, Au, Ta, Pb, Sn, In, Si, B, C, N, P, F, S, Se, Br, I, or a combination thereof, wherein the third element is different from the second element. Claim 3 In claim 2, the first and second sub-blocking layers are semiconductor devices comprising silicon oxide, aluminum oxide, aluminum silicate, or a combination thereof. Claim 4 In claim 2, the first and second fixed charge layers comprise a semiconductor device comprising silicon oxide doped with the third element, aluminum oxide doped with the third element, aluminum silicate doped with the third element, or a combination thereof. Claim 5 delete Claim 6 A semiconductor device according to claim 1, wherein the second fixed charge layer is disposed between the second sub-blocking layer and the charge storage layer, and the blocking layer further comprises a third sub-blocking layer between the second fixed charge layer and the charge storage layer. Claim 7 A semiconductor device according to claim 6, wherein the thickness of the second sub-blocking layer is greater than the thickness of the first sub-blocking layer or the third sub-blocking layer. Claim 8 delete Claim 9 A semiconductor device according to claim 1, wherein the thickness of the blocking layer is 0.5 nm to 50 nm (nanometers) and the thickness of each of the first and second fixed charge layers is 0.05 nm to 5 nm (nanometers). Claim 10 A semiconductor device according to claim 1, wherein the ratio of the third element within the first and second fixed charge layers is 1 wt% or less.

Images