Image sensor

Abstract

An image sensor with reduced stabilization time is provided. The image sensor comprises a first row driver, a first row line connected to the first row driver and extending in a first direction, a first pixel, a second pixel, a third pixel, and a fourth pixel connected to the first row line and arranged sequentially in a first direction, a first column line connected to the first pixel and receiving a first output signal from the first pixel, a second column line connected to the second pixel and receiving a second output signal from the second pixel, a third column line connected to the third pixel and receiving a third output signal from the third pixel, a fourth column line connected to the fourth pixel and receiving a fourth output signal from the fourth pixel, a boosting circuit connected to the first to fourth column lines, a second row line connected to the boosting circuit and extending in a first direction, a first boosting driver connected to a first terminal in a direction opposite to the first direction of the second row line, and a second boosting driver connected to a second terminal in the first direction of the second row line, wherein the boosting circuit comprises, from the first boosting driver The voltages of the first and second output signals are adjusted based on the received first boosting enable signal, and the voltages of the third and fourth output signals are adjusted based on the second boosting enable signal received from the second boosting driver.

Description

Technology Field

[0001] The present invention relates to an image sensor. Background Technology

[0002] An image sensing device is one of the semiconductor devices that converts optical information into electrical signals. Such image sensing devices may include Charge Coupled Device (CCD) image sensing devices and Complementary Metal-Oxide Semiconductor (CMOS) image sensing devices.

[0003] A CMOS type image sensor may be abbreviated as CIS (CMOS image sensor). A CIS may have multiple pixels arranged in two dimensions. Each pixel may include, for example, a photodiode (PD). The photodiode can convert incident light into an electrical signal.

[0004] Recently, with the development of the computer and telecommunications industries, the demand for high-performance image sensors is increasing in various fields, including digital cameras, camcorders, smartphones, gaming devices, security cameras, medical micro cameras, and robots. The problem to be solved

[0005] The technical problem that the present invention aims to solve is to provide an image sensor with reduced stabilization time.

[0006] The technical problem that the present invention aims to solve is to provide an image sensor in which dark shading or dark offset is reduced, thereby improving image quality.

[0007] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] An image sensor according to some embodiment of the present invention for achieving the above technical problem comprises: a first row driver; a first row line connected to the first row driver and extending in a first direction; a first pixel, a second pixel, a third pixel, and a fourth pixel connected to the first row line and arranged sequentially in a first direction; a first column line connected to the first pixel and receiving a first output signal from the first pixel; a second column line connected to the second pixel and receiving a second output signal from the second pixel; a third column line connected to the third pixel and receiving a third output signal from the third pixel; a fourth column line connected to the fourth pixel and receiving a fourth output signal from the fourth pixel; a boosting circuit connected to the first to fourth column lines; a second row line connected to the boosting circuit and extending in a first direction; a first boosting driver connected to a first terminal in a direction opposite to the first direction of the second row line; and a second boosting driver connected to a second terminal in the first direction of the second row line. The boosting circuit can adjust the voltages of the first and second output signals based on a first boosting enable signal received from a first boosting driver, and adjust the voltages of the third and fourth output signals based on a second boosting enable signal received from a second boosting driver.

[0009] An image sensor according to some embodiments of the present invention for achieving the above technical problem comprises a row driver, a row line connected to the row driver, a first pixel, a second pixel, and a third pixel connected to the row line, a first column line connected to the first pixel and receiving a first output signal from the first pixel, a second column line connected to the second pixel and receiving a second output signal from the second pixel, a third column line connected to the third pixel and receiving a third output signal from the third pixel, a first boosting circuit connected to the first column line and adjusting the voltage of the first output signal, a second boosting circuit connected to the second column line and adjusting the voltage of the second output signal, and a third boosting circuit connected to the third column line and adjusting the voltage of the third output signal, wherein the third pixel is positioned between the first and second pixels, the third column line is positioned between the first and second column lines, and the first and second boosting circuits may operate before the third boosting circuit.

[0010] An image sensor according to some embodiment of the present invention for achieving the above technical problem comprises a row driver, a first row line connected to the row driver and extending in a first direction, a first pixel and a second pixel connected to the first row line and arranged sequentially in the first direction, a first column line connected to the first pixel and receiving a first output signal from the first pixel, a second column line connected to the second pixel and receiving a second output signal from the second pixel, a first boosting circuit connected to the first column line, a second boosting circuit connected to the second column line, a second row line connected to the first and second boosting circuits, and a first boosting driver and a second boosting driver respectively connected to both ends of the second row line, wherein the second boosting circuit adjusts the voltage of a second output signal based on a first boosting enable signal received from the first boosting driver in a first mode, and adjusts the voltage of a second output signal based on a second boosting enable signal received from the second boosting driver in a second mode different from the first mode. It is possible.

[0011] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0012] FIG. 1 is a block diagram of an image sensing device according to some embodiments. Figure 2 is a diagram illustrating the conceptual layout of the image sensor of Figure 1. FIG. 3 is a drawing for explaining an image sensor according to some embodiments. Figure 4 is a diagram for explaining the pixels of Figure 3. Figure 5 is an enlarged view of the R1 region of Figure 3. Figure 6 is an enlarged view of the R2 region of Figure 3. FIG. 7 is a flowchart for explaining the operation of an image sensor according to some embodiments. FIG. 8 is a timing diagram for explaining the operation of an image sensor according to some embodiments. FIG. 9 is a timing diagram for explaining the operation of an image sensor according to some embodiments. FIG. 10 is a flowchart for explaining the operation of an image sensor according to some embodiments. FIG. 11 is a drawing of the R2 region to illustrate an image sensor according to some embodiments. FIG. 12 is a timing diagram for explaining the operation of an image sensor according to some embodiments. FIG. 13 is a flowchart for explaining the operation of an image sensor according to some embodiments. FIG. 14 is a drawing for illustrating an image sensor according to some embodiments. FIG. 15 is a block diagram illustrating an electronic device including a multi-camera module according to some embodiments. Figure 16 is a detailed block diagram of the camera module of Figure 15. Specific details for implementing the invention

[0013] Embodiments according to the technical concept of the present invention will be described below with reference to the attached drawings.

[0014] FIG. 1 is a block diagram of an image sensing device according to some embodiments.

[0015] Referring to FIG. 1, the image sensing device (1) may include an image sensor (100) and an image signal processor (900).

[0016] The image sensor (100) can generate an image signal (IMS) by using light to sense an image of a sensing target. In some embodiments, the generated image signal (IMS) may be, for example, a digital signal, but embodiments according to the technical concept of the present invention are not limited thereto.

[0017] The image signal (IMS) can be provided to and processed by an image signal processor (900). The image signal processor (900) receives the image signal (IMS) output from the buffer section (170) of the image sensor (100) and can process or modify the received image signal (IMS) to facilitate display.

[0018] In some embodiments, the image signal processor (900) may perform digital binning on an image signal (IMS) output from an image sensor (100). In this case, the image signal (IMS) output from the image sensor (100) may be a raw image signal from a pixel array (140) without analog binning, or it may be an image signal (IMS) that has already undergone analog binning.

[0019] In some embodiments, the image sensor (100) and the image signal processor (900) may be disposed separately from each other as illustrated. For example, the image sensor (100) may be mounted on a first chip and the image signal processor (900) may be mounted on a second chip and communicate with each other through a predetermined interface. However, the embodiments are not limited thereto, and the image sensor (100) and the image signal processor (900) may be implemented as a single package, such as a multi-chip package (MCP).

[0020] The image sensor (100) may include a control register block (110), a timing generator (120), a row driver (130), a pixel array (140), a read-out circuit (150), a ramp signal generator (160), and a buffer section (170).

[0021] The control register block (110) can control the operation of the image sensor (100) in its entirety. In particular, the control register block (110) can directly transmit operation signals to the timing generator (120), the ramp signal generator (160), and the buffer section (170).

[0022] The timing generator (120) can generate a signal that serves as a reference for the operation timing of various components of the image sensor (100). The operation timing reference signal generated by the timing generator (120) can be transmitted to a row driver (130), a read-out circuit (150), a ramp signal generator (160), etc.

[0023] The ramp signal generator (160) can generate and transmit a ramp signal used in the read-out circuit (150). For example, the read-out circuit (150) may include a correlation double sampler (CDS), a comparator, etc., and the ramp signal generator (160) can generate and transmit a ramp signal used in the correlation double sampler, the comparator, etc.

[0024] The buffer section (170) may include, for example, a latch section. The buffer section (170) may temporarily store an image signal (IMS) to be provided externally and may transmit the image signal (IMS) to an external memory or external device.

[0025] The pixel array (140) can sense an external image. The pixel array (140) may include multiple pixels (or unit pixels). The row driver (130) can selectively activate a row of the pixel array (140).

[0026] The read-out circuit (150) can sample a pixel signal provided from the pixel array (140), compare it with a ramp signal, and then convert an analog image signal (data) into a digital image signal (data) based on the comparison result.

[0027] Figure 2 is a diagram illustrating the conceptual layout of the image sensor of Figure 1.

[0028] Referring to FIG. 2, the image sensor (100) may include first and second regions (S1, S2) stacked in a third direction (Z). The first and second regions (S1, S2) may extend in a first direction (X) and a second direction (Y) as illustrated, and blocks illustrated in FIG. 1 may be placed in the first and second regions (S1, S2).

[0029] Although not illustrated in the drawing, a third region in which a memory is placed may be disposed below the second region (S2). In this case, the memory disposed in the third region can receive image data from the first and second regions (S1, S2), store or process it, and retransmit the image data to the first and second regions (S1, S2). In this case, the memory may include memory devices such as a DRAM (dynamic random access memory) device, an SRAM (static random access memory) device, an STT-MRAM (spin transfer torque magnetic random access memory) device, and a flash memory device. For example, if the memory includes a DRAM device, it can receive and process image data at a relatively high speed. Additionally, in some embodiments, the memory may be disposed in the second region (S2).

[0030] The first region (S1) may include a pixel array region (PA) and a first peripheral region (PH1), and the second region (S2) may include a logic circuit region (LC) and a second peripheral region (PH2). The first and second regions (S1, S2) may be stacked vertically in sequence.

[0031] In the first region (S1), the pixel array region (PA) may be an area where the pixel array (140 of FIG. 1) described with reference to FIG. 1 is placed. The pixel array region (PA) may include a plurality of unit pixels arranged in a matrix form. Each pixel may include photodiodes and transistors. A more detailed explanation regarding this will be provided later.

[0032] The first peripheral area (PH1) may include a plurality of pads and may be positioned around the pixel array area (PA). The plurality of pads may transmit and receive electrical signals to and from external devices, etc.

[0033] In the second region (S2), the logic circuit region (LC) may include electronic devices comprising a plurality of transistors. The electronic devices included in the logic circuit region (LC) are electrically connected to the pixel array region (PA) to provide a constant signal to each unit pixel (PX) of the pixel array region (PA) or to control an output signal.

[0034] In the logic circuit area (LC), for example, the control register block (110), timing generator (120), row driver (130), read-out circuit (150), ramp signal generator (160), buffer section (170), etc. described with reference to FIG. 1 may be placed. In the logic circuit area (LC), for example, blocks other than the pixel array (140) in the blocks of FIG. 1 may be placed.

[0035] In the second region (S2), a second peripheral region (PH2) may be disposed in an area corresponding to the first peripheral region (PH1) of the first region (S1), but the embodiments are not limited thereto.

[0036] FIG. 3 is a drawing for illustrating an image sensor according to some embodiments. FIG. 4 is a drawing for illustrating a pixel of FIG. 3.

[0037] Referring to FIGS. 3 and 4, the image sensor (100) may include a row driver (130), row lines (ROW1 to ROWn), column lines (COL1 to COLn), a pixel array (140), a first boosting driver (200), a second boosting driver (210), a plurality of boosting circuits (PB), a ramp signal generator (160), an analog-to-digital converter (151), and a buffer section (170).

[0038] The row driver (130) can drive the pixel array (140) in rows. The row driver (130) can generate a transmission control signal (TS), a reset control signal (RS), a selection control signal (SEL), etc., and provide them to the pixels (PX) of the pixel array (140).

[0039] A pixel array (140) may include a plurality of pixels (PX). Here, the pixels (PX) may be arranged in a grid shape along a plurality of rows and columns. The pixel array (140) may detect light using a plurality of pixels (PX) and convert it into an electrical signal to generate an image signal.

[0040] A plurality of row lines (ROW1 to ROWn) may be extended in a first direction (X). A plurality of row lines (ROW1 to ROWn) may be arranged sequentially in a third direction (Z). For example, a first row line (ROW1) may be spaced apart from a second row line (ROW2) in the third direction (Z). A plurality of column lines (COL1 to COLn) may be extended in the third direction (Z). A plurality of column lines (COL1 to COLn) may be arranged sequentially in a first direction (X). For example, a second column line (COL2) may be spaced apart from a first column line (COL1) in the first direction (X). However, embodiments of the present invention are not limited thereto.

[0041] Multiple pixels (PX) can be connected to row lines (ROW1 to ROWn) and column lines (COL1 to COLn). For example, a single pixel (PX) can be connected to both the first row line (ROW1) and the first column line (COL1). Additionally, a pixel (PX) can be located at the intersection of the first row line (ROW1) and the first column line (COL1). Accordingly, multiple pixels (PX) can be arranged in a grid shape.

[0042] Referring to FIG. 4, a pixel (PX) may include a photodiode (PD), a transfer transistor (TX), a reset transistor (RX), a source follower (SF), and a selection transistor (SX). Here, the pixel (PX) may be a unit constituting a pixel array (140) or a pixel array region (PA).

[0043] One end of the transfer transistor (TX) is connected to a photodiode (PD), and the other end can be connected to a floating diffusion region (FD). The control electrode of the transfer transistor (TX) can receive a transfer control signal (TS). Here, light incident on the image sensor (100) can be converted into an electrical signal through the photodiode (PD). The converted electrical signal can be transmitted to the floating diffusion region (FD) through the transfer transistor (TX).

[0044] One end of the reset transistor (RX) receives the power supply voltage (VDD), and the other end can be connected to the floating diffusion region (FD). The control electrode of the reset transistor (RX) can receive a reset control signal (RS). One end of the source follower (SF) receives the power supply voltage (VDD), and the other end can be connected to one end of the select transistor (SX). The control electrode of the source follower (SF) can be connected to the floating diffusion region (FD). The other end of the select transistor (SX) is connected to column lines (COL1 to COLn), and the control electrode can receive a select control signal (SEL).

[0045] Each control signal (TS, RS, and SEL) controlling each transistor (TX, RX, and SX) can be output from the row driver (130). The output signal (Vout) of the select transistor (SX) can be supplied to the column lines (COL1 to COLn). The output signal (Vout) can be an analog signal. That is, the output signal (Vout) output from the pixel (PX) can be converted into a digital signal through the read-out circuit (150) and can be transmitted to the image signal processor (900) as an image signal (IMS).

[0046] Here, the row lines (ROW1 to ROWn) of FIG. 3 may be signal lines that transmit a transmission control signal (TS), a reset control signal (RS), and a selection control signal (SEL) from the row driver (130) to the pixel (PX). Additionally, the column lines (COL1 to COLn) of FIG. 3 may be signal lines that transmit the output signal (Vout) of the selection transistor (SX).

[0047] Referring again to FIG. 3, a plurality of column lines (COL1 to COLn) can be connected to an analog-to-digital converter (151). Here, the analog-to-digital converter (151) can also be connected to a ramp signal generator (160). That is, the analog-to-digital converter (151) can receive a ramp signal from the ramp signal generator (160) and receive an output signal (Vout) from a plurality of column lines (COL1 to COLn). The analog-to-digital converter (151) can convert the output signal (Vout), which is an analog signal, into a digital signal by performing a CDS (correlation double sampling) operation, a counting operation, etc. Here, the analog-to-digital converter (151) can be included in the read-out circuit (150) of FIG. 1. The read-out circuit (150) including the analog-to-digital converter (151) can be spaced apart from the pixel array (140) in a direction opposite to the third direction (Z). Additionally, a plurality of analog-to-digital converters (151) may be arranged sequentially along a first direction (X). That is, the analog-to-digital converters (151) may be arranged to correspond to each pixel (PX).

[0048] The buffer unit (170) can be connected to a plurality of analog-to-digital converters (151) and can receive a converted digital signal from the analog-to-digital converters (151). The buffer unit (170) can be positioned in a direction opposite to the third direction (Z) from the analog-to-digital converters (151).

[0049] A row line (RL) may be positioned between a pixel array (140) and an analog-to-digital converter (151). The row line (RL) may extend in a first direction (X). For example, the row line (RL) may be formed to be parallel to a plurality of row lines (ROW1 to ROWn). The row line (RL) may include a first terminal in a direction opposite to the first direction (X) and a second terminal in the first direction (X). That is, the row line (RL) may extend along the first direction (X) from the first terminal to the second terminal.

[0050] Multiple boosting circuits (PB) can be connected to multiple column lines (COL1 to COLn). That is, the boosting circuits (PB) can be arranged sequentially in a first direction (X). For example, one boosting circuit (PB) can be placed to correspond to each column line (COL1 to COLn). The boosting circuits (PB) can be connected to a row line (RL). That is, the boosting circuit (PB) can be connected to both the row line (RL) and the column lines (COL1 to COLn). Additionally, the boosting circuit (PB) can be located at the intersection of the row line (RL) and the column lines (COL1 to COLn).

[0051] The first boosting driver (200) can be connected to a low line (RL). Specifically, the first boosting driver (200) can be connected to a first terminal in a direction opposite to the first direction (X) of the low line (RL). Additionally, the first boosting driver (200) can be spaced apart from a plurality of boosting circuits (PB) in a direction opposite to the first direction (X). Additionally, the first boosting driver (200) can be connected to a plurality of boosting circuits (PB) through the low line (RL).

[0052] The second boosting driver (210) can be connected to the low line (RL). Specifically, the second boosting driver (210) can be connected to the second terminal of the low line (RL) in the first direction (X). Additionally, the second boosting driver (210) can be spaced apart from the plurality of boosting circuits (PB) in the first direction (X). The second boosting driver (210) can be connected to the plurality of boosting circuits (PB) through the low line (RL).

[0053] The low line (RL) and the plurality of boosting circuits (PB) may be positioned between the first boosting driver (200) and the second boosting driver (210). That is, while the low driver (130) is positioned spaced apart from the pixel array (140) in a direction opposite to the first direction (X), the first and second boosting drivers (200, 210) may be located on both sides of the low line (RL) and the plurality of boosting circuits (PB). Additionally, the first and second boosting drivers (200, 210) may be positioned symmetrically.

[0054] The first switch (SWC1) can connect the low line (RL) and the first boosting driver (200). The first switch (SWC1) can be positioned between the low line (RL) and the first boosting driver (200). In this embodiment, the first switch (SWC1) may be in a closed state. That is, the first boosting driver (210), the low line (RL), and the boosting circuit (PB) can be connected by the closed first switch (SWC1). However, embodiments of the present invention are not limited thereto.

[0055] The second switch (SWC2) can connect the low line (RL) and the second boosting driver (210). That is, the second switch (SWC2) can be placed between the low line (RL) and the second boosting driver (210). In this embodiment, the second switch (SWC2) may be in a closed state. That is, the second boosting driver (210), the low line (RL), and the boosting circuit (PB) can be connected by the closed second switch (SWC2). However, embodiments of the present invention are not limited thereto.

[0056] The first boosting driver (200) can control the boosting circuit (PB) to turn on or off, and the boosting circuit (PB) can adjust the voltage of the output signal (Vout) output from the column lines (COL1 to COLn) in response to the control of the first boosting driver (200). Additionally, the second boosting driver (210) can control the boosting circuit (PB) to turn on or off, and the boosting circuit (PB) can adjust the voltage of the output signal (Vout) output from the column lines (COL1 to COLn) in response to the control of the second boosting driver (200).

[0057] Figure 5 is an enlarged view of the R1 region of Figure 3. Figure 6 is an enlarged view of the R2 region of Figure 3.

[0058] Referring to FIG. 5, in the R1 region, the first boosting driver (200) can be connected to the first boosting circuit (PB1) and the second boosting circuit (PB2) via a low line (RL). Here, the low line (RL) may include parasitic resistors (R1, R2) and parasitic capacitors (C1, C2). The parasitic resistors (R1, R2) and parasitic capacitors (C1, C2) may be due to the inherent characteristics of the low line (RL). The parasitic resistor (R1) and parasitic capacitor (C1) may exist between the first node (N1), where the first boosting circuit (PB1) and the low line (RL) are connected, and the third node (N3), where the second boosting circuit (PB2) and the low line (RL) are connected. Additionally, the parasitic resistor (R2) and parasitic capacitor (C2) may be connected to the third node (N3).

[0059] The boosting enable signal (VBST_ENa) output from the first boosting driver (200) can be delayed and transmitted by parasitic resistors (R1, R2) and parasitic capacitors (C1, C2). That is, the boosting enable signal (VBST_ENa) can be delayed by an RC delay. For example, the first boosting enable signal (VBST_ENa1) transmitted to the first boosting circuit (PB1) can arrive before the second boosting enable signal (VBST_ENa2) transmitted to the second boosting circuit (PB2). That is, the first boosting circuit (PB1) can operate before the second boosting circuit (PB2).

[0060] The first boosting driver (200) can output a boosting enable signal (VBST_ENa) to the low line (RL) to operate a plurality of boosting circuits (PB). The boosting enable signal (VBST_ENa) can be transmitted along the low line (RL) and may be delayed. The boosting enable signal (VBST_ENa) can be transmitted in the first direction (X), but embodiments of the present invention are not limited thereto.

[0061] The first boosting circuit (PB1) may include a first current source (I1), a second current source (I2), and a first switch (SW1). The first current source (I1) may be connected to a second node (N2) of a first column line (COL1), and the first switch (SW1) may be connected to a second node (N2) of a first column line (COL1). Additionally, the second current source (I2) may be connected to the first switch (SW1). That is, the first switch (SW1) may connect the second current source (I2) and the second node (N2). The first switch (SW1) may operate in response to a first boosting enable signal (VBST_ENa1) transmitted from a low line (RL). That is, when the first boosting enable signal (VBST_ENa1) is applied, the first switch (SW1) may be closed. However, if the first boosting enable signal (VBST_ENa1) is not applied, the first switch (SW1) may be opened.

[0062] The first current source (I1) can generate a constant current, and the second current source (I2) can also generate a constant current. That is, when the first boosting enable signal (VBST_ENa1) is not applied, only the current generated from the first current source (I1) can flow through the second node (N2). However, when the first boosting enable signal (VBST_ENa1) is applied, both the current generated from the first current source (I1) and the second current source (I2) can flow through the second node (N2). As both the current generated from the first current source (I1) and the second current source (I2) flow, the voltage of the first output signal (Vout1) can be adjusted. That is, the first boosting circuit (PB1) can be operated by the first boosting enable signal (VBST_ENa1) output from the first boosting driver (200), and the voltage of the first output signal (Vout1) can be adjusted. At this time, the first column line (COL1) has a capacitor (Ca). When a transmission control signal (TS) or a reset control signal (RS) is applied to the pixel (PX), the voltage of the first output signal (Vout1) can be temporarily increased. After the transmission control signal (TS) or the reset control signal (RS) is applied, the first boosting circuit (PB1) can reduce the increased voltage of the first output signal (Vout1). Specifically, the first boosting circuit (PB1) can boost so that the voltage of the first output signal (Vout1) decreases more quickly.

[0063] The second boosting circuit (PB2) may also include a first current source (I1), a second switch (SW2), and a second current source (I2) connected to the fourth node (N4) of the second column line (COL2). The second switch (SW2) may be turned on or off by a second boosting enable signal (VBST_ENa2). That is, the second boosting circuit (PB2) may boost the voltage of the second output signal (Vout2) so that it decreases more quickly. At this time, the second boosting enable signal (VBST_ENa2) may reach the second boosting circuit (PB2) later than the first boosting enable signal (VBST_ENa1). Accordingly, the second boosting circuit (PB2) may operate later than the first boosting circuit (PB1). The boosting enable signal (VBST_ENa) can then be transmitted along the low line (RL) to the first direction (X).

[0064] Referring to FIG. 6, in the R2 region, the second boosting driver (210) can be connected to the third boosting circuit (PB3) and the fourth boosting circuit (PB4) via a low line (RL). Here, the low line (RL) may include parasitic resistors (R3, R4) and parasitic capacitors (C3, C4). The parasitic resistor (R4) and the parasitic capacitor (C4) may exist between the fifth node (N5), where the third boosting circuit (PB3) and the low line (RL) are connected, and the seventh node (N7), where the fourth boosting circuit (PB4) and the low line (RL) are connected. Additionally, the parasitic resistor (R3) and the parasitic capacitor (C3) may be connected to the fifth node (N5).

[0065] The boosting enable signal (VBST_ENb) output from the second boosting driver (210) can be delayed and transmitted by parasitic resistors (R3, R4) and parasitic capacitors (C3, C4). That is, the boosting enable signal (VBST_ENb) can be delayed by an RC delay. For example, the first boosting enable signal (VBST_ENb1) transmitted to the fourth boosting circuit (PB4) can arrive before the second boosting enable signal (VBST_ENb2) transmitted to the third boosting circuit (PB3). That is, the third boosting circuit (PB3) can operate before the fourth boosting circuit (PB4). Here, the first to fourth boosting circuits (PB1 to PB4) can be arranged sequentially along the first direction (X).

[0066] The first boosting driver (210) can output a boosting enable signal (VBST_ENb) to the low line (RL) to operate a plurality of boosting circuits (PB). The boosting enable signal (VBST_ENb) can be transmitted along the low line (RL) and may be delayed. The boosting enable signal (VBST_ENb) can be transmitted in a direction opposite to the first direction (X), but embodiments of the present invention are not limited thereto.

[0067] The fourth boosting circuit (PB4) may include a first current source (I1), a fourth switch (SW4), and a second current source (I2) connected to the eighth node (N8) of the fourth column line (COL4). The fourth switch (SW4) may be turned on or off by the first boosting enable signal (VBST_ENb1). That is, the fourth boosting circuit (PB4) may boost the voltage of the fourth output signal (Vout4) so ​​that it decreases more quickly.

[0068] The third boosting circuit (PB3) may also include a first current source (I1), a third switch (SW3), and a second current source (I2) connected to the sixth node (N6) of the third column line (COL3). The third switch (SW3) may be turned on or off by a second boosting enable signal (VBST_ENb2). That is, the third boosting circuit (PB3) may boost the voltage of the third output signal (Vout3) so that it decreases more quickly. In this case, the second boosting enable signal (VBST_ENb2) may reach the third boosting circuit (PB3) later than the first boosting enable signal (VBST_ENb1). Accordingly, the third boosting circuit (PB3) may operate later than the fourth boosting circuit (PB4). The boosting enable signal (VBST_ENb) can then be transmitted along the low line (RL) in a direction opposite to the first direction (X).

[0069] The voltage reduction of the first to fourth output signals (Vout1 to Vout4) applied to a plurality of column lines (COL1 to COLn) can be boosted by the boosting enable signal (VBST_ENa) output from the first boosting driver (200) and the boosting enable signal (VBST_ENb) output from the second boosting driver (210). Here, as the boosting enable signal (VBST_ENa) from the first boosting driver (200) is transmitted along the low line (RL) in the first direction (X), and the boosting enable signal (VBST_ENb) from the second boosting driver (210) is transmitted along the low line (RL) in the direction opposite to the first direction (X), the symmetry of the boosting circuit (PB) and the settling time can be improved. A more detailed explanation of this will be provided later.

[0070] FIG. 7 is a flowchart for explaining the operation of an image sensor according to some embodiments. FIG. 8 is a timing diagram for explaining the operation of an image sensor according to some embodiments.

[0071] Referring to FIGS. 3 through 8, the row driver (130) can provide a transmission control signal (TS) to the transmission transistor (TX) (S300). For example, the row driver (130) can provide a transmission control signal (TS) to the transmission transistor (TX) of the pixel (PX), and charge generated from the photodiode (PD) can be transferred to the floating diffusion region (FD). That is, the floating diffusion voltage (VFD) of the floating diffusion region (FD) can be increased. Also, the voltage of the output signal (Vout) of the column lines (COL1 to COLn) receiving the floating diffusion voltage (VFD) from the pixel (PX) can be increased. However, the voltage of the output signal (Vout) can be increased gradually and can maintain a constant voltage after a certain period of time.

[0072] The low driver (130) may stop providing the transmission control signal (TS) (S301). For example, at the first time (t1), the transmission control signal (TS) may not be applied to the transmission transistor (TX). Accordingly, the floating diffusion voltage (VFD) may be reduced. Additionally, the voltage of the output signal (Vout) may be reduced, but may be reduced gradually rather than rapidly.

[0073] The first boosting driver (200) and the second boosting driver (210) can provide boosting enable signals (VBST_ENa, VBST_ENb) to the low line (RL) (S302).

[0074] For example, the first boosting driver (200) outputs a boosting enable signal (VBST_ENa), the first boosting enable signal (VBST_ENa1) may be transmitted to the first boosting circuit (PB1), and the second boosting enable signal (VBST_ENa2) may be transmitted to the second boosting circuit (PB2). Here, the first boosting enable signal (VBST_ENa1) may be applied from the first time (t1) to the third time (t3), and the second boosting enable signal (VBST_ENa2) may be applied from the second time (t2) to the fourth time (t4). Here, the first boosting enable signal (VBST_ENa1) may be transmitted before the second boosting enable signal (VBST_ENa2). That is, the first boosting circuit (PB1) can operate before the second boosting circuit (PB2).

[0075] For example, the second boosting driver (210) outputs a boosting enable signal (VBST_ENb), the first boosting enable signal (VBST_ENb1) may be transmitted to the fourth boosting circuit (PB4), and the second boosting enable signal (VBST_ENb2) may be transmitted to the third boosting circuit (PB3). Here, the first boosting enable signal (VBST_ENb1) may be applied from the first time (t1) to the third time (t3), and the second boosting enable signal (VBST_ENb2) may be applied from the second time (t2) to the fourth time (t4). Here, the first boosting enable signal (VBST_ENb1) may be transmitted before the second boosting enable signal (VBST_ENb2). That is, the fourth boosting circuit (PB4) can operate before the third boosting circuit (PB3).

[0076] The first boosting enable signal (VBST_ENa1) and the first boosting enable signal (VBST_ENb1) can be transmitted to the boosting circuit (PB) for the same amount of time, and the second boosting enable signal (VBST_ENa2) and the second boosting enable signal (VBST_ENb2) can be transmitted to the boosting circuit (PB) for the same amount of time. That is, the second boosting enable signal (VBST_ENa2) and the second boosting enable signal (VBST_ENb2) can be transmitted later than the first boosting enable signal (VBST_ENa1) and the first boosting enable signal (VBST_ENb1). However, embodiments of the present invention are not limited thereto.

[0077] Boosting circuits (PB) can operate based on boosting enable signals (VBST_ENa) and boosting enable signals (VBST_ENb) (S303). Accordingly, the voltage of the output signal (Vout) applied to the column lines (COL1 to COLn) can be stabilized.

[0078] Referring to FIG. 8, the voltage of the first output signal (Vout1) and the voltage of the fourth output signal (Vout4) can be reduced by the first boosting enable signal (VBST_ENa1) and the first boosting enable signal (VBST_ENb1). That is, the voltage of the first output signal (Vout1) and the voltage of the fourth output signal (Vout4) can be reduced more rapidly. Accordingly, the voltage of the first output signal (Vout1) and the voltage of the fourth output signal (Vout4) can be stabilized after the first stabilization time interval (ST1).

[0079] The voltage of the second output signal (Vout2) and the voltage of the third output signal (Vout3) can be reduced by the second boosting enable signal (VBST_ENa2) and the second boosting enable signal (VBST_ENb2). That is, the voltage of the second output signal (Vout2) and the voltage of the third output signal (Vout3) can be reduced more rapidly. Accordingly, the voltage of the second output signal (Vout2) and the voltage of the third output signal (Vout3) can be stabilized after the second stabilization time interval (ST2). Here, the second stabilization time interval (ST2) may be longer than the first stabilization time interval (ST1). That is, the stabilization time interval of the voltage of the output signal (Vout) applied to the column lines (COL1 to COLn) may increase as it moves further away from the boosting driver (200, 210).

[0080] In this case, as the boosting enable signal (VBST_ENa) and the boosting enable signal (VBST_ENb) are transmitted bidirectionally from the first boosting driver (200) and the second boosting driver (210) located on both sides of the low line (RL), the stabilization time interval of the voltage of the output signal (Vout) applied to the column lines (COL1 to COLn) can be reduced overall. Accordingly, the asymmetry of the image sensor (100) can be improved, and the image quality of the image sensor (100) can be improved.

[0081] Additionally, boosting the voltage of the output signal (Vout) may be even more necessary when light is not incident on the photodiode (PD). In this case, as the stabilization time interval of the voltage of the output signal (Vout) is reduced, the dark shading or dark offset of the image sensor (100) may be reduced. Additionally, as the stabilization time interval of the voltage of the output signal (Vout) is reduced, the image sensor (100) may operate at high speed.

[0082] Hereinafter, the operation of the image sensor (100) will be explained with reference to FIG. 9.

[0083] FIG. 9 is a timing diagram for explaining the operation of an image sensor according to some embodiments. For convenience of explanation, parts that overlap with those explained using FIGS. 1 to 8 are briefly explained or omitted.

[0084] Referring to FIG. 9, the row driver (130) can provide a reset control signal (RS) to the reset transistor (RX). For example, the row driver (130) can provide a reset control signal (RS) to the reset transistor (RX) of the pixel (PX). Accordingly, the floating diffusion voltage (VFD) of the floating diffusion region (FD) can be increased. Additionally, the voltage of the output signal (Vout) of the column lines (COL1 to COLn) receiving the floating diffusion voltage (VFD) from the pixel (PX) can be increased. However, the voltage of the output signal (Vout) can be increased gradually and can maintain a constant voltage after a certain period of time.

[0085] The low driver (130) may stop providing the reset control signal (RS). For example, at the first time (t1), the reset control signal (RS) may not be applied to the reset transistor (RX). Accordingly, the floating diffusion voltage (VFD) may be reduced. Additionally, the voltage of the output signal (Vout) may be reduced, but may be reduced gradually rather than rapidly.

[0086] The first boosting driver (200) and the second boosting driver (210) can provide boosting enable signals (VBST_ENa, VBST_ENb) to the low line (RL). Accordingly, the voltages of the first output signal (Vout1) and the fourth output signal (Vout4) can be stabilized during the first stabilization time interval (ST1'), and the voltages of the second output signal (Vout2) and the third output signal (Vout3) can be stabilized during the second stabilization time interval (ST2'). That is, even when a reset control signal (RS) is applied to the pixel (PX), the boosting circuit (PB) can boost the reduction of the voltage of the output signal (Vout) of the column lines (COL1 to COLn).

[0087] Hereinafter, the operation of the image sensor (100) will be explained with reference to FIGS. 10 to 12.

[0088] FIG. 10 is a flowchart for explaining the operation of an image sensor according to some embodiments. FIG. 11 is a diagram of the R2 region for explaining an image sensor according to some embodiments. FIG. 12 is a timing diagram for explaining the operation of an image sensor according to some embodiments. For convenience of explanation, parts that overlap with those explained using FIG. 1 to 9 are briefly explained or omitted.

[0089] Referring to FIG. 10, the low driver (130) may provide a reset control signal (RS) to the reset transistor (RX) or a transmission control signal (TS) to the transmission transistor (TX) (S310). Subsequently, the low driver (130) may stop providing the reset control signal (RS) or the transmission control signal (TS) to the pixel (PX). Here, it is described that the transmission control signal (TS) is provided to the pixel (PX), but embodiments of the present invention are not limited thereto. While the transmission control signal (TS) is provided, the voltage of the output signal (Vout) of the color lines (COL1 to COLn) may increase and become constant.

[0090] The image sensor (100) can determine whether the incident light is greater than a threshold value (S311). For example, the image sensor (100) can determine whether the incident light is greater than a threshold value by using a separate illuminance sensor, etc. However, embodiments of the present invention are not limited thereto, and the image sensor (100) can determine this in other ways.

[0091] When the incident light is not greater than the threshold value (S311-N), the image sensor (100) can operate the first boosting driver (200) and the second boosting driver (210) (S312). That is, the first boosting driver (200) and the second boosting driver (210) can both operate as described with reference to FIGS. 1 to 9. At this time, the first switch (SWC1) and the second switch (SWC2) can be closed. That is, the boosting circuit (PB) can be connected to the first boosting driver (200) through the first switch (SWC1), and the boosting circuit (PB) can be connected to the second boosting driver (210) through the second switch (SWC2).

[0092] When the incident light is greater than the threshold value (S311-Y), the image sensor (100) can operate the first boosting driver (200) (S313). That is, the second boosting driver (210) may not operate, and only the first boosting driver (200) may operate. When the incident light is greater than the threshold value, stabilization of the voltage of the output signal (Vout) may be less important. Accordingly, only the first boosting driver (200) may be used, and dark shading and dark offset may not occur.

[0093] Referring to FIG. 11, the second switch (SWC2) may be in an open state. That is, the second boosting driver (210) may not be connected to the low line (RL). Although not shown in the drawing, the first switch (SWC1) may be in a closed state. That is, all boosting circuits (PB) may be connected to the first boosting driver (200) through the first switch (SWC1) and the low line (RL). That is, the boosting circuits (PB) may be operated by a boosting enable signal (VBST_ENa) output from the first boosting driver (200). At this time, the boosting enable signal (VBST_ENa) may be transmitted only in the first direction (X) along the low line (RL). In this specification, only the first boosting driver (200) is described as being connected to the low line (RL), but embodiments of the invention are not limited thereto. For example, only the second boosting driver (210) can be connected to the low line (RL). In this case, the second switch (SWC2) can be in a closed state and the first switch (SWC1) can be in an open state.

[0094] The third boosting circuit (PB3) and the fourth boosting circuit (PB4) may be placed adjacent to the second boosting driver (210). However, the third boosting circuit (PB3) and the fourth boosting circuit (PB4) may not be connected to the second boosting driver (210) but may be connected to the first boosting driver (200).

[0095] Referring to FIGS. 11 and 12, the third boosting circuit (PB3) can receive a boosting enable signal (VBST_ENa). The boosting enable signal (VBST_ENa) can be delayed by a parasitic resistor (R3) and a parasitic capacitor (C3). Accordingly, the third boosting circuit (PB3) can receive a third boosting enable signal (VBST_ENa3). At this time, the third boosting enable signal (VBST_ENa3) can be delivered later than the first boosting enable signal (VBST_ENa1) and the second boosting enable signal (VBST_ENa2). Accordingly, the third stabilization time interval (ST3) of the voltage of the third output signal (Vout3) can be longer than the first stabilization time interval (ST1) and the second stabilization time interval (ST2).

[0096] The fourth boosting circuit (PB4) can receive a boosting enable signal (VBST_ENa). The boosting enable signal (VBST_ENa) can be delayed by a parasitic resistor (R4) and a parasitic capacitor (C4). Accordingly, the fourth boosting circuit (PB4) can receive a fourth boosting enable signal (VBST_ENa4). At this time, the fourth boosting enable signal (VBST_ENa4) may be delivered later than the first boosting enable signal (VBST_ENa1), the second boosting enable signal (VBST_ENa2), and the third boosting enable signal (VBST_ENa3). Accordingly, the fourth stabilization time interval (ST4) of the voltage of the fourth output signal (Vout4) may be larger than the first stabilization time interval (ST1), the second stabilization time interval (ST2), and the third stabilization time interval (ST3).

[0097] The operation of the image sensor (100) will be explained below with reference to FIG. 13.

[0098] FIG. 13 is a flowchart illustrating the operation of an image sensor according to some embodiments. For convenience of explanation, parts that overlap with those described using FIG. 1 to FIG. 12 are briefly explained or omitted.

[0099] Referring to FIG. 13, the low driver (130) may provide a reset control signal (RS) to the reset transistor (RX) or a transmission control signal (TS) to the transmission transistor (TX) (S320). Subsequently, the low driver (130) may stop providing the reset control signal (RS) or the transmission control signal (TS) to the pixel (PX). While the transmission control signal (TS) or the reset control signal (RS) is being provided, the voltage of the output signal (Vout) of the color lines (COL1 to COLn) may increase and become constant.

[0100] The image sensor (100) can determine whether the number of pixels (PX) is greater than a threshold value (S321). For example, the image sensor (100) can determine whether the pixel array (140) contains pixels (PX) greater than or equal to the threshold value.

[0101] When the number of pixels (PX) is greater than the threshold value (S321-Y), the image sensor (100) can determine whether the operating speed is greater than the threshold value (S322). For example, the image sensor (100) can determine whether the speed of the signal output from the row driver (130) is greater.

[0102] When the operating speed of the image sensor (100) is greater than the threshold value (S322-Y), the image sensor (100) can operate the first boosting driver (200) and the second boosting driver (210) (S323). That is, the first boosting driver (200) and the second boosting driver (210) can both operate as described with reference to FIGS. 1 to 9. In other words, when the number of pixels (PX) of the image sensor (100) is large and the operating speed is large, the image sensor (100) can use both the first boosting driver (200) and the second boosting driver (210) to boost the reduction of the voltage of the output signal (Vout) of the column lines (COL1 to COLn).

[0103] If the number of pixels (PX) is not greater than the threshold value (S321-N) or if the operating speed of the image sensor (100) is not greater than the threshold value (S322-N), the image sensor (100) can operate the first boosting driver (200) (S324). That is, the second boosting driver (210) may not operate, and only the first boosting driver (200) may operate.

[0104] Hereinafter, an image sensor (100) will be described with reference to FIG. 14.

[0105] FIG. 14 is a drawing for explaining an image sensor according to some embodiments. For convenience of explanation, parts that overlap with those explained using FIG. 1 to FIG. 13 are briefly explained or omitted.

[0106] Referring to FIG. 14, the image sensor (100) may include a row driver (132). Here, the row driver (132) may be different from the row driver (130). The row driver (132) may be spaced apart from the pixel array (140) in a first direction (X). The row driver (132) may be connected to a plurality of row lines (ROW1 to ROWn). That is, one end of the plurality of row lines (ROW1 to ROWn) may be connected to the row driver (130), and the other end of the plurality of row lines (ROW1 to ROWn) may be connected to the row driver (132). The row driver (132) may output control signals to the plurality of row lines (ROW1 to ROWn) and drive the image sensor (100). Additionally, the low driver (132) may be located on the same side as the second boosting driver (210).

[0107] Hereinafter, an electronic device (2000) according to several other embodiments will be described with reference to FIGS. 15 and 16.

[0108] FIG. 15 is a block diagram illustrating an electronic device including a multi-camera module according to some embodiments. FIG. 16 is a detailed block diagram of the camera module of FIG. 15. For convenience of explanation, parts that overlap with those described using FIG. 1 to FIG. 14 are briefly described or omitted.

[0109] Referring to FIG. 15, the electronic device (2000) may include a camera module group (2100), an application processor (2200), a PMIC (2300), an external memory (2400), and a display (2500).

[0110] The camera module group (2100) may include a plurality of camera modules (2100a, 2100b, 2100c). Although the drawing shows an embodiment in which three camera modules (2100a, 2100b, 2100c) are arranged, the embodiments are not limited thereto. In some embodiments, the camera module group (2100) may be modified to include only two camera modules. Also, in some embodiments, the camera module group (2100) may be modified to include n camera modules (where n is a natural number greater than or equal to 4).

[0111] Here, one of the three camera modules (2100a, 2100b, 2100c) may include an image sensor (100) described using FIGS. 1 to 14. That is, the image sensor (100) of the camera module (2100a, 2100b, 2100c) may include both a first boosting driver (200) and a second boosting driver (210).

[0112] Hereinafter, with reference to FIG. 16, the detailed configuration of the camera module (2100b) will be described in more detail, but the following description may be applied equally to other camera modules (2100a, 2100c) according to the embodiment.

[0113] Referring to FIG. 16, the camera module (2100b) may include a prism (2105), an optical path folding element (OPFE, hereinafter referred to as "OPFE") (2110), an actuator (2130), an image sensing device (2140), and a storage unit (2150).

[0114] The prism (2105) can modify the path of light (L) incident from the outside by including a reflective surface (2107) of a light-reflecting material.

[0115] In some embodiments, the prism (2105) can change the path of light (L) incident in a first direction (X) to a second direction (Y) perpendicular to the first direction (X). Additionally, the prism (2105) can change the path of light (L) incident in the first direction (X) to a second direction (Y) perpendicular to the first direction (X) by rotating the reflective surface (2107) of the light-reflecting material in direction A around the central axis (2106) or by rotating the central axis (2106) in direction B. At this time, the OPFE (2110) can also move to a third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

[0116] In some embodiments, as illustrated, the maximum rotation angle in the A direction of the prism (2105) may be 15 degrees or less in the plus (+) A direction and greater than 15 degrees in the minus (-) A direction, but the embodiments are not limited thereto.

[0117] In some embodiments, the prism (2105) can move in the plus (+) or minus (-) B direction by about 20 degrees, or between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement can be moved by the same angle in the plus (+) or minus (-) B direction, or by a nearly similar angle within a range of about 1 degree.

[0118] In some embodiments, the prism (2105) can move the reflective surface (2106) of the light-reflecting material in a third direction (e.g., Z direction) parallel to the extension direction of the central axis (2106).

[0119] OPFE (2110) may include, for example, groups of m (where m is a natural number) optical lenses. The m lenses can be moved in a second direction (Y) to change the optical zoom ratio of the camera module (2100b). For example, when the basic optical zoom ratio of the camera module (2100b) is Z, moving the m optical lenses included in the OPFE (2110) may change the optical zoom ratio of the camera module (2100b) to an optical zoom ratio of 3Z or 5Z or more.

[0120] The actuator (2130) can move the OPFE (2110) or the optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator (2130) can adjust the position of the optical lens so that the image sensor (2142) is positioned at the focal length of the optical lens for accurate sensing.

[0121] The image sensing device (2140) may include an image sensor (2142), control logic (2144), and memory (2146). The image sensor (2142) may sense an image of a sensing target using light (L) provided through an optical lens. In some embodiments, the image sensor (2142) may include the image sensor (100) described above.

[0122] The control logic (2144) can control the overall operation of the camera module (2100b). For example, the control logic (2144) can control the operation of the camera module (2100b) according to a control signal provided through the control signal line (CSLb).

[0123] The memory (2146) can store information necessary for the operation of the camera module (2100b), such as correction data (2147). The correction data (2147) may include information necessary for the camera module (2100b) to generate image data using light (L) provided from the outside. The correction data (2147) may include, for example, information regarding the degree of rotation described above, information regarding the focal length, information regarding the optical axis, etc. If the camera module (2100b) is implemented in the form of a multi-state camera in which the focal length changes according to the position of the optical lens, the correction data (2147) may include focal length values ​​for each position (or state) of the optical lens and information related to auto-focusing.

[0124] The storage unit (2150) can store image data sensed through the image sensor (2142). The storage unit (2150) may be placed outside the image sensing device (2140) and may be implemented in a stacked form with the sensor chip constituting the image sensing device (2140). In some embodiments, the storage unit (2150) may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiments are not limited thereto.

[0125] Referring to FIG. 15 and FIG. 16 together, in some embodiments, each of the plurality of camera modules (2100a, 2100b, 2100c) may include an actuator (2130). Accordingly, each of the plurality of camera modules (2100a, 2100b, 2100c) may include identical or different correction data (2147) according to the operation of the actuator (2130) included therein.

[0126] In some embodiments, one of the plurality of camera modules (2100a, 2100b, 2100c) camera module (e.g., 2100b) is a camera module in the form of a folded lens including the previously described prism (2105) and OPFE (2110), and the remaining camera modules (e.g., 2100a, 2100c) may be camera modules in the form of a vertical camera module that do not include the prism (2105) and OPFE (2110), but the embodiments are not limited thereto.

[0127] In some embodiments, one of the plurality of camera modules (2100a, 2100b, 2100c) (e.g., 2100c) may be a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In this case, the application processor (2200) may generate a 3D depth image by merging image data provided from this depth camera with image data provided from another camera module (e.g., 2100a or 2100b).

[0128] In some embodiments, at least two of the plurality of camera modules (2100a, 2100b, 2100c) may have different field of view angles. In this case, for example, the optical lenses of at least two of the plurality of camera modules (2100a, 2100b, 2100c) may be different from each other, but are not limited thereto.

[0129] Additionally, in some embodiments, the field of view of each of the plurality of camera modules (2100a, 2100b, 2100c) may be different from each other. In this case, the optical lenses included in each of the plurality of camera modules (2100a, 2100b, 2100c) may also be different from each other, but are not limited thereto.

[0130] In some embodiments, each of the plurality of camera modules (2100a, 2100b, 2100c) may be physically separated from one another. That is, instead of the plurality of camera modules (2100a, 2100b, 2100c) dividing and using the sensing area of ​​a single image sensor (2142), an independent image sensor (2142) may be placed inside each of the plurality of camera modules (2100a, 2100b, 2100c).

[0131] Referring again to FIG. 15, the application processor (2200) may include an image processing device (2210), a memory controller (2220), and an internal memory (2230). The application processor (2200) may be implemented separately from a plurality of camera modules (2100a, 2100b, 2100c). For example, the application processor (2200) and the plurality of camera modules (2100a, 2100b, 2100c) may be implemented separately from each other as separate semiconductor chips.

[0132] The image processing device (2210) may include a plurality of sub-image processors (2212a, 2212b, 2212c), an image generator (2214), and a camera module controller (2216).

[0133] The image processing device (2210) may include a plurality of sub-image processors (2212a, 2212b, 2212c) corresponding to the number of camera modules (2100a, 2100b, 2100c).

[0134] Image data generated from each camera module (2100a, 2100b, 2100c) can be provided to corresponding sub-image processors (2212a, 2212b, 2212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module (2100a) can be provided to sub-image processor (2212a) via image signal line (ISLa), image data generated from camera module (2100b) can be provided to sub-image processor (2212b) via image signal line (ISLb), and image data generated from camera module (2100c) can be provided to sub-image processor (2212c) via image signal line (ISLc). Such image data transmission can be performed, for example, using a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiments are not limited thereto.

[0135] Meanwhile, in some embodiments, a single sub-image processor may be arranged to correspond to a plurality of camera modules. For example, the sub-image processor (2212a) and the sub-image processor (2212c) are not implemented separately as illustrated, but are integrated into a single sub-image processor, and image data provided from the camera module (2100a) and the camera module (2100c) may be selected through a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0136] Image data provided to each sub-image processor (2212a, 2212b, and 2212c) may be provided to an image generator (2214). The image generator (2214) may generate an output image using image data provided from each sub-image processor (2212a, 2212b, and 2212c) according to image generating information or a mode signal.

[0137] Specifically, the image generator (2214) can generate an output image by merging at least some of the image data generated from camera modules (2100a, 2100b, and 2100c) having different viewing angles according to image generation information or a mode signal. Additionally, the image generator (2214) can generate an output image by selecting any one of the image data generated from camera modules (2100a, 2100b, and 2100c) having different viewing angles according to image generation information or a mode signal.

[0138] In some embodiments, the image generation information may include a zoom signal (or zoom factor). Additionally, in some embodiments, the mode signal may be a signal based, for example, on a mode selected by a user.

[0139] When the image generation information is a zoom signal (zoom factor) and each camera module (2100a, 2100b, and 2100c) has a different viewing angle (angle of view), the image generator (2214) can perform different operations depending on the type of zoom signal. For example, if the zoom signal is a first signal, the image data output from the camera module (2100a) and the image data output from the camera module (2100c) can be merged, and then an output image can be generated using the merged image signal and the image data output from the camera module (2100b) that was not used for merging. If the zoom signal is a second signal different from the first signal, the image generator (2214) can generate an output image by selecting one of the image data output from each camera module (2100a, 2100b, and 2100c) without performing such image data merging. However, the embodiments are not limited thereto, and the method of processing image data can be modified as needed.

[0140] In some embodiments, the image generator (2214) receives multiple image data with different exposure times from at least one of a plurality of sub-image processors (2212a, 2212b and 2212c) and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with increased dynamic range.

[0141] The camera module controller (2216) can provide control signals to each camera module (2100a, 2100b, and 2100c). The control signals generated from the camera module controller (2216) can be provided to the corresponding camera modules (2100a, 2100b, and 2100c) through separate control signal lines (CSLa, CSLb, and CSLc).

[0142] One of the plurality of camera modules (2100a, 2100b, and 2100c) may be designated as a master camera (e.g., 2100a) according to image generation information or a mode signal including a zoom signal, and the remaining camera modules (e.g., 2100b and 2100c) may be designated as slave cameras. This information may be included in a control signal and provided to the corresponding camera modules (2100a, 2100b, and 2100c) through separate control signal lines (CSLa, CSLb, and CSLc).

[0143] The camera module operating as a master and slave may be changed according to the zoom factor or operation mode signal. For example, if the field of view of the camera module (2100a) is wider than the field of view of the camera module (2100c) and the zoom factor indicates a low zoom magnification, the camera module (2100c) may operate as a master and the camera module (2100a) may operate as a slave. Conversely, if the zoom factor indicates a high zoom magnification, the camera module (2100a) may operate as a master and the camera module (2100c) may operate as a slave.

[0144] In some embodiments, the control signal provided from the camera module controller (2216) to each camera module (2100a, 2100b, and 2100c) may include a sync enable signal. For example, if the camera module (2100b) is a master camera and the camera modules (2100a, 2100c) are slave cameras, the camera module controller (2216) may transmit a sync enable signal to the camera module (2100b). The camera module (2100b) that receives this sync enable signal may generate a sync signal based on the received sync enable signal and provide the generated sync signal to the camera modules (2100a and 2100c) through a sync signal line (SSL). The camera module (2100b) and camera modules (2100a and 2100c) can be synchronized with this sink signal to transmit image data to the application processor (2200).

[0145] In some embodiments, the control signal provided from the camera module controller (2216) to the plurality of camera modules (2100a, 2100b, and 2100c) may include mode information according to the mode signal. Based on this mode information, the plurality of camera modules (2100a, 2100b, and 2100c) may operate in a first operation mode and a second operation mode with respect to the sensing speed.

[0146] A plurality of camera modules (2100a, 2100b, and 2100c) can, in a first operating mode, generate an image signal at a first speed (e.g., generate an image signal at a first frame rate) and encode it at a second speed higher than the first speed (e.g., encode an image signal at a second frame rate higher than the first frame rate), and transmit the encoded image signal to an application processor (2200). At this time, the second speed may be 30 times or less of the first speed.

[0147] The application processor (2200) stores the received image signal, that is, the encoded image signal, in a memory (2230) provided internally or in a storage (2400) outside the application processor (2200), and subsequently reads the encoded image signal from the memory (2230) or the storage (2400) to decode it, and can display image data generated based on the decoded image signal. For example, a corresponding sub-processor among a plurality of sub-processors (2212a, 2212b, 2212c) of the image processing device (2210) can perform decoding and can also perform image processing on the decoded image signal. For example, image data generated based on the decoded image signal can be displayed on a display (2500).

[0148] A plurality of camera modules (2100a, 2100b, and 2100c) can generate an image signal at a third speed lower than a first speed in a second operation mode (e.g., generate an image signal at a third frame rate lower than a first frame rate) and transmit the image signal to an application processor (2200). The image signal provided to the application processor (2200) may be an unencoded signal. The application processor (2200) may perform image processing on the received image signal or store the image signal in memory (2230) or storage (2400).

[0149] The PMIC (2300) can supply power, such as power voltage, to each of the plurality of camera modules (2100a, 2100b and 2100c). For example, the PMIC (2300) can supply first power to the camera module (2100a) through a power signal line (PSLa), supply second power to the camera module (2100b) through a power signal line (PSLb), and supply third power to the camera module (2100c) through a power signal line (PSLc), under the control of the application processor (2200).

[0150] The PMIC (2300) can generate power corresponding to each of the plurality of camera modules (2100a, 2100b, and 2100c) and adjust the power level in response to a power control signal (PCON) from the application processor (2200). The power control signal (PCON) may include power adjustment signals for each operating mode of the plurality of camera modules (2100a, 2100b, and 2100c). For example, the operating mode may include a low power mode, and in this case, the power control signal (PCON) may include information about the camera module operating in the low power mode and the power level being set. The power levels provided to each of the plurality of camera modules (2100a, 2100b, and 2100c) may be the same or different from each other. Additionally, the power level may be changed dynamically.

[0151] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0152] 1: Image sensing device 100: Image sensor 130: Raw driver 140: Pixel array 200: 1st Boosting Driver 210: 2nd Boosting Driver PB: Boosting circuit

Claims

Claim 1 A first row driver; a first row line connected to the first row driver and extending in a first direction; a first pixel, a second pixel, a third pixel, and a fourth pixel connected to the first row line and arranged sequentially in the first direction; a first column line connected to the first pixel and receiving a first output signal from the first pixel; a second column line connected to the second pixel and receiving a second output signal from the second pixel; a third column line connected to the third pixel and receiving a third output signal from the third pixel; a fourth column line connected to the fourth pixel and receiving a fourth output signal from the fourth pixel; a boosting circuit connected to the first to fourth column lines; a second row line connected to the boosting circuit and extending in the first direction; a first boosting driver connected to a first terminal in a direction opposite to the first direction of the second row line, wherein the first boosting driver outputs a first boosting enable signal; An image sensor comprising a second boosting driver connected to a second terminal of the first direction of the second low line, the second boosting driver outputting a second boosting enable signal, wherein the boosting circuit adjusts the voltage of the first and second output signals based on the first boosting enable signal received from the first boosting driver, and adjusts the voltage of the third and fourth output signals based on the second boosting enable signal received from the second boosting driver, wherein either the first boosting enable signal or the second boosting enable signal is delayed compared to the other of the first boosting enable signal or the second boosting enable signal, and thus adjusting the voltage of at least one output signal among the first to fourth output signals is delayed compared to the other three output signals among the first to fourth output signals. Claim 2 An image sensor according to claim 1, further comprising an analog-to-digital converter connected to the first to fourth column lines, receiving the first to fourth output signals, and converting the received first to fourth output signals into digital signals. Claim 3 In paragraph 2, the boosting circuit is an image sensor positioned between the first to fourth pixels and the analog-to-digital converter. Claim 4 In claim 1, the boosting circuit includes a first current source connected to the first column line, a first switch connected to the first column line, and a second current source connected to the first switch, and the first switch is an image sensor that operates in response to the first boosting enable signal transmitted through the second row line. Claim 5 An image sensor according to claim 1, wherein the boosting circuit comprises: a first sub-boosting circuit connected between the first column line and the second row line; a second sub-boosting circuit connected between the second column line and the second row line; a third sub-boosting circuit connected between the third column line and the second row line; and a fourth sub-boosting circuit connected between the fourth column line and the second row line. Claim 6 An image sensor according to claim 5, wherein the time at which the first boosting enable signal is applied to the first sub-boosting circuit is equal to the time at which the second boosting enable signal is applied to the fourth sub-boosting circuit, and the time at which the first boosting enable signal is applied to the second sub-boosting circuit is equal to the time at which the second boosting enable signal is applied to the third sub-boosting circuit. Claim 7 In claim 5, the time at which the second boosting enable signal is applied to the third sub-boosting circuit is earlier than the time at which the first boosting enable signal is applied to the first sub-boosting circuit and the time at which the second boosting enable signal is applied to the first sub-boosting circuit. Claim 8 An image sensor according to claim 1, wherein the first pixel comprises a photoelectric conversion element that receives incident light, and a transmission transistor that connects the photoelectric conversion element and the control electrode of a source follower connected to the first column line, the transmission transistor operates in response to a transmission control signal received from the first row driver, and the first boosting driver outputs the first boosting enable signal after the transmission control signal is applied. Claim 9 In claim 8, the first pixel includes a reset transistor that connects a power supply voltage to a control electrode of the source follower, the reset transistor operates in response to a reset control signal received from the first row driver, and the first boosting driver outputs the first boosting enable signal after the reset control signal is applied. Claim 10 In claim 1, the image sensor further comprises a second row driver connected to the first row line, wherein the first row line and the first to fourth pixels are positioned between the first and second row drivers.

Images