Pad-out structure for xtacking architecture

Abstract

The present disclosure provides a method for manufacturing a semiconductor device. The method may include the step of bonding a first die and a second die face-to-face, wherein the first die may include a substrate, a transistor formed on the front surface of the first die on a semiconductor layer having an insulating layer between the substrate and the semiconductor layer, and a first contact structure on the front surface of the first die extending through the insulating layer. The method may include the steps of exposing the first contact structure from the back surface of the first die, exposing the semiconductor layer by forming a contact hole in the insulating layer from the back surface of the first die, forming a first pad-out structure connected to the first contact structure on the back surface of the first die, and forming a second pad-out structure conductively connected to the semiconductor layer in the contact hole.

Description

Technology Field

[0001] The present application generally describes embodiments related to semiconductor memory devices. Background Technology

[0002] Three-dimensional (3D) NAND flash memory technology has been developed to achieve higher data storage density without requiring smaller memory cells. 3D NAND memory devices typically include array transistors that form vertical memory cell strings and peripheral transistors that form peripheral circuits. In conventional 3D NAND devices, the array transistors and peripheral transistors are processed on the same substrate. However, in the Xtacking architecture, the array substrate containing the array transistors and the peripheral substrate containing the peripheral transistors are stacked face-to-face via a bonding interface, with the transistors sandwiched between the two substrates. Consequently, the Xtacking architecture can achieve higher storage density, a simpler process flow, and shorter cycle times.

[0003] The Xtacking architecture may also include a pad-out structure on the back of the array substrate or peripheral substrate. Thus, external circuitry can provide control signals to a transistor sandwiched between the two substrates via the pad-out structure. The pad-out structure can be manufactured in a through-silicon-contact (TSC) configuration. means of solving the problem

[0004] An aspect of the present disclosure provides a pad-out structure of a semiconductor device of an X-tacking architecture and a method for forming the pad-out structure.

[0005] According to a first embodiment, a semiconductor device of an X-tacking architecture having a pad-out structure is disclosed. The semiconductor device may include a first die and a second die bonded face-to-face. The first die may include an insulating layer on the back surface of the first die, a first contact structure extending from the front surface of the first die through a first portion of the insulating layer, a semiconductor layer on the front surface of a second portion of the insulating layer, and a first transistor formed on the front surface of the semiconductor layer.

[0006] In some embodiments, the first transistor may include a memory cell formed on a semiconductor layer on the front surface of the first die. The memory cell may include a stack of alternating word line layers and insulating layers and a plurality of channel structures extending through the stack. In some embodiments, the first die may further include a plurality of contact structures formed in a stepped region of the stack, and the plurality of contact structures are connected to the word line layers. The stepped region may be on the boundary of the stack or in the middle of the stack. Additionally, the channel structure may include a channel layer surrounded by one or more insulating layers.

[0007] In some embodiments, the second die may include a substrate and peripheral circuits of a memory cell formed on the front surface of the substrate.

[0008] The semiconductor device may also include a first pad-out structure disposed on the back surface of the first die, and the first pad-out structure is electrically connected to the first contact structure. The semiconductor device may further include a second pad-out structure disposed on the back surface of the first die, the second pad-out structure is electrically connected to the semiconductor layer through a contact hole, and the second pad-out structure fills the contact hole.

[0009] The first pad-out structure may include a first portion of the first conductive layer, and the second pad-out structure may include a second portion of the first conductive layer. The first portion of the first conductive layer may be spaced apart from the second portion of the first conductive layer. The first conductive layer may be made of a first metal material. In some embodiments, the first pad-out structure may further include a first portion of the second conductive layer disposed between the first contact structure and the first pad layer. The second pad-out structure may further include a second portion of the second conductive layer disposed between the semiconductor layer and the second pad layer. The first portion of the second conductive layer may be spaced apart from the second portion of the second conductive layer. The second conductive layer may be made of a second metal material. For example, the first metal material is made of aluminum, and the second metal material is made of titanium.

[0010] In some embodiments, the first pad-out structure may be connected to an input / output circuit of a peripheral circuit through a first contact structure, a bonding interface between the first die and the second die, and a corresponding second contact structure of the second die. The peripheral circuit may be connected to a memory cell through a corresponding third contact structure of the first die, a bonding interface, and a corresponding fourth contact structure of the second die. The second pad-out structure may be configured to provide an array common source to the memory cell.

[0011] In an alternative embodiment, the second die may further include a memory cell formed on the front surface of the substrate, and the first transistor may include a peripheral circuit of the memory cell formed on the front surface of the substrate. Additionally, the first pad-out structure may be connected to the input / output circuit of the peripheral circuit through the first contact structure, and the peripheral circuit may be connected to the memory cell through the corresponding contact structure of the first die, the bonding interface between the first die and the second die, and the corresponding contact structure of the second die.

[0012] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device of an X-tacking architecture having a pad-out structure is provided. The method may include the step of bonding a first die and a second die face-to-face, wherein the first die comprises a first substrate, an insulating layer on the face side of the first substrate, a first contact structure on the face side of the first die extending through a first portion of the insulating layer, and a semiconductor layer on the face side of the second portion of the insulating layer.

[0013] In some embodiments, the first die may further include a memory cell formed on the front surface of a semiconductor layer, and the second die may include a peripheral circuit of the memory cell on the front surface of the second substrate. In some embodiments, the step of bonding the first die and the second die face-to-face may include bonding a first bonding structure connected to a first contact structure of the first die with a second bonding structure connected to an input / output circuit of the peripheral circuit of the second die.

[0014] In an alternative embodiment, the second die may include a memory cell disposed on the front of the second die, and the first die may further include peripheral circuits of the memory cell.

[0015] This method may further include the step of exposing a first contact structure from the back surface of a first die by removing a first substrate from the back surface of a first die. In some embodiments, this method may further include the step of removing an etching stop layer after removing the first substrate, wherein the etching stop layer is sandwiched between the first substrate and an insulating layer.

[0016] This method may further include the steps of forming a contact hole in a second portion of an insulating layer from the back surface of a first die, and forming a first pad-out structure conductively connected to a first contact structure and a second pad-out structure on the contact hole conductively connected to a semiconductor layer on the back surface of the first die, wherein the contact hole exposes the semiconductor layer. In some embodiments, the second pad-out structure may be configured to provide an array common source to a memory cell.

[0017] Additionally, forming a first pad-out structure and a second pad-out structure may include forming a first conductive layer on a first contact structure and a semiconductor layer from the back surface of a first die—the first conductive layer fills the contact hole—and patterning the first conductive layer from the back surface of the first die to form a first pad-out structure conductively connected to the first contact structure and a second pad-out structure conductively connected to the semiconductor layer. In some embodiments, a second conductive layer may be formed on the back surface of an insulating layer, wherein the second conductive layer interfaces the first conductive layer and the first contact structure and interfaces the first conductive layer and the semiconductor layer—and the second conductive layer is patterned using the same photomask as the first conductive layer.

[0018] In some embodiments, the first conductive layer may be made of a first metal material, and the second conductive layer may be made of a second metal material. For example, the first conductive layer comprises at least aluminum, and the second conductive layer comprises at least titanium. Brief explanation of the drawing

[0019] The aspects of the present disclosure are best understood by reading the following detailed description together with the accompanying drawings. In accordance with standard industry practice, various features are not depicted at actual scale. In fact, the dimensions of various features may be enlarged or reduced to clarify the description. FIG. 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure. FIGS. 2 to 8 are cross-sectional views of a semiconductor device at various intermediate stages of manufacturing according to exemplary embodiments of the present disclosure. FIG. 9 is a flowchart of an exemplary process for manufacturing an exemplary semiconductor device according to an embodiment of the present disclosure. Specific details for implementing the invention

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the claimed subject matter. Specific examples of components and arrangements are described below for the sake of brevity. Of course, this is merely illustrative and not limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature do not make direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not affect the relationships between the various embodiments and / or configurations discussed in itself.

[0021] Additionally, spatial terms such as "immediately below," "below," "lower," "above," and "upper" may be used in this specification for convenience of description to describe the relationship between one element or feature and another element(s) or feature(s) as illustrated in the drawings. Spatial terms are intended to include different orientations of the device in use or operation in addition to the orientations illustrated in the drawings. The device may be oriented in other ways (it may be rotated 90 degrees or in other directions), and accordingly, spatial descriptors used in this specification may be interpreted likewise.

[0022] The present disclosure provides a method for forming a pad-out structure of a 3D memory device of an Xtacking architecture. The method may include the steps of bonding a first die and a second die, removing the substrate of the first die, forming contact holes, and forming a pad-out structure. Compared to through-silicon contact (TSC) pads for an Xtacking architecture, the disclosed method eliminates the need for additional dielectric layers and the deposition and etching of TSC metals, thereby simplifying the manufacturing process.

[0023] FIG. 1 is a cross-sectional view of a semiconductor device (100) according to an exemplary embodiment of the present disclosure. As illustrated, the device (100) may include a first die (D1) and a second die (D2) bonded to each other face-to-face (the circuit side is the front, and the substrate side is the back) through a bonding interface (140). The first die (D1) and the second die (D2) may each include bonding structures (141, 142) that are aligned with each other. Additionally, the bonding structure (141) may be electrically connected to the corresponding bonding structure (142).

[0024] As illustrated in FIG. 1, the first die (D1) may include an insulating layer (103) (e.g., silicon oxide), a semiconductor layer (105) (e.g., doped polysilicon) on the front surface of the insulating layer (103), and a first contact structure (121) (e.g., tungsten) formed on the front surface of the insulating layer (103) and extending therethrough.

[0025] The first die (D1) may also include 3D NAND memory cells. For example, a stack of alternating insulating layers (111) and word line layers (112) (also called gate layers) may be disposed on the front surface of the semiconductor layer (105). This stack may include an array region (110) that extends into the semiconductor layer (105) through this stack, in which at least one channel structure (130) is formed. The stack of insulating layers (111) and word line layers (112) and the channel structure (130) may form a stack of transistors, such as an array of vertical memory cell columns. In some examples, the stack of transistors may include memory cells and select transistors, such as one or more lower select transistors and one or more upper select transistors. In some examples, the stack of transistors may also include one or more dummy select transistors.

[0026] The insulating layer (111) may be made of insulating material(s) such as silicon nitride, silicon dioxide, etc. The word line layer (112) may be made of gate stack material such as a high-k gate insulator layer, a metal gate electrode, etc. The channel structure (130) may include a channel layer (131) (e.g., polysilicon) surrounded by one or more insulating layers (132), such as a tunneling layer (e.g., silicon oxide), a charge capture layer (e.g., silicon nitride), and a barrier layer (e.g., silicon oxide) together forming an oxide-nitride-oxide structure surrounding the channel layer (131).

[0027] Additionally, the stack may have a stepped region (120) in which a plurality of second contact structures (122) and third contact structures (123) are formed. The second contact structures (122) are connected to a word line layer (112) that can function as gates and dummy gates of a vertical memory cell column. The third contact structures (123) are connected to a semiconductor layer (105). The device (100) may have various stepped configurations, such as a central stepped implementation, a side stepped implementation, etc.

[0028] In FIG. 1, the first die (D1) may further include a first conductive layer (171) (also referred to as a pad layer) on the back surface of the second conductive layer (161) (also referred to as a liner layer), and the second conductive layer (161) has a first portion (161a) covering the back surface of the first contact structure (121) and a second portion (161b) covering a hole in the insulating layer (103). The first portion (171a) of the first conductive layer and the second portion (171b) of the first conductive layer may be disposed on the back surfaces of the first and second portions of the first conductive layer (161a, 161b) to form a first pad-out structure and a second pad-out structure, respectively. A first portion (171a) of the first conductive layer may be electrically connected to the first contact structure (121), and a second portion (171b) of the first conductive layer may be electrically connected to the semiconductor layer (105). In this example, the first conductive layer (171) is aluminum, and the semiconductor layer (105) is polysilicon. The second conductive layer (161) may be an adhesive layer, such as a titanium layer having a thickness in the range of 10 to 20 nm, disposed between the aluminum and the polysilicon. In some embodiments, the second conductive layer (161) may be formed of titanium silicide at a relatively high temperature (e.g., 500°C or higher). In other examples, the first conductive layer (171) may be made of a different conductive material, and the second conductive layer (161) may be a barrier layer, a seed layer, and / or an adhesive layer. The second conductive layer (161) can also be used to reduce contact resistance. In some embodiments, the second conductive layer (161) may not be necessary.

[0029] In the example of FIG. 1, the first die (D1) may include a 3D memory cell, and the second die (D2) may include peripheral circuits (e.g., an address decoder, a driving circuit, a sensing amplifier, etc.). Generally, the peripheral circuits of the second die (D2) may interface the memory cell with an external circuit. For example, the peripheral circuits receive commands from the external circuit through the first pad-out structures (171a and 161a), provide control signals to the memory cell, receive data from the memory cell, and output data to the external circuit through the first pad-out structures (171a and 161a). Additionally, in some embodiments, the semiconductor layer (105) is connected to the array common source (ACS) of the memory cell array so that the second pad-out structures (171b and 161b) can provide an input / output pad-out structure of the ACS.

[0030] For brevity, the second die (D2) is illustrated with a substrate (191) and two transistors (180) formed thereon. For example, the transistors (180) may form a CMOS (complementary metal oxide semiconductor). The substrate (191) may be any suitable substrate, such as a Si (silicon) substrate, a Ge (germanium) substrate, a SiGe (silicon-germanium) substrate, and / or a SOI (silicon-on-insulator) substrate. The substrate may comprise a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may comprise Si, Ge, or SiGe. The substrate (191) may be a bulk wafer or an epitaxial layer. The first die (D1) initially comprises a substrate on which a semiconductor layer (105) and an insulating layer (103) are disposed. The substrate is removed before forming the pad-out structure (171 and 161).

[0031] In some embodiments, the semiconductor memory device may include a plurality of array dies (e.g., a first die (D1)) and a CMOS die (e.g., a second die (D2)). The plurality of array dies and CMOS dies may be stacked and bonded together. Each array die is connected to a portion of the CMOS die, and the CMOS die may drive the array dies individually or drive them together in a similar manner. Additionally, in some examples, the semiconductor device (100) includes at least one first wafer and a second wafer that are bonded face-to-face. The first die (D1) is placed on the first wafer together with another array die such as D1, and the second die (D2) is placed on the second wafer together with another CMOS die such as D2. The first wafer and the second wafer are bonded together in such a manner that the array die on the first wafer is bonded to the corresponding CMOS die on the second wafer.

[0032] In an alternative embodiment, the first die (D1) may include peripheral circuitry, and the second die (D2) may include 3D memory cells (not shown). Pad-out structures (171 and 161) may still be placed on the back of the first die (D1). Since the input / output signal does not need to be routed through the memory cell array die, the input / output signal path may be shorter than the signal path of FIG. 1.

[0033] FIGS. 2 through 9 are cross-sectional views of a semiconductor device, such as a device (100), at various intermediate stages of manufacturing according to exemplary embodiments of the present disclosure. The device (100) may refer to any suitable device, for example, a memory circuit, a semiconductor chip (or die) having a memory circuit formed on a semiconductor chip, a semiconductor wafer having a plurality of semiconductor dies formed thereon, a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips assembled on a package substrate, etc.

[0034] FIG. 2 illustrates a cross-sectional view of a semiconductor device (200) that ultimately becomes the device (100). It should be understood that FIG. 2 illustrates only a part of the device (200). Similar to the device (100), the device (200) may include a first die (D1)' corresponding to a first die (D1) and a second die (D2) corresponding to a second die (D2) (not shown), which are bonded together through a bonding interface (not shown) corresponding to a bonding interface (140). For simplicity, the bonding structure (141) and cap layer (106) of the first die (D1) in FIG. 1 are omitted in FIG. 2.

[0035] As illustrated, the device (200) may include a substrate (201) (e.g., silicon) on the back side of the first die (D1') and an etching stop layer (202) (e.g., silicon nitride) on the front side of the substrate (201). The device (200) may also include an insulating layer (203) (e.g., silicon oxide) on the front side of the etching stop layer (202), which will eventually become the insulating layer (103) of FIG. 1. In some embodiments, the etching stop layer (202) may not be required.

[0036] As illustrated in FIG. 2, the device (200) has components configured similarly to the corresponding components of the device (100) of FIG. 1. For example, the first contact structure (221), the semiconductor layer (205), the stack of alternating insulating layers (211) and word line layers (212), the array region (210), the step region (220), the channel structure (230), the plurality of second contact structures (222) and the third contact structure (223) are configured similarly to the first contact structure (121), the semiconductor layer (105), the stack of alternating stacked insulating layers (111) and word line layers (112), the array region (110), the step region (120), the channel structure (130), the plurality of second contact structures (122) and the third contact structure (123), respectively. Descriptions of these components have been provided above and are omitted here for brevity.

[0037] FIG. 3 illustrates the device (200) of FIG. 2 after the substrate (201) has been removed from the back surface. Removal of the substrate (201) can be achieved by chemical mechanical polishing (CMP) and / or wet etching. An etching stop layer (202) can be used to determine when the CMP and / or wet etching process should be stopped.

[0038] FIG. 4 illustrates the device (200) of FIG. 3 after a portion of the etching stop layer (202) and the first contact structure (221) has been removed. Consequently, the remaining first contact structure (221) and the insulating layer (203) are exposed from the back side. Similar to FIG. 3, the removal of a portion of the etching stop layer (202) and the first contact structure (221) can be achieved by a CMP process. Alternatively, the etching stop layer (202) may be removed by a first etching process, and a portion of the first contact structure (221) may be removed by a second etching process. In some embodiments, a portion of the first contact structure (221) may not need to be removed. As a result, a portion of the first contact structure (221) will be exposed (not shown). Additionally, although it is shown as extending into the etching stop layer (202), in some embodiments, the first contact structure (221) extends only to the back surface (203') of the insulating layer (203) (not shown). Therefore, any part of the first contact structure (221) may not need to be removed.

[0039] In FIG. 5, a contact hole (251) may be formed in the insulating layer (203) of the device (200) so that a portion of the semiconductor layer (205) is exposed. The contact hole (251) may have a bottom (251') and two side walls (251"). In the example of FIG. 5, the two contact holes (251) are shown to have a trapezoidal shape with a cross-section that widens from the front to the back. It is understood that any number of contact holes (251) may be formed, and that the contact holes (251) may have other shapes, such as a rectangular shape. The contact hole (251) may be formed by an etching process using photoresist, as an etching mask defined by a photolithography process.

[0040] In FIG. 6, a second conductive layer (261), which ultimately becomes the second conductive layer (161) of FIG. 1, may be formed to conformally coat the exposed portions of the exposed first contact structure (221), insulating layer (203), and semiconductor layer (205). As a result, the second conductive layer (261) covers the bottom (251') and sidewall (251") of the contact hole (251). The second conductive layer (261) is made of titanium and may be formed by chemical vapor deposition. The second conductive layer (261) may have a thickness in the range of 10 to 20 nm. In some embodiments, the second conductive layer (261) may not be required, and this step may be omitted.

[0041] In FIG. 7, a first conductive layer (271), which ultimately becomes the first conductive layer (171) of FIG. 1, can be formed from the back surface on the second conductive layer (261), thereby filling the contact hole (251) with the first conductive layer (271). The first conductive layer (271) may be made of aluminum and be a conductive layer formed by chemical vapor deposition. In an example where the second conductive layer (261) is titanium and the semiconductor layer (205) is polysilicon, the titanium may be an adhesive layer between aluminum and polysilicon. Additionally, a concave structure (272) may be formed on the back surface of the first conductive layer (271) by the contact hole (251).

[0042] FIG. 8 illustrates the device (100) of FIG. 7 after removing a portion of the first conductive layer (271) and a portion of the second conductive layer (261). Removing a portion of the first conductive layer (271) and a portion of the second conductive layer (261) can be achieved by etching with a photoresist and / or hard mask layer. As a result, a first portion (271a) of the first conductive layer can be placed over a first portion (261a) of the second conductive layer to form a first pad-out structure, and a second portion (271b) of the first conductive layer can be placed over a second portion (261b) of the second conductive layer to form a second pad-out structure. Similar to the device (100), an external circuit (not shown) can provide a control signal to a peripheral circuit (not shown) of the second die (D2') of the device (200) and receive data therefrom through a first pad-out structure (271a and 261a) connected to a peripheral circuit through a first contact structure (221). Subsequently, the peripheral circuit can interact with a transistor of the first die (D1').

[0043] FIG. 9 is a flowchart of an exemplary process (900) for manufacturing an exemplary semiconductor device such as the device (100) of FIG. 1, the device (200) of FIG. 8, etc. The process (900) begins with step S901, in which a first die and a second die are bonded face-to-face (the circuit side is the front and the substrate side is the back). The first die may include a first substrate, a first transistor formed on the front of the first die of a semiconductor layer having an insulating layer between the first substrate and the semiconductor layer, and a first contact structure on the front of the first die extending through the insulating layer. The second die may include a second substrate having a structure formed on the front of the second die.

[0044] In order to bond the first die to the second die, a plurality of first bonding structures, such as pillars, may be formed on the front surface of the first die, and a plurality of second bonding structures may be formed on the front surface of the second die. The bonding structures may include Cu, Ni, and SnAg. The bonding process is operated at a temperature of 220°C or higher so that the bonding structures melt, and the first bonding structures can be connected to the corresponding second bonding structures. Consequently, the first transistor of the first die can be connected to the structure of the second die through the corresponding bonding structures at the bonding interface and the contact structure of the two dies.

[0045] Additionally, the first transistor may form a vertical memory cell column, and the second die may include peripheral circuitry as illustrated in the example of FIG. 1. In an alternative embodiment, the first transistor may include peripheral circuitry, and the second die may include memory cells.

[0046] In step S902, the first substrate is removed from the back surface of the first die to expose the first contact structure from the back surface of the first die. As a result, the insulating layer is also exposed from the back surface of the first die. In an example where the etching stop layer is sandwiched between the first substrate and the insulating layer, the etching stop layer may also be removed from the back surface of the first die. The removal of the first substrate and the etching stop layer may be achieved by CMP and / or etching.

[0047] In step S903, a contact hole exposing a portion of the semiconductor layer is formed in the insulating layer from the back of the first die. The contact hole has a bottom and two side walls. Photolithography techniques may be used to define a channel hole pattern in the photoresist and / or hard mask layer, and etching techniques may be used to transfer the pattern to the insulating layer and then remove the photoresist and / or hard mask layer.

[0048] In step S904, a first pad-out structure and a second pad-out structure may be formed on the back surface of the first die by two deposition processes, a photolithography process, and two etching processes. First, a conformal liner layer may be formed by the first deposition process, and the liner layer may cover the exposed portions of the first contact structure, the insulating layer, and the semiconductor layer. The liner layer may also cover the bottom and sidewalls of the contact hole. Subsequently, a pad layer may be formed on the liner layer from the back surface by the second deposition process. The pad layer may fill the contact hole and form a concave structure on the back surface by the contact hole. Next, a photolithography process may be performed to define a pad-out pattern of a photoresist and / or hard mask layer that functions as an etching mask. Next, two etching processes may be performed to transfer the pad-out pattern to the pad layer and the liner layer to form the first pad-out structure and the second pad-out structure. In some embodiments, the two etching processes may be replaced with a single etching process. Additionally, the photoresist and / or hard mask layer will be removed.

[0049] As a result, a first pad-out structure is conductively connected to a first contact structure, with a first portion of a liner layer sandwiched between them. Through the first pad-out structure and the first contact structure, an external circuit can be connected to the peripheral circuit of the device. Similarly, a second pad-out structure is formed on a contact hole and conductively connected to a semiconductor layer, with a second portion of a liner layer sandwiched between them. The second pad-out structure can be configured to provide a common source array for memory cells.

[0050] Additionally, in one example where the pad-out structure is aluminum and the semiconductor layer is polysilicon, the liner layer may be made of an adhesive material such as titanium. In other examples, the pad-out structure may be made of other conductive materials, and the liner layer may be a barrier layer, a seed layer, and / or an adhesive layer. The liner layer may also be used to reduce contact resistance. In some embodiments, the liner layer may not be required.

[0051] It should be noted that additional steps may be provided before, during, and after the process (900), and some of the described steps may be replaced, removed, or performed in a different order in additional embodiments of the process (900). For example, the formation of a liner layer may not be necessary. In particular, in step S904, the pad layer having a recessed structure may be flattened by a CMP process prior to the photolithography process defining an etching mask. As a result, the pad-out structure will have a flat surface on the back side. Furthermore, a lift-off process may be used to form the pad-out structure, in which a photolithography process is performed before depositing the liner layer and the pad layer.

[0052] The various embodiments described herein provide several advantages. For example, in a related 3D NAND memory device, the pad-out structure is formed in a TSC configuration, which requires depositing and etching an interlayer dielectric (e.g., silicon oxide, silicon nitride, etc.) and a TSC metal (e.g., tungsten) on the back surface of a first substrate. The disclosed method simplifies the manufacturing process and can form a non-TSC pad-out structure.

[0053] The foregoing describes the features of some embodiments to better enable those skilled in the art to understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or to achieve the same benefits of the embodiments derived from this specification. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications to the present disclosure can be made without departing from the spirit and scope of the present disclosure.

Claims

Claim 1 A semiconductor device comprising a first die including a first insulating layer, a semiconductor layer, and a stack of alternating gate layers and a second insulating layer, wherein the semiconductor layer is located between the first insulating layer and the stack in a first direction, and the first die further comprises a first contact structure extending through at least a portion of the first die in the first direction; a second die bonded to the first die; a first conductive structure connected to the first contact structure; and a second conductive structure connected to the semiconductor layer and spaced apart from the first conductive structure, wherein both the first conductive structure and the second conductive structure are located on the surface of the first insulating layer farther from the semiconductor layer, and the second conductive structure comprises a first portion of the first conductive layer and a first portion of the second conductive layer, wherein the first portion of the second conductive layer is located between the first insulating layer and the first portion of the first conductive layer and between the semiconductor layer and the first A semiconductor device located between the first portions of the conductive layer. Claim 2 A semiconductor device according to claim 1, wherein the second conductive structure includes a concave structure on the surface far from the first insulating layer. Claim 3 A semiconductor device according to claim 2, wherein the first insulating layer includes a contact hole, and in the second conductive structure, a portion within the contact hole is connected to the semiconductor layer. Claim 4 A semiconductor device according to claim 3, wherein the first insulating layer includes contact holes, and portions within each of the contact holes in the second conductive structure are connected to each other. Claim 5 A semiconductor device according to claim 3, wherein the concave structure and the contact hole are arranged correspondingly in the first direction. Claim 6 A semiconductor device according to claim 3, wherein the cross-section of the contact hole parallel to the first direction is trapezoidal. Claim 7 A semiconductor device according to claim 3, wherein the size of the side of the contact hole closer to the semiconductor layer in the second direction is smaller than the size of the side of the contact hole further from the semiconductor layer in the second direction, and the second direction is perpendicular to the first direction. Claim 8 A semiconductor device according to claim 1, wherein the first conductive structure comprises a second portion of the first conductive layer, the first portion of the first conductive layer is spaced apart from the second portion of the first conductive layer, and the first conductive structure comprises a second portion of the second conductive layer between the first contact structure and the second portion of the first conductive layer, the first portion of the second conductive layer is spaced apart from the second portion of the second conductive layer. Claim 9 A semiconductor device according to claim 8, wherein the first insulating layer includes a contact hole, and both the first portion of the first conductive layer and the first portion of the second conductive layer extend into the contact hole, wherein the portion extending into the contact hole in the first portion of the first conductive layer has a trapezoidal cross-section, and the portion extending into the contact hole in the first portion of the second conductive layer surrounds the trapezoidal cross-section. Claim 10 In claim 9, the semiconductor device, wherein the portion extending to the contact hole in the first portion of the second conductive layer contacts the semiconductor layer. Claim 11 A semiconductor device according to claim 8, wherein, in the first direction, the thickness of the first conductive layer is greater than the thickness of the second conductive layer. Claim 12 A semiconductor device according to claim 8, wherein the first conductive layer comprises aluminum and the second conductive layer comprises titanium. Claim 13 A semiconductor device according to claim 1, wherein the stack is located between the semiconductor layer and the second die in the first direction, and the second die includes peripheral circuits. Claim 14 In claim 13, the semiconductor device, wherein the first conductive structure is connected to the peripheral circuit through the first contact structure. Claim 15 A semiconductor device according to claim 1, wherein the stack includes a stepped region in which a second contact structure is formed, and the second contact structure is connected to the gate layer. Claim 16 A semiconductor device according to claim 1, further comprising a third contact structure connected to the semiconductor layer. Claim 17 A semiconductor device according to claim 1, further comprising a channel structure extending to the semiconductor layer through the stack, wherein the second conductive structure overlaps with at least one of the channel structures in the first direction. Claim 18 A method for manufacturing a semiconductor device comprises the steps of: bonding a first die and a second die, wherein the first die comprises a first insulating layer, a first contact structure extending through at least a portion of the first die in a first direction, a semiconductor layer, and a stack of alternating gate layers and a second insulating layer, wherein the semiconductor layer is located between the first insulating layer and the stack in the first direction; forming a first conductive structure, wherein the first conductive structure is connected to the first contact structure; forming a second conductive structure, wherein the second conductive structure is connected to the semiconductor layer and spaced apart from the first conductive structure; and positioning the first conductive structure and the second conductive structure on a surface of the first insulating layer far from the semiconductor layer, wherein the second conductive structure comprises a first portion of the first conductive layer and a first portion of the second conductive layer, and the first portion of the second conductive layer is the first A method located between the insulating layer and the first portion of the first conductive layer and between the semiconductor layer and the first portion of the first conductive layer. Claim 19 In claim 18, the method further comprises the step of forming a contact hole in the first insulating layer—the contact hole exposes the semiconductor layer—and the step of forming the second conductive structure comprises the step of forming the second conductive structure in the contact hole—in the second conductive structure, a portion within the contact hole is connected to the semiconductor layer. Claim 20 In claim 19, the step of forming the second conductive structure comprises: the step of forming a first conductive layer on the semiconductor layer - the first conductive layer fills the contact hole - and the step of forming a second conductive layer on the first conductive layer - the second conductive layer fills the contact hole -.

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