Neuron circuit for determining firing pattern based on parameter and method for controlling the same

Abstract

A neuron circuit that determines a firing pattern according to parameters and a method for controlling the same are disclosed. The neuron circuit includes a membrane circuit that receives a weighted sum of synaptic currents from a synaptic array and an adaptive current from an adaptive circuit; a comparator circuit that controls a pulse generation circuit when the voltage of the membrane circuit exceeds a predetermined threshold voltage; a pulse generation circuit that controls the membrane circuit and the adaptive circuit based on an output signal from the comparator circuit and generates a pulse having a firing pattern; and an adaptive circuit connected to the membrane circuit and the pulse generation circuit to determine the firing pattern of the pulse generation circuit.

Description

Technology Field

[0001] The present disclosure relates to a neuron circuit that determines a firing pattern according to parameters and a method for controlling the same. Background Technology

[0003] Research is being conducted on spiking-based neural networks that mimic the operating principles of biological nervous systems to study the interactions between neurons. As the structure of neural networks becomes more complex, there is a growing demand for neural circuits capable of minimizing hardware complexity and power loss while acquiring spiking firing patterns suitable for research purposes. means of solving the problem

[0005] A neuron circuit according to one embodiment may include: a membrane circuit that receives a weighted summed synaptic current from a synaptic array and receives an adaptive current from an adaptive circuit; a comparator circuit that controls a pulse generation circuit when the voltage of the membrane circuit exceeds a predetermined threshold voltage; a pulse generation circuit that controls the membrane circuit and the adaptive circuit based on an output signal from the comparator circuit and generates a pulse having a firing pattern; and an adaptive circuit connected to the membrane circuit and the pulse generation circuit to determine the firing pattern of the pulse generation circuit.

[0006] The adaptive circuit can transmit an adaptive current to the membrane circuit and determine the ignition pattern based on the adaptive time constant parameter, subthreshold adaptation conductance parameter, and spike-triggered adaptation current parameter of the adaptive circuit.

[0007] The above membrane circuit can receive the adaptive current from the adaptive circuit based on the adaptive time constant parameter of the membrane circuit and the reset voltage parameter of the membrane circuit, and determine the ignition pattern.

[0008] The above membrane circuit and the above adaptive circuit may include a variable resistor element and a capacitor element.

[0009] The variable resistor of the above membrane circuit and the variable resistor of the above adaptive circuit may include PCM (phase change material) or RRAM (resistive random access memory).

[0010] The variable resistor of the above membrane circuit and the variable resistor of the above adaptive circuit may include an IGZO transistor.

[0011] The above pulse generating circuit can perform the operation of controlling the membrane circuit by changing the voltage of the membrane circuit to a reset voltage based on a feedback spike.

[0012] The above pulse generation circuit can perform the operation of controlling the adaptive circuit by charging an adaptive capacitor included in the adaptive circuit based on a feedback spike.

[0013] The above pulse generation circuit may include a plurality of PMOS and a plurality of NMOS.

[0014] The above pulse generation circuit can perform the operation of applying pulses to the adaptive circuit based on the common voltage and the output voltage.

[0015] The above pulse generation circuit may be a digital pulse generation circuit.

[0016] The voltage value of the capacitor element of the above adaptive circuit may be proportional to the voltage value of the capacitor element of the above membrane circuit.

[0017] The capacitor element of the above adaptive circuit can lower the voltage value of the capacitor element of the above membrane circuit.

[0018] A control method for a neuron circuit according to one embodiment may include: receiving parameter values ​​that determine a firing pattern based on a membrane circuit and an adaptive circuit included in the neuron circuit; and outputting a voltage having a spiking firing pattern based on the received parameter values. Brief explanation of the drawing

[0020] Figure 1 is a diagram illustrating a biological neuron and its operation. FIG. 2 is a diagram illustrating an example of a neural network according to one embodiment. Figure 3 is a diagram showing the configuration of a neuron circuit according to one embodiment. FIGS. 4a and FIGS. 4b are drawings for explaining the main parameters of a neuron circuit according to one embodiment. FIG. 5 is a diagram illustrating the operation of a neuron circuit according to one embodiment when the neuron circuit is implemented with analog elements and current is applied from a synapse array. FIG. 6 is a diagram illustrating an example of implementing a variable resistor in a neuron circuit according to one embodiment. FIG. 7 is a diagram illustrating the operation of a neuron circuit according to one embodiment when the neuron circuit is implemented with digital elements and current is applied from a synapse array. FIG. 8 is a flowchart illustrating a method for controlling a neuron circuit according to one embodiment. Specific details for implementing the invention

[0021] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Accordingly, actual implementations are not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or substitutions included in the technical concept described by the embodiments.

[0022] Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component.

[0023] When it is stated that a component is "connected" to another component, it should be understood that it may be directly connected to or joined to that other component, or that there may be other components in between.

[0024] The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, terms such as "comprising" or "having" are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0025] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification.

[0026] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the attached drawings, identical components are given the same reference numeral regardless of the drawing number, and redundant descriptions thereof will be omitted.

[0028] Figure 1 is a diagram illustrating a biological neuron and its operation.

[0029] Referring to FIG. 1, a biological neuron (10) refers to a cell present in the human nervous system and is one of the basic biological computational entities. The human brain contains approximately 100 billion biological neurons and about 100 trillion interconnections located between them.

[0030] A biological neuron (10) is a single cell and comprises a cell body containing a nucleus and various organelles. The various organelles include mitochondria, numerous dendrites radiating from the cell body, and an axon terminating at many branching extensions.

[0031] Generally, axons perform the function of transmitting signals from one neuron to another, while dendrites perform the function of receiving signals from other neurons. For example, when different neurons are connected, a signal transmitted through a neuron's axon can be received by another neuron's dendrite. In this case, signals between neurons are transmitted through specialized connections called synapses, and multiple neurons are connected to form a neural network. Based on the synapse, neurons that secrete neurotransmitters are referred to as pre-synaptic neurons, and neurons that receive information transmitted through neurotransmitters can be referred to as post-synaptic neurons.

[0032] The human brain is capable of learning and remembering vast amounts of information by transmitting and processing various signals through neural networks formed by the interconnection of a large number of neurons. Various attempts are continuously being made to develop processing or computing devices that mimic these biological neural networks to efficiently process such vast amounts of information.

[0033] In this regard, the AdEx neuron model is one of the various types of neuron models proposed to simulate biological neuron models, and corresponds to a neuron model defined as shown in the following mathematical equation 1.

[0034]

[0035] Here can refer to the capacitance of the membrane capacitor included in the membrane circuit included in the neuron model. can refer to the voltage of a capacitor included in a membrane circuit included in a neuron model. This can mean leak reversal potential. This can mean leak conductance. can refer to the current of a membrane capacitor included in a membrane circuit included in a neuron model. can mean adaptive current. can mean the adaptive thalamic constant. ε represents subthreshold adaptation conductance, and b represents spike-triggered adaptation current. When the membrane capacitor voltage exceeds 0mV (exceeds the threshold voltage), the membrane capacitor voltage signifies the idle voltage (reset voltage). This can be, and the adaptive current in the idle state at this time The value can be the sum of the adaptive current and the spike-triggered adaptive current.

[0036] Since the voltage rises rapidly during the rise of the action potential, the coupling of voltage and adaptation in the neuron model can be explained by parameter a, which may also contribute to spike-triggered adaptation. Under the assumption that calcium influx primarily occurs during the action potential of the neuron model, the effect of calcium-dependent potassium channels can be explained by the spike-triggered adaptive current parameter b.

[0037] As shown in Equation 1, unlike the existing Leaky-Integrated-Fire (LIF) neuron, the AdEx neuron model defines a differential equation that expresses the dynamics of the adaptive voltage. The AdEx neuron model is characterized by its ability to express the adaptive voltage of the neuron model by reflecting the dynamics of the membrane potential through the defined differential equation. Through the AdEx neuron model, vw dynamics can be interpreted in phase plane analysis, and various spiking firing patterns can be implemented in the same model by adjusting the parameters.

[0039] FIG. 2 is a diagram illustrating an example of a neural network according to one embodiment.

[0040] Referring to FIG. 2, the neural network (20) is an example of an artificial neural network that mimics the biological neural network described above, and may correspond to a deep neural network (DNN). For convenience of explanation, the neural network (20) is depicted as having two hidden layers, but it may have various numbers of hidden layers. Additionally, in FIG. 2, the neural network (20) is depicted as having a separate input layer (21) for receiving input data, but input data may be input directly into the hidden layer.

[0041] Artificial nodes in layers other than the output layer in the neural network (20) can be connected to artificial nodes in the next layer through links for transmitting output signals. Through these links, values ​​obtained by multiplying the node values ​​of the artificial nodes included in the previous layer by the weights assigned to each link can be input to one artificial node. The node values ​​of the previous layer correspond to axon values, and the weights correspond to synaptic weights. The weights can be referred to as parameters of the neural network (20). The activation function may include sigmoid, hyperbolic tangent (Tanh), and rectified linear unit (ReLU), and non-linearity may be formed in the neural network (20) by the activation function.

[0042] The output of any node (22) included in such a neural network (20) can be represented as shown in Equation 2 below.

[0044]

[0045] Equation 2 is the output value at time t of the i-th node (22) for m input values ​​in an arbitrary layer. It can represent. can represent the output value of the j-th node of the previous layer at time t, and can represent a weight applied to the connection between the j-th node of the previous layer and the i-th node (22) of the current layer. f() can represent an activation function. As shown in Equation 2, for the activation function, the input value and weight The cumulative result of multiplication can be used. In other words, an appropriate input value at the desired time and weight Multiplication and addition operations (MAC operations) can be repeated. In addition to this use, there are various applications that require MAC operations, and for this purpose, a processing unit capable of processing MAC operations in the analog circuit area may be used.

[0046] Neurons in a neural network may include a combination of weights or biases. A neural network may include multiple layers composed of multiple neurons or nodes. A neural network can infer a result to be predicted from an arbitrary input by changing the weights of the neurons through learning.

[0047] Neural networks can include deep neural networks. Neural networks include convolutional neural network (CNN), recurrent neural network (RNN), perceptron, multilayer perceptron, feed forward (FF), radial basis network (RBF), deep feed forward (DFF), long short term memory (LSTM), gated recurrent unit (GRU), auto encoder (AE), variational auto encoder (VAE), and denoising auto (DAE). encoder), SAE (sparse auto encoder), MC (markov chain), HN (hopfield network), BM (boltzmann machine), RBM (restricted boltzmann machine), DBN (deep belief network), DCN (deep convolutional network), DN (deconvolutional network), DCIGN (deep convolutional inverse graphics network), GAN (generative adversarial network), LSM (liquid state machine), ELM (extreme learning machine), ESN (echo state network), DRN (deep residual network), DNC (differentiable neural computer), It may include NTM (neural turning machine), CN (capsule network), KN (kohonen network) and AN (attention network).

[0049] Figure 3 is a diagram showing the configuration of a neuron circuit according to one embodiment.

[0050] Various studies based on the AdEx neuron model described in Fig. 1 have been conducted. When the circuit was implemented using only analog components without digital components, it was possible to implement an analog neuron circuit that generates an adaptation or adaptive firing pattern, which is a phenomenon where the time interval between output spikes increases due to feedback of output spikes. Additionally, it was possible to implement an analog neuron circuit that controls the threshold voltage through a method of controlling the potential of an adaptive capacitor by reflecting it in a MOSFET that implements the input synaptic current and controlling it via the back gate effect, as well as through programming of a PCM (phase change memory). However, unlike the method of subtracting the adaptive voltage from the membrane potential as in the AdEx neuron model, there were problems in that it was not possible to generate different spiking firing patterns in the same circuit, and it was also impossible to program the neuron's operation to match a specific signal.

[0051] By combining digital and analog components, it was possible to implement hybrid circuits that represent all necessary circuit elements, such as exponential circuits. However, there was a problem in that the neuromorphic chips required for circuit implementation demanded hundreds to thousands of neurons, making them unsuitable for the overall circuit's space and power efficiency.

[0052] Furthermore, existing CMOS-based analog neuron circuits required increasing the size of capacitors due to MOSFET leakage current, which caused spatial limitations when implemented in hardware. Due to the nature of neuron models that store and operate with precise potentials only temporarily, leakage current through CMOS could cause critical information loss in neuromorphic circuits.

[0053] By implementing specific parts as programmable resistors through a neuron circuit according to one embodiment of the present disclosure, the adaptive circuit , of membrane circuits , reset voltage Parameters such as can be programmed. Such programming can be implemented not only through software but also through the hardware of the device included in the neuron circuit itself. Through the programming of parameters, an analog neuron circuit platform capable of implementing various spiking firing patterns, including adaptive firing patterns and bursting firing patterns, within the same circuit can be implemented. Furthermore, the neuron circuit according to one embodiment of the present disclosure is a circuit designed around NMOS, and may include an IGZO TFT as a component of the NMOS. The neuron circuit can minimize leakage current by implementing the point where leakage current can flow in the capacitor with an IGZO transistor. By minimizing leakage current, the size of the capacitor can be reduced, thereby increasing space efficiency when implemented in hardware, and the stored charge can be maintained for a relatively long period in accordance with biological time units (maximum ms).

[0054] It is expected that a neuron circuit according to one embodiment can be used to control spike encoding and neural plasticity of a neuromorphic system by changing the internal properties of the neuron depending on the neuromorphic computing structure or a specific signal (e.g., a neuromodulator).

[0055] Referring to FIG. 3, a neuron circuit (300) according to one embodiment may include a membrane circuit (320) that receives a weighted summed synaptic current from a synaptic array (310) and receives an adaptive current from an adaptive circuit (350). The membrane circuit (320) may receive the adaptive current from the adaptive circuit (350) and determine a firing pattern based on an adaptive time constant parameter of the membrane circuit (320) and a reset voltage parameter of the membrane circuit (320).

[0056] The neuron circuit (300) may further include a comparator circuit (330) that controls a pulse generation circuit (340) when the voltage of the membrane circuit (320) exceeds a predetermined threshold voltage. The neuron circuit (300) may further include a pulse generation circuit (340) that controls the membrane circuit (320) and the adaptive circuit (350) based on an output signal from the comparator circuit (330) and generates a pulse having a firing pattern. The pulse generation circuit (340) may perform an operation of controlling the membrane circuit (320) by changing the voltage of the membrane circuit (320) to a reset voltage based on a feedback spike. The pulse generation circuit (340) may perform an operation of controlling the adaptive circuit (350) by charging an adaptive capacitor included in the adaptive circuit (350) based on a feedback spike. The pulse generation circuit (340) may include a plurality of PMOS and a plurality of NMOS. The pulse generation circuit (340) may perform the operation of applying a pulse to the adaptive circuit (350) based on a common voltage and an output voltage. The pulse generation circuit (340) may be a digital pulse generation circuit.

[0057] The neuron circuit (300) may further include an adaptive circuit (350) connected to the membrane circuit (320) and the pulse generation circuit (340) to determine the firing pattern of the pulse generation circuit (340). The adaptive circuit (350) can transmit an adaptive current to the membrane circuit (320) and determine the firing pattern based on the adaptive time constant parameter, subthreshold adaptation conductance parameter, and spike-triggered adaptation current parameter of the adaptive circuit (350).

[0058] The adaptive circuit (350) and membrane circuit (320) of the neuron circuit (300) may include a variable resistor element and a capacitor element. Synaptic current from the synapse array (310) is applied to the membrane circuit (320), and the voltage of the membrane capacitor of the membrane circuit (320) may increase. When the voltage of the membrane capacitor reaches a specific threshold voltage, a spike may be generated from the pulse generation circuit (340) based on a signal from the threshold voltage comparator circuit (330). When a feedback spike is generated from the pulse generation circuit (340) by the spike from the pulse generation circuit (340), the voltage of the membrane capacitor of the membrane circuit (320) may be changed to a reset voltage. Additionally, if a feedback spike is generated from the pulse generating circuit (340) by a spike from the pulse generating circuit (340), the voltage of the adaptive capacitor of the adaptive circuit (350) may increase through the feedback spike. The voltage value of the capacitor element of the adaptive circuit (350) may be proportional to the voltage value of the membrane capacitor element of the membrane circuit (320). The capacitor element of the adaptive circuit (350) may lower the voltage value of the capacitor element of the membrane circuit (320).

[0060] FIGS. 4a and FIGS. 4b are drawings for explaining the main parameters of a neuron circuit according to one embodiment.

[0061] Referring to FIG. 4a, the configuration of the neuron circuit (400) can be examined. The membrane circuit (420) and the adaptive circuit (450) of the neuron circuit (400) may include a variable resistor (421; 451) and a capacitor element (422; 452). The variable resistor (421; 451) of the membrane circuit (420) and the adaptive circuit (450) of the neuron circuit (400) may include a non-volatile memory such as PCM (phase change material) or RRAM (resistive random access memory). The variable resistor (421; 451) of the membrane circuit (420) and the adaptive circuit (450) of the neuron circuit (400) may include an IGZO transistor which is an NMOS transistor.

[0062] IGZO is a material used as the active layer of a thin film transistor. It is a compound composed of four atoms—indium, gallium, zinc, and oxygen—in a fixed ratio, and is a material with semiconductor characteristics that exhibit high electron mobility. The IGZO transistor used in the neuron circuit (400) can be implemented by applying a bias voltage to the gate node of the transistor. In the case of the IGZO transistor, the off-state current is small, so when a specific bias voltage is applied to the gate, a mega ohm ( Resistance greater than ) can be implemented. Through this, the neuron circuit (400) can have a time constant of up to ms as a biological time constant value.

[0063] Certain parts of the membrane circuit (420) included in the neuron circuit (400) (e.g., variable resistor (421)) are configured as programmable resistors, so that through parameter programming, the adaptive time constant of the membrane circuit , and the reset voltage You can adjust it.

[0064] Certain parts of the adaptive circuit (450) included in the neuron circuit (400) (e.g., variable resistor (451)) are composed of programmable resistors, so that the adaptive time constant of the adaptive circuit is, through parameter programming , adaptive conductance below the threshold voltage and can adjust the spike-triggered adaptive current b. By adjusting these parameters, the neuron circuit (400) can obtain an output having various spiking firing patterns through the pulse generation circuit (435).

[0065] Referring to FIG. 4b, an example of implementation of sub-threshold voltage adaptive conductance a according to one embodiment can be observed.

[0066] In the case of so-called a reflection, which implements a sub-threshold voltage adaptive conductance in the circuit portion (455) of the neuron circuit (400), it can be implemented by reflecting the parameter table of the AdEx neuron model. SW1 (456) can be switched according to the sub-threshold voltage adaptive conductance a.

[0067] The circuit portion (455) of the neuron circuit (400) can change the spiking firing pattern of the neuron circuit (400) in real time by switching SW1 (456) and SW2 (458) alternately. SW2 (458) can be used to prevent current from being applied to M3 (457) so that M3 (457) operates as a MOSCAP (metal oxide semiconductor capacitor).

[0068] When a synaptic input current is applied with a constant current value while changing the main parameters of the neuron circuit (400), an adaptive firing pattern may appear in which the spacing between output spikes becomes wider. Additionally, a bursting firing pattern may appear in which high-frequency output spikes appear at the beginning of the input and no further output spikes occur, but the embodiments according to the present disclosure are not limited to the specific cases mentioned.

[0070] FIG. 5 is a diagram illustrating the operation of a neuron circuit according to one embodiment when the neuron circuit is implemented with analog elements and current is applied from a synapse array.

[0071] Referring to FIG. 5, a synaptic current that is weighted and added from the synapse array (310) and an adaptive current that reflects the magnitude of the potential of the adaptive capacitor can be applied to the membrane capacitor (422) included in the membrane circuit (420).

[0072] Subsequently, when the voltage of the membrane capacitor (422) included in the membrane circuit (420) exceeds the threshold voltage of the pulse generation circuit (435), the transistor M8 (435-1) turns on and the common voltage (436) decreases, and as the common voltage (436) decreases, the transistor M11 can turn on due to the change in gate voltage. Accordingly, the membrane voltage (426) of the membrane capacitor (422) included in the membrane circuit (420) can rise rapidly, and this phenomenon can be interpreted as an implementation of an Exponential Leaky-Integrated-Fire (ELIF) neuron model.

[0073] As the common voltage (436) decreases, transistor M2 is turned off and transistor M1 (450-1) is turned on due to a change in the gate voltage, thereby increasing the voltage of the adaptive capacitor (452) included in the adaptive circuit (450). This phenomenon is caused by the spike-triggered adaptation current b. This can be reflected in a way that the value decreases. This so-called '+b potentiation' operation can be implemented by using a switch transistor (e.g., M1 (450-1) in the adaptive circuit (450) to float the adaptive capacitor (452) and then applying a pulse to apply a specific charge value to the adaptive capacitor (452).

[0074] As the common voltage (436) decreases, transistor M10 (435-2) is simultaneously turned off and M9 (435-3) is turned on, so that the output voltage (437) can increase. Subsequently, as the output voltage (437) increases, M12 (420-1) is turned on, so that the membrane voltage (426) decreases to the reset voltage, and as the common voltage (436) increases, the output voltage (437) can decrease.

[0075] M4 (450-2) can reflect the effect of the adaptive current on the membrane voltage (426) through the current mirrors (450-3) of M5 and M6, and M3 (450-4) reads the membrane voltage (426) and the effect of this is reflected in the resting voltage This can be reflected in. This means that the combination of voltage and adaptation of the neuron model through parameter a can also contribute to spike-trigger adaptation because the voltage rises rapidly while the action potential is rising. Such so-called '*a reflection' operation can be implemented by reflecting the membrane voltage (426), which is the voltage of the membrane capacitor (422), to the adaptive capacitor (452) through the read transistor (e.g., M3 (450-4)) of the adaptive circuit (450).

[0077] FIG. 6 is a diagram for comparatively explaining an example of implementing a variable resistor in a neuron circuit according to one embodiment.

[0078] Referring to (a), an example can be seen in which a neuron circuit is implemented using a digital pulse generation circuit (640) that directly pulses digital data, unlike the analog pulse generation circuit including multiple PMOS and multiple NMOS in FIGS. 4a to 5. If pulses can be applied to the circuit through the digital pulse generation circuit (640), a more accurate spiking firing pattern can be obtained than when the analog pulse generation circuit including multiple PMOS and multiple NMOS in FIGS. 4a to 5 is used.

[0079] Referring to (b), a neuron circuit composed solely of a digital pulse generating circuit (610) and an NMOS including an IGZO transistor can be seen. Unlike the neuron circuit of (b), which uses a resistor as a variable resistor (420-1) in the membrane circuit (420) and a resistor as a variable resistor (451) in the adaptive circuit (450) in FIGS. 4a to 5, the neuron circuit of (b) uses an IGZO transistor (421-1; 451-1) having the aforementioned characteristics to minimize leakage current.

[0081] FIG. 7 is a diagram illustrating the operation of a neuron circuit according to one embodiment when the neuron circuit is implemented with digital elements and current is applied from a synapse array.

[0082] Referring to FIG. 7, as in FIG. 6(b), a synaptic current that is weighted and added from the synapse array (710) and an adaptive current that reflects the magnitude of the potential of the adaptive capacitor (752) included in the adaptive circuit (750) can be applied to the membrane capacitor (722) included in the membrane circuit (720).

[0083] When the voltage of the membrane capacitor (722) exceeds the threshold potential, a spike can be output from the pulse generation circuit (610) through the comparator circuit (330).

[0084] When a spike is output from the pulse generating circuit (610), M7 (720-1) is turned on and the voltage of the membrane capacitor (722) can be induced to a reset voltage.

[0085] When a spike is output from the pulse generation circuit (610), a large spike pulse that is fed back can turn on M1 (750-1) and an inverted large pulse that is fed back can turn on M3 (750-2). At this time, while M1 (750-1) is turned on, a high voltage (Vdd) is applied to the membrane circuit through M5 (750-3), but since the voltage of the membrane capacitor (722) is already induced to a reset voltage by M7 (720-1), the two transistors (M5 and M7) enter into a competitive state regarding which voltage to apply to the membrane capacitor (722). However, since the influence of M7 (720-1) on the membrane capacitor (722) is superior to that of M5 (750-3), the voltage of the membrane capacitor (722) can still be induced to a reset voltage.

[0086] When a spike pulse is applied to M2 (750-4), the adaptive capacitor (752) of the adaptive circuit (750) is filled with charge, causing the voltage to rise, and by stably turning off M6 (750-5), the current from M2 (750-4) is reflected in the adaptive capacitor (752) of the adaptive circuit (750), thereby enabling the implementation of '+b potentiation'.

[0087] Next, M5 (750-3) can read the voltage of the adaptive capacitor (752) of the adaptive circuit (750) and reflect it in the membrane circuit (720). When M6 (750-5) is turned on, the influence of the voltage of the membrane capacitor (722) of the membrane circuit (720) is reflected in the adaptive capacitor (752) included in the adaptive circuit (750) through M4 (750-6), thereby enabling the implementation of '*a reflection'.

[0089] FIG. 8 is a diagram illustrating a method for controlling a neuron circuit according to one embodiment. The description regarding the operations of the method for controlling a neuron circuit may correspond to the description regarding the neuron circuit in FIG. 1 to 7.

[0090] Referring to FIG. 8, in operation (810), the neuron circuit may receive parameter values ​​that determine a firing pattern based on the membrane circuit and the adaptive circuit included in the neuron circuit. The parameter values ​​are the adaptive time constants of the membrane circuit described in FIG. 4a and 4b. , and the reset voltage It may include. The parameter values ​​are the adaptive time constants of the adaptive circuit described in FIGS. 4a and 4b. , adaptive conductance below the threshold voltage and may include b, which is a spike-triggered adaptive current.

[0091] In operation (820), the neuron circuit can output a voltage having a spiking firing pattern based on parameter values. The parameter values ​​are the adaptive time constants of the membrane circuit described in FIGS. 4a and 4b. , and the reset voltage It may include. The parameter values ​​are the adaptive time constants of the adaptive circuit described in FIGS. 4a and 4b. , adaptive conductance below the threshold voltage and may include a spike-triggered adaptive current b. The spiking firing pattern may include an adaptive firing pattern in which the spacing between output spikes is widened as described in FIG. 4b, or a bursting firing pattern in which a high-frequency output spike appears at the beginning of the input and no further output spikes occur, but the embodiments according to the present disclosure are not limited to the specific cases mentioned above.

[0093] The embodiments described above may be implemented as hardware components, software components, and / or combinations of hardware and software components. For example, the devices, methods, and components described in the embodiments may be implemented using a general-purpose computer or a special-purpose computer, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and software applications executed on said operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. In addition, other processing configurations, such as parallel processors, are also possible.

[0094] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or instruct the processing unit independently or collectively. Software and / or data may be permanently or temporarily embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on computer-readable recording media.

[0095] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may store program instructions, data files, data structures, etc., either individually or in combination, and the program instructions recorded on the medium may be those specifically designed and configured for the embodiment or those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

[0096] The hardware device described above may be configured to operate as one or more software modules to perform the operation of the embodiment, and vice versa.

[0097] Although the embodiments have been described above with reference to the limited drawings, those skilled in the art can apply various technical modifications and variations based thereon. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0098] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

Claim 1 A neuron circuit comprising: a membrane circuit that receives a weighted summed synaptic current from a synaptic array and receives an adaptive current from an adaptive circuit; a comparator circuit that controls a pulse generation circuit when the voltage of the membrane circuit exceeds a predetermined threshold voltage; a pulse generation circuit that controls the membrane circuit and the adaptive circuit based on an output signal from the comparator circuit and generates a pulse having a firing pattern; and an adaptive circuit connected to the membrane circuit and the pulse generation circuit to determine the firing pattern of the pulse generation circuit. Claim 2 In claim 1, the adaptive circuit transmits an adaptive current to the membrane circuit and determines the firing pattern based on the adaptive time constant parameter, subthreshold adaptation conductance parameter, and spike-triggered adaptation current parameter of the adaptive circuit. Claim 3 In claim 1, the membrane circuit receives the adaptive current from the adaptive circuit based on the adaptive time constant parameter of the membrane circuit and the reset voltage parameter of the membrane circuit, and determines the firing pattern, a neuron circuit. Claim 4 In claim 1, the membrane circuit and the adaptive circuit are a neuron circuit comprising a variable resistor element and a capacitor element. Claim 5 In paragraph 4, the variable resistor of the membrane circuit and the variable resistor of the adaptive circuit comprise a neuron circuit including PCM (phase change material) or RRAM (resistive random access memory). Claim 6 In paragraph 4, the variable resistor of the membrane circuit and the variable resistor of the adaptive circuit comprise a neuron circuit including an IGZO transistor. Claim 7 In claim 1, the pulse generating circuit is a neuron circuit that performs the operation of controlling the membrane circuit by changing the voltage of the membrane circuit to a reset voltage based on a feedback spike. Claim 8 In claim 1, the pulse generating circuit is a neuron circuit that performs the operation of controlling the adaptive circuit by charging an adaptive capacitor included in the adaptive circuit based on a feedback spike. Claim 9 In claim 1, the pulse generating circuit comprises a plurality of PMOS and a plurality of NMOS, a neuron circuit. Claim 10 In claim 9, the pulse generating circuit is a neuron circuit that performs the operation of applying a pulse to the adaptive circuit based on a common voltage and an output voltage. Claim 11 In paragraph 1, the pulse generating circuit is a neuron circuit that is a digital pulse generating circuit. Claim 12 In paragraph 2, the voltage value of the capacitor element of the adaptive circuit is proportional to the voltage value of the capacitor element of the membrane circuit, in a neuron circuit. Claim 13 In paragraph 2, the capacitor element of the adaptive circuit is a neuron circuit that lowers the voltage value of the capacitor element of the membrane circuit. Claim 14 A method for controlling a neuron circuit, comprising: receiving parameter values ​​that determine a firing pattern based on a membrane circuit and an adaptive circuit included in the neuron circuit; and outputting a voltage having a spiking firing pattern based on the received parameter values. Claim 15 A computer-readable recording medium storing a computer program containing instructions for performing the method of paragraph 14.

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