A lif neuronal circuit

Abstract

The application discloses a LIF neuron circuit which can realize connection of multiple synapses based on delay. The application comprises a membrane potential accumulation circuit, a waveform shaping circuit, a leakage circuit, a pulse generation circuit, a refractory period circuit and a delay circuit. The LIF neuron with a memristor has the advantages of simple circuit structure, and can control the spike pulse width, peak strength, refractory period length of neuron excitation and delay connection of multiple synapses. The LIF neuron with a memristor not only can better match the function structure of a biological neuron, but also can transmit more abundant space-time information for multiple synapses in actual application, and enhance the adaptability of a neural network. Moreover, the LIF neuron circuit with a memristor and multiple synapses delay has fewer devices, and is favorable for improving the integration density of a brain-like chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of spiking neural network, and particularly relates to a LIF neuron circuit capable of delaying connection of multiple synapses. BACKGROUND

[0002] As the third generation of neural network, spiking neural network is closer to the working principle of biology than traditional artificial neural network, and can effectively simulate the connection and communication between biological neurons. In the spiking neural network, neurons as a basic unit can receive pulse signals and emit spike pulses, which is an important basis for realizing complex spatio-temporal information processing. LIF (leaky integrate-and-fire) neurons are modeled on biological neurons, and can effectively simulate the information transmission characteristics of biological neurons, such as the presence or absence of spike of action potential spike, cumulative firing and refractory period. However, due to the complexity of the excitation pulse of biological neurons, the LIF neuron circuit constructed by traditional devices not only needs a large number of components, but also has low similarity between the LIF neuron excitation spike pulse and the biological neuron excitation pulse. This leads to low practicability, high power consumption and other problems, which is not conducive to circuit integration. As a new type of component, the memristor increases or decreases the memristor value along with the direction of the applied voltage. Since the non-linear change of the memristor value is more similar to the non-linear change of the ion channel switch value of biological neurons, the LIF neuron circuit based on the memristor can effectively reduce the complexity of the LIF circuit, which will help to improve the integration density of the brain-like chip and reduce the power consumption of the brain-like chip. However, the current large-memristor LIF neuron excitation spike pulse width, peak strength and refractory period length are not controllable, which limits the information encoding mode and transmission rate in the spiking neural network, resulting in a significant decrease in neural computing flexibility.

[0003] In biological neural networks, synapses are the sites where neurons functionally connect and are the key to information transmission between two neurons. The transmission rate and the amplitude of the transmitted spike information of a single neuron connected to multiple synapses may be affected by various factors such as synapse type, neurotransmitter type, receptor type, presynaptic and postsynaptic mechanisms, etc. In the hardware research related to bionic neurons, researchers often ignore the different transmission of spike information on different synapses due to various factors when a single neuron is connected to multiple synapses, which leads to differences between the excitation pulse characteristics of bionic neurons and biological neurons. Due to this difference, the behavior of the model may be different from that of the real biological neural network in the neural network constructed in this way, resulting in a decrease in the prediction accuracy of the neural network. SUMMARY

[0004] In view of the deficiencies of the prior art, the purpose of the present application is to invent a LIF neuron circuit with spike initiation and refractory period range regulation and delay connection of multiple synapses.

[0005] In order to achieve the above technical purpose, the technical scheme of the present application is,

[0006] A LIF neuron circuit, comprising a current input end and at least two voltage output ends, and a membrane potential accumulation unit, a waveform shaping unit, a leakage unit, a pulse generation unit, a refractory period unit, and a delay unit equal in number to the voltage output ends.

[0007] The current input end is connected to the input end of the membrane potential accumulation unit, and the input current is integrated by the membrane potential accumulation unit.

[0008] The output end of the membrane potential accumulation unit is connected to the input end of the waveform shaping unit through the leakage unit, so as to output the voltage reaching the preset threshold to the waveform shaping unit through the leakage unit.

[0009] The output end of the waveform shaping unit is connected to the pulse generation unit and each delay unit, respectively, so as to output the digital signal converted and shaped from the analog signal generated by the membrane potential accumulation unit.

[0010] The pulse generation unit generates a spike pulse output based on the received digital signal, and the output end of the pulse generation unit serves as one of the voltage output ends and is also connected to the refractory period unit to control the refractory period unit.

[0011] The output end of the refractory period unit is connected to the input end of the membrane potential accumulation unit to control the input of the membrane potential accumulation unit.

[0012] Each delay unit generates a spike pulse output with different delays based on the received digital signal, and the output end of each delay unit serves as a voltage output end.

[0013] The membrane potential accumulation unit comprises a capacitor, one end of the capacitor is connected between the current input end and the waveform shaping unit, and the other end is grounded. The leakage unit comprises a leakage resistor, one end of the leakage resistor is connected between the membrane potential accumulation unit and the waveform shaping unit, and the other end is grounded.

[0014] The waveform shaping unit comprises a first inverter and a second inverter, the input end of the first inverter is connected to the membrane potential accumulation unit through a leakage unit, and the first inverter is immediately switched from outputting a positive voltage to outputting 0 voltage after receiving a voltage of a preset threshold, thereby outputting a square wave signal switching between positive voltage and 0 to the second inverter. The second inverter is immediately switched from outputting a negative voltage to outputting a positive voltage after receiving 0 voltage, thereby outputting a square wave signal switching between negative voltage and positive voltage.

[0015] The first inverter comprises a first NMOS tube and a first PMOS tube, the gates of the first NMOS tube and the first PMOS tube are connected to each other, and the first NMOS tube and the first PMOS tube are connected to the membrane potential accumulation unit through a leakage unit. The drain of the first NMOS tube is connected to the drain of the first PMOS tube. The source of the first NMOS tube is grounded, and the source of the first PMOS tube is connected to a positive voltage.

[0016] The second inverter comprises a second NMOS tube and a second PMOS tube, the gates of the second NMOS tube and the second PMOS tube are connected to each other, and the second NMOS tube and the second PMOS tube are connected to the membrane potential accumulation unit through a leakage unit. The drain of the second NMOS tube is connected to the drain of the second PMOS tube. The source of the second NMOS tube is connected to a negative voltage, and the source of the second PMOS tube is connected to a positive voltage.

[0017] The pulse generation unit comprises a pulse unit memristor and a pulse unit resistor, the input end of the pulse unit memristor is connected to the output end of the waveform shaping unit, the output end of the pulse unit memristor is connected to the voltage output end, and the pulse unit memristor is connected to the refractory period unit. One end of the pulse unit resistor is connected to the output end of the pulse unit memristor, and the other end of the pulse unit resistor is connected to a positive voltage.

[0018] The refractory period unit comprises a refractory period unit PMOS tube, the gate of the refractory period unit PMOS tube is connected to the pulse generation unit, the drain of the refractory period unit PMOS tube is connected between the current input end and the membrane potential accumulation unit, and the source of the refractory period unit PMOS tube is grounded.

[0019] The delay unit comprises a first inverter, a D flip-flop, a second inverter, a delay unit memristor and a delay unit resistor connected in sequence.

[0020] The input end of the first inverter is connected to the output end of the waveform shaping unit, and the first inverter is immediately switched from outputting a positive voltage to outputting 0 voltage after receiving a voltage of a predetermined threshold, thereby outputting a square wave signal switching between positive voltage and 0 to the D flip-flop.

[0021] The output end of the D flip-flop is connected to the second inverter, and the CLK end of the D flip-flop controls the delay time, and after the delay time reaches, 0 voltage is output to the second inverter.

[0022] The second inverter is converted from outputting a negative voltage to outputting a positive voltage as soon as receiving the 0 voltage, so that a square wave signal converted between the negative voltage and the positive voltage is output to the input end of the delay unit memristor.

[0023] The output end of the delay unit memristor is a voltage output end.

[0024] One end of the delay unit resistor is connected to the output end of the pulse unit memristor, and the other end is connected to a positive voltage.

[0025] The first inverter comprises an NMOS tube and a PMOS tube. The gates of the NMOS tube and the PMOS tube are connected to each other and connected to the output end of the waveform shaping unit. The drain of the NMOS tube and the drain of the PMOS tube are connected and connected to the input end of the D flip-flop. The source of the NMOS tube is grounded, and the source of the PMOS tube is connected to a positive voltage.

[0026] The second inverter comprises an NMOS tube and a PMOS tube. The gates of the NMOS tube and the PMOS tube are connected to each other and connected to the output end of the D flip-flop. The drain of the NMOS tube and the drain of the PMOS tube are connected and connected to the input end of the delay unit memristor. The source of the NMOS tube is connected to a negative voltage, and the source of the PMOS tube is connected to a positive voltage.

[0027] The technical effect of the present application is that the memristor LIF neuron realizes the adjustable control of the firing spike pulse width, peak potential size and refractory period length through the change of the resistance value of the memristor and the switching characteristics of the MOS tube. The memristor LIF neuron of the present application realizes the connection of multiple synapses and the excitation of delayed spike pulses through the signal delay of the D flip-flop. Such a memristor LIF neuron is closer to the information transmission mechanism of biological neurons, improves the diversity and stability of the information transmission of neural synapses, and provides flexible and efficient space-time information for the rate coding and pulse amplitude coding methods in the pulse neural network. In the application of image classification and speech recognition based on the pulse neural network, the neuron has great advantages when encoding different features of the input image and speech. In addition, the number of components used is small, which is conducive to high-density integration and cost reduction. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings described below only illustrate the embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0029] Figure 1 is the structural diagram of the synapse connected by the memristor LIF neuron in the embodiment.

[0030] Figure 2 is the circuit of the memristor LIF neuron connected with multiple synapses with delay in the embodiment.

[0031] Figure 3 is the input pulse and output spike pulse curve of the memristor LIF neuron in the embodiment.

[0032] Figure 4 is the output pulse spike control curve of the memristor LIF neuron under different inputs in the embodiment.

[0033] Figure 5 is the firing spike pulse and delay firing spike pulse curve of the memristor LIF neuron connected with multiple synapses with delay under different inputs in the embodiment. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present application.

[0035] The purpose of the embodiment is to provide a memristor LIF neuron circuit with low area cost after integration, good real-time performance, adjustable firing spike pulse and refractory period, and the ability to connect multiple synapses with delay.

[0036] The circuit of the memristor LIF neuron for firing spike range control of the pulse neural network in the embodiment includes a membrane potential accumulation circuit, a waveform shaping circuit, a leakage circuit, a pulse generation circuit, a refractory period circuit, and a delay circuit.

[0037] Figure 1 is the schematic diagram of the synapse connected by the neuron in the embodiment, where (a) is the multiple synapse delay connection of two memristor LIF neurons, (b) is the multiple synapse delay connection of multiple memristor LIF neurons, V out2 , V out3 , and V out4 are V out1delayed spike pulse. Figure 1 The synapse is a memristor.

[0038] Figure 2 A hardware implementation circuit diagram of the memristor LIF neuron circuit in the embodiment is shown in Figure 1. Figure 2 The potential across the capacitor C1 is regarded as the membrane potential of the neuron and is used to integrate the input current.

[0039] The memristor LIF neuron circuit in the embodiment is composed of one memristor, five MOS transistors, two resistors and one capacitor. Since the memristor LIF neuron can delay the connection of multiple synapses, if the number of synapses to be connected is N, only 4*N MOS transistors and N D flip-flops need to be added to form N spike delay pulses. The membrane potential accumulation circuit in the embodiment is connected to the leakage circuit, the output end of the membrane potential accumulation circuit is connected to the input end of the waveform shaping circuit, the waveform shaping circuit converts the analog signal generated by the membrane potential into a digital signal and shapes it, the output end of the waveform shaping circuit is connected to the input end of the pulse generation circuit. The output end of the pulse generation circuit is connected to the refractory period circuit, the output end of the refractory period circuit is connected to the input end of the membrane potential accumulation circuit. The output end of the waveform shaping circuit is connected to the input end of the delay circuit, and the output end of the delay circuit is connected to the pulse generation circuit of the delayed spike pulse.

[0040] The memristor LIF neuron includes a current input end I in , a voltage output end V out1 , and a delayed voltage output end V out2 .

[0041] The waveform shaping circuit is composed of N1, P1, N2 and P2, a first inverter is composed of N1 and P1, and a second inverter is composed of N2 and P2. When the membrane potential does not reach the threshold voltage of N1, P1 is turned on, and the output of the first inverter is high. When the membrane potential reaches the threshold voltage of N1, N1 is turned on, and the output of the first inverter is low, at which time the analog voltage of the membrane potential is converted into a square wave signal of the digital circuit. The output end of the first inverter is connected to the gate of N2 and P2, which controls the working state of N2 and P2. When the output end of the first inverter is high, N2 is turned on, at which time the waveform shaping circuit outputs a stable negative voltage because the source of N2 is connected to a negative voltage. When the output end of the first inverter is low, P2 is turned on, and the waveform shaping circuit outputs a stable positive voltage.

[0042] The pulse generation circuit consists of a memristor M1 and a resistor R2. The memristor M1 is a non-linear threshold memristor. The square wave voltage signal output by the waveform shaping circuit causes a change in the memristor's resistance. When the resistance exceeds the memristor's positive threshold, the resistance of M1 gradually decreases to a low-resistance state. on As the resistance of memristor M1 decreases, the voltage across resistor R2 gradually increases, and the output pulse V... out1 The potential will gradually increase, generating a spike pulse signal.

[0043] The membrane potential accumulation circuit is implemented using a capacitor C1. Capacitor C1 accumulates the input signal, thus increasing the membrane potential V. C When the voltage reaches the threshold value of N1 in the first-stage inverter, N1 turns on to generate a square wave signal.

[0044] The leakage circuit is implemented by resistor R1. When the capacitor voltage V C If the N1 tube voltage threshold is not reached, the membrane voltage will leak to the resting potential or wait until the next signal arrives.

[0045] The refractory period circuit is implemented using a P3 transistor. When the pulse generation circuit does not output a spike pulse signal, the P3 transistor is not conducting, and the current at the neuron's input terminal flows to the membrane potential accumulation circuit. After the pulse generation circuit generates an output spike pulse signal, the P3 transistor conducts, and the current at the neuron's input terminal flows to ground. During the conduction period of the P3 transistor, the neuron's capacitance C1 does not integrate, similar to the refractory period of a biological neuron. The duration of the refractory period can be controlled by the threshold voltage of the P3 transistor.

[0046] The delay circuit consists of a first inverter, a D flip-flop, a second inverter, a memristor M2, and a resistor R3. Transistors P4 and N3 form the first inverter in the delay circuit. The output of the waveform shaping circuit is connected to the input of one of the inverters in the delay circuit. The output of the first inverter is connected to the input of the D flip-flop. NMOS transistor N4 and PMOS transistor P5 form the second inverter. The output of the D flip-flop is connected to the gates of NMOS transistors N4 and PMOS transistor P5 in the second inverter. The drain of P5 is connected to the drain of N4 and then to the positive terminal of memristor M2. The negative terminal of memristor M2 is connected to R3. Since the input of the delay circuit is connected in parallel with the pulse generation circuit of the neuron, and the parallel voltage remains constant, the input voltage of the delay circuit is the same as the input voltage of the pulse generation circuit. The D flip-flop delays the digital signal, and the delay time can be adjusted by the CLK pin. The delayed digital signal is then input to memristor M2 via the second inverter. This will cause the memristor resistance to change, exceeding the memristor's positive threshold, causing the resistance of M2 to gradually decrease to a low-resistance state. on As the resistance of memristor M2 decreases, the voltage across resistor R3 gradually increases, and the output pulse V... out2The potential will gradually increase to generate a delayed spike pulse signal.

[0047] P1, P2, P3, P4 and P5 in this embodiment are P-type MOS transistors, and N1, N2, N3 and N4 are N-type MOS transistors. The switching threshold of N1 is the threshold of the neuron. The output voltage of the second inverter can affect the resistance change of the memristor M1. The resistance R2 is connected in series with the memristor M1, and the pulse voltage V out The output of the neuron is the output of the neuron. The output voltage of the neuron controls the on-off of P3, and determines the refractory period of the neuron. The source of P1, P2, P4 and P5 is connected to +Vcc, and the source of N2 and N4 is connected to -Vdd. One end of R2 is connected to the memristor M1. The other end is connected to +Vcc. In the resting state, the potential on the capacitor is 0, P1 is turned on, and the output potential of the first inverter is +Vcc. N2 is turned on, and the output potential of the second inverter is -Vdd. The memristor M1 is in a high resistance state Roff, and the voltage divided by the resistance R2 can be ignored. The output pulse Vout1 is almost 0V, and the voltage drop on M1 is about -Vdd, reaching the inverting threshold of the memristor. At this time, the memristance has reached the maximum value and will not change. P2, P3 and N1 are in the off state, and the membrane potential C1 of the neuron is waiting for the signal to arrive and accumulate charge.

[0048] P4 and N3 in the delay circuit form the first inverter in the delay circuit, and the output end of the waveform shaping circuit is connected to the input end of one inverter in the delay circuit. The output end of the first inverter is connected to the input end of the D flip-flop. NMOS transistor N4 and the second PMOS transistor P5 form the second inverter. The output end of the D flip-flop is connected to the gate of NMOS transistor N4 and PMOS transistor P5 in the second inverter, and the drain of P5 is connected to the drain of N4 and connected to the positive end of the memristor M2. The negative end of the memristor M2 is connected to R3. Since the input end of the delay circuit and the pulse generating circuit of the neuron are connected in parallel, the parallel voltage does not change, so the input voltage of the delay circuit and the input voltage of the pulse generating circuit are the same. In the resting state, since the output of the delay circuit is low, the output end of the first inverter in the delay circuit is high, and the D flip-flop is controlled by the CLK clock signal to delay the time but does not change the level of the signal, and the output of the D flip-flop is high, and the output of the second inverter in the delay circuit is low. The memristor M2 is in a high resistance state Roff, and the voltage divided by the resistance R3 can be ignored. The output delay pulse Vout2 is almost 0V, and the voltage drop on M2 is about -Vdd, reaching the inverting threshold of the memristor. At this time, the memristance has reached the maximum value and will not change.

[0049] Figure 3This describes the charging and discharging process of the neuron's capacitor voltage Vc and the voltage change process of the neuron's output peak Vout1 when the input signal is a DC square wave current Iin. The input current Iin is the weighted sum of the inputs received by the neuron from its connected previous neurons. When a signal enters the neuron Iin, as the charge is integrated across capacitor C1, the voltage across C1 will flow to ground along resistor R1 if it does not exceed the threshold of N1. Figure 1 As shown in the third signal of the Iin curve, the capacitor voltage Vc slowly releases. If the voltage of capacitor C1 exceeds the threshold of N1, N1 will conduct, causing the first-stage inverter to output +Vcc in the static state and 0 voltage when N1 is conducting, i.e., the first-stage inverter outputs a square wave signal from +Vcc to 0. The memristor M1 will receive a voltage exceeding the threshold, causing the resistance of memristor M1 to gradually decrease to the low-resistance state Ron. As the resistance of memristor M1 decreases, the voltage division of resistor R2 gradually increases, and the potential of output Vout1 gradually increases. The neuron excites a spike pulse. Since the second-stage inverter outputs a square wave signal with a level from -Vdd to +Vcc, the output Vout1 will output a high level of approximately +Vcc.

[0050] The first inverter in the delay circuit outputs a low voltage (0). The D flip-flop's delay time is controlled by the CLK clock signal, but this does not change the signal level. The second inverter in the delay circuit outputs a high voltage (+Vcc). Memristor M2 will exceed its threshold voltage, and its resistance will gradually decrease to a low resistance state (Ron). As the resistance of memristor M2 decreases, the voltage drop across resistor R3 gradually increases, and the output voltage Vout2 gradually increases, causing the neuron to generate a delayed spike pulse.

[0051] As the output pulse potential gradually increases, the capacitor charge is gradually released, and its potential gradually decreases. The potentials of the first and second stage inverters rapidly reverse, and the waveform shaping circuit outputs -Vdd. The instant of reversal forms a drop in the action potential. The voltage division on memristor M1 exceeds its reverse threshold, and the memristor value gradually increases to the high-resistance state Roff. Simultaneously, the voltage across resistor R2 gradually decreases from its negative maximum value until it becomes negligible, and the output pulse Vout slowly rises from its negative minimum value until it returns to the initial potential. When the excitation spike reaches the threshold of P3, P3 conducts, and the capacitor charge is rapidly released. During the conduction of P3, when the neuron receives the Iin signal again, the capacitor no longer integrates the charge. This achieves the refractory period of the biological neuron. The neuron cannot respond to new inputs or generate new pulses. Finally, the circuit returns to the initial state, waiting for a new round of input. The duration of the refractory period is controlled by the threshold voltage of P3.

[0052] Figure 4The charging and discharging process of the capacitor voltage Vc of the neuron and the voltage change process of the neuron output spike Vout1 are shown in the range of 24us to 35us direct current square wave current of the neuron input signal. The neuron input signal needs to be between 24us to 35us direct current square wave current and is not limited to that shown in the figure.

[0053] Figure 5 The voltage change process of the neuron output spike Vout1 and Vout2 delayed output spike pulse is shown in the range of 24us to 35us direct current square wave current of the neuron input signal.

[0054] The above examples should be understood as only for illustrating the present application and not for limiting the protection scope of the present application. After reading the content of the present application, the skilled person can make various changes or modifications to the present application, and these equivalent changes and modifications also fall within the scope defined by the claims of the present application.

Claims

1. A LIF neuron circuit, characterized by, The current input end and at least two voltage output ends, and a membrane potential accumulation unit, a waveform shaping unit, a leakage unit, a pulse generation unit, a refractory period unit and a delay unit equal in number to the voltage output ends; wherein each voltage output end generates a spike pulse output but with different time delays; The current input end is connected to the input end of the membrane potential accumulation unit, and the input current is integrated by the membrane potential accumulation unit; The output end of the membrane potential accumulation unit is connected to the input end of the waveform shaping unit through the leakage unit to output a voltage reaching a preset threshold to the waveform shaping unit through the leakage unit; The output end of the waveform shaping unit is connected to the pulse generation unit and each delay unit to output a digital signal converted and shaped from the analog signal generated by the membrane potential accumulation unit; The pulse generation unit generates a spike pulse output based on the received digital signal, and the output end of the pulse generation unit serves as one of the voltage output ends and is also connected to the refractory period unit to control the refractory period unit; The output end of the refractory period unit is connected to the input end of the membrane potential accumulation unit to control the input of the membrane potential accumulation unit; Each delay unit generates a spike pulse output with different time delays based on the received digital signal, and the output end of each delay unit serves as a voltage output end; The delay unit comprises a first inverter, a D flip-flop, a second inverter, a delay unit memristor and a delay unit resistor connected in sequence; The input end of the first inverter is connected to the output end of the waveform shaping unit, and the first inverter outputs a positive voltage and then outputs 0 voltage as soon as it receives a voltage reaching a predetermined threshold, thereby outputting a square wave signal between the positive voltage and 0 to the D flip-flop; The output end of the D flip-flop is connected to the second inverter, and the CLK end of the D flip-flop controls the delay time, and outputs 0 voltage to the second inverter after the delay time reaches; The second inverter outputs a negative voltage and then outputs a positive voltage as soon as it receives 0 voltage, thereby outputting a square wave signal between the negative voltage and the positive voltage to the input end of the delay unit memristor; The output end of the delay unit memristor serves as a voltage output end; One end of the delay unit resistor is connected to the output end of the pulse unit memristor, and the other end is connected to a positive voltage; The first inverter comprises an NMOS tube and a PMOS tube; the gates of the NMOS tube and the PMOS tube are connected to each other and connected to the output end of the waveform shaping unit; the drain of the NMOS tube and the drain of the PMOS tube are connected and connected to the input end of the D flip-flop; the source of the NMOS tube is grounded, and the source of the PMOS tube is connected to a positive voltage; The second inverter comprises an NMOS tube and a PMOS tube; the gates of the NMOS tube and the PMOS tube are connected to each other and connected to the output end of the D flip-flop; the drain of the NMOS tube and the drain of the PMOS tube are connected and connected to the input end of the delay unit memristor; the source of the NMOS tube is connected to a negative voltage, and the source of the PMOS tube is connected to a positive voltage.

2. The LIF neuron circuit of claim 1, wherein, The membrane potential accumulation unit comprises a capacitor, one end of the capacitor is connected between the current input end and the waveform shaping unit, and the other end is grounded; the leakage unit comprises a leakage resistor, one end of the leakage resistor is connected between the membrane potential accumulation unit and the waveform shaping unit, and the other end is grounded.

3. The LIF neuron circuit of claim 1, wherein, The waveform shaping unit comprises a first inverter and a second inverter, the input end of the first inverter is connected to the membrane potential accumulation unit through the leakage unit, and immediately changes from outputting a positive voltage to outputting 0 voltage after receiving a preset threshold voltage, so as to output a square wave signal between the positive voltage and 0 to the second inverter; The second inverter immediately changes from outputting a negative voltage to outputting a positive voltage after receiving the 0 voltage, so as to output a square wave signal between the negative voltage and the positive voltage.

4. The LIF neuron circuit of claim 3, wherein, The first inverter comprises a first NMOS tube and a first PMOS tube; the gates of the first NMOS tube and the first PMOS tube are connected to each other and connected to the membrane potential accumulation unit through the leakage unit; the drain of the first NMOS tube and the drain of the first PMOS tube are connected; the source of the first NMOS tube is grounded, and the source of the first PMOS tube is connected to a positive voltage; The second inverter comprises a second NMOS tube and a second PMOS tube; the gates of the second NMOS tube and the second PMOS tube are connected to each other and connected to the membrane potential accumulation unit through the leakage unit; the drain of the second NMOS tube and the drain of the second PMOS tube are connected; the source of the second NMOS tube is connected to a negative voltage, and the source of the second PMOS tube is connected to a positive voltage.

5. The LIF neuron circuit of claim 1, wherein, The pulse generation unit comprises a pulse unit memristor and a pulse unit resistor, the input end of the pulse unit memristor is connected to the output end of the waveform shaping unit, the output end of the pulse unit memristor serves as a voltage output end and is connected to the refractory period unit; one end of the pulse unit resistor is connected to the output end of the pulse unit memristor, and the other end is connected to a positive voltage.

6. The LIF neuron circuit of claim 1, wherein, The refractory period unit comprises a refractory period unit PMOS tube, the gate of the refractory period unit PMOS tube is connected to the pulse generation unit, the drain is connected between the current input end and the membrane potential accumulation unit, and the source is grounded.

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