Semiconductor memory and capacity configuration method for storage block thereon

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The method addresses low utilization rates in semiconductor memory banks by selectively trimming damaged regions based on bank-specific conditions, improving density configuration efficiency.

SG11202301423PBActive Publication Date: 2026-06-04

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Authority / Receiving Office: SG · SG
Patent Type: Patents
Filing Date: 2021-11-02
Publication Date: 2026-06-04

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Abstract

Embodiments of the present application provide a semiconductor memory and a capacity configuration method for a storage block thereon. The method comprises: determining a target storage block to be configured on a memory; determining a capacity configuration parameter of the target storage block, and determining a target code from a group of codes of the target storage block, wherein the target code corresponds to a storage region to be trimmed in the target storage block; on the basis of the target code, generating a region selection signal used for selecting the storage region to be trimmed in the target storage block; and on the basis of the region selection signal, trimming the storage region to be trimmed, so as to configure the capacity of the target storage block. The present application can flexibly select the storage region to be trimmed, thereby improving the effective utilization rate of the capacity configuration for the storage block on the semiconductor memory. [Fig. 2]

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Description

[ 0001] This application is based on and claims priority to Chinese patent applicationNo. 202110783912.0 filed on July 12, 2021 and entitled “SEMICONDUCTORMEMORY AND METHOD FOR CONFIGURING DENSITY OF BANK OFSEMICONDUCTOR MEMORY”, the disclosure of which is hereby incorporated byreference in its entirety.TECHNICAL FIELD[ 0002] The embodiments of the disclosure relate to the field of semiconductortechnologies, and relate to, but are not limited to, a semiconductor memory and a methodfor density configuration of a bank of the semiconductor memory.BACKGROUND[ 0003] At present, in order to achieve different densities for the same type of chips, aset of trim commands may be adopted to trim same storage regions (arrays) of all thebanks of each full-chip to obtain different densities.[ 0004] Since the damaged arrays of different banks may be completely different, inorder to utilize the chip whose arrays are partially damaged, the method of selecting thesame arrays of the full-chip for trimming is obviously defective and results in the loweffective utilization rate of the density configuration of the banks of the semiconductormemory.SUMMARY[ 0005] In view of this, an embodiment of the disclosure provides a semiconductormemory and a method for density configuration of a bank of the semiconductor memory,which is able to flexibly select a storage region to be trimmed and improve the effectiveutilization rate of the density configuration of banks of the semiconductor memory.[ 0006] In a first aspect, an embodiment of the disclosure provides a method fordensity configuration of a bank of a semiconductor memory, including:[ 0007] determining a target bank to be configured of the memory;[ 0008] determining a density configuration parameter of the target bank, the densityconfiguration parameter being configured to represent a density to be configured for thetarget bank;[ 0009] determining, based on the density configuration parameter of the target bank, atarget code from a set of codes of the target bank, the target code corresponding to astorage region to be trimmed in the target bank;[ 0010] generating, based on the target code, a region selection signal configured toselect the storage region to be trimmed in the target bank; and[ 0011] trimming, based on the region selection signal, the storage region to betrimmed to configure the density of the target bank.[ 0012] In a second aspect, an embodiment of the disclosure provides a semiconductormemory, including:[ 0013] a target bank, including at least two storage regions;[ 0014] an address processing unit, configured to output an address of the target bank,an output terminal of the address processing unit being connected to the target bank;[ 0015] a code acquisition unit, configured to receive a target code, the target codecorresponding to at least one storage region to be trimmed in the target bank;[ 0016] a region selection signal generation unit, configured to generate, based on thetarget code, a region selection signal configured to select the storage region to betrimmed in the target bank, an output terminal of the region selection signal generationunit being connected to an input terminal of a trim unit; and[ 0017] the trim unit, configured to trim the storage region to be trimmed based on theregion selection signal to configure the density of the target bank, an output terminal ofthe trim unit being connected to the target bank.[ 0018] According to the embodiments of the disclosure, since the densityconfiguration parameters of different target banks to be configured may be different, thetarget codes determined based on the different density configuration parameters may bedifferent, and the region selection signals generated based on the different target codesmay be different. Therefore, different storage regions to be trimmed of different targetbanks to be configured can be trimmed through different region selection signals, so thatthe storage region to be trimmed can be flexibly selected, thereby improving the effectiveutilization rate of the density configuration of the banks of the semiconductor memory.BRIEF DESCRIPTION OF THE DRAWINGS[ 0019] In the drawings (which are not necessarily drawn to scale), similar referencenumerals may describe similar components in different views. Similar referencenumerals with different letter suffixes may represent different examples of similarcomponents. The drawings generally illustrate, by way of examples and not limitation,various embodiments of the disclosure.[ 0020] FIG. 1 is a diagram of composition structure of a Dynamic Random AccessMemory (DRAM) in the related art.[ 0021] FIG. 2 is a flowchart of implementation of a method for density configurationof a bank of a semiconductor memory according to an embodiment of the disclosure.[ 0022] FIG. 3a is a structural diagram of storage regions and addresses of a full-chipaccording to an embodiment of the disclosure.[ 0023] FIG. 3b is an enlarged structural diagram of Bank8 of FIG. 3a according to anembodiment of the disclosure.[ 0024] FIG. 3c is a structural diagram of Bank8 after trimming according to anembodiment of the disclosure.[ 0025] FIG. 3d is a logic circuit diagram of performing logic NOT operation on atarget code according to an embodiment of the disclosure.[ 0026] FIG. 3e is a logic circuit diagram of performing logic NOT operation onRa<15:14> according to an embodiment of the disclosure.[ 0027] FIG. 3f is a logic circuit diagram of performing logic operation onDensityTrim<0> and DensityTrim<1> according to an embodiment of the disclosure.[ 0028] FIG. 3g is a logic circuit diagram of performing logic operation onDensityTrimB<0> and DensityTrimB<1> according to an embodiment of the disclosure.[ 0029] FIG. 3h is a logic circuit diagram of obtaining a region selection signalRa1514<0> based on a target code and a high 2-bit address according to an embodimentof the disclosure.[ 0030] FIG. 3i is a logic circuit diagram of obtaining a region selection signalRa1514<1> based on a target code and a high 2-bit address according to an embodimentof the disclosure.[ 0031] FIG. 3j is a logic circuit diagram of obtaining a region selection signalRa1514<2> based on a target code and a high 2-bit address according to an embodimentof the disclosure.[ 0032] FIG. 4 is a structural diagram of a system for density configuration of a bankof a semiconductor memory according to an embodiment of the disclosure.[ 0033] FIG. 5 is a structural diagram of a semiconductor memory according to anembodiment of the disclosure.DETAILED DESCRIPTION[ 0034] To make the objectives, technical solutions and advantages of the embodimentsof the disclosure be understood more clearly, the specific technical solutions of thedisclosure will be described in further detail below with reference to the drawings in theembodiments of the disclosure. The following embodiments are merely used to illustratethe disclosure, but are not intended to limit the scope of the embodiments of thedisclosure.[ 0035] In the following description, the suffixes such as “module” or “unit” used torepresent the components are merely to facilitate the illustration of the embodiments ofthe disclosure and have no specific meaning. Therefore, “module” or “unit” may be usedinterchangeably.[ 0036] In the related art, due to the high cost of each set of masks for memory chips,the trims are usually adopted to achieve different densities in the design of the same typeof chips so as to quickly dominate the market. In actual production, there will also besome chips whose arrays are partially damaged. In this case, these chips may be sold aslow-density chips to increase the yield. For example, 8Gb (Gigabit) chips may be used as4Gb / 2Gb chips. In order to achieve different densities for the same type of chips, a set oftrims is generally adopted to select the same arrays of all the banks of the full-chip fortrimming. Such a method is relatively simple in design, but not flexible enough. In orderto utilize these chips whose arrays are partially damaged, considering that damagedarrays of different banks may be completely different, the method of selecting the samearrays of all the banks of the full-chip for trimming is obviously defective.[ 0037] It should be understood that the banks refer to physical memory banks in theDRAM or the bank refers to logic storage repositories in the DRAM. A chip may includemultiple banks, for example, the chip may include 8 banks. Each bank may includemultiple arrays, and the number of the arrays in each bank represents the data bit-widthof the chip. Each array includes multiple memory cells.[ 0038] In a possible implementation, a semiconductor memory may be a DRAM. FIG.1 is a diagram of composition structural of a DRAM in the related art. As shown in FIG.1, a controller 10 is configured to control two DIMMs (Dual-Inline-Memory-Modules)101, and each DIMM 101 includes at least two DIMM dies 1011.[ 0039] In view of the foregoing technical problems, an embodiment of the disclosureprovides a method for density configuration of a bank of a semiconductor memory. Asshown in FIG. 2, the method includes the operation S202 to S210 including:[ 0040] In S202, determining a target bank to be configured of the memory.[ 0041] It should be understood that the memory may be a DRAM of the megabit-levelmonolithic storage density or may be another semiconductor memory which supports thetrim function; and the target bank may be any bank to be configured of the memory. In anexample, a bank may be an implementation of a memory block. Taking a chip including16 banks as an example, when the 16 banks are Bank0 to Bank15 respectively, the targetbank may be any one of the Bank0 to Bank15. For example, the target bank may beBank8 or Bank0.[ 0042] In some possible implementations, determining the target bank to beconfigured of the memory may include: determining each bank of the memory as thetarget bank to be configured, when each bank of the memory is required to be configured.[ 0043] According to some embodiments, a density of the target bank is determinedaccording to a density of the memory chip. For example, for a 16Gb chip including 16banks, the density of each bank is 1Gb, i.e., the density of the target bank is 1Gb.[ 0044] In S204, determining a density configuration parameter of the target bank, thedensity configuration parameter being configured to represent a density to be configuredfor the target bank.[ 0045] In some possible implementations, the density configuration parameter of thetarget bank may include at least one of: a target density of the target bank, a storageregion to be trimmed in the target bank, or an available storage region in the target bank.[ 0046] It should be understood that a storage region may be an implementation of anarray, and the storage region may be represented by “Region”, for example, each bankmay be divided into 6 regions, e.g., Region<5:0> including Region<0> to Region<5>,where Region<5> may be one of the storage regions.[ 0047] In an example, the density of the target bank Bank8 without being damaged ortrimmed may be 1Gb, and the target density of Bank8 may be less than or equal to 1Gb,for example, the target density may be (1 / 8)Gb, (1 / 4)Gb, (1 / 2)Gb, (2 / 3)Gb, or the like.Therefore, there are two situations as follows.[ 0048] First situation: Bank8 includes 6 regions, e.g., Region<5:0>, and Bank8 is notdamaged. When the density of 1Gb is required to be changed into the target density of(2 / 3)Gb to meet the demands, any storage region in Region<3:2>, Region<1:0> andRegion<5:4> in Region<5:0> may be determined as the storage region to be trimmed inthe target bank Bank8. Since Bank8 is not damaged, all the storage regions may be takenas the available storage region in the target bank.[ 0049] It can be seen that when the target bank is not damaged, only the target densityof the target bank is required to be determined, and there are three methods forimplementing the density configuration.[ 0050] Second situation: Bank8 includes 6 regions, e.g., Region<5:0>, andRegion<1:0> is damaged. When the density of 1Gb is required to be changed into thetarget density of (2 / 3)Gb to meet the demands, Region<1:0> in Region<5:0> may bedetermined as the storage region to be trimmed in the target bank Bank8, and theremaining Region<5:2> is taken as the available storage region in the target bank. Whenthe density of 1Gb is required to be changed into the target density of (1 / 3)Gb, theavailable storage region in the target bank may be Region<3:2>, and Region<1:0> andRegion<5:4> may be determined as the storage region to be trimmed in the target bankBank8.[ 0051] It can be seen that when the target bank is damaged, the correspondingremaining region may be taken as the available storage region in the target bank, and thestorage region including the damaged region is required to be determined as the storageregion to be trimmed according to the determined target density of the target bank.[ 0052] Determining the density configuration parameter of the target bank mayinclude: determining the density configuration parameter of the target bank according tothe damage information of the target bank and the density configuration requirement ofthe target bank.[ 0053] In S206, determining, based on the density configuration parameter of thetarget bank, a target code from a set of codes of the target bank, the target codecorresponding to a storage region to be trimmed in the target bank.[ 0054] It should be understood that the set of codes of the target bank may be thecodes representing different storage regions to be trimmed among the storage regions ofthe target bank. For example, each code among the set of codes of the target bank may berepresented by trim_halfGoodBnk<1:0> or Density<1:0>, wheretrim_halfGoodBnk<1:0> or Density<1:0> may be 00, 01, 10, or 11. For example,trim_halfGoodBnk<1:0>=00 may represent that there is no storage region to be trimmedin Region<5:0> of the target bank Bank8; trim_halfGoodBnk<1:0>=01 may representthat the storage region to be trimmed in Region<5:0> of the target bank Bank8 isRegion<5:4>; trim_halfGoodBnk<1:0>=10 may represent that the storage region to betrimmed in Region<5:0> of the target bank Bank8 is Region<3:2>; andtrim_halfGoodBnk<1:0>=11 may represent that the storage region to be trimmed inRegion<5:0> of the target bank Bank8 is Region<1:0>.[ 0055] In an example, the target code is determined according to the storage region tobe trimmed in the target bank, for example, the target code may be 10 when the storageregion to be trimmed is Region<3:2>.[ 0056] In a possible implementation, determining, based on the density configurationparameter of the target bank, the target code from the set of codes of a target bank mayinclude: determining the target code corresponding to any storage region to be trimmedcorresponding to the target density from the set of codes of the target bank according tothe target density of the target bank, when the target bank is determined to be notdamaged.[ 0057] For example, the density of the target bank Bank8 without being damaged maybe 1Gb, and Bank8 includes 6 regions, e.g., Region<5:0>. When the target density is(2 / 3)G, and trim_halfGoodBnk<1:0> or Density<1:0> may be 00, 01, 10, 11 whichrepresent different storage regions to be trimmed, any code representing (2 / 3)G may beselected as the target code from the set of codes represented by rim_halfGoodBnk<1:0>or Density<1:0>, and therefore the target code may be any of 01, 10 or 11.[ 0058] In another possible implementation, determining, based on the densityconfiguration parameter of the target bank, the target code from the set of codes of atarget bank may include: when the target bank is determined to be damaged, determininga storage region to be trimmed and an available storage region according to a damagedstorage region and the target density, and determining the target code from the set ofcodes of the target bank according to the storage region to be trimmed and the availablestorage region. It should be understood that the determined target code is unique, whenthe sum of the target density and the density of the damaged storage region is equal to thedensity of the target bank without being damaged.[ 0059] For example, the density of the target bank Bank8 without being damaged maybe 1Gb, and Bank8 includes 6 regions, e.g., Region<5:0>. When Region<5:4> isdamaged, and when the target density is (2 / 3)G and trim_halfGoodBnk<1:0> orDensity<1:0> may be 00, 01, 10, 11 which represent different storage regions to betrimmed, a code representing the storage region to be trimmed (i.e., Region<5:4>) maybe selected, from the set of codes represented by trim_halfGoodBnk<1:0> orDensity<1:0>, as the target code, and therefore the target code is unique, i.e., 01.[ 0060] In S208, generating, based on the target code, a region selection signalconfigured to select the storage region to be trimmed in the target bank.[ 0061] It should be understood that the region selection signal is a target output levelobtained by performing logic operation on the target code.[ 0062] In S210, trimming, based on the region selection signal, the storage region tobe trimmed to configure the density of the target bank.[ 0063] It should be understood that trimming the storage region may be performed bychanging a logic level of the storage region. For example, the level of the storage regionbefore trimming may be low, and after the level of the storage region is converted fromlow to high, the storage region can be trimmed.[ 0064] In a possible implementation, trimming, based on the region selection signal,the storage region to be trimmed to configure the density of the target bank may include:determining, according to the region selection signal, to apply a high voltage (high level)to the storage region to be trimmed, and to apply a low voltage (low level) to at least onestorage region, other than the storage region to be trimmed, in the target bank so as tochange a logic level of the storage region to be trimmed to trim the storage region to betrimmed and configure the density of the target bank.[ 0065] According to the embodiments of the disclosure, since the densityconfiguration parameters of different target banks to be configured may be different, thetarget codes determined based on the different density configuration parameters may bedifferent, and the region selection signals generated based on the different target codesmay further be different. Therefore, different storage regions to be trimmed of differenttarget banks to be configured can be trimmed through different region selection signals,so that the storage region to be trimmed can be flexibly selected, thereby improving theeffective utilization rate of the density configuration of the banks of the semiconductormemory.[ 0066] An embodiment of the disclosure further provides a method for densityconfiguration of a bank of a semiconductor memory, which includes the operations 101to 117 including:[ 0067] In 101, determining a target bank to be configured of the memory.[ 0068] In 103, determining a density configuration parameter of the target bank, thedensity configuration parameter being configured to represent a density to be configuredfor the target bank.[ 0069] In 105, determining, when the density configuration parameter of the targetbank includes a storage region to be trimmed in the target bank or an available storageregion in the target bank, the storage region to be trimmed based on the storage region tobe trimmed or the available storage region.[ 0070] It should be understood that the available storage region may be at least onestorage region in the target bank other than the storage region to be trimmed.[ 0071] In some possible implementations, determining the storage region to betrimmed based on the storage region to be trimmed or the available storage region mayinclude: determining a damaged region in the target bank, determining the availablestorage region based on the damaged region, and then determining the storage region tobe trimmed.[ 0072] In an example, the density of the target bank Bank8 may be 1Gb, and Bank8includes 6 regions, e.g., Region<5:0>. When the target density is (2 / 3)Gb andRegion<5:4> is damaged, the storage region to be trimmed may be determined asRegion<5:4>; when the target density is (1 / 3)Gb and Region<5:4> is damaged, thestorage region to be trimmed may be determined as Region<5:2> or determined asRegion<1:0> and Region<5:4>.[ 0073] In 107, determining a target code from a set of codes of the target bank basedon the storage region to be trimmed, each code among the set of codes of the target bankcorresponding to at least one storage region to be trimmed in the target bank.[ 0074] In a possible implementation, determining the target code from the set of codesof the target bank based on the storage region to be trimmed may include: determining acode corresponding to the storage region to be trimmed from the set of codes of the targetbank according to the storage region to be trimmed, regardless of whether the target bankis damaged or not. For example, when the storage region to be trimmed is determined asRegion<5:4>, a code 01 corresponding to Region<5:4> is determined as the target code.[ 0075] In 109, determining, when the density configuration parameter of the targetbank includes a target density of the target bank, multiple codes corresponding to thedensity configuration parameter of the target bank from a set of codes of the target bank.[ 0076] It should be understood that the multiple codes corresponding to the densityconfiguration parameter of the target bank may be determined from the set of codes ofthe target bank directly according to the target density of the target bank and the densityof the target bank without being damaged, when the storage regions of the target bank arenot damaged. For example, the density of the target bank Bank8 may be 1Gb, and Bank8includes 6 regions, e.g., Region<5:0>. When the target density is (2 / 3)Gb and Bank8 isnot damaged, the multiple codes corresponding to the target density of the target bank aredetermined as 01, 10 and 11 from the set of codes including 00, 01, 10 and 11.[ 0077] In 111, randomly selecting a code as the target code from the multiple codescorresponding to the density configuration parameter of the target bank, the target codecorresponding to a storage region to be trimmed in the target bank.[ 0078] In a possible implementation, the densities of storage regions to be trimmedwhich correspond to the respective codes among the multiple codes corresponding to thedensity configuration parameter of the target bank are same, and the target bank is notdamaged, therefore, any one of the multiple codes corresponding to the densityconfiguration parameter of the target bank may be taken as the target code.[ 0079] In 113, determining a row address of the storage region to be trimmed in thetarget bank based on the target code.[ 0080] Herein, the row address of the storage region to be trimmed in the target bankmay be a 16-bit row address, e.g., Ra<15:0>, and Ra<15>, Ra<14> and Ra<13>represent a high 3-bit address of the row address.[ 0081] It should be understood that the storage region to be trimmed may bedetermined according to the target code, and the row address of the storage region to betrimmed may be determined according to the storage region to be trimmed.[ 0082] In some possible implementations, row addresses corresponding to differentstorage regions to be trimmed in the target bank may be different. For example, thedensity of the target bank Bank8 is 1Gb, and Bank8 includes 6 regions, e.g.,Region<5:0>. Memory addresses corresponding to the storage regions to be trimmed(e.g., Region<4> and Region<5>) in the target bank are different, where the high 3-bitaddress of the row address of Region<4> is 100, and the high 3-bit address of the rowaddress of Region<5> is 101.[ 0083] In 115, generating, based on the target code and the row address of the storageregion to be trimmed, a region selection signal configured to select the storage region tobe trimmed in the target bank.[ 0084] In some possible implementations, generating, based on the target code and therow address of the storage region to be trimmed, the region selection signal configured toselect the storage region to be trimmed in the target bank may include: inputting thetarget code and the row address of the storage region to be trimmed into a logic circuitincluding a NAND gate, the logic gate circuit being configured to output the regionselection signal configured to select the storage region to be trimmed in the target bank.[ 0085] In 117, trimming the storage region to be trimmed based on the regionselection signal to configure the density of the target bank.[ 0086] According to the embodiments of the disclosure, when the densityconfiguration parameter of the target bank includes the storage region to be trimmed inthe target bank or the available storage region in the target bank, the storage region to betrimmed may be determined according to the storage region to be trimmed in the targetbank or the available storage region in the target bank, and the code corresponding to thestorage region to be trimmed is determined as the target code; when the densityconfiguration parameter of the target bank includes the target density of the target bank,multiple codes corresponding to the target density of the target bank may be determined,and any one of the multiple codes may be taken as the target code. In such way, since thedensity configuration parameter is determined according to the actual situation of thetarget bank, the determined target code corresponds to the storage region to be trimmedwhich is determined according to the actual situation of the target bank, so that thedetermined target code can better meet the actual demands of the actual densityconfiguration. Moreover, since the region selection signal is generated according to thetarget code and the row address of the storage region to be trimmed simultaneously, thedetermined region selection signal may be used to perform the trimming of the storageregion to be trimmed in the target bank accurately.[ 0087] An embodiment of the disclosure provides a method for density configurationof a bank of a semiconductor memory, which includes the operations 201 to 213including:[ 0088] In 201, determining a target bank to be configured of the memory.[ 0089] In 203, determining a density configuration parameter of the target bank, thedensity configuration parameter being configured to represent a density to be configuredfor the target bank.[ 0090] In 205, determining a target code from a set of codes of the target bank basedon the density configuration parameter of the target bank, the target code correspondingto a storage region to be trimmed in the target bank.[ 0091] In 207, determining the storage region to be trimmed in the target bank basedon the target code.[ 0092] In 209, performing logic processing on the target code and a row address of thestorage region to be trimmed corresponding to the target code to obtain a target level.[ 0093] In a possible implementation, performing the logic processing on the targetcode and the row address of the storage region to be trimmed corresponding to the targetcode to obtain the target level may include: performing the logic processing on the targetcode and a high-bit address of the row address of the storage region to be trimmedcorresponding to the target code to obtain the target level. Here, the high-bit address isconfigured to distinguish different storage regions in the target bank.[ 0094] It should be understood that the high-bit address of the row address of thestorage region to be trimmed may be a high 3-bit address or a high 2-bit address in therow address. In an example, the density of the target bank Bank8 is 1Gb, and Bank8includes 6 regions, e.g., Region<5:0>. The high 3-bit address of the row address of thestorage region to be trimmed (e.g., Region<4>) is 100, and the high 3-bit address of therow address of the storage region to be trimmed (e.g., Region<5>) is 101.[ 0095] In an example, the target code may be understood as a mapping factorconfigured to map the row address.[ 0096] In a possible implementation, performing the logic processing on the targetcode and the row address of the storage region to be trimmed corresponding to the targetcode to obtain the target level may include: inputting the target code and the row addressof the storage region to be trimmed corresponding to the target code into a decoderincluding a NAND gate, and performing logic processing on the target code and the rowaddress of the storage region to be trimmed corresponding to the target code through thedecoder to obtain the target level after the logic processing.[ 0097] In 211, taking the target level as a region selection signal; and[ 0098] In 213, trimming the storage region to be trimmed based on the regionselection signal to configure the density of the target bank.[ 0099] According to the embodiments of the disclosure, logic processing is performedon the target code and the high-bit address of the row address of the storage region to betrimmed corresponding to the target code, the target level obtained through the logicprocessing is taken as the region selection signal. Since the target level is obtained bymapping the high-bit address of the row address by taking the code corresponding to thestorage region to be trimmed as the mapping factor, the obtained region selection signalmay be used to perform the trimming of the storage region to be trimmed moreaccurately.[ 00100] An embodiment of the disclosure provides a method for density configurationof a bank of a semiconductor memory, which includes the operations 301 to 311including:[ 00101] In 301, determining a target bank to be configured of the memory.[ 00102] In 303, determining a density configuration parameter of the target bank, thedensity configuration parameter being configured to represent a density to be configuredfor the target bank.[ 00103] In 305, determining a maximum density of the target bank, when the densityconfiguration parameter of the target bank includes a target density of the target bank.[ 00104] It should be understood that the maximum density of the target bank may bethe density of the target bank without being damaged or trimmed. For example, themaximum density of the target bank may be 1Gb.[ 00105] In 307, determining, when the target density is less than the maximum density,a target code from a set of codes of the target bank based on the target density, the targetcode corresponding to a storage region to be trimmed in the target bank.[ 00106] It should be understood that during the density configuration of the target bankof the semiconductor memory, the target density must be less than or equal to themaximum density of the target bank, i.e., the density of the target bank can only beconfigured to be less than the maximum density of the target bank, and the density of thetarget bank cannot be configured to be greater than the maximum density of the targetbank. For example, when the maximum density of the target bank of the semiconductormemory is 1Gb, the target density is required to be less than or equal to 1Gb, and cannotbe greater than 1Gb.[ 00107] In a possible implementation, determining, when the target density is less thanthe maximum density, the target code from the set of codes of the target bank based onthe target density may include: determining, when the target density of the target bank isless than the maximum density of the target bank, a density of the storage region to betrimmed according to a difference between the maximum density and the target density;determining whether the target bank has a damaged region or not; in response todetermining that the target bank has a damaged region, determining the damaged regionand a density of the damaged region, and determining the storage region to be trimmedaccording to the density of the storage region to be trimmed, the damaged region and thedensity of the damaged region; and determining a code corresponding to the storageregion to be trimmed as the target code from the set of codes of the target bank.[ 00108] In another possible implementation, determining, when the target density isless than the maximum density, the target code from the set of codes of the target bankbased on the target density may include: determining, when the target density of thetarget bank is less than the maximum density of the target bank, a density of the storageregion to be trimmed according to a difference between the maximum density and thetarget density; determining whether the target bank has a damaged region or not; inresponse to determining that the target bank has no damaged region, determining, as thestorage region to be trimmed, any storage region with the same density as the storageregion to be trimmed; and determining a code corresponding to the storage region to betrimmed as the target code from the set of codes of the target bank.[ 00109] In 309, generating, based on the target code, a region selection signalconfigured to select the storage region to be trimmed in the target bank.[ 00110] In 311, trimming the storage region to be trimmed based on the regionselection signal to configure the density of the target bank.[ 00111] According to the embodiment of the disclosure, the target code is determinedfrom the set of codes of the target bank based on the target density when the targetdensity of the target bank is determined to be less than the maximum density. In such away, the density of banks of the semiconductor memory can be configured reasonably.[ 00112] An embodiment of the disclosure provides another method for densityconfiguration of a bank of a semiconductor memory, which includes the operations 401to 411 including:[ 00113] In 401, determining a target bank to be configured of the memory, the targetbank including at least two logic storage regions, each of the at least two logic storageregions includes at least two consecutive physical storage regions, and a storage region tobe trimmed in the target bank including at least two consecutive physical storage regionsto be trimmed.[ 00114] In a possible implementation, a density of the target bank is 1G, and the targetbank may include 6 regions, e.g., Region<5:0>, where Region<1:0> may be a logicstorage region 1, Region<3:2> may be a logic storage region 2, and Region<5:4> may bea logic storage region 3, i.e., the target bank includes three logic storage regions.Region<0> to Region<5> may include physical storage regions 1 to 6, where the logicstorage region 1 may include consecutive Region<0> and Region<1>, the logic storageregion 2 may include consecutive Region<2> and Region<3>, and the logic storageregion 3 may include consecutive Region<4> and Region<5>. It can be seen that eachlogic storage region includes two consecutive physical storage regions.[ 00115] In 403, determining a density configuration parameter of the target bank, thedensity configuration parameter being configured to represent a density to be configuredfor the target bank.[ 00116] In 405, determining, when the density configuration parameter of the targetbank includes the physical storage regions to be trimmed in the target bank, a logicstorage region to be trimmed from the at least two logic storage regions in the target bankbased on the at least two consecutive physical storage regions to be trimmed in the targetbank.[ 00117] It should be understood that according to the embodiment of the disclosure, thetrimming is performed in a unit of a logic storage region, i.e., as long as any physicalstorage region in the logic storage region is damaged, the logic storage region in whichthe physical storage region is located is required to be trimmed. For example, for thelogic storage region Region<1:0>, when the physical storage region Region<1> isdamaged, the logic storage region Region<1:0> in which Region<1> is located isrequired to be trimmed.[ 00118] In some possible implementations, determining, when the densityconfiguration parameter of the target bank includes the physical storage regions to betrimmed in the target bank, a logic storage region to be trimmed from the at least twologic storage regions in the target bank based on the physical storage regions to betrimmed in the target bank may include: determining, as the logic storage region to betrimmed, a logic storage region including the physical storage regions to be trimmedamong the at least two logic storage regions in the target bank, when the densityconfiguration parameter of the target bank includes the physical storage regions to betrimmed in the target bank.[ 00119] In 407, determining a target code from a set of codes of the target bank basedon the logic storage region to be trimmed, the target code corresponding to the storageregion to be trimmed in the target bank.[ 00120] It should be understood that the logic storage region to be trimmed may be animplementation of the storage region to be trimmed.[ 00121] In 409, generating, based on the target code, a region selection signalconfigured to select the storage region to be trimmed in the target bank.[ 00122] In 411, trimming the storage region to be trimmed based on the regionselection signal to configure the density of the target bank.[ 00123] According to the embodiment of the disclosure, the minimum unit of thetrimming for the target bank is determined as a logic storage region, and if the physicalstorage region belonging to the logic storage region is damaged, the logic storage regionin which the physical storage region is located is required to be trimmed, so that thepossibility of missing the trimming for the damaged storage region can be reduced.[ 00124] An embodiment of the disclosure provides another method for densityconfiguration of a bank of a semiconductor memory, which includes the operations 501to 521 including:[ 00125] In 501, determining a target bank to be configured of the memory, the targetbank including at least two logic storage regions, each of the at least two logic storageregions including at least two consecutive physical storage regions.[ 00126] In 503, determining a density configuration parameter of the target bank, thedensity configuration parameter being configured to represent a density to be configuredfor the target bank, and the density configuration parameter of the target bank including atarget density of the target bank.[ 00127] In 505, determining a density of each physical storage region in the targetbank.[ 00128] It should be understood that the density of each physical storage region isequal to a ratio of a total density of the target bank to the number of the physical storageregions in the target bank. For example, if the total density of the target bank is 1Gb andthe number of the physical storage regions is 6, the density of each physical storageregion is (1 / 6)Gb.[ 00129] In 507, determining the number of the consecutive physical storage regions ineach logic storage region.[ 00130] In an example, the number of the consecutive physical storage regions in eachlogic storage region may be 2, or may be an integer larger than 2.[ 00131] In a possible implementation, the number of the consecutive physical storageregions in each logic storage region is determined according to the number of bits of eachcode among of the set of codes of the target bank and the number of the physical storageregions in the target bank.[ 00132] In 509, determining, based on the number of the consecutive physical storageregions in each logic storage region and the density of each physical storage region, adensity of the logic storage region.[ 00133] In some possible implementations, determining, based on the number of theconsecutive physical storage regions in each logic storage region and the density of eachphysical storage region, the density of the logic storage region may include: determininga product of the number of the consecutive physical storage regions in each logic storageregion and the density of each physical storage region as the density of the logic storageregion. For example, if the number of the consecutive physical storage regions in eachlogic storage region is 2 and the density of each physical storage region is (1 / 3)Gb, thedensity of each logic storage region is (2 / 3)Gb.[ 00134] In 511, determining a maximum density of the target bank.[ 00135] It should be understood that the maximum density of the target bank may bethe density of the target bank without being damaged or trimmed. Determining themaximum density of the target bank may include obtaining the maximum density fromfactory test data of the semiconductor memory.[ 00136] In a possible implementation, the maximum density of the target bank Bank8 is1Gb and Bank8 includes 6 physical storage regions, e.g., Region<5:0>, where every twoconsecutive physical storage regions are determined as a logic storage region, so that alogic storage region 1 (e.g., Region<1:0>), a logic storage region 2 (e.g., Region<3:2>)and a logic storage region 3 (e.g., Region<5:4>) are formed. It can be seen that thedensity of each physical storage region is (1 / 6)Gb and the density of each logic storageregion is (1 / 3)Gb.[ 00137] In 513, determining at least one configurable density of the target bank basedon the density of each logic storage region and the maximum density of the target bank,the density of each logic storage region being a sum of densities of respective physicalstorage regions in the logic storage region.[ 00138] According to an embodiment, if the logic storage region includes two physicalstorage regions and the density of each physical storage region is (1 / 6)Gb, the density ofthe logic storage region is (1 / 3)Gb.[ 00139] According to an embodiment, determining the at least one configurable densityof the target bank based on the density of each logic storage region and the maximumdensity of the target bank may include: determining a difference between the maximumdensity of the target bank and an integer multiple of the density of each logic storageregion as the at least one configurable density of the target bank. For example, if themaximum density of the target bank is 1Gb and the density of the logic storage region is(1 / 3)Gb, the at least one configurable density of the target bank may include (1 / 3)Gb,(2 / 3)Gb and 1Gb, each of which is an integer multiple of (1 / 3)Gb.[ 00140] In 515, determining an actual density to be configured based on the at least oneconfigurable density and the target density.[ 00141] In a possible implementation, determining the actual density to be configuredbased on the at least one configurable density and the target density may include:comparing the at least one configurable density and the target density, and determining,as the actual density to be configured, a configurable density among the at least oneconfigurable density that is closest to and less than the target density.[ 00142] It should be understood that when the maximum density of the target bank is1Gb, and when the density of the logic storage region is (1 / 3)Gb and the target density is(5 / 6)Gb, the at least one configurable density may include at least (1 / 3)Gb and (2 / 3)Gb.Since (2 / 3)Gb is the configurable density closest to (5 / 6)Gb ((5 / 6)Gb is not an integermultiple of the density of the logic storage region), the actual density to be configuredmay be determined to be (2 / 3)Gb.[ 00143] In 517, determining, when the actual density is inconsistent with the targetdensity, a target code from a set of codes of the target bank based on the actual density,the target code corresponding to a storage region to be trimmed in the target bank.[ 00144] It should be understood that because the configurable density may be actuallyimplemented or obtained, when the actual density is inconsistent with the target density,the target code may be determined from the set of codes of the target bank according tothe actual density.[ 00145] In 519, generating, based on the target code, a region selection signalconfigured to select the storage region to be trimmed in the target bank.[ 00146] In 521, trimming the storage region to be trimmed based on the regionselection signal to configure the density of the target bank.[ 00147] According to the embodiment of the disclosure, the density of each logicstorage region may be determined according to the density of each physical storageregion and the number of the consecutive physical storage regions in the logic storageregion; the at least one configurable density of the target bank may be determinedaccording to the density of each logic storage region and the maximum density of thetarget bank; and the actual density to be configured may be determined according to theat least one configurable density and the target density of the target bank; and the targetcode may be determined based on the actual density, when the actual density isinconsistent with the target density.[ 00148] An embodiment of the disclosure provides another method for densityconfiguration of a bank of a semiconductor memory, which includes the operations 601to 623 including:[ 00149] In 601, determining a target bank to be configured of the memory, the targetbank including at least two logic storage regions, each of the at least two logic storageregions including at least two consecutive physical storage regions.[ 00150] In 603, determining a density configuration parameter of the target bank, thedensity configuration parameter being configured to represent a density to be configuredfor the target bank, and the density configuration parameter of the target bank including atarget density of the target bank.[ 00151] In 605, determining a density of each physical storage region in the targetbank.[ 00152] In 607, determining the number of bits of each code among a set of codes ofthe target bank.[ 00153] It should be understood that the number of bits of each code among the set ofcodes of the target bank is determined according to the number of logic storage regions inthe target bank. For example, if the number of bits of each code among the set of codes ofthe target bank is 2, the number of the logic storage regions cannot be larger than thepower of 2.[ 00154] In 609, determining the number of physical storage regions in each logicstorage region based on the number of physical storage regions in the target bank and thenumber of bits of each code.[ 00155] In some possible implementations, determining the number of physical storageregions in each logic storage region based on the number of physical storage regions inthe target bank and the number of bits of each code may include: determining, accordingto the number of bits of each code, the maximum number of logic storage regionscapable of being distinguished by the set of codes of the target bank; and determining thenumber of consecutive physical storage regions in each logic storage region according tothe determined maximum number of the logic storage regions and the number of physicalstorage regions.[ 00156] According to an embodiment, determining the number of consecutive physicalstorage regions in each logic storage region according to the determined maximumnumber of logic storage regions and the number of physical storage regions may include:determining the number of the consecutive physical storage region in each logic storageregion to be 1, when the maximum number of the logic storage regions is greater than orequal to the number of the physical storage regions; determining the number of theconsecutive physical storage regions in each logic storage region to be 2, when themaximum number of the logic storage regions is less than the number of the physicalstorage regions and twice the maximum number of the logic storage regions is greaterthan the number of the physical storage regions.[ 00157] For example, if the number of bits of each code among the set of codes of thetarget bank is 2, and the number of the physical storage regions is 6, the maximumnumber of the logic storage regions (which is determined based on the number of bits ofeach code among the set of codes of the target bank being 2) may be determined to be 4.It is clear that the maximum number 4 of the logic storage regions is less than the number6 of the physical storage regions, but twice the maximum number of the logic storageregions (i.e., 8) is greater than the number 6 of the physical storage regions, and thus thenumber of the consecutive physical storage regions in each logic storage region may bedetermined to be 2.[ 00158] For another example, if the number of bits of each code among the set of codesof the target bank is 3, and the number of the physical storage regions is 6, the maximumnumber of the logic storage regions (which is determined based on the number of bits ofeach code among the set of codes of the target bank being 3) may be determined to be 8.It is clear that the maximum number 8 of the logic storage regions is greater than thenumber 6 of the physical storage regions, and thus the number of the consecutivephysical storage region in each logic storage region may be determined to be 1.[ 00159] In 611, determining, based on the number of consecutive physical storageregions in each logic storage region and the density of each physical storage region, adensity of the logic storage region.[ 00160] In a possible implementation, determining, based on the number of consecutivephysical storage regions in each logic storage region and the density of each physicalstorage region, the density of the logic storage region may include: determining a productof the number of the consecutive physical storage regions in each logic storage regionand the density of each physical storage region to be the density of the logic storageregion. For example, if the number of the consecutive physical storage regions in eachlogic storage region is 2 and the density of each physical storage region is (1 / 6)Gb, thedensity of each logic storage region may be determined to be (1 / 3)Gb.[ 00161] In 613, determining a maximum density of the target bank.[ 00162] In 615, determining at least one configurable density of the target bank basedon the density of each logic storage region and the maximum density of the target bank,the density of each logic storage region being a sum of densities of respective physicalstorage regions in the logic storage region.[ 00163] In 617, determining an actual density to be configured based on the at least oneconfigurable density and the target density.[ 00164] In 619, determining, when the actual density is inconsistent with the targetdensity, a target code from the set of codes of the target bank based on the actual density,the target code corresponding to a storage region to be trimmed in the target bank.[ 00165] In 621, generating, based on the target code, a region selection signalconfigured to select the storage region to be trimmed in the target bank.[ 00166] In 623, trimming the storage region to be trimmed based on the regionselection signal to configure the density of the target bank.[ 00167] According to the embodiment of the disclosure, the number of the consecutivephysical storage regions in each logic storage region may be accurately determinedaccording to the number of bits of each code among the set of codes of the target bankand the number of the physical storage regions in the target bank.[ 00168] According to the embodiment of the disclosure, if the maximum density of thetarget bank without being damaged or trimmed is 1Gb, the density of (2 / 3)Gb may beimplemented by trim. The target bank is divided into 6 regions, e.g., Region<5:0>, if thedensity of the target bank is 1G, all the 6 regions including Region<5:0> are utilized; ifthe density of the target bank is (2 / 3)G, 4 regions are selected from the 6 regionsincluding Region<5:0>. For example, a die of a DRAM may include 16 banks, and thedensity of each bank may be 1Gb (which means that the bank includes at least 2^30storage capacitors; in fact, the DRAM further includes redundant storage capacitors, andif the density of the bank is 1Gb, the bank includes more than 2^30 storage capacitors),thus the density of the full die may reach 16Gb. If partial storage capacitors of a diecannot work due to manufacturing process or other reasons, the density of the die may beconfigured to 12Gb, 8Gb, 4Gb or 2Gb through trim, so that the DRAM die may beutilized as much as possible, when the partial storage capacitors cannot work.Table 1trim_halfGoodBnk< Density1:0>00 Region<0,1> Region<2,3> Region<4,5> 1G01 Region<0,1> Region<2,3> (2 / 3)G10 Region<0,1> Region<4,5> (2 / 3)G11 Region<2,3> Region<4,5> (2 / 3)G[ 00169] With reference to Table 1, it can be seen that whentrim_halfGoodBnk<1:0>=01, 4 regions including Region<3:0> are selected andRegion<4,5> is trimmed to implement the density of (2 / 3)G; whentrim_halfGoodBnk<1:0>=10, 4 regions including Region<1:0> and Region<5:4> areselected and Region<3,2> is trimmed to implement the density of (2 / 3)G; whentrim_halfGoodBnk<1:0>=11, 4 regions including Region<5:2> are selected andRegion<1:0> is trimmed to implement the density of (2 / 3)G.[ 00170] FIG. 3a is a structural diagram of storage regions and addresses of a full-chipaccording to an embodiment of the disclosure. As shown in FIG. 3a, the full-chipincludes 16 banks, where the number of bits of a row control line guided by the rowcontrol 301 is 16; Bank4, Bank6, Bank5, Bank7, Bank0, Bank2, Bank1 and Bank3 aredistributed on the left side; and Bank8, Bank10, Bank9, Bank11, Bank 12, Bank 14, Bank13 and Bank 15 are distributed on the right side.[ 00171] FIG. 3b is an enlarged structural diagram of Bank8 of FIG. 3a according to anembodiment of the disclosure. As shown in FIG. 3b, Bank 8 includes 6 physical storageregions from Region<0> to Region<5>, where the 6 regions from Region<0> toRegion<5> are encoded by Ra<15>, Ra<14> and Ra<13> in a row address Ra<15:0>. Itcan be seen that a code corresponding to Region<0> is 000; a code corresponding toRegion<1> is 001; a code corresponding to Region<2> is 010; a code corresponding toRegion<3> is 011; a code corresponding to Region<4> is 100; and a code correspondingto Region<5> is 101.[ 00172] FIG. 3c is a structural diagram of Bank8 after trimming according to anembodiment of the disclosure. As shown in FIG. 3c, two consecutive physical storageregions (i.e., Region<4> and Region<5>) of Bank8 are trimmed to change the density ofBank8 from 1Gb to (2 / 3)Gb. For example, Region<4> and Region<5> may be thedamaged physical storage regions, or may be any two consecutive physical storageregions randomly selected when each physical storage region from Region<0> toRegion<5> is not damaged.[ 00173] According to the embodiment of the disclosure, in the process of generating,based on the target code, the region selection signal configured to select the storageregion to be trimmed in the target bank, the target code is required to be decoded. Herein,three region selection signals (e.g., Ra1514<0>, Ra1514<1> and Ra1514<2>) aredefined. The relations between (Ra1514<0>, Ra1514<1>, and Ra1514<2>) and eachstorage region may be understood with reference to Table 2.Table 2Ra1514<0> Ra1514<1> Ra1514<2>Ra13=0 Ra13=1 Ra13=0 Ra13=1 Ra13=0 Ra13=1Region<0> Region<1> Region<2> Region<3> Region<4> Region<5>[ 00174] As shown in Table 2, Ra1514<0> represents 2 regions including Region<0,1>;Ra1514<1> represents 2 regions including Region<2,3>; and Ra1514<2> represents 2regions including Region<4,5>.[ 00175] The region selection signal (e.g., Ra1514<0>, Ra1514<1>, Ra1514<2>) maybe obtained by performing logic processing on a target code and a high 2-bit address(Ra<15> and Ra<14>) of Bank8 through a logic circuit.[ 00176] Before obtaining the region selection signal (e.g., Ra1514<0>, Ra1514<1>,Ra1514<2>), some intermediate signals may be determined, such as a signal obtained byperforming logic NOT operation on the target code, a signal obtained by performinglogic NOT operation on Ra<15:14>, and the like.[ 00177] FIG. 3d is a logic circuit diagram of performing logic NOT operation on atarget code according to an embodiment of the disclosure. As shown in FIG. 3d,DensityTrim<1:0> represents the target code, and DensityTrimB<1:0> may be obtainedby performing logic NOT operation on DensityTrim<1:0>.[ 00178] FIG. 3e is a logic circuit diagram of performing logic NOT operation on a high2-bit address according to an embodiment of the disclosure. As shown in FIG. 3e,Ra<15:14> is the high 2-bit address, and RaB<15:14> may be obtained by performinglogic NOT operation on Ra<15:14>.[ 00179] FIG. 3f is a logic circuit diagram of performing logic operation onDensityTrim<0> and DensityTrim<1> according to an embodiment of the disclosure. Asshown in FIG. 3f, S11N may be obtained by performing logic NAND operation onDensityTrim<0> and DensityTrim<1>, and S11 may be obtained by performing logicNOT operation on S11N.[ 00180] FIG. 3g is a logic circuit diagram of performing logic operation onDensityTrimB<0> and DensityTrimB<1> according to an embodiment of the disclosure.As shown in FIG. 3g, S00N may be obtained by performing logic NAND operation onDensityTrimB<0> and DensityTrimB<1>, and S00 may be obtained by performing logicNOT operation on S00N.[ 00181] FIG. 3h is a logic circuit diagram of obtaining the region selection signalRa1514<0> based on a target code and a high 2-bit address according to an embodimentof the disclosure. As shown in FIG. 3h, Ra1514<0> may be obtained by performing logicNOT operation on a logic result which is obtained by performing logic NAND operationon RaB<15>, RaB<14> and S11N.[ 00182] FIG. 3i is a logic circuit diagram of obtaining the region selection signalRa1514<1> based on a target code and a high 2-bit address according to an embodimentof the disclosure. As shown in FIG. 3i, logic NAND operation is performed on RaB<15>,RaB<14> and S11 to obtain a first logic result; and logic NAND operation is performedon RaB<15>, Ra<14> and DensityTrimB<1> to obtain a second logic result; and logicNAND operation is performed on the first logic result and the second logic result toobtain Ra1514<1>.[ 00183] FIG. 3j is a logic circuit diagram of obtaining the region selection signalRa1514<2> based on a target code and a high 2-bit address according to an embodimentof the disclosure. As shown in FIG. 3j, logic NAND operation is performed on Ra<15>,RaB<14> and S00 to obtain a third logic result; logic NAND operation is performed onRaB<15>, Ra<14> and DensityTrim<1> to obtain a fourth logic result; and logic NANDoperation is performed on the third logic result and the fourth logic result to obtainRa1514<2>.[ 00184] According to the embodiments of the disclosure, there are multiple options fordensity configuration of a target bank, which may be understood with reference to Table3.Table 3Density<1:0>00 (1G) Ra1514<0> Ra1514<1> Ra1514<2>01 ((2 / 3) G) Ra1514<0> Ra1514<2> Ra1514<2>=010 ((2 / 3) G) Ra1514<0> Ra1514<1>=0 Ra1514<2>11 ((2 / 3) G) Ra1514<0>=0 Ra1514<1> Ra1514<2>[ 00185] As shown in Table 3, Density<1:0> may represent different densities.Density<1:0> is 00 which represents that the density of the target bank is 1G, andRa1514<0> to Ra1514<2> are all 1 which represents that Region<0> to Region<5> areall 1 (because Ra1514<0> represents Region<0,1>, Ra1514<1> represents Region<2,3>,and Ra1514<2> represents Region<4,5>), i.e., available.[ 00186] Density<1:0> is 01 which represents that the density of the target bank is(2 / 3)G, and Ra1514<0> and Ra1514<1> are 1 and Ra1514<2> is 0 which represent thatRegion<0> to Region<3> are all 1 (available) and Region<4> and Region<5> are 0(unavailable) (because Ra1514<0> represents Region<0,1>, Ra1514<1> representsRegion<2,3>, and Ra1514<2> represents Region<4,5>).[ 00187] Density<1:0> is 10 which represents that the density of the target bank is(2 / 3)G, and Ra1514<0> and Ra1514<2> are 1 and Ra1514<1> is 0 which represent thatRegion<0>, Region<1>, Region<4> and Region<5> are all 1 (available) and Region<2>and Region<3> are 0 (unavailable) (because Ra1514<0> represents Region<0,1>,Ra1514<1> represents Region<2,3>, and Ra1514<2> represents Region<4,5>).[ 00188] Density<1:0> is 11 which represents that the density of the target bank is(2 / 3)G, and Ra1514<0> is 0 and Ra1514<1> and Ra1514<2> are 1 which represent thatRegion<0> and Region<1> are 0 (unavailable) and Region<2> to Region<5> are all 1(available) (because Ra1514<0> represents Region<0:1>, Ra1514<1> representsRegion<2:3>, and Ra1514<2> represents Region<4:5>).[ 00189] FIG. 4 illustrates a structural diagram of a system for density configuration of abank of a semiconductor memory according to an embodiment of the disclosure. Asshown in FIG. 4, the system structure includes a read-write system 401, a control unit402, a decoding unit 403 and a bank 404. Ra<12:0> in a row address line Ra<15:0>guided by the read-write system 401 is directly connected to the bank 404, andRa<15:13> is connected to the control unit 402. The control unit 402 is configured toinput Ra<15:13> and the generated DensityTrim<1:0> into the decoding unit 403. Thedecoding unit 403 is connected to the bank 404, and the decoding unit 403 is configuredto perform logic operation on Ra<15:13> and DensityTrim<1:0> to obtain a regionselection signal, and transmit the obtained region selection signal to the bank 404. Thebank 404 is configured to trim a corresponding region to be trimmed according to theregion selection signal to configure the density of the bank.[ 00190] It should be understood that the decoding unit 403 may be implemented by thecircuits shown in FIG. 3h to FIG. 3j. The reference may be made in the foregoingdescription.[ 00191] According to the embodiment of the disclosure, different encoding states ofRa1514<2:0> correspond to different regions of the bank 404, for example, the regioncorresponding to Ra1514<2:0>=100 is Region<0:1>.[ 00192] Furthermore, an embodiment of the disclosure further provides asemiconductor memory, which supports the methods for density configuration of thebank of the semiconductor memory according the foregoing embodiments. FIG. 5 is astructural diagram of the semiconductor memory according to the embodiment of thedisclosure. As shown in FIG. 5, the semiconductor memory includes a target bank 501,an address processing unit 502, a code obtaining unit 503 and a region selection signalgeneration unit 504 and a trim unit 505.[ 00193] The target bank 501 includes at least two storage regions.[ 00194] The address processing unit 502 is configured to output an address of the targetbank 501, here, an output terminal of the address processing unit 502 is connected to thetarget bank 501.[ 00195] The code obtaining unit 503 is configured to receive a target code, here, thetarget code corresponds to at least one storage region to be trimmed in the target bank501.[ 00196] The region selection signal generation unit 504 is configured to generate, basedon the target code, a region selection signal configured to select the storage region to betrimmed in the target bank 501, here, an output terminal of the region selection signalgeneration unit 504 is connected to an input terminal of a trim unit 505.[ 00197] The trim unit 505 is configured to trim the storage region to be trimmed basedon the region selection signal to configure a density of the target bank 501, here, anoutput terminal of the trim unit 505 is connected to the target bank 501.[ 00198] According to some embodiments, the semiconductor memory further includes:a control unit, configured to determine the target bank 501 to be configured of thesemiconductor memory; to determine a density configuration parameter of the targetbank 501, here, the density configuration parameter is configured to represent the densityto be configured for the target bank 501; and to determine the target code from a set ofcodes of the target bank 501 based on the density configuration parameter of the targetbank 501, here, the target code corresponds to the storage region to be trimmed in thetarget bank 501. An output terminal of the control unit is connected to the code obtainingunit.[ 00199] According to some embodiments, the address processing unit 502 includes: arow address processing unit, configured to output a row address of the target bank 501,here, an output terminal of the row address processing unit is connected to an inputterminal of the region selection signal generation unit and the target bank 501; a columnaddress processing unit, configured to output a column address of the target bank 501,here, an output terminal of the column address processing unit is connected to the targetbank 501; and a bank address processing unit, configured to output a bank address of thetarget bank 501, here, an output terminal of the bank address processing unit is connectedto the target bank 501. The region selection signal generation unit 503 is configured toperform logic processing on the target code and a row address of the storage region to betrimmed corresponding to the target code to obtain a target level, and take the target levelas the region selection signal.[ 00200] According to some embodiments, an output terminal of a high-bit address inthe row address processing unit is connected to the input terminal of the region selectionsignal generation unit; here, the high-bit address is configured to distinguish differentstorage regions in the target bank 501.[ 00201] According to some embodiments, the region selection signal generation unit503 includes a logic gate circuit including a NAND gate and a NOT gate, here, an inputterminal of the logic gate circuit includes a signal line corresponding to the target codeand a signal line corresponding to the row address of the storage region to be trimmed;and the logic gate circuit is configured to perform logic processing on the target code andthe row address of the storage region to be trimmed corresponding to the target code toobtain the target level, and to take the target level as the region selection signal.[ 00202] According to some embodiments, the region selection signal generation unit503 includes a decoder. Here, an input terminal of the decoder is a signal linecorresponding to the target code; and each level output by the decoder is taken as theregion selection signal when the level is valid, and each output terminal of the decoder isconnected to the input terminal of the trim unit.[ 00203] The semiconductor memory according to the embodiments of the disclosure issimilar to the methods for density configuration of the bank of the semiconductormemory according to the foregoing embodiments. The technical features not disclosed indetail according to the embodiments of the disclosure can be understood with referenceto the foregoing embodiments, which will not be repeated herein.[ 00204] The embodiments of the disclosure provide the semiconductor memory.Considering that the density configuration parameters of different target banks to beconfigured of the semiconductor memory may be different, the target codes determinedbased on the different density configuration parameters may further be different, and theregion selection signals generated based on the different target codes may further bedifferent. Therefore, different storage regions to be trimmed of different target banks tobe configured can be trimmed through different region selection signals, so that thestorage region(s) to be trimmed can be flexibly selected, and the effective utilization rateof the density configuration of the banks of the semiconductor memory is improved.[ 00205] It should be understood that in the embodiments of the disclosure, thedisclosed devices and methods may be implemented in a non-targeted manner. Theforegoing device embodiments are merely illustrative. For example, the division of theunits is only a logical function division. In actual implementation, there may be otherdivision methods. For example, a plurality of units or components may be combined, ormay be integrated into another system, or some features may be ignored or notimplemented.[ 00206] The features disclosed in the method or device embodiments of the disclosuremay be combined arbitrarily without conflict to obtain new method or deviceembodiments.[ 00207] The foregoing description is merely for the illustration of specificembodiments of the disclosure. The scope of protection of the disclosure is not limitedthereto. Those skilled in the art may make modifications or substitutions within thetechnical scope of the disclosure, which shall fall within the scope of the disclosure.Therefore, the scope of protection of the disclosure shall be defined by the scope of the

Claims

INDUSTRIAL APPLICABILITY[ 00208] In the embodiments of the disclosure, since the density configurationparameters of different target banks to be configured may be different, the target codesdetermined based on the different density configuration parameters may be different, andthe region selection signals generated based on the different target codes may further bedifferent. Therefore, different storage regions to be trimmed of different target banks tobe configured can be trimmed through different region selection signals, so that thestorage region to be trimmed can be flexibly selected, thereby improving the effectiveutilization rate of the density configuration of the banks of the semiconductor memory.CLAIMS1. A method for density configuration of a bank of a semiconductor memory, comprising:determining a target bank to be configured of the memory;determining a density configuration parameter of the target bank, wherein the densityconfiguration parameter is configured to represent a density to be configured for the targetbank;determining, based on the density configuration parameter of the target bank, a targetcode from a set of codes of the target bank, wherein the target code corresponds to a storageregion to be trimmed in the target bank;generating, based on the target code, a region selection signal configured to select thestorage region to be trimmed in the target bank; andtrimming the storage region to be trimmed based on the region selection signal toconfigure the density of the target bank.

2. The method of claim 1, wherein the density configuration parameter of the target bankcomprises at least one of:a target density of the target bank,the storage region to be trimmed in the target bank, oran available storage region in the target bank.

3. The method of claim 2, wherein in response to determining that the density configurationparameter of the target bank comprises the storage region to be trimmed in the target bank orthe available storage region in the target bank,determining, based on the density configuration parameter of the target bank, thetarget code from the set of codes of the target bank comprises:determining the storage region to be trimmed based on the storage region to betrimmed or the available storage region; anddetermining, based on the storage region to be trimmed, the target code from the set ofcodes of the target bank, wherein each code among the set of codes of the target bankcorresponds to at least one storage region to be trimmed in the target bank.

4. The method of claim 2 or 3, wherein in response to determining that the densityconfiguration parameter of the target bank comprises the target density of the target bank,determining, based on the density configuration parameter of the target bank, thetarget code from the set of codes of the target bank comprises:determining, from the set of codes of the target bank, a plurality of codescorresponding to the density configuration parameter of the target bank; andrandomly selecting, from the plurality of codes corresponding to the densityconfiguration parameter of the target bank, a code as the target code.

5. The method of any of claims 1 to 4, wherein generating, based on the target code, theregion selection signal configured to select the storage region to be trimmed in the target bankcomprises:determining, based on the target code, a row address of the storage region to betrimmed in the target bank; andgenerating, based on the target code and the row address of the storage region to betrimmed, the region selection signal configured to select the storage region to be trimmed inthe target bank.

6. The method of claim 5, wherein generating, based on the target code and the row address ofthe storage region to be trimmed, the region selection signal configured to select the storageregion to be trimmed in the target bank comprises:performing logic processing on the target code and the row address of the storageregion to be trimmed corresponding to the target code, to obtain a target level; andtaking the target level as the region selection signal.

7. The method of claim 6, wherein performing logic processing on the target code and the rowaddress of the storage region to be trimmed corresponding to the target code, to obtain thetarget level comprising:performing the logical processing on the target code and a high-bit address of the rowaddress of the storage region to be trimmed, to obtain the target level, the high-bit addressbeing configured to distinguish different storage regions in the target bank.

8. The method of any of claims 2 to 7, wherein in response to determining that the densityconfiguration parameter of the target bank comprises the target density of the target bank,determining, based on the density configuration parameter of the target bank, thetarget code from the set of codes of the target bank comprises:determining a maximum density of the target bank; anddetermining, based on the target density, the target code from the set of codes of thetarget bank, in response to the target density being less than the maximum density.

9. The method of any of claims 2 to 8, wherein the target bank comprises at least two logicstorage regions, and each of the at least two logic storage regions comprises at least twoconsecutive physical storage regions; wherein the storage region to be trimmed in the targetbank comprises at least two consecutive physical storage regions to be trimmed; andwherein in response to determining that the density configuration parameter of thetarget bank comprises the physical storage regions to be trimmed in the target bank,determining, based on the density configuration parameter of the target bank, thetarget code from the set of codes of the target bank comprises:determining, based on the at least two consecutive physical storage regions to betrimmed in the target bank, a logic storage region to be trimmed from the at least two logicstorage regions in the target bank; anddetermining, based on the logic storage region to be trimmed, the target code from theset of codes of the target bank.

10. The method of any of claims 1 to 7, wherein the density configuration parameter of thetarget banks comprises a target density of the target bank; wherein the target bank comprisesat least two logic storage regions, and each of the at least two logic storage regions comprisesat least two consecutive physical storage regions; andwherein determining, based on the density configuration parameter of the target bank,the target code from the set of codes of the target bank comprises:determining a density of each logic storage region and a maximum density of thetarget bank;determining at least one configurable density of the target bank based on the density ofeach logic storage region and the maximum density of the target bank, wherein the density ofeach logic storage region is a sum of densities of respective physical storage regions in thelogic storage region;determining, based on the at least one configurable density and the target density, anactual density to be configured; anddetermining, based on the actual density, the target code from the set of codes of thetarget bank, in response to the actual density being inconsistent with the target density.

11. The method of claim 10, further comprising:determining a density of each physical storage region in the target bank;determining a number of the consecutive physical storage regions in each logic storageregion; anddetermining, based on the number of the consecutive physical storage regions in eachlogic storage region and the density of each physical storage region, the density of the logicstorage region.

12. The method of claim 11, wherein determining the number of the consecutive physicalstorage regions in each logic storage region comprises:determining a number of bits of each code among the set of codes of the target bank;anddetermining the number of the physical storage regions in each logic storage regionbased on a number of the physical storage regions in the target bank and the number of bits ofeach code.

13. A semiconductor memory, comprising:a target bank, comprising at least two storage regions;an address processing unit, configured to output an address of the target bank, whereinan output terminal of the address processing unit is connected to the target bank;a code obtaining unit, configured to receive a target code, wherein the target codecorresponds to at least one storage region to be trimmed in the target bank;a region selection signal generation unit, configured to generate, based on the targetcode, a region selection signal configured to select the storage region to be trimmed in thetarget bank, wherein an output terminal of the region selection signal generation unit isconnected to an input terminal of a trim unit; andthe trim unit, configured to trim the storage region to be trimmed based on the regionselection signal to configure a density of the target bank, wherein an output terminal of thetrim unit is connected to the target bank.

14. The semiconductor memory of claim 13, further comprising:a control unit, configured to:determine the target bank to be configured of the semiconductor memory;determine a density configuration parameter of the target bank, wherein the densityconfiguration parameter is configured to represent the density to be configured for the targetbank; anddetermine, based on the density configuration parameter of the target bank, the targetcode from a set of codes of the target bank, wherein the target code corresponds to the storageregion to be trimmed in the target bank,wherein an output terminal of the control unit is connected to the code obtaining unit.

15. The semiconductor memory of claim 13 or 14, wherein the address processing unitcomprises:a row address processing unit, configured to output a row address of the target bank,wherein an output terminal of the row address processing unit is connected to an inputterminal of the region selection signal generation unit and the target bank;a column address processing unit, configured to output a column address of the targetbank, wherein an output terminal of the column address processing unit is connected to thetarget bank; anda bank address processing unit, configured to output a bank address of the target bank,wherein an output terminal of the bank address processing unit is connected to the targetbank;wherein the region selection signal generation unit is configured to perform logicprocessing on the target code and a row address of the storage region to be trimmedcorresponding to the target code to obtain a target level, and take the target level as the regionselection signal.

16. The semiconductor memory of claim 15, wherein an output terminal of a high-bit addressin the row address processing unit is connected to the input terminal of the region selectionsignal generation unit; andwherein the high-bit address is configured to distinguish different storage regions inthe target bank.

17. The semiconductor memory of claim 15 or 16, wherein the region selection signalgeneration unit comprises: a logic gate circuit comprising a NAND gate and a NOT gate;an input terminal of the logic gate circuit comprises a signal line corresponding to thetarget code and a signal line corresponding to the row address of the storage region to betrimmed; andthe logic gate circuit is configured to perform logic processing on the target code andthe row address of the storage region to be trimmed corresponding to the target code to obtainthe target level, and take the target level as the region selection signal.

18. The semiconductor memory of claim 15 or 16, wherein the region selection signalgeneration unit comprises a decoder;wherein an input terminal of the decoder is a signal line corresponding to the targetcode; andeach level output by the decoder is taken as a region selection signal when the level isvalid, and each output terminal of the decoder is connected to the input terminal of the trimunit.