Semiconductor device with spacer and method for fabricating the same

Abstract

This application discloses a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device includes: a substrate; an embedded conductive layer including: a bottom portion located in the substrate; and a top portion located in the substrate and on the bottom portion; an isolation layer located within the substrate; an air gap structure located in the isolation layer; and a recessed spacer located in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion is substantially coplanar with a top surface of the substrate. A bottom surface of the recessed spacer is substantially coplanar with a bottom surface of the bottom portion. A sidewall of the recessed spacer is substantially coplanar with a sidewall of the top portion.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 765,102 (i.e., priority date "July 5, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having spacers and a method for manufacturing the same. Prior Technology

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, this shrinkage process also introduces many problems, and these problems are constantly increasing. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The discussion in the preceding technical paragraphs is for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes the prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion in the preceding technical paragraphs, constitutes the prior art of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device comprising: a substrate; an embedded conductive layer including: a bottom portion located in the substrate; and a top portion located in the substrate and on the bottom portion; an isolation layer located within the substrate; an air gap structure located in the isolation layer; and a recessed spacer located in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion is substantially coplanar with a top surface of the substrate. A bottom surface of the recessed spacer is substantially coplanar with a bottom surface of the bottom portion. A sidewall of the recessed spacer is substantially coplanar with a sidewall of the top portion.

[0006] Another aspect of this disclosure provides a semiconductor device comprising: a substrate; an embedded conductive layer including: a bottom portion located in the substrate; and a top portion located in the substrate and on the bottom portion; a shallow trench isolation structure located in the substrate; and a recessed spacer located in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion is substantially coplanar with a top surface of the substrate. A bottom surface of the recessed spacer is substantially coplanar with a bottom surface of the bottom portion. A sidewall of the recessed spacer is substantially coplanar with a sidewall of the top portion.

[0007] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate and forming an isolation layer in the substrate to define a plurality of active regions; forming an opening in the substrate; conformally forming a spacer material in the opening; performing a spacer etching process to remove a portion of the spacer material and forming a recessed spacer in the opening; and forming an embedded conductive layer in the opening and covering the recessed spacer, wherein an air gap structure is formed in the isolation layer.

[0008] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate and forming an isolation layer in the substrate to define a plurality of active regions; forming an opening in the substrate; conformally forming a spacer material in the opening; performing a spacer etching process to remove a portion of the spacer material and forming an in-groove spacer in the opening; and forming an embedded conductive layer in the opening and covering the in-groove spacer, wherein a shallow trench isolation structure is formed in the substrate.

[0009] Due to the design of the semiconductor device disclosed herein, the electric field near the buried conductive layer can be reduced by using spacers within the groove. Therefore, the gate-induced drain leakage current can be reduced due to the lower electric field. This improves the performance of the semiconductor device.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0011] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the drawings that combine the embodiments with the scope of the patent application. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased. Figure 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 2 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 3 is a cross-sectional view taken along the sections A-A' and B-B' in Figure 2. Figure 4 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of this disclosure. Figure 5 is a cross-sectional view taken along the sections A-A' and B-B' in Figure 4. Figure 6 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 7 is a cross-sectional view taken along the sections A-A' and B-B' in Figure 6. Figure 8 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figures 9 to 20 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 8. Figure 21 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 22 is a cross-sectional view taken along the sections A-A' and B-B' in Figure 21. Figure 23 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figures 24 and 25 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 23. Figure 26 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figures 27 and 28 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 26. Figure 29 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figures 30 and 31 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 29. Figure 32 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 33 is a cross-sectional view taken along the sections A-A' and B-B' in Figure 32. Figure 34 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figures 35 and 36 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 29. Figure 37 is a cross-sectional view taken along the sections A-A' and B-B' in Figure 32. Implementation

[0012] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used in this document to describe the relative relationship between one element or feature depicted in the diagram and another. In addition to the orientations shown in the diagram, spatially related terms are intended to cover different orientations of the element during use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0014] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to the other component or layer, or there may be intermediate components or intermediate layers.

[0015] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one component from another. Thus, for example, the first component, first member, or first part discussed below may be referred to as the second component, second member, or second part without departing from the teachings of this disclosure.

[0016] Unless the context otherwise indicates, terms such as “identical,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure when referring to orientation, layout, location, shape, size, quantity, or other measure, but are intended to cover substantially identical orientations, layouts, locations, shapes, sizes, quantities, or other measures within an acceptable range of possible variations (e.g., due to manufacturing processes). The term “substantially” may be used herein to reflect this meaning. For example, articles described as “substantially identical,” “substantially equal,” or “substantially coplanar” may be exactly the same, equal, or coplanar, or may be substantially identical, equal, or coplanar within an acceptable range of possible variations (e.g., due to manufacturing processes).

[0017] In this disclosure, semiconductor devices generally refer to devices that can operate using semiconductor properties, and electro-optic devices, light-emitting display devices, semiconductor circuits and electronic devices are all included in the category of semiconductor devices.

[0018] It should be noted that in the description disclosed herein, "above" (or "up") corresponds to the direction of the arrow in the Z direction, and "below" (or "down") corresponds to the opposite direction of the arrow in the Z direction.

[0019] It should be noted that, in the description of this disclosure, the terms "to form," "to be formed," and "form" can mean and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, lithography, dry etching, and wet etching.

[0020] It should be noted that, in the description of this disclosure, the functions or steps mentioned herein may occur in a different order than that shown in the diagrams. For example, two diagrams shown consecutively may actually be performed substantially simultaneously or sometimes in reverse order, depending on the functions or steps involved.

[0021] Figure 1 is a flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figure 2 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figure 3 is a cross-sectional view taken along sections A-A' and B-B' in Figure 2. Figure 4 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figure 5 is a cross-sectional view taken along sections A-A' and B-B' in Figure 4. Figure 6 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figure 7 is a cross-sectional view taken along sections A-A' and B-B' in Figure 6. Figure 8 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figure 9 is a cross-sectional view illustrating a portion of the manufacturing process of the semiconductor device 1A according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 8.

[0022] Referring to Figures 1 to 9, in step S11, a substrate 101 can be provided, an isolation layer 107 can be formed in the substrate 101 to define a plurality of active regions AA, and a plurality of character line trenches 703 can be formed in the substrate 101 to divide the plurality of active regions AA into a plurality of first regions R1 and a plurality of second regions R2.

[0023] Referring to Figures 2 and 3, in some embodiments, substrate 101 may include a main semiconductor substrate made of at least one semiconductor material. The main semiconductor substrate may be formed of, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0024] In some embodiments, substrate 101 may include a semiconductor-on-insulator substrate, which comprises, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer may be formed of the same material as the aforementioned main semiconductor substrate. The insulating layer may be a crystalline or amorphous dielectric material, such as oxides and / or nitrides. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is that the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides in any order, which is a stack of silicon oxide and either silicon nitride or boron nitride. The insulating layer may have a thickness between about 10 nm and 200 nm. The insulating layer can eliminate leakage current between adjacent elements in substrate 101 and reduce parasitic capacitance associated with the source / drain.

[0025] It should be noted that the term "about," used to modify the amount of ingredients, components, or reactants disclosed herein, refers, for example, to numerical variations that may occur through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to unintentional errors in the measurement procedures, differences in the manufacture, source, or purity of the ingredients used to prepare the composition or to carry out the method. On one hand, the term "about" means within 10% of the reported value. On another hand, the term "about" means within 5% of the reported value. And yet another hand, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0026] Referring to Figures 2 and 3, a series of deposition processes can be performed to deposit pad oxide 103 and pad nitride 105 on substrate 101. A photolithography process can be performed to form a first mask layer 801 on pad nitride 105 and define the position of isolation layer 107.

[0027] Referring to Figures 4 and 5, after the photolithography process, an etching process, such as anisotropic dry etching, can be performed to form a first trench 701 that penetrates the pad oxide 103 and the pad nitride 105 and extends into the substrate 101. After the first trench 701 is formed, the first mask layer 801 can be removed.

[0028] Referring to Figures 6 and 7, an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, can be deposited into the first trench 701, and a planarization process, such as chemical mechanical polishing, can then be performed to remove excess filler material until the top surface of the substrate 101 is exposed to form an insulating layer 107.

[0029] Referring to Figures 6 and 7, the isolation layer 107 can define a plurality of active regions AA. In some embodiments, when viewed from a top viewpoint, the plurality of active regions AA can extend in directions at an angle relative to the X-axis and Y-axis.

[0030] It should be noted that each of the active regions AA may include a portion of the substrate 101 and the space above that portion of the substrate 101. When describing a component as being disposed on the active region AA, it means that the component is disposed on the top surface of that portion of the substrate 101. When describing a component as being disposed in the active region AA, it means that the component is disposed in that portion of the substrate 101; however, the top surface of the component may be flush with the top surface of that portion of the substrate 101. When describing a component as being disposed above the active region AA, it means that the component is disposed above the top surface of that portion of the substrate 101.

[0031] It should be noted that, in the description of this disclosure, the surface of the element (or feature) at its highest vertical height along the Z-axis is referred to as the top surface of this element (or feature). The surface of the element (or feature) at its lowest vertical height along the Z-axis is referred to as the bottom surface of this element (or feature).

[0032] It should be noted that silicon nitride in this disclosure refers to a substance containing silicon, nitrogen, and oxygen, with the proportion of oxygen being greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, with the proportion of nitrogen being greater than the proportion of oxygen.

[0033] Referring to Figures 8 and 9, a plurality of character line trenches 703 can be formed in the substrate 101 to define the positions of the plurality of character line structures 200 described below. The plurality of character line trenches 703 can be formed by a photolithography process and subsequent etching process. In some embodiments, when viewed from a top viewpoint, the plurality of character line trenches 703 can have a linear shape and extend along the X direction, spanning a plurality of active regions AA. For example, each active region AA can be intersected by two character line trenches 703. The plurality of character line trenches 703 can divide each of the plurality of active regions AA into a plurality of first regions R1 and a plurality of second regions R2. For one active region AA, a first region R1 can be formed between two character line trenches 703, and two second regions R2 can be formed respectively and correspondingly between the isolation layer 107 and the two character line trenches 703.

[0034] Figures 10 to 20 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 8. Figure 21 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figure 22 is a cross-sectional view taken along sections A-A' and B-B' in Figure 21.

[0035] Referring to Figures 1 and 10 to 22, in step S13, a plurality of character line structures 200 can be formed in a plurality of character line grooves 703.

[0036] Referring to Figure 10, a first dielectric material 601 can be compliantly formed on the pad nitride 105, the insulating layer 107, and the plurality of character line trenches 703. This first dielectric material 601 can have a U-shaped cross-sectional profile in the plurality of character line trenches 703. In some embodiments, this first dielectric material 601 can have a thickness between about 1 nm and about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0037] In some embodiments, the first dielectric material 601 may be formed by a thermal oxidation process. For example, the first dielectric material 601 may be formed by oxidizing the surfaces of a plurality of character line trenches 703. In some embodiments, the first dielectric material 601 may be formed by a deposition process, such as chemical vapor deposition or atomic layer deposition. The first dielectric material 601 may include a high dielectric constant material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, the first dielectric material 601 may be formed by radical oxidation of the polycrystalline silicon liner (not shown for clarity) after deposition. In some embodiments, the first dielectric material 601 may be formed by radical oxidation of the silicon nitride liner (not shown for clarity) after formation of the silicon nitride liner.

[0038] In some embodiments, the high dielectric constant material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high dielectric constant material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0039] Referring to Figure 11, a first conductive material 611 can be formed on this first dielectric material 601 and completely fill the plurality of character line trenches 703. In some embodiments, the first conductive material 611 can be a work function material, such as titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. It should be noted that the term "work function" refers to the bulk chemical potential of a material (e.g., a metal) relative to a vacuum level.

[0040] For example, in this embodiment, the first conductive material 611 is titanium nitride and can be formed by chemical vapor deposition. In some embodiments, the formation of this first conductive material 611 layer may include: a source gas introduction step, a first purging step, a reactant flow step, and a second purging step. The source gas introduction step, the first purging step, the reactant flow step, and the second purging step may be collectively referred to as a cycle. A plurality of cycles may be performed to obtain the desired thickness of this first conductive material 611 layer.

[0041] In some embodiments, the intermediate semiconductor element shown in FIG10 can be loaded into a reaction chamber. In the source gas introduction step, a source gas containing precursors and reactants can be introduced into the reaction chamber containing the intermediate semiconductor element. The precursors and reactants can diffuse through the boundary layer and reach the surface of the intermediate semiconductor element (i.e., the surface of the first dielectric material 601). The precursors and reactants can adsorb onto the surface of the intermediate semiconductor element and subsequently migrate on the surface. The adsorbed precursors and adsorbed reactants can react on the surface to form solid byproducts. The solid byproducts can form nuclei on the surface. The nuclei can grow into islands, and the islands can merge on the surface into a continuous thin film. In the first purging step, a purging gas (e.g., argon) can be injected into the reaction chamber to purge gaseous byproducts, unreacted precursors, and unreacted reactants.

[0042] In the reactant flow step, reactants can be introduced individually into the reaction chamber to transform the continuous thin film into this first conductive material 611. In the second purging step, a purging gas (e.g., argon) can be injected into the reaction chamber to purge gaseous byproducts and unreacted reactants.

[0043] In some embodiments, the formation of this first conductive material 611 using chemical vapor deposition can be performed with the aid of plasma. The plasma source can be, for example, argon, hydrogen, or a combination thereof.

[0044] For example, the precursor can be titanium tetrachloride. The reactant can be ammonia. Due to the incomplete reaction between titanium tetrachloride and ammonia, titanium tetrachloride and ammonia may react on the aforementioned surface and form a titanium nitride film containing high chloride contamination. The ammonia in the reactant flow step can reduce the chloride content of the titanium nitride film. After ammonia treatment, the titanium nitride film can be referred to as the first conductive material 611 of this layer.

[0045] Alternatively, in some other embodiments, the first conductive material 611 can be formed by atomic layer deposition, such as photo-assisted atomic layer deposition or liquid injection atomic layer deposition. In some embodiments, the formation of the first conductive material 611 may include: a first precursor introduction step, a first purging step, a second precursor introduction step, and a second purging step. The first precursor introduction step, the first purging step, the second precursor introduction step, and the second purging step may be collectively referred to as a cycle. A plurality of cycles may be performed to obtain the desired thickness of the first conductive material 611.

[0046] In some embodiments, the intermediate semiconductor element shown in FIG10 can be loaded into the reaction chamber. In the first precursor introduction step, a first precursor can be introduced into the reaction chamber. The first precursor can diffuse through the boundary layer and reach the surface of the intermediate semiconductor element (i.e., the surface of the first dielectric material 601). The first precursor can adsorb onto the surface to form a monolayer at the single atomic layer level. In the first purging step, a purging gas (e.g., argon) can be injected into the reaction chamber to purge unreacted first precursor.

[0047] In the second precursor introduction step, a second precursor can be introduced into the reaction chamber. The second precursor can react with the monolayer and transform the monolayer into the first conductive material 611. In the second purging step, a purging gas (e.g., argon) can be injected into the reaction chamber to purge unreacted second precursor and gaseous byproducts. Compared to chemical vapor deposition, because the first and second precursors are introduced separately, particle generation caused by gas-phase reactions can be suppressed.

[0048] For example, the first precursor can be titanium tetrachloride. The second precursor can be ammonia. The adsorbed titanium tetrachloride can form a titanium nitride monolayer. The ammonia in the second precursor introduction step can react with the titanium nitride monolayer and transform this titanium nitride monolayer into the first conductive material 611 of this layer.

[0049] In some embodiments, the formation of this first conductive material 611 using atomic layer deposition can be performed with the assistance of plasma. The plasma source can be, for example, argon, hydrogen, oxygen, or a combination thereof. In some embodiments, the oxygen source can be, for example, water, oxygen, or ozone. In some embodiments, a co-reactant can be introduced into the reaction chamber. The co-reactant can be selected from the group consisting of hydrogen, hydrogen plasma, oxygen, air, water, ammonia, hydrazine, alkylhydrazine, borane, silane, ozone, and combinations thereof.

[0050] In some embodiments, the formation of this first conductive material 611 layer can be performed using the following process conditions: The substrate temperature can be between about 160°C and about 300°C. The evaporator temperature can be about 175°C. The pressure in the reaction chamber can be about 5 mbar. The solvent for the first and second precursors can be toluene.

[0051] Referring to Figure 12, a first etching process can be performed to remove a portion of the first conductive material 611. In some embodiments, during the first etching process, the ratio of the etching rate of the first conductive material 611 to the etching rate of the first dielectric material 601 can be between about 100:1 and about 1.05:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. After the first etching process, the remaining first conductive material 611 in the plurality of character line trenches 703 can be referred to as a plurality of bottom conductive layers 221.

[0052] Referring to Figure 13, a first substrate material 621 can be compliantly formed on the first dielectric material 601 and on the plurality of bottom conductive layers 221. In some embodiments, the first substrate material 621 may be a material that is etch-selective to the first dielectric material 601. In some embodiments, the first substrate material 621 may be a material that is etch-selective to the pad nitride 105. In some embodiments, the first substrate material 621 may be, for example, a material comprising carbon atoms mixed with sp2. In some embodiments, the first substrate material 621 may be, for example, a material comprising carbon having a hexagonal crystal structure. In some embodiments, the first substrate material 621 may be, for example, graphene, graphite, or other similar materials.

[0053] In some embodiments, this first liner material 621 may be formed on a catalyst substrate and then transferred onto the intermediate semiconductor element shown in FIG12. The catalyst substrate may include nickel, copper, cobalt, platinum, silver, ruthenium, iridium, palladium, an alloy of iron and nickel, an alloy of copper and nickel, an alloy of nickel and molybdenum, an alloy of gold and nickel, or an alloy of cobalt and copper.

[0054] In some embodiments, this first liner material 621 can be formed with the assistance of a catalyst. The catalyst can be a single-crystal metal, a polycrystalline metal, a binary alloy, or a liquid metal. The single-crystal metal or polycrystalline metal can be, for example, nickel, copper, cobalt, platinum, silver, ruthenium, iridium, or palladium. The binary alloy can be, for example, an alloy of iron and nickel, an alloy of copper and nickel, an alloy of nickel and molybdenum, an alloy of gold and nickel, or an alloy of cobalt and copper. The liquid metal can be, for example, liquid gallium, liquid indium, or liquid copper.

[0055] In some embodiments, a catalytic conductive layer (not shown for clarity) may be compliantly formed on the first dielectric material 601 and on a plurality of bottom conductive layers 221. A first liner material 621 may be formed on the catalytic conductive layer. The catalytic conductive layer may include nickel, copper, cobalt, platinum, silver, ruthenium, iridium, palladium, an alloy of iron and nickel, an alloy of copper and nickel, an alloy of nickel and molybdenum, an alloy of gold and nickel, or an alloy of cobalt and copper.

[0056] Referring to Figure 14, a second conductive material 613 can be formed on this first substrate material 621 and can completely fill the plurality of character line trenches 703. In some embodiments, the second conductive material 613 can be, for example, tungsten, tungsten nitride, or a combination thereof. In some embodiments, this second conductive material 613 can be formed by, for example, pulse nucleation, chemical vapor deposition, physical vapor deposition, or other suitable deposition processes. In some embodiments, a planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially flat surface for subsequent process steps.

[0057] Referring to Figure 15, a second etching process can be performed to remove a portion of the second conductive material 613. In some embodiments, during the second etching process, the ratio of the etching rate of the second conductive material 613 to the etching rate of the first substrate material 621 can be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. After the second etching process, the remaining second conductive material 613 in the plurality of character line trenches 703 can be referred to as a plurality of intermediate conductive layers 223.

[0058] Referring to Figure 16, a second liner material 623 can be compliantly formed on the first liner material 621 and on the plurality of intermediate conductive layers 223. In some embodiments, the second liner material 623 may be a material that is etch-selective to the first dielectric material 601. In some embodiments, the second liner material 623 may be the same material as the first liner material 621. In some embodiments, the second liner material 623 may be a material that is etch-selective to the pad nitride 105. In some embodiments, the second liner material 623 may be, for example, a material comprising carbon atoms mixed with sp2. In some embodiments, the second liner material 623 may be, for example, a material comprising carbon having a hexagonal crystal structure. In some embodiments, the second liner material 623 may be, for example, graphene, graphite, or other similar materials.

[0059] In some embodiments, this second liner material 623 may be formed on a catalyst substrate and then transferred onto the intermediate semiconductor element shown in FIG. 15. The catalyst substrate may include nickel, copper, cobalt, platinum, silver, ruthenium, iridium, palladium, an alloy of iron and nickel, an alloy of copper and nickel, an alloy of nickel and molybdenum, an alloy of gold and nickel, or an alloy of cobalt and copper.

[0060] In some embodiments, the second liner material 623 may be formed with the assistance of a catalyst. The catalyst may be a single-crystal metal, a polycrystalline metal, a binary alloy, or a liquid metal. The single-crystal or polycrystalline metal may be, for example, nickel, copper, cobalt, platinum, silver, ruthenium, iridium, or palladium. The binary alloy may be, for example, an alloy of iron and nickel, an alloy of copper and nickel, an alloy of nickel and molybdenum, an alloy of gold and nickel, or an alloy of cobalt and copper. The liquid metal may be, for example, liquid gallium, liquid indium, or liquid copper.

[0061] In some embodiments, a catalytic conductive layer (not shown for clarity) may be compliantly formed on the first liner material 621 and on a plurality of intermediate conductive layers 223. A second liner material 623 may be formed on the catalytic conductive layer. The catalytic conductive layer may include nickel, copper, cobalt, platinum, silver, ruthenium, iridium, palladium, alloys of iron and nickel, alloys of copper and nickel, alloys of nickel and molybdenum, alloys of gold and nickel, or alloys of cobalt and copper.

[0062] Referring to Figure 17, a third conductive material 615 can be formed on this second liner material 623 and can completely fill the plurality of character line trenches 703. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, the third conductive material 615 can be, for example, molybdenum or other suitable conductive material.

[0063] In some embodiments, the third conductive material 615 may be formed by a chemical vapor deposition process. For example, the intermediate semiconductor element shown in FIG16 may be exposed in a molybdenum precursor and reactants. In some embodiments, the reactants may flow continuously, and the flow of the molybdenum precursor into the chamber may be turned on and off.

[0064] In some embodiments, the molybdenum precursor may include molybdenum halide. In some embodiments, molybdenum halide may include molybdenum fluoride, molybdenum chloride, or a combination thereof. In some embodiments, the molybdenum precursor may be flowed through the intermediate semiconductor element shown in FIG16 using a carrier gas. In some embodiments, the carrier gas may flow through an ampoule containing the molybdenum precursor. In some embodiments, the carrier gas may be an inert gas. In some embodiments, the inert gas may include one or more of nitrogen (N2), argon (Ar), and helium (He).

[0065] In some embodiments, the flow rate of the molybdenum precursor can be in the range of 100 slm (standard liters / minute) to 1000 slm, 100 slm to 700 slm, 100 slm to 400 slm, 400 slm to 1000 slm, 400 slm to 700 slm, or 700 slm to 1000 slm. In some embodiments, the duration of the molybdenum precursor can be in the range of 0.3 seconds to 5 seconds, 0.3 seconds to 3 seconds, 0.3 seconds to 1 second, 1 second to 5 seconds, 1 second to 3 seconds, or 3 seconds to 5 seconds.

[0066] In some embodiments, the intermediate semiconductor element shown in FIG16 may be exposed to a continuous fluid or a plurality of pulses of the molybdenum precursor. In some embodiments, the pulse duration of the plurality of pulses of the molybdenum precursor may be in the range of 0.3 seconds to 30 seconds, 0.3 seconds to 10 seconds, 0.3 seconds to 5 seconds, 0.3 seconds to 1 second, 0.5 seconds to 5 seconds, 1 second to 30 seconds, 1 second to 10 seconds, 1 second to 5 seconds, 5 seconds to 30 seconds, 5 seconds to 10 seconds, or 10 seconds to 30 seconds.

[0067] In some embodiments, the duration of each of the plurality of pulses of the molybdenum precursor applied may be in the range of 0.3 seconds to 5 seconds, 0.3 seconds to 3 seconds, 0.3 seconds to 1 second, 1 second to 5 seconds, 1 second to 3 seconds, or 3 seconds to 5 seconds. In some embodiments, the duration of at least one of the plurality of pulses of the molybdenum precursor applied may be in the range of 0.3 seconds to 5 seconds, 0.3 seconds to 3 seconds, 0.3 seconds to 1 second, 1 second to 5 seconds, 1 second to 3 seconds, or 3 seconds to 5 seconds.

[0068] In some embodiments, the reactants may include an oxidizing agent, a reducing agent, or a combination thereof. In some embodiments, the reactants may include hydrogen, ammonia, silane, polysilane, or a combination thereof. In some embodiments, the silane may be selected from one or more of disilane, trisilane, tetrasilane, higher order silanes, and substituted silanes. In some embodiments, the first reactant may be passed through the intermediate semiconductor element shown in FIG16 using a carrier gas. In some embodiments, the carrier gas may be an inert gas. In some embodiments, the inert gas may include one or more of nitrogen, argon, and helium.

[0069] In some embodiments, the flow rate of the reactants may be in the range of 0.5 slm to 15 slm, 0.5 slm to 10 slm, 0.5 slm to 5 slm, 5 slm to 15 slm, 5 slm to 10 slm, or 10 slm to 15 slm. In some embodiments, the duration of the reactants may be in the range of 0.5 seconds to 10 seconds, 0.5 seconds to 5 seconds, 0.5 seconds to 1 second, 1 second to 10 seconds, 1 second to 5 seconds, or 5 seconds to 10 seconds.

[0070] In some embodiments, the intermediate semiconductor element shown in FIG16 may be exposed to a continuous fluid of reactants or to a plurality of pulses. In some embodiments, the pulse duration of the plurality of pulses of reactants may be in the range of 0.3 seconds to 30 seconds, 0.3 seconds to 10 seconds, 0.3 seconds to 5 seconds, 0.3 seconds to 1 second, 0.5 seconds to 5 seconds, 1 second to 30 seconds, 1 second to 10 seconds, 1 second to 5 seconds, 5 seconds to 30 seconds, 5 seconds to 10 seconds, or 10 seconds to 30 seconds.

[0071] In some embodiments, the duration of each of the plurality of pulses of the reactant applied may be in the range of 0.5 seconds to 10 seconds, 0.5 seconds to 5 seconds, 0.5 seconds to 1 second, 1 second to 10 seconds, 1 second to 5 seconds, or 5 seconds to 10 seconds. In some embodiments, the duration of at least one of the plurality of pulses of the reactant applied may be in the range of 0.5 seconds to 10 seconds, 0.5 seconds to 5 seconds, 0.5 seconds to 1 second, 1 second to 10 seconds, 1 second to 5 seconds, or 5 seconds to 10 seconds.

[0072] In some embodiments, this third conductive material 615 may be formed under the following pressures: a range of 2 Torr to 60 Torr, a range of 2 Torr to 40 Torr, a range of 2 Torr to 20 Torr, a range of 20 Torr to 60 Torr, a range of 20 Torr to 40 Torr, or a range of 40 Torr to 60 Torr. In some embodiments, this third conductive material 615 may be formed at the following temperatures: a range of 350°C to 550°C, a range of 350°C to 500°C, a range of 350°C to 450°C, a range of 350°C to 400°C, a range of 400°C to 550°C, a range of 400°C to 450°C, a range of 450°C to 550°C, a range of 450°C to 500°C, or a range of 500°C to 550°C.

[0073] In some embodiments, after the formation of this third conductive material 615, an annealing process may be performed as needed. In some embodiments, the annealing process may be performed at a temperature higher than the formation temperature of this third conductive material 615. In some embodiments, the annealing process may be performed at temperatures ranging from 100°C to 550°C, from 100°C to 450°C, from 100°C to 350°C, from 100°C to 250°C, from 200°C to 550°C, from 200°C to 450°C, from 200°C to 350°C, from 300°C to 550°C, from 300°C to 450°C, or from 400°C to 550°C.

[0074] In some embodiments, the environment of the annealing process may include one or more of an inert gas (e.g., molecular nitrogen, argon) and a reducing gas (e.g., molecular hydrogen or ammonia).

[0075] In some embodiments, the duration of the annealing process can range from 1 hour to 24 hours, from 1 hour to 20 hours, from 1 hour to 15 hours, from 1 hour to 10 hours, from 1 hour to 5 hours, from 5 hours to 24 hours, from 5 hours to 20 hours, from 5 hours to 15 hours, from 5 hours to 10 hours, from 10 hours to 24 hours, from 10 hours to 20 hours, from 10 hours to 15 hours, from 15 hours to 24 hours, from 15 hours to 20 hours, or from 20 hours to 24 hours. The annealing process can increase the density of the plurality of layers of the third conductive material 615, reduce the resistivity, and / or increase the purity.

[0076] Referring to Figure 18, a third etching process can be performed to remove a portion of the third conductive material 615. In some embodiments, during the third etching process, the ratio of the etching rate of the third conductive material 615 to the etching rate of the second substrate material 623 can be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0077] After the third etching process, the remaining third conductive material 615 in the plurality of character line trenches 703 can be referred to as the plurality of top conductive layers 225.

[0078] Referring to Figure 19, a removal process can be performed to remove portions of the second substrate material 623, the first substrate material 621, and the first dielectric material 601. In some embodiments, the removal process can be a multi-stage etching process. For example, the removal process can be a two-stage anisotropic dry etching process. The etching chemicals in each stage can be different to provide different etching selectivity.

[0079] In some embodiments, during the first stage of the removal process, the ratio of the etching rate of the second liner material 623 (and the first liner material 621) to the etching rate of the first dielectric material 601 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the first stage of the removal process, the ratio of the etching rate of the second liner material 623 (and the first liner material 621) to the etching rate of the plurality of top conductive layers 225 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0080] In some embodiments, during the second stage of the removal process, the ratio of the etching rate of the first dielectric material 601 to the etching rate of the pad nitride 105 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the second stage of the removal process, the ratio of the etching rate of the first dielectric material 601 to the etching rate of the plurality of top conductive layers 225 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0081] Referring to Figure 19, after the removal process, the remaining second liner material 623 in the plurality of character line trenches 703 can be referred to as a plurality of top liners 233. The top liners 233 can have a U-shaped cross-sectional profile. The remaining first liner material 621 in the plurality of character line trenches 703 can be referred to as a plurality of bottom liners 231. The bottom liners 231 can have a U-shaped cross-sectional profile. The remaining first dielectric material 601 in the plurality of character line trenches 703 can be referred to as a plurality of character line dielectric layers 211. The plurality of character line dielectric layers 211 can have a U-shaped cross-sectional profile.

[0082] In some embodiments, the top surfaces 211TS of a plurality of character line dielectric layers 211, the top surfaces 231TS of a plurality of bottom liner layers 231, the top surfaces 233TS of a plurality of top line liner layers 233, and the top surfaces 225TS of a plurality of top conductive layers 225 may be substantially coplanar.

[0083] Referring to Figure 20, a cover material 603 can be formed to completely fill the plurality of character line trenches 703. In some embodiments, the cover material 603 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride, or other suitable materials. In some embodiments, the cover material 603 may be, for example, germanium oxide. In some embodiments, this cover material 603 may be formed by, for example, chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0084] For example, when this cover material 603 is formed by atomic layer deposition, the atomic layer deposition process may include using a gaseous germanium precursor and an oxygen-containing reactant (also known as an oxygen source) to alternately and sequentially contact the intermediate semiconductor element shown in FIG19, so that a germanium precursor is formed on the surface of the intermediate semiconductor element, and then the oxygen-containing reactant reacts with the germanium precursor to form this cover material 603.

[0085] In detail, a germanium precursor can be introduced into a process chamber containing an intermediate semiconductor element as shown in Figure 19 via a gas-phase pulse, and the germanium precursor is brought into contact with the surface of the intermediate semiconductor element. Excess germanium precursor and reaction byproducts (if any) can be removed from the intermediate semiconductor element, from the surface of the intermediate semiconductor element, and from the vicinity of the intermediate semiconductor element.

[0086] In some embodiments, excess germanium precursors and reaction byproducts (if any) can be removed by purging. For example, purging can be performed using pulses of an inert gas (e.g., nitrogen or argon). Purging a process chamber means removing gaseous precursors and / or gaseous byproducts from the process chamber, for example, by evacuating the process chamber using a vacuum pump and / or by replacing the gas inside the process chamber with an inert gas (e.g., argon or nitrogen). In some embodiments, the purging time can be between about 0.05 seconds and about 20 seconds, between about 1 second and about 10 seconds, or between about 1 second and about 20 seconds.

[0087] An oxygen source can be pulsed into a process chamber, where it reacts with a germanium precursor on the surface of an intermediate semiconductor element to form a capping material 603 comprising germanium oxide. Excess oxygen source and gaseous byproducts of the surface reaction can be removed from the intermediate semiconductor element, for example, by purging them out of the process chamber using an inert gas.

[0088] The pulse and removal steps can be repeated until the layer covering material 603 reaches the desired thickness on the intermediate semiconductor device.

[0089] In some embodiments, the germanium precursor is not a halide. In some embodiments, the germanium precursor may include a halogen in at least one ligand, but not in all ligands. In some embodiments, the germanium precursor may include ethoxy germanium or tetra(dimethylamino) germanium.

[0090] In some embodiments, the oxygen source may be water, ozone, oxygen plasma, oxygen radicals, or oxygen atoms. In some embodiments, the oxygen source is not water. In some embodiments, the germanium precursor used may be a solid, liquid, or gaseous material at standard temperature and pressure, provided that the germanium precursor is in the gas phase before being introduced into the process chamber and brought into contact with the intermediate semiconductor element.

[0091] It should be noted that, in this disclosure, the term "pulse delivery" of the evaporated precursor refers to the introduction of the precursor vapor into the process chamber for a limited period of time. In some embodiments, the duration of pulse delivery of the germanium precursor may be between about 0.05 seconds and about 10 seconds, between about 0.1 seconds and about 5 seconds, or between about 0.3 seconds and about 3 seconds. In some embodiments, the duration of pulse delivery of the oxygen source may be between about 0.05 seconds and about 10 seconds, between about 0.1 seconds and about 5 seconds, or between about 0.2 seconds and about 3 seconds.

[0092] In some embodiments, the oxygen source may be an oxygen-containing gas pulse and may be a mixture of oxygen and an inert gas (e.g., nitrogen or argon). In some embodiments, the oxygen source may be a gas pulse containing molecular oxygen. The oxygen content of the oxygen source gas may be between about 10% and about 25%. Therefore, one of the oxygen sources may be air.

[0093] In some embodiments, the oxygen source may be molecular oxygen. In some embodiments, the oxygen source may include activated or excited oxygen. In some embodiments, the oxygen source may include ozone. In some embodiments, the oxygen source may be pure ozone, or a mixture of ozone, molecular oxygen, and other gases, such as inert gases (e.g., nitrogen or argon).

[0094] Ozone can be generated by an ozone generator and introduced into the process chamber using an inert gas (e.g., nitrogen) or oxygen. In some embodiments, ozone can be provided at a concentration between about 5% to about 40% by volume, or between about 15% to about 25% by volume. In some embodiments, the oxygen source can be oxygen plasma. In some embodiments, ozone or a mixture of ozone and other gases can be pulsed into the process chamber. In some embodiments, ozone can be formed inside the process chamber, for example, by introducing oxygen-containing gas through an electric arc. In some embodiments, oxygen-containing plasma can be formed in the process chamber. In some embodiments, plasma can be formed upstream of the process chamber in a remote plasma generator, and plasma products can be guided into the process chamber to contact intermediate semiconductor devices.

[0095] In some embodiments, the oxygen source may be any source other than water. Therefore, water is not provided in such embodiments.

[0096] In some embodiments, the forming temperature of this covering material 603 may be between about 20°C and about 600°C, between about 100°C and about 400°C, or between about 150°C and about 300°C.

[0097] In some embodiments, the covering material 603 is a pure germanium oxide layer. That is, apart from trace impurities, no other metal or half-metal elements are present in the covering material 603. In some embodiments, the covering material 603 may include less than 1 atomic% of non-germanium metal or half-metal elements. In some embodiments, the covering material 603 may include less than about 5 atomic% of any non-hydrogen impurities, less than about 3 atomic% of any non-hydrogen impurities, or less than about 1 atomic% of any non-hydrogen impurities.

[0098] Referring to Figures 21 and 22, a planarization process can be performed until the top surface of the pad nitride 105 is exposed. After the planarization process, the remaining cover material 603 can be referred to as the plurality of character line cover layers 213. In some embodiments, the planarization process can be an etching process, a chemical mechanical polishing process, or a combination thereof. At this stage, the top surface of the pad nitride 105 and the top surface of the plurality of character line cover layers 213 can be substantially coplanar.

[0099] Referring to Figures 21 and 22, a plurality of character line dielectric layers 211, a plurality of character line cover layers 213, a plurality of bottom conductive layers 221, a plurality of intermediate conductive layers 223, a plurality of top conductive layers 225, a plurality of bottom liner layers 231, and a plurality of top liner layers 233 together constitute a plurality of character line structures 200.

[0100] In some embodiments, the bottom liner 231 and the intermediate conductive layer 223 can be configured to work in conjunction with the bottom conductive layer 221 to adjust the work function, thereby obtaining a character line structure 200 with low resistance. In this way, the performance of the character line structure 200 is improved.

[0101] By employing a word line capping layer 213 formed of germanium oxide, leakage current in the word line structure 200 can be prevented and trap density can be reduced. As a result, the performance of semiconductor device 1A is improved.

[0102] In some embodiments, the complex number of character line structures 200 may have a power function greater than or equal to 4.3 eV. In some embodiments, the complex number of character line structures 200 may have a power function greater than or equal to 4.5 eV. In some embodiments, the complex number of character line structures 200 may have a power function greater than or equal to 4.3 eV, including greater than or equal to 4.4 eV, greater than or equal to 4.5 eV, greater than or equal to 4.6 eV, greater than or equal to 4.7 eV, greater than or equal to 4.8 eV, greater than or equal to 4.9 eV, greater than or equal to 5.0 eV, greater than or equal to 5.1 eV, or greater than or equal to 5.2 eV.

[0103] In some embodiments, when the total thickness is 100 Å, the resistance of the plurality of character line structures 200 can be less than or equal to 40 μΩ-cm, less than or equal to 30 μΩ-cm, less than or equal to 25 μΩ-cm, less than or equal to 20 μΩ-cm, or less than or equal to 15 μΩ-cm. In some embodiments, when the total thickness is 100 Å, the plurality of character line structures 200 can have a resistance less than or equal to 20 μΩ-cm. In some embodiments, when the total thickness is 100 Å, the resistance of the plurality of character line structures 200 can be in the range of 5 μΩ-cm to 50 μΩ-cm, from 10 μΩ-cm to 40 μΩ-cm, from 10 μΩ-cm to 30 μΩ-cm, from 10 μΩ-cm to 25 μΩ-cm, or from 10 μΩ-cm to 20 μΩ-cm.

[0104] Figure 23 is a top view of an intermediate semiconductor device according to an embodiment of the present disclosure. Figures 24 and 25 are cross-sectional views illustrating a portion of the manufacturing process of semiconductor device 1A according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 23. Figure 26 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figure 27 is a cross-sectional view illustrating a portion of the manufacturing process of semiconductor device 1A according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 26.

[0105] Referring to Figures 1 and 23 to 27, in step S15, a plurality of openings 705 can be formed in a plurality of first regions R1, and a plurality of groove spacers 301 can be formed in the plurality of openings 705.

[0106] Referring to Figures 23 and 24, a plurality of openings 705 can be formed by a photolithography process and a subsequent etching process. The bottom surface 705BS of the opening 705 can be located at a vertical height VL1 between the bottom surface 213BS of the character line overlay layer 213 and the top surface 101TS of the substrate 101. In some embodiments, the opening 705 may have a square cross-sectional profile when viewed from above, but this disclosure is not limited thereto. In some embodiments, the opening 705 may have a rectangular, circular, or other suitable cross-sectional profile when viewed from above.

[0107] Referring to Figure 25, a spacer material 605 can be compliantly formed on the liner nitride 105, the insulating layer 107, the character line overlay 213, and the plurality of openings 705. In some embodiments, this spacer material 605 can be formed by, for example, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes. In some embodiments, the spacer material 605 can be a material that has etch selectivity for the character line overlay 213. In some embodiments, the spacer material 605 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, boron silicon nitride, boron phosphorus nitride, silicon boron carbon nitride, or other suitable insulating materials.

[0108] Referring to Figures 26 and 27, a spacer etching process can be performed to remove a portion of the spacer material 605. The remaining spacer material 605 may be referred to as a plurality of in-groove spacers 301. In some embodiments, the spacer etching process may be, for example, an anisotropic etching process, such as reactive ion etching.

[0109] In some embodiments, viewed from a top view, the spacer 301 within the groove may have a square ring-shaped cross-sectional profile, but this disclosure is not limited thereto. In some embodiments, viewed from a top view, the spacer 301 within the groove may have a rectangular ring-shaped, annular, or other suitable shaped cross-sectional profile.

[0110] In some embodiments, the bottom surface 301BS of the recessed spacer 301 may be located at a vertical height position VL1 between the bottom surface 213BS of the character line overlay layer 213 and the top surface 101TS of the substrate 101. In some embodiments, the top portion of the recessed spacer 301 may be lower than the top surface 101TS of the substrate 101. In some embodiments, a portion of the recessed spacer 301 extending along the X direction (viewed from a top view) may be disposed against the character line overlay layer 213 (viewed from a cross-sectional view). A portion of the recessed spacer 301 extending along the Y direction (viewed from a top view) may be disposed against the substrate 101 (viewed from a cross-sectional view).

[0111] Figure 28 is a cross-sectional view illustrating a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 26. Figure 29 is a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 30 and 31 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 29. Referring to Figures 1 and 28 to 31, in step S17, a plurality of buried conductive layers 401 may be formed in a plurality of openings 705.

[0112] Referring to Figure 28, a fourth conductive material 617 can be formed to cover the spacers 301 within the plurality of grooves and completely fill the plurality of openings 705. In some embodiments, this fourth conductive material 617 can be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, sputtering, electroplating, electroless plating, or other suitable deposition processes. In some embodiments, the fourth conductive material 617 can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0113] Referring to Figures 29 and 30, a planarization process can be performed until a plurality of character line overlays 213 are exposed to remove excess material and provide a substantially flat surface for subsequent process steps. The remaining fourth conductive material 617 may be referred to as a plurality of embedded conductive layers 401. At this stage, the top surface 213TS of the character line overlay 213, the top surface of the embedded conductive layers 401, and the top surface of the pad nitride 105 may be substantially coplanar. In some embodiments, the planarization process may be an etching process, a chemical mechanical polishing process, or a combination thereof. Furthermore, a heat treatment process is performed. In some embodiments, during the heat treatment process, an air gap structure 109 is formed in the isolation layer 107 between the two embedded conductive layers 401. In some embodiments, the air gap structure 109 includes an air gap 1093 surrounded by a liner 1091. In some embodiments, the air gap structure 109 is formed between the two pad nitrides 105 and between the two pad oxides 103.

[0114] Referring to Figure 31, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 101TS of the substrate 101 is exposed, thereby removing the pad oxide 103 and the pad nitride 105. At this stage, the top surface 109TS of the air gap structure 109, the top surface 401TS of the embedded conductive layer 401, the top surface 213TS of the character line cover layer 213, and the top surface 101TS of the substrate 101 can be substantially coplanar.

[0115] The embedded conductive layer 401 may include a bottom portion 411 and a top portion 413. The bottom portion 411 may be disposed in the opening 705. The bottom surface 411BS of the bottom portion 411 may contact the substrate 101. The bottom surface 411BS of the bottom portion 411 (i.e., the bottom surface of the embedded conductive layer 401) and the bottom surface 301BS of the recessed spacer 301 may be substantially coplanar. The sidewalls 411SW of the bottom portion 411 may be surrounded by the recessed spacer 301. The bottom surface 411BS of the bottom portion 411 may be at a vertical height position VL1 above the bottom surface 213BS of the character line overlay layer 213. Alternatively, the bottom surface 411BS of the bottom portion 411 and the bottom surface 301BS of the recessed spacer 301 may be at a vertical height position below the bottom surface 213BS of the character line overlay layer 213 (not shown).

[0116] The top portion 413 can be disposed on the bottom portion 411 and can cover the top portion of the recessed spacer 301. The top surface 413TS of the top portion 413 (i.e., the top surface of the embedded conductive layer 401), the top surface 213TS of the character line cover layer 213, and the top surface 101TS of the substrate 101 can be substantially coplanar. The sidewall 413SW of the top portion 413 and the sidewall 301SW of the recessed spacer 301 can be substantially coplanar.

[0117] In some embodiments, the ratio of the width W1 of the bottom surface 411BS of the bottom portion 411 to the width W2 of the top surface 413TS of the top portion 413 can be between about 0.5 and about 0.95. In some embodiments, the ratio of the thickness T1 of the recessed spacer 301 to the width W2 of the top surface 413TS of the top portion 413 can be between about 0.025 and about 0.25. In some embodiments, the ratio of the height H1 of the recessed spacer 301 to the height H2 of the embedded conductive layer 401 can be between about 0.5 and about 0.85.

[0118] The electric field near the embedded conductive layer 401 can be reduced by using spacers 301 within the groove. Therefore, the gate-induced drain leakage (GIDL) is reduced due to the lower electric field. This improves the performance of the semiconductor device 1A.

[0119] Figure 32 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figure 33 is a cross-sectional view taken along sections A-A' and B-B' in Figure 32.

[0120] Referring to Figures 32 and 33, semiconductor element 1B may have a structure similar to that shown in Figure 31. Elements in Figures 32 and 33 that are the same as or similar to those in Figure 31 are marked with similar element symbols, and repeated descriptions are omitted.

[0121] Referring to Figures 32 and 33, semiconductor device 1B may include a plurality of sources SR and a plurality of drains DR. Each source SR may be disposed in a corresponding first region R1 among the plurality of first regions R1. Each drain DR may be disposed in a corresponding second region R2 among the plurality of second regions R2. One of the recess spacers 301 and one of the buried conductive layers 401 may be disposed in a corresponding source SR among the plurality of sources SR.

[0122] A plurality of source SRs and a plurality of drain DRs can be formed by a placement process. The placement process can employ, for example, n-type doping. n-type dopants can be added to an intrinsic semiconductor to contribute free electrons to it. Examples of n-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus. In some embodiments, the dopant concentration of the plurality of source SRs and the plurality of drain DRs can be between about 1E19 atoms / cm³ and about 1E21 atoms / cm³; although other dopant concentrations less than or greater than this range are also applicable in this application.

[0123] In some embodiments, an annealing process may be performed to activate a plurality of source electrodes (SRs) and a plurality of drain electrodes (DRs). The annealing process may have a process temperature between about 800°C and about 1250°C. The annealing process may have a process duration between about 1 millisecond and about 500 milliseconds. The annealing process may be, for example, rapid thermal annealing, laser spike annealing, or flash annealing.

[0124] Figure 34 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 35 and 36 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 29. Figure 37 is a cross-sectional view taken along sections A-A' and B-B' in Figure 32.

[0125] Referring to Figure 34, the semiconductor device manufacturing method 30 includes steps S31, S33, S35, and S37, wherein steps S31, S33, and S35 are the same as steps S11, S13, and S15 of method 10, respectively, and repeated descriptions are omitted. Step S37 of method 30 is similar to step S17 of method 10, wherein the difference between step S37 and step S17 is that the air gap structure 109 in step S17 is replaced with a shallow trench isolation (STI) structure 107a, which is as described below.

[0126] Referring to Figures 34 and 35, a shallow trench isolation structure 107a is formed in the substrate 101. In some embodiments, the shallow trench isolation structure 107a is formed between two buried conductive layers 401. In some embodiments, the shallow trench isolation structure 107a is formed between two pad nitrides 105 and between two pad oxides 103. In some embodiments, the shallow trench isolation structure 107a includes a first liner 1070 (i.e., the same as the isolation layer 107 in Figure 30), a second liner 1071 disposed on the first liner 1070, a third liner 1073 disposed on the second liner 1071, and a trench filling layer 1075 disposed on the third liner 1073. In some embodiments, the trench filling layer 1075 is surrounded by the third liner 1073, the third liner 1073 is surrounded by the second liner 1071, and the second liner 1071 is separated from the substrate 101 by the first liner 1070. In some embodiments, as shown in FIG35, the top surface T3 of the second liner 1071 is higher than the top surface T2 of the first liner 1070.

[0127] Furthermore, the first liner 1070, the second liner 1071, and the third liner 1073 of the shallow trench isolation structure 107a are made of different materials. For example, the first liner 1070 is made of silicon oxide, the second liner 1071 is made of nitride, and the third liner 1073 is made of silicon oxynitride. Moreover, there is a first etch selectivity between the second liner 1071 and the trench fill layer 1075, and a second etch selectivity between the third liner 1073 and the trench fill layer 1075.

[0128] Referring to Figures 36 and 37, semiconductor element 1A' in Figure 36 is similar to semiconductor element 1A in Figure 31, and semiconductor element 1B' in Figure 37 is similar to semiconductor element 1B in Figure 32. The differences between semiconductor element 1A' and semiconductor element 1A, and between semiconductor element 1B' and semiconductor element 1B, are found in the shallow trench isolation structure 107a of semiconductor elements 1A' and 1B'. In some embodiments, as shown in Figures 36 and 37, after planarization, the top surface 1070TS of the first substrate 1070, the top surface 1071TS of the second substrate 1071, the top surface 1073TS of the third substrate 1073, and the top surface 1075TS of the trench fill layer 1075 are substantially coplanar.

[0129] One aspect of this disclosure provides a semiconductor device comprising: a substrate; an embedded conductive layer including: a bottom portion located in the substrate; and a top portion located in the substrate and on the bottom portion; an isolation layer located within the substrate; an air gap structure located in the isolation layer; and a recessed spacer located in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion is substantially coplanar with a top surface of the substrate. A bottom surface of the recessed spacer is substantially coplanar with a bottom surface of the bottom portion. A sidewall of the recessed spacer is substantially coplanar with a sidewall of the top portion.

[0130] Another aspect of this disclosure provides a semiconductor device comprising: a substrate; an embedded conductive layer including: a bottom portion located in the substrate; and a top portion located in the substrate and on the bottom portion; a shallow trench isolation structure located in the substrate; and a recessed spacer located in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion is substantially coplanar with a top surface of the substrate. A bottom surface of the recessed spacer is substantially coplanar with a bottom surface of the bottom portion. A sidewall of the recessed spacer is substantially coplanar with a sidewall of the top portion.

[0131] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate and forming an isolation layer in the substrate to define a plurality of active regions; forming an opening in the substrate; conformally forming a spacer material in the opening; performing a spacer etching process to remove a portion of the spacer material and forming a recessed spacer in the opening; and forming an embedded conductive layer in the opening and covering the recessed spacer, wherein an air gap structure is formed in the isolation layer.

[0132] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate and forming an isolation layer in the substrate to define a plurality of active regions; forming an opening in the substrate; conformally forming a spacer material in the opening; performing a spacer etching process to remove a portion of the spacer material and forming an in-groove spacer in the opening; and forming an embedded conductive layer in the opening and covering the in-groove spacer, wherein a shallow trench isolation structure is formed in the substrate.

[0133] Due to the design of the semiconductor device disclosed herein, the electric field near the buried conductive layer can be reduced by using spacers within the groove. Therefore, the gate-induced drain leakage current can be reduced due to the lower electric field. This improves the performance of the semiconductor device.

[0134] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0135] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0136] 10: Method 30: Method 101:Substrate 101TS: Top Surface 103: Pad Oxides 105: Pad Nitride 107: Isolation Layer 107a: Shallow trench isolation structure 109: Air gap structure 109TS: Top surface 200: Character Line Structure 211: Character line dielectric layer 211TS: Top Surface 213: Character Line Overlay 213BS: Bottom surface 213TS: Top surface 221: Bottom conductive layer 223: Intermediate conductive layer 225: Top conductive layer 225TS: Top surface 231: Bottom Liner 231TS: Top Surface 233: Top Liner 233TS: Top surface 301: Spacer in the groove 301BS: Bottom surface 301SW: Sidewall 401: Embedded conductive layer 411BS: Bottom surface 401TS: Top Surface 411: Bottom section 411SW: Sidewall 413: Top section 413SW: Sidewall 413TS: Top surface 601: First dielectric material 603: Covering material 605: Spacer Material 611: First conductive material 613: Second conductive material 615: Third conductive material 617: Fourth Conductive Material 621: First Liner Material 623: Second Liner Material 701: First trench 703: Character line groove 705: Opening 705BS: Bottom surface 801: First Cover Layer 1070: First Liner 1070TS: Top Surface 1071: Second Liner 1071TS: Top Surface 1073: Third Liner 1073TS: Top Surface 1075: Trench filling layer 1075TS: Top Surface 1091: Lining 1093: Air gap AA: Active Zone DR: Jiji H1: Height H2: Height R1: First Region R2: Second Region S11: Steps S13: Steps S15: Steps S17: Steps S31: Steps S33: Steps S35: Steps S37: Steps SR: Source Extreme T1: Thickness T2: Top surface T3: Top surface VL1: Vertical height position W1: Width W2: Width

Claims

1. A semiconductor device, comprising: One substrate; An embedded conductive layer includes: a bottom portion located in a substrate; and a top portion located in the substrate and on the bottom portion; an insulating layer located within the substrate; an air gap structure located in the insulating layer; and a recessed spacer located in the substrate, surrounding the bottom portion and covered by the top portion; wherein a top surface of the top portion is substantially coplanar with a top surface of the substrate, wherein a bottom surface of the recessed spacer is substantially coplanar with a bottom surface of the bottom portion, and wherein a sidewall of the recessed spacer is substantially coplanar with a sidewall of the top portion.

2. The semiconductor element as claimed in claim 1, wherein the width ratio of a width of the bottom surface of the bottom portion to the width of the top surface of the top portion is between about 0.5 and about 0.

95.

3. The semiconductor device as claimed in claim 1, wherein the ratio of the thickness of the spacer in the recess to the width of the top surface of the top portion is between about 0.025 and about 0.

25.

4. The semiconductor device as claimed in claim 1, wherein the ratio of the height of the spacer in the recess to the height of the embedded conductive layer is between about 0.5 and about 0.

85.

5. The semiconductor element as claimed in claim 1, wherein, viewed from a top-viewing angle, the spacer within the recess has a square annular cross-sectional profile.

6. The semiconductor device as claimed in claim 1, wherein the embedded conductive layer has a square cross-sectional profile when viewed from an upward angle.

7. The semiconductor device as claimed in claim 1, wherein the embedded conductive layer comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminum compound, or a combination thereof.

8. The semiconductor device as claimed in claim 7, wherein the spacer in the recess comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, boron silicon nitride, boron phosphorus nitride, or silicon boron carbide.

9. The semiconductor device as claimed in claim 1, wherein the air gap structure includes an air gap surrounded by a liner.

10. The semiconductor device as claimed in claim 9, wherein a top surface of the air gap structure is coplanar with a top surface of the embedded conductive layer.

11. A semiconductor element, comprising: One substrate; An embedded conductive layer includes: a bottom portion located in a substrate; and a top portion located in the substrate and on the bottom portion; a shallow trench isolation structure located in the substrate; and a recessed spacer located in the substrate, surrounding the bottom portion and covered by the top portion, wherein a top surface of the top portion is substantially coplanar with a top surface of the substrate, wherein a bottom surface of the recessed spacer is substantially coplanar with a bottom surface of the bottom portion, wherein a side wall of the recessed spacer is substantially coplanar with a side wall of the top portion, and wherein, viewed from a top view angle, the recessed spacer has a square annular cross-sectional profile.

12. The semiconductor device as claimed in claim 11, wherein, viewed from the top view, the embedded conductive layer has a square cross-sectional profile.

13. The semiconductor device as claimed in claim 11, wherein the embedded conductive layer comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminum compound, or a combination thereof.

14. The semiconductor device as claimed in claim 13, wherein the spacer in the recess comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, boron silicon nitride, boron phosphorus nitride, or silicon boron carbide.

15. The semiconductor device as claimed in claim 11, wherein the shallow trench isolation structure comprises: First liner; A second liner is disposed on top of the first liner; A third liner is disposed on top of the second liner; And a groove filling layer, disposed on the third liner.

16. The semiconductor device of claim 15, wherein the trench filling layer is surrounded by the third liner, the third liner is surrounded by the second liner, and the second liner is separated from the substrate by the first liner, and a top surface of the first liner, a top surface of the second liner, a top surface of the third liner and a top surface of the trench filling layer are substantially coplanar.

17. The semiconductor device as claimed in claim 16, wherein the first substrate, the second substrate, and the third substrate of the shallow trench isolation structure are made of different materials, and the first substrate is made of silicon oxide, the second substrate is made of nitride, and the third substrate is made of silicon oxynitride.

18. The semiconductor device of claim 15, wherein there is a first etch selectivity between the second liner and the trench fill layer, and a second etch selectivity between the third liner and the trench fill layer.

19. The semiconductor device of claim 11, wherein the ratio of the width of the bottom surface of the bottom portion to the width of the top surface of the top portion is between about 0.5 and about 0.95, the ratio of the thickness of the spacer in the recess to the width of the top surface of the top portion is between about 0.025 and about 0.25, and the ratio of the height of the spacer in the recess to the height of the embedded conductive layer is between about 0.5 and about 0.85.

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