Display device

Abstract

Each pixel of a display device according to an embodiment of the present invention comprises: a first transistor; a second transistor connected to a first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a first capacitor comprising a first electrode connected to the first gate of the first transistor and a second electrode connected to a second terminal of the first transistor; and a second capacitor comprising a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor, wherein the first electrode of the second capacitor and the first voltage line are arranged on the same layer.

Description

display device

[0001] The present invention relates to a pixel and a display device including the pixel.

[0002] In recent years, the uses of display devices have become increasingly diverse. Furthermore, as display devices become thinner and lighter, their applications are expanding.

[0003] As display devices are utilized in various ways, there are various methods for designing the form of display devices, and the functions that can be grafted or linked to display devices are increasing.

[0004] Embodiments of the present invention can provide a display device with improved display quality. However, these tasks are exemplary and do not limit the scope of the present invention.

[0005] In a display device including a plurality of pixels according to one embodiment of the present invention, each of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal of the first transistor and a second voltage line; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor; wherein the first electrode of the second capacitor and the first voltage line are disposed on the same layer.

[0006] In one embodiment, the second electrode of the second capacitor may be connected to the second gate of the first transistor.

[0007] In one embodiment, the first capacitor includes a first electrode including an upper electrode and a lower electrode, the upper electrode and the first gate of the first transistor are disposed on the same layer, the lower electrode and the first electrode of the second capacitor are disposed on the same layer, and the lower electrode can be connected to the lower electrode.

[0008] In one embodiment, during one frame, a gate signal may be supplied to the gate of the third transistor once, and a gate signal may be supplied to the gate of the fourth transistor twice or more.

[0009] In one embodiment, each of the plurality of pixels further includes a fifth transistor connected to the second terminal of the first transistor and the third voltage line; a sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and a seventh transistor connected to the light-emitting diode and the fourth voltage line; and the same gate signal can be supplied to the gate of the fifth transistor and the gate of the seventh transistor.

[0010] In one embodiment, the timing at which the gate signal is applied to the gate of the fourth transistor may be earlier than the timing at which the gate signal is applied to the gate of the sixth transistor.

[0011] In one embodiment, each of the plurality of pixels further includes a fifth transistor connected to the second terminal of the first transistor and the third voltage line; a sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and a seventh transistor connected to the light-emitting diode and the fourth voltage line; and a gate signal supplied to the gate of the fifth transistor and a gate signal supplied to the gate of the seventh transistor may be different.

[0012] In one embodiment, during one frame, a gate signal may be supplied to the gate of the fifth transistor once, and a gate signal may be supplied to the gate of the seventh transistor twice or more.

[0013] In one embodiment, a frame includes a first scan period including a first non-emission period and a first emission period, and a second scan period including a second non-emission period and a second emission period, wherein each of the plurality of pixels further includes a fifth transistor connected to a second terminal of the first transistor and a third voltage line, and wherein the first non-emission period may include: a writing period in which a first gate signal is applied to a gate of the second transistor; a first period in which a second gate signal is applied to a gate of the fifth transistor and a third gate signal is applied to a gate of the third transistor before the writing period; and a second period between the writing period and the first period in which the third gate signal is applied to a gate of the third transistor and a fourth gate signal is applied to a gate of the fourth transistor.

[0014] In one embodiment, the second non-luminous period may include a third period during which a second gate signal is applied to the gate of the fifth transistor.

[0015] In a display device including a plurality of pixels according to one embodiment of the present invention, each of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal of the first transistor and a second voltage line; a fifth transistor connected to the second terminal of the first transistor and a light-emitting diode; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; And a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor; and the timing at which a gate signal is applied to the gate of the fourth transistor may be earlier than the timing at which a gate signal is applied to the gate of the fifth transistor.

[0016] In one embodiment, the second electrode of the second capacitor may be connected to the second gate of the first transistor.

[0017] In one embodiment, the first electrode of the first capacitor includes an upper electrode and a lower electrode, the upper electrode and the first gate of the first transistor are disposed on the same layer, the lower electrode and the first electrode of the second capacitor are disposed on the same layer, and the lower electrode can be connected to the upper electrode.

[0018] In one embodiment, during one frame, a gate signal may be supplied to the gate of the third transistor once, and a gate signal may be supplied to the gate of the fourth transistor twice or more.

[0019] In one embodiment, each of the plurality of pixels further includes a sixth transistor connected to the second terminal of the first transistor and the third voltage line; and a seventh transistor connected to the light-emitting diode and the fourth voltage line; and the same gate signal can be supplied to the gate of the sixth transistor and the gate of the seventh transistor.

[0020] In one embodiment, each of the plurality of pixels further includes a sixth transistor connected to the second terminal of the first transistor and the third voltage line; and a seventh transistor connected to the light-emitting diode and the fourth voltage line; and a gate signal supplied to the gate of the sixth transistor and a gate signal supplied to the gate of the seventh transistor may be different.

[0021] In one embodiment, during one frame, a gate signal may be supplied to the gate of the sixth transistor once, and a gate signal may be supplied to the gate of the seventh transistor twice or more.

[0022] In a display device including a plurality of pixels according to one embodiment of the present invention, each of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal of the first transistor and a second voltage line; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; a second capacitor including a first electrode connected to the second voltage line and a second electrode connected to the second terminal of the first transistor; And a third capacitor including a first electrode connected to a second terminal of the first transistor and a second electrode connected to one electrode of the light-emitting diode.

[0023] In one embodiment, each of the plurality of pixels further includes a fifth transistor connected to the second terminal of the first transistor and the third voltage line; a sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and a seventh transistor connected to the light-emitting diode and the fourth voltage line; wherein the same gate signal is supplied to the gate of the fifth transistor and the gate of the seventh transistor, and the timing at which the gate signal is applied to the gate of the fourth transistor may be earlier than the timing at which the gate signal is applied to the gate of the sixth transistor.

[0024] In one embodiment, each of the plurality of pixels further includes a fifth transistor connected to the second terminal of the first transistor and the third voltage line; a sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and a seventh transistor connected to the light-emitting diode and the fourth voltage line; wherein a gate signal supplied to a gate of the fifth transistor and a gate signal supplied to a gate of the seventh transistor are different, and a timing at which the gate signal is applied to the gate of the fourth transistor may be earlier than a timing at which the gate signal is applied to the gate of the sixth transistor.

[0025] In a display device including a plurality of pixels according to one embodiment of the present invention, each of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal of the first transistor and a second voltage line; a fifth transistor connected to the second terminal of the first transistor and a first electrode of a light-emitting diode; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; And a second capacitor including a first electrode connected to a second terminal of the first transistor and a second electrode connected to a second electrode of the light-emitting diode;

[0026] In one embodiment, the first electrode of the second capacitor may be connected to the second gate of the first transistor.

[0027] In one embodiment, the first capacitor may include an upper electrode disposed on the same layer as the first gate of the first transistor and a lower electrode disposed on the same layer as the first electrode of the second capacitor and connected to the upper electrode.

[0028] In one embodiment, during one frame, a gate signal may be supplied to the gate of the third transistor once, and a gate signal may be supplied to the gate of the fourth transistor twice or more.

[0029] In one embodiment, each of the plurality of pixels further includes a sixth transistor connected to the second terminal of the first transistor and the third voltage line; and a seventh transistor connected to the first electrode of the light-emitting diode and the fourth voltage line; and the same gate signal can be supplied to the gate of the fifth transistor and the gate of the seventh transistor.

[0030] In one embodiment, the timing at which the gate signal is applied to the gate of the fourth transistor may be earlier than the timing at which the gate signal is applied to the gate of the fifth transistor.

[0031] In one embodiment, each of the plurality of pixels further includes a sixth transistor connected to the second terminal of the first transistor and the third voltage line; and a seventh transistor connected to the first electrode of the light-emitting diode and the fourth voltage line; and a gate signal supplied to the gate of the sixth transistor and a gate signal supplied to the gate of the seventh transistor may be different.

[0032] In one embodiment, during one frame, a gate signal may be supplied to the gate of the sixth transistor once, and a gate signal may be supplied to the gate of the seventh transistor twice or more.

[0033] In one embodiment, a frame includes a first scan period including a first non-emission period and a first emission period, and a second scan period including a second non-emission period and a second emission period, wherein each of the plurality of pixels further includes a sixth transistor connected to a second terminal of the first transistor and a third voltage line, and wherein the first non-emission period may include: a writing period in which a first gate signal is applied to a gate of the second transistor; a first period in which a second gate signal is applied to a gate of the sixth transistor and a third gate signal is applied to a gate of the third transistor before the writing period; and a second period between the writing period and the first period in which the third gate signal is applied to a gate of the third transistor and a fourth gate signal is applied to a gate of the fourth transistor.

[0034] In one embodiment, the second non-luminous period may include a third period during which a second gate signal is applied to the gate of the sixth transistor.

[0035] According to embodiments of the present invention, a display device with improved display quality can be provided. Of course, the scope of the present invention is not limited by these effects.

[0036] FIG. 1A and FIG. 1B are schematic plan views illustrating a display device according to one embodiment.

[0037] Figure 2 is a schematic diagram illustrating a display device according to one embodiment.

[0038] Figures 3a and 3b are conceptual diagrams for explaining a method of driving a display device according to a driving frequency.

[0039] Figure 4 is a schematic diagram of an equivalent circuit of a pixel according to one embodiment.

[0040] Figures 5 to 7 are schematic diagrams showing signals for explaining the operation of the pixel illustrated in Figure 4.

[0041] Figure 8 is a schematic diagram of an equivalent circuit of a pixel according to a comparative example.

[0042] FIG. 9 is a diagram schematically showing the change in the first driving voltage (ELVDD) as the fourth gate signal (EM) is applied to the pixel shown in FIG. 8 during one frame.

[0043] Fig. 10 is a drawing schematically showing the arrangement of light-emitting areas of a plurality of pixels according to one embodiment.

[0044] Figures 11 to 19 are plan views (or layout drawings) schematically illustrating the elements of the pixel illustrated in Figure 4 layer by layer.

[0045] Figure 20 is a schematic cross-sectional view taken along line I-I' of Figure 19.

[0046] Fig. 21 is a schematic cross-sectional view taken along line II-II' of Fig. 19.

[0047] Fig. 22 is a schematic diagram of an equivalent circuit of a pixel according to one embodiment.

[0048] Figures 23 and 24 are schematic diagrams showing signals for explaining the operation of the pixel shown in Figure 22.

[0049] Figures 25 to 27 are schematic diagrams of equivalent circuits of pixels according to one embodiment.

[0050] Figures 28a to 29b are schematic cross-sectional views showing the structure of a display element according to one embodiment.

[0051] Fig. 30 is a schematic cross-sectional view showing the structure of a pixel of a display device according to one embodiment.

[0052] According to one embodiment of the present invention, a display device includes a plurality of pixels, each of the plurality of pixels including: a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal of the first transistor and a second voltage line; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor. The first electrode of the second capacitor and the first voltage line are disposed on the same layer.

[0053] The following embodiments will be described in detail, examples of which are illustrated in the accompanying drawings, wherein like reference numerals designate like elements throughout. In this regard, the present embodiments are not limited to the descriptions set forth herein and may be implemented in other forms. Accordingly, the embodiments will be described below with reference to the drawings to illustrate aspects of the present specification.

[0054] The term "and / or" includes any combination of one or more that the relevant configuration may define. For example, "A and / or B" may be understood to mean "A, B, or A and B." For the purposes of this disclosure, the phrase "at least one of A and B" may be interpreted as A alone, B alone, or any combination of A and B. Additionally, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as X alone, Y alone, Z alone, or any combination of two or more of X, Y, and Z.

[0055] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0056] In the examples below, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0057] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0058] In the examples below, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0059] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0060] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0061] In the following examples, when X and Y are said to be connected, this may include cases where X and Y are electrically connected, cases where X and Y are functionally connected, and cases where X and Y are physically connected. When X and Y are said to be connected to each other, this may include cases where X and Y are directly connected to each other or cases where X and Y are indirectly connected to each other. Here, X and Y may be objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a given connection relationship, for example, a connection relationship shown in the drawings or detailed description, and may also include connection relationships other than those shown in the drawings or detailed description.

[0062] The case where X and Y are electrically connected to each other may include, for example, a case where X and Y are directly electrically connected to each other, or a case where one or more elements (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) that enable electrical connection between X and Y are connected between X and Y.

[0063] In the following examples, the term "ON" used in connection with a device state may refer to an activated state of the device, and "OFF" may refer to a deactivated state of the device. "ON" used in connection with a signal received by the device may refer to a signal that activates the device, and "OFF" may refer to a signal that deactivates the device. The device may be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the "ON" voltages for P-type transistors and N-type transistors are opposite (low vs. high) voltage levels.

[0064] In this specification, supplying any signal may mean supplying an on voltage (e.g., a high-level voltage), and not supplying any signal may mean supplying an off voltage (e.g., a low-level voltage).

[0065] In the following examples, the x-direction, y-direction, and z-direction are not limited to directions along the three axes on the orthogonal coordinate system, but can be interpreted in a broad sense that includes them. For example, the x-direction, y-direction, and z-direction may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

[0066] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and disclosure, and should not be interpreted idealistically or overly formally unless explicitly defined herein.

[0067] The display device according to embodiments of the present invention may be implemented as an electronic device such as a smartphone, a mobile phone, a smart watch, a navigation device, a game console, a TV, a vehicle head unit, a notebook computer, a laptop computer, a tablet computer, a PMP (Personal Media Player), a PDA (Personal Digital Assistant), etc. In addition, the electronic device may be a flexible device.

[0068] Figures 1a and 1b are schematic drawings of a display device according to one embodiment. Figure 2 is a schematic drawing of a display device according to one embodiment. Figures 3a and 3b are schematic conceptual diagrams for explaining a method of driving a display device according to a driving frequency.

[0069] Referring to FIGS. 1A and 1B, the display device (10) may include a display area (DA) for displaying an image and a peripheral area (PA) outside the display area (DA). The display area (DA) may be entirely surrounded by the peripheral area (PA).

[0070] When the display area (DA) is viewed in a planar shape, the display area (DA) may have a rectangular shape. In another embodiment, the display area (DA) may have a polygonal shape such as a triangle, a pentagon, a hexagon, a circular shape, an oval shape, an irregular shape, etc. The display area (DA) may have a rounded corner at an edge. In one embodiment, the display device (10) may have a display area (DA) of a shape in which the length in the x direction is longer than the length in the y direction, as illustrated in FIG. 1A. In another embodiment, the display device (10) may have a display area (DA) of a shape in which the length in the y direction is longer than the length in the x direction, as illustrated in FIG. 1B.

[0071] Referring to FIG. 2, a display device (10) according to one embodiment may include a pixel unit (11), a gate driving circuit (13), a data driving circuit (15), a power supply circuit (17), and a controller (19).

[0072] The pixel unit (11) may be provided in the display area (DA). The peripheral area (PA) may include various conductive lines for transmitting electrical signals to be applied to the display area (DA), peripheral circuits electrically connected to the pixel circuits, and pads to which a printed circuit board or driver IC chip is attached. For example, the peripheral area (PA) may include a gate driving circuit (13), a data driving circuit (15), a power supply circuit (17), and a controller (19).

[0073] As illustrated in FIG. 2, a plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of pixels (PX) connected thereto may be arranged in a display area (DA). The plurality of pixels (PX) may be arranged in various configurations, such as a stripe arrangement, a pentile arrangement, a diamond arrangement, and a mosaic arrangement, to implement an image. Each of the pixels (PX) includes an organic light-emitting diode (OLED) as a display element (light-emitting element), and the organic light-emitting diode (OLED) may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. The pixel (PX) may emit light of, for example, red, green, blue, or white through the organic light-emitting diode (OLED). Each pixel (PX) may be connected to at least one corresponding gate line among the plurality of gate lines (GL) and to a corresponding data line among the plurality of data lines (DL).

[0074] The gate lines (GL) can each extend in the x direction (row direction) and be connected to pixels (PX) located in the same row. The gate lines (GL) can each transmit a gate signal to the pixels (PX) located in the same row. The data lines (DL) can each extend in the y direction (column direction) and be connected to pixels (PX) located in the same column. The data lines (DL) can each transmit a data signal to the pixels (PX) located in the same column in synchronization with the gate signal.

[0075] In one embodiment, the peripheral area (PA) may be a non-display area where pixels (PX) are not arranged. In another embodiment, a portion of the peripheral area (PA) may be implemented as a display area (DA). For example, a plurality of pixels (PX) may be arranged in at least one corner of the peripheral area (PA) and may overlap the gate driving circuit (13). Accordingly, dead space can be reduced and the display area (DA) can be expanded.

[0076] The gate driving circuit (13) is connected to a plurality of gate lines (GL), and can generate gate signals in response to a control signal (GCS) from a controller (19) and sequentially supply the same to the gate lines (GL). The gate line (GL) can be connected to a gate of a transistor included in a pixel (PX). The gate signal can be a gate control signal that controls turning on and off of a transistor whose gate is connected to the gate line (GL). The gate signal can be a square wave signal including an on voltage that can turn on the transistor and an off voltage that can turn off the transistor. In one embodiment, the on voltage can be a high level voltage (first level voltage) or a low level voltage (second level voltage).

[0077] In FIG. 2, the pixel (PX) is illustrated as being connected to one gate line (GL), but this is merely exemplary, and the pixel (PX) may be connected to two or more gate lines, and the gate driving circuit (13) may supply two or more gate signals, the timings at which the on voltages are applied, to the corresponding gate lines. For example, the pixel (PX) may be connected to the first to sixth gate lines, and the gate driving circuit (13) may apply the first gate signal (GW), the second gate signal (GI), the third gate signal (GR), the fourth gate signal (EM), and the fifth gate signal (EMB) to the first gate lines, the second gate lines, the third gate lines, the fourth gate lines, and the fifth gate lines, respectively.

[0078] The data driving circuit (15) is connected to a plurality of data lines (DL) and can supply a data signal to the data lines (DL) in response to a control signal (DCS) from a controller (19). The data signal supplied to the data line (DL) can be supplied to a pixel (PX) supplied with a gate signal. The data driving circuit (15) can convert input image data (DATA) having a grayscale input from the controller (19) into a data signal in the form of a voltage or current. Fig. 2 illustrates an example in which the data driving circuit (15) outputs a data signal (Vdata) in the form of a voltage.

[0079] The power supply circuit (17) can generate voltages necessary for driving the pixel (PX) in response to a control signal (PCS) from the control unit (19). The power supply circuit (17) can generate a first driving voltage (ELVDD) and a second driving voltage (ELVSS) and supply them to the pixels (PX). The first driving voltage (ELVDD) can be a high-level voltage provided to a driving transistor electrically connected to a first electrode (e.g., a pixel electrode or an anode) of a display element included in the pixel (PX). The second driving voltage (ELVSS) can be a low-level voltage provided to a second electrode (e.g., a counter electrode or a cathode) of a display element included in the pixel (PX). The power supply circuit (17) can generate a reference voltage (Vref), a first initialization voltage (Vint), and a second initialization voltage (Vaint) and supply them to the pixels (PX).

[0080] The voltage level of the first driving voltage (ELVDD) may be higher than the voltage level of the second driving voltage (ELVSS). The voltage level of the reference voltage (Vref) may be lower than the voltage level of the first driving voltage (ELVDD). The voltage level of the first initialization voltage (Vint) may be lower than the voltage level of the second driving voltage (ELVSS). The voltage level of the second initialization voltage (Vaint) may be higher than the voltage level of the first initialization voltage (Vint). The voltage level of the second initialization voltage (Vaint) may be substantially the same as the voltage level of the second driving voltage (ELVSS) or higher than the voltage level of the second driving voltage (ELVSS).

[0081] The controller (19) can generate control signals (GCS, DCS, PCS) based on signals input from the outside and supply them to the gate driving circuit (13), the data driving circuit (15), and the power supply circuit (17). The control signal (GCS) output to the gate driving circuit (13) can include a plurality of clock signals and a gate start signal. The control signal (DCS) output to the data driving circuit (15) can include a source start signal and clock signals.

[0082] The display device (10) includes a display panel, and the display panel may include a substrate. Pixels (PX) may be arranged in a display area (DA) of the substrate. Part or all of the gate driving circuit (13) may be formed directly in a peripheral area (PA) of the substrate during a process of forming transistors constituting a pixel circuit in the display area (DA) of the substrate. The data driving circuit (15), the power supply circuit (17), and the controller (19) may be formed in the form of separate integrated circuit chips or a single integrated circuit chip, respectively, and may be arranged on an FPCB (flexible printed circuit board) electrically connected to pads arranged on one side of the substrate. In another embodiment, the data driving circuit (15), the power supply circuit (17), and the controller (17) may be arranged directly on the substrate in a COG (Chip On Glass) or COP (Chip On Plastic) manner.

[0083] In one embodiment, the plurality of transistors included in the pixel circuit may be N-type oxide thin film transistors. In another embodiment, the plurality of transistors included in the pixel circuit may be P-type silicon thin film transistors. In another embodiment, some of the plurality of transistors included in the pixel circuit may be N-type oxide thin film transistors, and other some may be P-type silicon thin film transistors.

[0084] An oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor in which an active pattern (semiconductor layer) includes an oxide. However, this is merely an example, and N-type transistors are not limited thereto. For example, an active pattern (semiconductor layer) included in an N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, polysilicon), an organic semiconductor, etc. A silicon thin film transistor may be an LTPS (Low Temperature Poly-Silicon) thin film transistor in which an active pattern (semiconductor layer) includes amorphous silicon, polysilicon, etc.

[0085] The display device (10) can support a variable refresh rate (VRR). The refresh rate is the frequency at which a data signal is actually written to a driving transistor of a pixel (PX), and is also called a screen scan rate or a screen refresh rate, and can represent the number of image frames played back per second. In one embodiment, the refresh rate may be an output frequency of the gate driving circuit (13) and / or the data driving circuit (15). A frequency corresponding to the refresh rate may be a driving frequency. The display device (10) can adjust the output frequency of the gate driving circuit (13) and the output frequency of the data driving circuit (15) corresponding thereto according to the driving frequency. The display device (10) supporting a variable refresh rate (VRR) can operate by changing the driving frequency within a range of a maximum driving frequency and a minimum driving frequency. For example, when the refresh rate is approximately 60 Hz, a gate signal for writing a data signal from the gate drive circuit (13) 60 times per second can be supplied to each horizontal line (row). The display device (10) can display an image while changing the drive frequency according to the refresh rate.

[0086] Depending on the driving frequency, one frame (1F) may include a first scan period (AS) and one or more second scan periods (SS). For example, in a display device (10) operating at a driving frequency of AHz as illustrated in FIG. 3A, one frame (1F) may include one first scan period (AS) and one second scan period (SS). In a display device (10) operating at a BHz driving frequency lower than the AHz driving frequency as illustrated in FIG. 3B, one frame (1F) may include one first scan period (AS) and two or more second scan periods (SS). The lower the driving frequency, the longer one frame (1F) may be. In another embodiment, one frame (1F) may include only one first scan period (AS).

[0087] The first scan period (AS) can be defined as an address scan period (Adress Scan Period) in which a data signal is written to a pixel (PX) in response to the first gate signal (GW) and the pixel emits light in response to the data signal. The operation in which a data signal is written to a pixel (PX) from a data line (DL) can also be referred to as a data programming operation. The second scan period (SS) can be defined as a self-scan period (Self Scan Period) in which the first gate signal (GW) is not applied to the pixel (PX) and the data signal is not written. During the second scan period (SS), the data signal written in the first scan period (AS) is maintained and the pixel can emit light in response to the maintained data signal. The length of the second scan period (SS) can be substantially the same as the length of the first scan period (AS).

[0088] Fig. 4 is a schematic diagram of an equivalent circuit of a pixel according to one embodiment. Figs. 5 to 7 are schematic diagrams illustrating signals for explaining the operation of the pixel illustrated in Fig. 4.

[0089] Referring to FIG. 4, a pixel (PX) may include an organic light-emitting diode (OLED) as a display element and a pixel circuit (PC) connected to the organic light-emitting diode (OLED). The pixel circuit (PC) may include first to seventh transistors (T1 to T7) and first and second capacitors (C1 and C2). The first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal, and the second to seventh transistors (T2 to T7) may be switching transistors that transmit signals. The first terminal (first electrode) and the second terminal (second electrode) of each of the first to seventh transistors (T1 to T7) may be a source or a drain depending on the voltage of the first terminal and the second terminal. For example, depending on the voltages of the first and second terminals, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. The node to which the first gate of the first transistor (T1) is connected may be defined as a first node (N1), and the node to which the second terminal of the first transistor (T1) is connected may be defined as a second node (N2).

[0090] A pixel (PX) can be connected to a first gate line (GWL) that transmits a first gate signal (GW), a second gate line (GIL) that transmits a second gate signal (GI), a third gate line (GRL) that transmits a third gate signal (GR), a fourth gate line (EML) that transmits a fourth gate signal (EM), a fifth gate line (EMBL) that transmits a fifth gate signal (EMB), and a data line (DL) that transmits a data signal (Vdata). Since the light emission of the pixel (PX) is controlled by the fourth gate signal (EM) and the fifth gate signal (EMB), the fourth gate signal (EM) and the fifth gate signal (EMB) can be referred to as light emission control signals, and the fourth gate line (GRL) and the fifth gate line (EMBL) can be referred to as light emission control lines.

[0091] Additionally, the pixel (PX) can be connected to a driving voltage line (PL) that transmits a first driving voltage (ELVDD), a reference voltage line (VRL) that transmits a reference voltage (Vref), a first initialization voltage line (VL1) that transmits a first initialization voltage (Vint), and a second initialization voltage line (VL2) that transmits a second initialization voltage (Vaint).

[0092] A first transistor (T1) may be connected between a driving voltage line (PL) and a second node (N2). The first transistor (T1) may include a gate, a first terminal, and a second terminal connected to a second node (N2). The gate of the first transistor (T1) may include a first gate connected to the first node (N1) and a second gate connected to the second node (N2). The first gate and the second gate may be arranged to face each other in different layers. For example, the first gate and the second gate of the first transistor (T1) may be positioned to face each other with a semiconductor layer therebetween.

[0093] A first gate of a first transistor (T1) may be connected to a second terminal of a second transistor (T2), a first terminal of a third transistor (T3), and a first capacitor (C1). A second gate of the first transistor (T1) may be connected to a first terminal of a sixth transistor (T6), a first capacitor (C1), and a second capacitor (C2). A first terminal of the first transistor (T1) may be connected to a driving voltage line (PL) via a fifth transistor (T5), and a second terminal may be connected to a pixel electrode of an organic light-emitting diode (OLED) via a sixth transistor (T6). The second terminal of the first transistor (T1) can be connected to the first terminal of the fourth transistor (T4), the first terminal of the sixth transistor (T6), the first capacitor (C1), and the second capacitor (C2). The first transistor (T1) can receive a data signal (Vdata) according to the switching operation of the second transistor (T2) and control the amount of driving current flowing to the organic light-emitting diode (OLED).

[0094] A second transistor (T2) (data write transistor) may be connected between a data line (DL) and a first gate of the first transistor (T1). The second transistor (T2) may include a gate connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second terminal of the second transistor (T2) may be connected to the first gate of the first transistor (T1), the first terminal of the third transistor (T3), and the first capacitor (C1). The second transistor (T2) is turned on by the first gate signal (GW) transmitted to the first gate line (GWL), electrically connects the data line (DL) and the first node (N1), and can transmit the data signal (Vdata) transmitted to the data line (DL) to the first node (N1).

[0095] A third transistor (T3) (first initialization transistor) may be connected between a first gate of the first transistor (T1) and a reference voltage line (VRL). The third transistor (T3) may include a gate connected to the third gate line (GRL), a first terminal connected to a first node (N1), and a second terminal connected to the reference voltage line (VRL). The first terminal of the third transistor (T3) may be connected to the first gate of the first transistor (T1), the second terminal of the second transistor (T2), and the first capacitor (C1). The third transistor (T3) may be turned on by a third gate signal (GR) transmitted to the third gate line (GRL) and may transmit the reference voltage (Vref) transmitted to the reference voltage line (VRL) to the first node (N1).

[0096] The fourth transistor (T4) (second initialization transistor) may be connected between the first transistor (T1) and the first initialization voltage line (VL1). The fourth transistor (T4) may include a gate connected to the second gate line (GIL), a first terminal connected to the second node (N2), and a second terminal connected to the first initialization voltage line (VL1). The first terminal of the fourth transistor (T4) may be connected to the second terminal of the first transistor (T1), the first terminal of the sixth transistor (T1), the first capacitor (C1), and the second capacitor (C2). The fourth transistor (T4) is turned on by the second gate signal (GI) transmitted to the second gate line (GIL) and can transmit the first initialization voltage (Vint) transmitted to the first initialization voltage line (VL1) to the second node (N2).

[0097] The fifth transistor (T5) (first light-emitting control transistor) may be connected between the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate connected to the fourth gate line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to a fourth gate signal (EM) transmitted to the fourth gate line (EML).

[0098] The sixth transistor (T6) (second emission control transistor) may be connected between the first transistor (T1) and the organic light emitting diode (OLED). The sixth transistor (T6) may be connected between the second node (N2) and the third node (N3). The sixth transistor (T6) may include a gate connected to the fifth gate line (EMBL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The first terminal of the sixth transistor (T6) may be connected to the second terminal of the first transistor (T1), the first terminal of the fourth transistor (T4), the first capacitor (C1), and the second capacitor (C2). The second terminal of the sixth transistor (T6) can be connected to the first terminal of the seventh transistor (T7) and the pixel electrode of the organic light-emitting diode (OLED). The sixth transistor (T6) can be turned on or off according to the fifth gate signal (EMB) transmitted to the fifth gate line (EMBL).

[0099] The seventh transistor (T7) (third initialization transistor) may be connected between the organic light-emitting diode (OLED) and the second initialization voltage line (VL2). The seventh transistor (T7) may be connected between the sixth transistor (T6) and the second initialization voltage line (VL2). The seventh transistor (T7) may include a gate connected to the second gate line (GIL), a first terminal connected to the third node (N3), and a second terminal connected to the second initialization voltage line (VL2). The first terminal of the seventh transistor (T7) may be connected to the second terminal of the sixth transistor (T6) and the pixel electrode of the organic light-emitting diode (OLED). The seventh transistor (T7) is turned on by the second gate signal (GI) transmitted to the second gate line (GIL) and can transmit the second initialization voltage (Vaint) transmitted to the second initialization voltage line (VL2) to the third node (N3).

[0100] A first capacitor (C1) may be connected between a first gate of a first transistor (T1) and a second terminal of the first transistor (T1). A first electrode of the first capacitor (C1) may be connected to a first node (N1), and a second electrode may be connected to a second node (N2). A first electrode of the first capacitor (C1) may be connected to a first gate of the first transistor (T1), a second terminal of the second transistor (T2), and a first terminal of a third transistor (T3). The second electrode of the first capacitor (C1) can be connected to the second terminal and the second gate of the first transistor (T1), the second electrode of the second capacitor (C2), the first terminal of the fourth transistor (T4), and the first terminal of the sixth transistor (T6). The first capacitor (C1) serves as a storage capacitor and can store a voltage corresponding to the threshold voltage of the first transistor (T1) and a data signal (Vdata).

[0101] A second capacitor (C2) may be connected between a reference voltage line (VRL) and a second node (N2). A first electrode of the second capacitor (C2) may be connected to the reference voltage line (VRL). A second electrode of the second capacitor (C2) may be connected to a second terminal and a second gate of the first transistor (T1), a second electrode of the first capacitor (C1), a first terminal of the fourth transistor (T4), and a first terminal of the sixth transistor (T6). A capacitance of the first capacitor (C1) may be greater than a capacitance of the second capacitor (C2).

[0102] An organic light-emitting diode (OLED) may be connected to a first transistor (T1) via a sixth transistor (T6). The organic light-emitting diode (OLED) includes a pixel electrode (anode) connected to a third node (N3) and a counter electrode (cathode) facing the pixel electrode, and the counter electrode may be supplied with a second driving voltage (ELVSS). The counter electrode may be a common electrode common to a plurality of pixels (PX).

[0103] In one embodiment, as illustrated in FIG. 5, a pixel (PX) can be driven for one first scan period (AS) and one second scan period (SS) during one frame (1F). Most of the first scan period (AS) and the second scan period (SS) may be a light-emitting period. Voltage levels of the first gate signal (GW), the second gate signal (GI), the third gate signal (GR), the fourth gate signal (EM), and the fifth gate signal (EMB) applied to the pixel (PX) in the first scan period (AS) and the second scan period (SS) may be different.

[0104] As illustrated in Fig. 6, the first scan period (AS) may include a first non-emission period (ND1) in which the pixel (PX) does not emit light and a first emission period (DD1) in which the pixel (PX) emits light. The first non-emission period (ND1) may include a first period (P1), a second period (P2), a third period (P3), and a fourth period (P4).

[0105] Each of the first gate signal (GW), the second gate signal (GI), the third gate signal (GR), the fourth gate signal (EM), and the fifth gate signal (EMB) may have a high-level voltage (first-level voltage) for a portion of the period and a low-level voltage (second-level voltage) for a portion of the period. Here, the high-level voltage may be an on-voltage that turns on the transistor, and the low-level voltage may be an off-voltage that turns off the transistor.

[0106] The first period (P1) may be a first initialization period for initializing the first node (N1), the second node (N2) to which the first transistor (T1) is connected, and the third node (N3) to which the pixel electrode of the organic light-emitting diode (OLED) is connected. In the first period (P1), a second gate signal (GI) of an on voltage may be supplied (applied) to the second gate line (GIL). And, a third gate signal (GR) of an on voltage may be supplied to the third gate line (GRL). The first gate signal (GW), the fourth gate signal (EM), and the fifth gate signal (EMB) may be supplied as an off voltage. The timing of applying the on voltage of the third gate signal (GR) may be delayed by a predetermined time (for example, a pre-designated or selectable time) from the timing of applying the on voltage of the second gate signal (GI).

[0107] The fourth transistor (T4) and the seventh transistor (T7) may be turned on by the second gate signal (GI), and the third transistor (T3) may be turned on by the third gate signal (GR). The second node (N2), for example, the second terminal of the first transistor (T1), may be initialized to a first initialization voltage (Vint) by the turned-on fourth transistor (T4). The first node (N1), for example, the first gate of the first transistor (T1), may be initialized to a reference voltage (Vref) by the turned-on third transistor (T3). The third node (N3), for example, the pixel electrode of an organic light-emitting diode (OLED), may be initialized to a second initialization voltage (Vaint) by the turned-on seventh transistor (T7). The first capacitor (C1) and the second capacitor (C2) can be initialized by the turned-on third transistor (T3) and fourth transistor (T4).

[0108] The second period (P2) may be a compensation period for compensating the threshold voltage of the first transistor (T1). In the second period (P2), a third gate signal (GR) of an on voltage may be supplied to the third gate line (GRL), and a fourth gate signal (EM) may be supplied to the fourth gate line (EML). In addition, the first gate signal (GW), the second gate signal (GI), and the fifth gate signal (EMB) may be supplied with an off voltage.

[0109] The third transistor (T3) can be turned on by the third gate signal (GR), and the fifth transistor (T5) can be turned on by the fourth gate signal (EM). Accordingly, the reference voltage (Vref) is supplied to the first node (N1), and the first driving voltage (ELVDD) is supplied to the first terminal of the first transistor (T1), so that the first transistor (T1) can be turned on. When the voltage of the second terminal of the first transistor (T1) reaches the difference (Vref-Vth) between the reference voltage (Vref) and the threshold voltage (Vth) of the first transistor (T1), the first transistor (T1) can be turned off. And, a voltage corresponding to the threshold voltage (Vth) of the first transistor (T1) is stored in the first capacitor (C1), so that the threshold voltage (Vth) of the first transistor (T1) can be compensated.

[0110] The third period (P3) may be a write period in which a data signal is supplied to a pixel. In the third period (P3), a first gate signal (GW) of an on voltage may be supplied to the first gate line (GWL). In one embodiment, the on voltage of the first scan signal (GW) may have a width of approximately two horizontal periods (2H). In addition, the second gate signal (GI), the third gate signal (GR), the fourth gate signal (EM), and the fifth gate signal (EMB) may be supplied as an off voltage.

[0111] The second transistor (T2) is turned on by the first gate signal (GW). The turned-on second transistor (T2) can transfer the data signal (Vdata) from the data line (DL) to the first node (N1), for example, the first gate of the first transistor (T1). Accordingly, the voltage of the first node (N1) can be changed from the reference voltage (Vref) to a voltage corresponding to the data signal (Vdata). At this time, the voltage of the second node (N2) can also be changed in response to the amount of voltage change of the first node (N1). The voltage of the second node (N2) can be a voltage (Vref-Vth+αХ(Vdata-Vref)) changed according to the capacity ratio (α=C1 / (C1+C2)) of the first capacitor (C1) and the second capacitor (C2). Accordingly, the first capacitor (C1) can be charged with a voltage corresponding to the threshold voltage (Vth) and data signal (Vdata) of the first transistor (T1).

[0112] The fourth period (P4) may be a second initialization period for initializing the second node (N2) connected to the second terminal of the first transistor (T1) and the third node (N3) connected to the pixel electrode of the organic light-emitting diode (OLED) before the first emission period (DD1) after data writing. In the fourth period (P4), a second gate signal (GI) of an on voltage may be supplied (applied) to the second gate line (GIL). In addition, the first gate signal (GW), the third gate signal (GR), the fourth gate signal (EM), and the fifth gate signal (EMB) may be supplied as an off voltage.

[0113] The fourth transistor (T4) and the seventh transistor (T7) can be turned on by the second gate signal (GI). The first initialization voltage (Vint) can be transmitted to the second terminal of the first transistor (T1) to the turned-on fourth transistor (T4). The second initialization voltage (Vaint) can be transmitted to the pixel electrode of the organic light-emitting diode (OLED) by the turned-on seventh transistor (T7).

[0114] When displaying low grayscale (e.g., 11 to 31 grayscale), luminance change may occur due to the voltage remaining in the organic light-emitting diode (OLED). By initializing the third node (N3) during the fourth period (P4) after data writing and before pixel emission, luminance change of the organic light-emitting diode (OLED) when displaying low grayscale can be minimized, thereby further improving image quality. In addition, by using a voltage different from the first initialization voltage (Vint), for example, a voltage higher than the first initialization voltage (Vint), as the second initialization voltage (Vaint), the voltage change time of the pixel electrode can be minimized, thereby minimizing screen flicker.

[0115] The first emission period (DD1) may be a period during which the organic light-emitting diode (OLED) emits light. In the first emission period (DD1), a fourth gate signal (EM) having an on voltage may be supplied to the fourth gate line (EML), and a fifth gate signal (EMB) having an on voltage may be supplied to the fifth gate line (EMBL). In addition, the first gate signal (GW), the second gate signal (GI), and the third gate signal (GR) may be off voltages.

[0116] In the first emission period (DD1), the fifth transistor (T5) is turned on by the fourth gate signal (EM), and the first driving voltage (ELVDD) can be supplied to the first terminal of the first transistor (T1) by the turned-on fifth transistor (T5). The first transistor (T1) is supplied with a driving current (Id∝(Vgs-Vth)) having a magnitude corresponding to a voltage corresponding to a data signal (Vdata) stored in the first capacitor (C1), for example, a voltage (Vgs-Vth) obtained by subtracting the threshold voltage (Vth) of the first transistor (T1) from the gate-source voltage (Vgs) of the first transistor (T1). 2 ) outputs, and the driving current flows through the organic light-emitting diode (OLED) through the sixth transistor (T6) turned on by the fifth gate signal (EMB), and the organic light-emitting diode (OLED) can emit light with a brightness corresponding to the size of the driving current.

[0117] As illustrated in Fig. 7, the second scan period (SS) may include a second non-emission period (ND2) in which the pixel (PX) does not emit light and a second emission period (DD2) in which the pixel (PX) emits light. The second non-emission period (ND2) may include a fifth period (P5) and a sixth period (P6). The second scan period (SS) may not include a compensation period corresponding to the second period (P2) of the first scan period (AS) and a writing period corresponding to the third period (P3).

[0118] Each of the first gate signal (GW), the second gate signal (GI), the third gate signal (GR), the fourth gate signal (EM), and the fifth gate signal (EMB) can have a high-level voltage (first-level voltage) for some period of time and a low-level voltage (second-level voltage) for some period of time.

[0119] The fifth period (P5) may be a third initialization period for initializing the third node (N3) connected to the pixel electrode of the organic light-emitting diode (OLED). The fifth period (P5) may correspond to the first period (P1) of the first scan period (AS). In the fifth period (P5), a second gate signal (GI) of an on voltage may be supplied to the second gate line (GIL). The first gate signal (GW), the third gate signal (GR), the fourth gate signal (EM), and the fifth gate signal (EMB) may be supplied as an off voltage. The fourth transistor (T4) and the seventh transistor (T7) may be turned on by the second gate signal (GI). A second node (N2), for example, a second terminal of a first transistor (T1), can be initialized to a first initialization voltage (Vint) by a turned-on fourth transistor (T4). A third node (N3), for example, a pixel electrode of an organic light-emitting diode (OLED), can be initialized to a second initialization voltage (Vaint) by a turned-on seventh transistor (T7).

[0120] The sixth period (P6) may be a fourth initialization period that initializes the third node (N3) connected to the pixel electrode of the organic light-emitting diode (OLED) prior to the second emission period (DD2). The sixth period (P6) may correspond to the fourth period (P4) of the first scan period (AS). In the sixth period (P6), a second gate signal (GI) of an on voltage may be supplied to the second gate line (GIL). The first gate signal (GW), the third gate signal (GR), the fourth gate signal (EM), and the fifth gate signal (EMB) may be supplied as an off voltage. The fourth transistor (T4) and the seventh transistor (T7) may be turned on by the second gate signal (GI). A second node (N2), for example, a second terminal of a first transistor (T1), can be initialized to a first initialization voltage (Vint) by a turned-on fourth transistor (T4). A third node (N3), for example, a pixel electrode of an organic light-emitting diode (OLED), can be initialized to a second initialization voltage (Vaint) by a turned-on seventh transistor (T7).

[0121] The second emission period (DD2) may be a period in which the organic light emitting diode (OLED) emits light. The second emission period (DD2) may correspond to the first emission period (DD1) of the first scan period (AS). In the second emission period (DD2), a fourth gate signal (EM) of an on voltage may be supplied to the fourth gate line (EML), and a fifth gate signal (EMB) of an on voltage may be supplied to the fifth gate line (EMBL). In addition, the first gate signal (GW), the second gate signal (GI), and the third gate signal (GR) may be off voltages.

[0122] In the second emission period (DD2), the fifth transistor (T5) is turned on by the fourth gate signal (EM), and the first driving voltage (ELVDD) can be supplied to the first terminal of the first transistor (T1) by the turned-on fifth transistor (T5). The first transistor (T1) outputs a driving current having a magnitude corresponding to the voltage stored in the first capacitor (C1), for example, the data signal (Vdata), and the driving current flows through the organic light-emitting diode (OLED) through the sixth transistor (T6) turned on by the fifth gate signal (EMB), and the organic light-emitting diode (OLED) can emit light with a brightness corresponding to the magnitude of the driving current. The data signal (Vdata) stored in the first capacitor (C1) during the second emission period (DD2) may be a signal that is maintained as a data signal supplied to the pixel during the third period (P3) of the first scan period (AS).

[0123] In the fourth period (P4) and the sixth period (P6), when the first initialization voltage (Vint) and the second initialization voltage (Vaint) are applied to the second node (N2) and the third node (N3), for example, the first terminal and the second terminal of the sixth transistor (T6), respectively, and when the on voltages of the fourth gate signal (EM) and the fifth gate signal (EMB) are applied at the same timing, the voltage of the third node (N3) may change to a voltage lower than the second initialization voltage (Vaint) due to the voltage difference between the first terminal and the second terminal of the sixth transistor (T6). Accordingly, the effect of minimizing the flicker phenomenon by initializing the third node (N3) to the second initialization voltage (Vaint) higher than the first initialization voltage (Vint) may be reduced. In an embodiment of the present invention, in each of the first emission period (DD1) and the second emission period (DD2), the timing of applying the on voltage of the fifth gate signal (EMB) may be delayed by a predetermined time (DT) (e.g., a pre-designated or selectable time) from the timing of applying the on voltage of the fourth gate signal (EM). By first applying the on voltage of the fourth gate signal (EM) to increase the voltage level of the voltage applied to the first terminal of the sixth transistor (T6), and then applying the on voltage of the fifth gate signal (EMB), the voltage difference between the first terminal and the second terminal of the sixth transistor (T6) is reduced, thereby minimizing the voltage fluctuation of the third node (N3) and minimizing the flicker phenomenon.

[0124] In addition, the embodiment of the present invention can minimize the luminance deviation according to the driving speed even if one frame includes one or more second scan periods (SS) by performing initialization of the pixel electrode twice in a second scan period (SS) similar to the first scan period (AS).

[0125] In the above-described embodiment, during one frame, the threshold voltage compensation and data writing of the driving transistor are each performed once, so that the first gate signal (GW) and the third gate signal (GR) can be supplied only during the first scan period (AS). The second gate signal (GI), the fifth gate signal (EM), and the sixth gate signal (EMB) can be supplied during the first scan period (AS) and the second scan period (SS), respectively. That is, during one frame, the cycle of the first gate signal (GW) and the third gate signal (GR) may be one cycle, and the cycles of the second gate signal (GI), the fourth gate signal (EM), and the fifth gate signal (EMB) may be two cycles. Here, the fourth gate signal (EM) is supplied during the compensation period (P2) of the first scan period (AS), and is not supplied during the period corresponding to the compensation period (P2) during the second scan period (SS). However, considering the fourth gate signal (EM) as a light emission control signal, the fourth gate signal (EM) is supplied to the first light emission period (DD1) of the first scan period (AS) and the second light emission period (DD2) of the second scan period (SS), so it is interpreted as having a period of two cycles during one frame.

[0126] The first gate signal (GW) can be supplied to the pixel once only in the third period (P3) of the first scan period (AS), and can be supplied to the pixel at an interval of one cycle per frame. The second gate signal (GI) can be supplied to the pixel twice in the first period (P1) and the fourth period (P4) of the first scan period (AS), and twice in the fifth period (P5) and the sixth period (P6) of the second scan period (SS), and can be supplied to the pixel at an interval of two cycles per frame. The third gate signal (GR) can be supplied to the pixel once continuously only in the first period (P1) and the second period (P2) of the first scan period (AS), and can be supplied to the pixel at an interval of one cycle per frame. The fourth gate signal (EM) is supplied to the pixel once in the first emission period (DD1) of the first scan period (AS) and once in the second emission period (DD2) of the second scan period (SS), so that it can be supplied to the pixel at an interval of two cycles per frame. Here, the case where the fourth gate signal (EM) is supplied to the second period (P2) of the first scan period (AS) is omitted. The fifth gate signal (EMB) is supplied to the pixel once in the first emission period (DD1) of the first scan period (AS) and once in the second emission period (DD2) of the second scan period (SS), so that it can be supplied to the pixel at an interval of two cycles per frame.

[0127] In another embodiment, the fourth period (P4) of the first scan period (AS) and the sixth period (P6) of the second scan period (SS) may be omitted. In this case, the second gate signal (GI) may be supplied to the pixel once in the first period (P1) of the first scan period (AS) and once in the fifth period (P5) of the second scan period (SS), at an interval of two cycles per frame.

[0128] FIGS. 5 to 7 illustrate that in an embodiment in which one frame includes one first scan period (AS) and one second scan period (SS), the fourth gate signal (EM) is supplied to the pixel at a cycle of two cycles per frame. In another embodiment, as illustrated in FIG. 3b, in an embodiment in which one frame includes one first scan period (AS) and two or more second scan periods (SS), it can be understood that the third gate signal (GR) may be supplied to the pixel at an interval of one cycle per frame, and the fourth gate signal (EM) may be supplied to the pixel at an interval of three or more cycles per frame.

[0129] Fig. 8 is a schematic diagram of an equivalent circuit of a pixel according to a comparative example. Fig. 9 is a diagram schematically showing a change in a first driving voltage (ELVDD) as a fourth gate signal (EM) is applied to the pixel illustrated in Fig. 8 during one frame.

[0130] In the pixel circuit (PC') of the pixel (PX') illustrated in FIG. 8, a second capacitor (C2') is connected between the driving voltage line (PL) and the second node (N2). As illustrated in FIGS. 6 and 7, the fourth gate signal (EM) can be sequentially applied to the display area (DA) from the first line to the last line during one frame. When the fourth gate signal (EM) is applied as an on voltage, the first driving voltage (ELVDD) can drop, and when the fourth gate signal (EM) is applied as an off voltage, the first driving voltage (ELVDD) can rise. When the fourth gate signal (EM) is applied as an on voltage to the pixel (PX') displaying white, the drop in the first driving voltage (ELVDD) is large, and when the fourth gate signal (EM) is applied as an on voltage to the pixel (PX') displaying black, the drop in the first driving voltage (ELVDD) is small.

[0131] FIG. 9 shows the variation of the first driving voltage (ELVDD) according to the time (t) measured for the entire display area (DA) as the fourth gate signal (EM) is applied at intervals of two cycles during one frame. As illustrated in FIG. 9, as the fourth gate signal (EM) is applied at intervals of two cycles during one frame, a voltage variation of the first driving voltage (ELVDD) may appear in the middle of one frame. Accordingly, each pixel (PX') of the display area (DA) is affected by the drop and rise of the first driving voltage (ELVDD) depending on the operating state, and mura may occur in the image. For example, when the first driving voltage (ELVDD) has a falling slope, the pixel (PX') in the latter half of the second period (P2), for example, before the third gate signal (GR) transitions from the on voltage to the off voltage, may be displayed as a dark region due to a drop in the voltage of the second terminal of the first transistor (T1) caused by the voltage fluctuation of the second capacitor (C2'). In addition, when the first driving voltage (ELVDD) has a rising slope, the pixel (PX') in the first half of the third period (P3), for example, before the fourth gate signal (EM) is the off voltage and the first gate signal (GW) is applied as the on voltage, may be displayed as a light region due to a rise in the voltage of the second terminal of the first transistor (T1) caused by the voltage fluctuation of the second capacitor (C2').

[0132] In a pixel (PX) according to an embodiment of the present invention, the second capacitor (C2') is connected to the reference voltage line (VRL) rather than the driving voltage line (PL), and the third gate signal (GR) is applied at intervals of one cycle during one frame, so that there is no voltage fluctuation of the reference voltage line (VRL) to which the third transistor (T3) is connected in the middle of one frame, and thus the occurrence of Mura can be minimized.

[0133] Fig. 10 is a drawing schematically showing the arrangement of light-emitting areas of a plurality of pixels according to one embodiment.

[0134] Referring to FIG. 10, the display area (DA) defined in the substrate (100) may include a plurality of pixel areas where rows and columns intersect and pixel circuits are arranged. In one embodiment, a unit pixel area including two or more pixel areas adjacent in the x-direction may be defined. For example, a unit pixel area (PCAu) may include three first pixel areas (PCA1), second pixel areas (PCA2), and / or third pixel areas (PCA3) adjacent in the x-direction.

[0135] A plurality of pixels (PX) arranged in a display area (DA) may include a first pixel (PX1) that emits light in a first color, a second pixel (PX2) that emits light in a second color, and a third pixel (PX3) that emits light in a third color. For example, the first pixel (PX1) may be a red pixel, the second pixel (PX2) may be a green pixel, and the third pixel (PX3) may be a blue pixel. The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may be repeatedly arranged in a predetermined pattern in the x direction and the y direction. The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may each include a pixel circuit and an organic light-emitting diode (OLED) electrically connected to the pixel circuit.

[0136] The first pixel area (PCA1) may be an area where the pixel circuit of the first pixel (PX1) is arranged. The second pixel area (PCA2) may be an area where the pixel circuit of the second pixel (PX2) is arranged. The third pixel area (PCA3) may be an area where the pixel circuit of the third pixel (PX3) is arranged. An organic light-emitting diode (OLED) may be arranged in an upper layer of the pixel circuit. The organic light-emitting diode (OLED) may be arranged directly above the connected pixel circuit so as to overlap, or may be arranged so as to partially overlap with the pixel circuit of another pixel arranged in an adjacent row and / or column and offset from the connected pixel circuit.

[0137] Fig. 10 shows the pixel electrode (211) and the light-emitting area (EA) of each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3). The light-emitting area (EA) is an area where the light-emitting layer of an organic light-emitting diode (OLED) is arranged. The light-emitting area (EA) can be defined by the opening of the pixel definition layer described later. Since the light-emitting layer is arranged on the pixel electrode (211), the arrangement of the light-emitting areas illustrated in Fig. 10 can represent the arrangement of the pixel electrodes or the arrangement of pixels.

[0138] The emitting area (EA) can have a shape such as a polygon, such as a square or octagon, a circle, or an oval, and the polygon can also include a shape with rounded corners (vertices).

[0139] As illustrated in FIG. 10, the light-emitting area (EA) of the first pixel (PX1) and the light-emitting area (EA) of the second pixel (PX2) may be arranged adjacent to each other in the y direction, and the light-emitting area (EA) of the third pixel (PX3) may be arranged adjacent to the light-emitting area (EA) of the first pixel (PX1) and the light-emitting area (EA) of the second pixel (PX2) in the x direction. Accordingly, the light-emitting area (EA) of the first pixel (PX1) and the light-emitting area (EA) of the second pixel (PX2) may be arranged alternately in the y direction along an imaginary straight line (IL1), and the light-emitting area (EA) of the third pixel (PX3) may be arranged repeatedly in the y direction along an imaginary straight line (IL2).

[0140] The lengths in the x direction and the lengths in the y direction of the light-emitting area (EA) of the first pixel (PX1), the light-emitting area (EA) of the second pixel (PX2), and the light-emitting area (EA) of the third pixel (PX3) may be the same or different. For example, the light-emitting area (EA) of the first pixel (PX1) and the light-emitting area (EA) of the second pixel (PX2) may have square shapes, and the light-emitting area (EA) of the third pixel (PX3) may have a rectangular shape having a long side in the y direction. The length in the y direction of the light-emitting area (EA) of the third pixel (PX3) may be substantially the same as or greater than the sum of the lengths in the y direction of the light-emitting area (EA) of the first pixel (PX1) and the lengths in the y direction of the light-emitting area (EA) of the second pixel (PX2).

[0141] The first light-emitting area (EA) of the first pixel (PX1), the second light-emitting area (EA) of the second pixel (PX2), and the third light-emitting area (EA) of the third pixel (PX3) may have the same or different areas (sizes). In one embodiment, the light-emitting area (EA) of the third pixel (PX3) may have a larger area than the light-emitting area (EA) of the first pixel (PX1). The light-emitting area (EA) of the third pixel (PX3) may have a larger area than the light-emitting area (EA) of the second pixel (PX). The light-emitting area (EA) of the first pixel (PX1) may have substantially the same area as the light-emitting area (EA) of the second pixel (PX).

[0142] Figures 11 to 19 are schematic layout diagrams illustrating the elements of the pixel illustrated in Figure 4, layer by layer. Figure 15 is a schematic plan view illustrating elements of the first pixel area (PCA1), which is part of Figure 14. Figure 20 is a schematic cross-sectional view taken along line I-I' of Figure 19. Figure 21 is a schematic cross-sectional view taken along line II-II' of Figure 19.

[0143] In one embodiment, different second initialization voltages (Vaint) may be supplied to the first pixel, the second pixel, and the third pixel in consideration of the light-emitting characteristics of the first pixel, the second pixel, and the third pixel. For example, the pixel circuit of the first pixel may be connected to the 2-1 initialization voltage line (VL21), and the pixel circuits of the second pixel and the third pixel may be connected to the 2-2 initialization voltage line (VL22). The second initialization voltage supplied to the 2-1 initialization voltage line (VL21) and the second initialization voltage supplied to the 2-2 initialization voltage line (VL22) may be different.

[0144] The same components may be arranged in each layer of the first pixel area (PCA1), the second pixel area (PCA2), and the third pixel area (PCA3). Hereinafter, for convenience of illustration and description, identification numbers are assigned to the components of the pixel circuit arranged in the first pixel area (PCA1), and the description will focus on the first pixel area (PCA1), and the description of the same components may be substantially identically applied to the components of the second pixel area (PCA2) and the third pixel area (PCA3). The cross-sectional views of FIGS. 20 and 21 are cross-sectional views of the first pixel area (PCA1). Hereinafter, description will be made with reference to FIGS. 11 to 21 together.

[0145] The substrate (100) may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable characteristics. The substrate (100) may have a single-layer structure of an organic layer or a multi-layer structure of an organic layer and an inorganic layer. For example, the substrate (100) may have a laminated structure of a first base layer / barrier layer / second base layer. The first base layer and the second base layer may each be an organic layer including a polymer resin. The first base layer and the second base layer may include a transparent polymer resin. The barrier layer is a barrier layer that prevents the penetration of external foreign substances, and is made of silicon nitride (SiN). x ) or silicon oxide (SiO x ) may be single-layered or multi-layered, including inorganic materials such as:

[0146] Referring to FIG. 11, a first conductive layer may be disposed on a substrate (100). The first conductive layer may include a reference voltage line (VRL), a first electrode layer, and a first driving voltage line (PLh). In another embodiment, a barrier layer may be further disposed between the substrate (100) and the first conductive layer.

[0147] The reference voltage line (VRL) extends in the x direction and can be arranged across the first pixel area (PCA1), the second pixel area (PCA2), and the third pixel area (PCA3).

[0148] The first driving voltage line (PLh) may include a main line (PLm1) extending in the x direction and a protruding line (PLp) extending in the y direction from the main line (PLm1). The main line (PLm1) of the first driving voltage line (PLh) may be arranged to cross the first pixel area (PCA1), the second pixel area (PCA2), and the third pixel area (PCA3). The protruding line (PLp) may be arranged adjacent to a boundary between adjacent pixel areas in each pixel area.

[0149] The first electrode layer may include a third electrode (C13) of a first capacitor (C1) and a first electrode (C21) of a second capacitor (C2) that are spaced apart from each other. The third electrode (C13) of the first capacitor (C1) may be provided in an island type. The first electrode (C21) of the second capacitor (C2) may be connected to a reference voltage line (VRL). The first electrode (C21) of the second capacitor (C2) may be connected to the reference voltage line (VRL) through a connection portion (CP). The first electrodes (C21) of the second capacitors (C2) of the first pixel area (PCA1), the second pixel area (PCA2), and the third pixel area (PCA3) may be connected to each other. In one embodiment, the first electrode (C21), the connection portion (CP), and the reference voltage line (VRL) of the second capacitor (C2) may be formed integrally and provided on the same layer. The connection portion (CP) may be arranged in one of the first pixel area (PCA1), the second pixel area (PCA2), and the third pixel area (PCA3), for example, the third pixel area (PCA3).

[0150] In one embodiment, the first conductive layer may further include a repair line (RL). The repair line (RL) may extend in the x-direction and be arranged to cross the first pixel area (PCA1), the second pixel area (PCA2), and the third pixel area (PCA3).

[0151] A first insulating layer (111) may be disposed over a first conductive layer covering a substrate (100), and a second conductive layer may be disposed over the first insulating layer (111). As illustrated in Fig. 12, the second conductive layer may include a second electrode layer, a lower first gate line (GWL1), a first initialization voltage line (VL1), and a second-second initialization voltage line (VL22).

[0152] The second electrode layer may be provided in an island type. A part of the second electrode layer may be the second gate electrode (G12) as the lower gate electrode (bottom gate electrode) of the first transistor (T1). Another part of the second electrode layer may be the second electrode (C12) of the first capacitor (C1), and another part of the second electrode layer may be the second electrode (C22) of the second capacitor (C2). The second electrode (C12) of the first capacitor (C1) may overlap the third electrode (C13) of the first capacitor (C1). The second electrode (C22) of the second capacitor (C2) may overlap the first electrode (C21) of the second capacitor (C2). An opening (SOP1) may be defined in the second electrode layer.

[0153] The first initialization voltage line (VL1) and the second-second initialization voltage line (VL22) extend in the x direction and can be arranged in the first pixel area (PCA1), the second pixel area (PCA2), and the third pixel area (PCA3).

[0154] A second conductive layer is disposed on the first insulating layer (111), and a second insulating layer (112) is disposed thereon, and a semiconductor layer (ACT) may be positioned on the second insulating layer (112). The semiconductor layer (ACT) may include an organic semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor. As illustrated in FIG. 13, the semiconductor layer (ACT) may include a first semiconductor layer (ACT1), a second semiconductor layer (ACT2), a third semiconductor layer (ACT3), and a fourth semiconductor layer (ACT4). The semiconductor layer (ACT) may include a channel region of each of the first to seventh transistors (T1 to T7), and a source region and a drain region next to the channel region (e.g., on both sides). The source region or the drain region may in some cases be interpreted as a source electrode or a drain electrode of the transistor.

[0155] Referring to FIG. 15, the first semiconductor layer (ACT1) may include a source region (S1) and a drain region (D1) of the first transistor (T1) and a source region (S5) and a drain region (D5) of the fifth transistor (T5). The second semiconductor layer (ACT2) may include a source region (S2) and a drain region (D2) of the second transistor (T2) and a source region (S3) and a drain region (D3) of the third transistor (T3). The third semiconductor layer (ACT3) may include a source region (S6) and a drain region (D6) of the sixth transistor (T6) and a source region (S7) and a drain region (D7) of the seventh transistor (T7). The fourth semiconductor layer (ACT4) may include a source region (S4) and a drain region (D4) of the fourth transistor (T4).

[0156] The width (length in the x direction) of the channel region of the first transistor (T1) in the third pixel region (PCA3) may be greater than the width of the channel region of the first transistor (T1) in each of the first pixel region (PCA1) and the second pixel region (PCA2).

[0157] In the comparative example where the second capacitor (C2) and the reference voltage line (VRL) are arranged on different layers, a connecting electrode that acts as a bridge to connect the first electrode (C21) of the second capacitor (C2) to the reference voltage line (VRL) is required, and a space for forming a contact hole for connecting the connecting electrode and the reference voltage line (VRL) may be required.

[0158] According to an embodiment of the present invention, as illustrated in FIGS. 15 and 20, the first electrode (C21) of the second capacitor (C2) and the reference voltage line (VRL) are arranged on the same layer, thereby reducing the wiring arrangement space and increasing the resolution, and increasing the capacitance capacity of the second capacitor (C2).

[0159] A third insulating layer (113) may be disposed on the second insulating layer (112) to cover a semiconductor layer (ACT), and a third conductive layer may be disposed on the third insulating layer (113). As illustrated in FIG. 14, the third conductive layer may include a third electrode layer and gate electrodes (G2 to G7) of the second to seventh transistors (T2 to T7). The third conductive layer may further include an upper first gate line (GWL2), a second gate line (GIL), a third gate line (GRL), a fourth gate line (EML), a fifth gate line (EMBL), and a second-first initialization voltage line (VL21). In addition, the third conductive layer may further include connection electrodes (121, 122). Only the region of the third insulating layer (113) overlapping the third conductive layer may remain, and the other regions may be removed.

[0160] The third electrode layer is provided in an island type, and an opening (SOP2) may be defined in the third electrode layer. A part of the third electrode layer may be the first gate electrode (G11), which is the upper gate electrode (top gate electrode) of the first transistor (T1). Another part of the third electrode layer may be the first electrode (C11) of the first capacitor (C1). The first electrode (C11) of the first capacitor (C1) may overlap the second electrode (C12) and the third electrode (C13) of the first capacitor (C1). The first electrode (C11) of the first capacitor (C1) can be electrically connected to the third electrode (C13) of the first capacitor (C1) by contacting it through a contact hole (21) penetrating the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113). The contact hole (21) can be located within the opening (SOP1) of the second electrode (C12) of the first capacitor (C1). The first capacitor (C1) includes the third electrode (C13), the second electrode (C12), and the first electrode (C11) sequentially arranged in the z direction on the upper portion of the substrate (100), and the first electrode (C11) and the third electrode (C13) can be electrically connected.

[0161] The upper first gate line (GWL2), second gate line (GIL), third gate line (GRL), fourth gate line (EML), fifth gate line (EMBL), and second-first initialization voltage line (VL21) extend in the x direction and can be arranged to cross the first pixel area (PCA1), the second pixel area (PCA2), and the third pixel area (PCA3).

[0162] The upper first gate line (GWL2) overlaps the lower first gate line (GWL1) and can be electrically connected to the lower first gate line (GWL1) through a contact hole (24) penetrating the second insulating layer (112) and the third insulating layer (113). The first gate line (GWL) can have a two-layer structure, including the lower first gate line (GWL1) and the upper first gate line (GWL2) arranged in different layers.

[0163] The gate electrodes (G1 to G7) of the first to seventh transistors (T1 to T7) can overlap the channel regions of the semiconductor layer (ACT).

[0164] Referring to FIG. 15, the first gate electrode (G11) of the first transistor (T1) may be provided in an island type. The first gate electrode (G11) of the first transistor (T1) may overlap the first semiconductor layer (ACT1). The first gate electrode (G11) of the first transistor (T1) may overlap the second gate electrode (G12). The gate electrode (G2) of the second transistor (T2) may be provided in an island type. The gate electrode (G2) of the second transistor (T2) may overlap the second semiconductor layer (ACT2). The gate electrode (G3) of the third transistor (T3) may be a portion of the third gate line (GRL) that intersects (overlaps) the second semiconductor layer (ACT2). The gate electrode (G4) of the fourth transistor (T4) may be a portion of the second gate line (GIL) that intersects (overlaps) the fourth semiconductor layer (ACT4). The gate electrode (G5) of the fifth transistor (T5) may be a portion of the fourth gate line (EML) that intersects (overlaps) the first semiconductor layer (ACT1). The gate electrode (G6) of the sixth transistor (T6) may be a portion of the fifth gate line (EMBL) that intersects (overlaps) the third semiconductor layer (ACT3). The gate electrode (G7) of the seventh transistor (T7) may be a portion of the second gate line (GIL) that intersects (overlaps) the third semiconductor layer (ACT3).

[0165] The connecting electrode (121) can be electrically connected to the reference voltage line (VRL) through a contact hole (22) penetrating the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113). The connecting electrode (122) can be electrically connected to the first driving voltage line (PLh) through a contact hole (23) penetrating the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113).

[0166] A fourth insulating layer (114) may be disposed on the third conductive layer to cover the third conductive layer, and a fourth conductive layer may be disposed on the fourth insulating layer (114). The fourth insulating layer (114) may be disposed on the second insulating layer (112) in an area where the third insulating layer (113) has been removed, and may contact the upper surface of the second insulating layer (112). As illustrated in Fig. 16, the fourth conductive layer may include a data line (DL) and connection electrodes (131, 132, 133, 134, 135, 136, 137, 138). For convenience of illustration and description, Fig. 16 illustrates only the fourth conductive layer.

[0167] The data line (DL) can be arranged to extend in the y direction for each pixel area. The data line (DL) can be electrically connected to the drain area (D2) of the second transistor (T2) through a contact hole (31) penetrating the fourth insulating layer (114).

[0168] One end of the connecting electrode (131) can be electrically connected to the gate electrode (G2) of the second transistor (T2) through a contact hole (32) penetrating the fourth insulating layer (114). The other end of the connecting electrode (131) can be electrically connected to the upper first gate line (GWL2) through a contact hole (33) penetrating the fourth insulating layer (114).

[0169] The connecting electrode (132) can be electrically connected to the source region (S3) of the third transistor (T3) through a contact hole (34) penetrating the fourth insulating layer (114), and can be electrically connected to the connecting electrode (121) through a contact hole (35) penetrating the fourth insulating layer (114). Accordingly, the source region (S3) of the third transistor (T3) can be electrically connected to the reference voltage line (VRL).

[0170] One end of the connecting electrode (133) can be electrically connected to the third electrode layer through a contact hole (36) penetrating the fourth insulating layer (114), and can be electrically connected to the first gate electrode (G11) of the first transistor (T1). The other end of the connecting electrode (133) can be electrically connected to the source region (S2) of the second transistor (T2) and the drain region (D3) of the third transistor (T3) through a contact hole (37) penetrating the fourth insulating layer (114).

[0171] The connecting electrode (134) may include a first region (134a) overlapping the third electrode layer and a second region (134b) protruding and extending in the y direction from the first region (134a). The connecting electrode (134) may electrically connect the source region (S1) of the first transistor (T1) to the fourth transistor (T4) and the sixth transistor (T6).

[0172] The first region (134a) of the connecting electrode (134) can be electrically connected to the source region (S1) of the first transistor (T1) through a contact hole (38) penetrating the fourth insulating layer (114). The first region (134a) of the connecting electrode (134) can be electrically connected to the second electrode layer through a contact hole (39) penetrating the second insulating layer (112) and the fourth insulating layer (114), and can be electrically connected to the second gate electrode (G12) of the first transistor (T1), the second electrode (C12) of the first capacitor (C1), and the second electrode (C22) of the second capacitor (C2). The contact hole (38) and the contact hole (39) can be located within the opening (SOP2) of the third electrode layer. The second region (134b) of the connecting electrode (134) can be electrically connected to the drain region (D6) of the sixth transistor (T6) through a contact hole (40) penetrating the fourth insulating layer (114). The second region (134b) of the connecting electrode (134) can be electrically connected to the drain region (D4) of the fourth transistor (T4) through a contact hole (41) penetrating the fourth insulating layer (114).

[0173] The connecting electrode (135) is electrically connected to the connecting electrode (122) through a contact hole (43) penetrating the fourth insulating layer (114), and can be electrically connected to the drain region (D5) of the fifth transistor (T5) through a contact hole (42) penetrating the fourth insulating layer (114). Accordingly, the drain region (D5) of the fifth transistor (T5) can be electrically connected to the first driving voltage line (PLh).

[0174] One end of the connection electrode (136) can be electrically connected to the source region (S6) of the sixth transistor (T6) through a contact hole (44) penetrating the fourth insulating layer (114). The other end of the connection electrode (136) can overlap a portion of the repair line (RL). The other end of the connection electrode (136) is insulated from the repair line (RL) and can be electrically connected to the repair line (RL) in the event that a defect occurs in the pixel circuit arranged in the corresponding pixel area in the future.

[0175] The connecting electrode (137) is electrically connected to the source region (S4) of the fourth transistor (T4) through a contact hole (45) penetrating the fourth insulating layer (114), and can be connected to the first initialization voltage line (VL1) through a contact hole (46) penetrating the second insulating layer (112) and the fourth insulating layer (114).

[0176] The connecting electrode (138) is electrically connected to the source region (S7) of the seventh transistor (T4) through a contact hole (47) penetrating the fourth insulating layer (114), and can be connected to the second initialization voltage line (VL2) through a contact hole (48) penetrating the second insulating layer (112) and the fourth insulating layer (114). In one embodiment, the connecting electrode (138) arranged in the first pixel area (PCA1) is electrically connected to the second-first initialization voltage line (VL21) through a contact hole (48a), and the connecting electrodes (138) arranged in the second pixel area (PCA2) and the third pixel area (PCA3) can be electrically connected to the second-second initialization voltage line (VL22) through a contact hole (48b), respectively.

[0177] A fifth insulating layer (115) may be disposed on top of a fourth insulating layer (114) to cover a fourth conductive layer, and a fifth conductive layer may be disposed on top of the fifth insulating layer (115). As illustrated in FIGS. 17a to 17c, the fifth conductive layer may include a plurality of vertical conductive lines and a connection electrode (141). For convenience of illustration and description in FIGS. 17a to 17c, only some of the fifth conductive layer and the lower conductive layers are illustrated.

[0178] The connecting electrode (141) is electrically connected to the connecting electrode (136) through a contact hole (51) penetrating the fifth insulating layer (115), and can be electrically connected to the source region (S6) of the sixth transistor (T6).

[0179] The vertical conductive lines may include a second driving voltage line (PLv), vertical initialization voltage lines, a common voltage line (EL), and a vertical reference voltage line (VRLv). The vertical initialization voltage lines may include a first vertical initialization voltage line (VL1v), a second-first vertical initialization voltage line (VL21v), and a second-second vertical initialization voltage line (VL22v). The second driving voltage line (PLv), the vertical initialization voltage lines, the common voltage line (EL), and the vertical reference voltage line (VRLv) may each extend in the y direction and be spaced apart from each other in the x direction in the first pixel area (PCA1), the second pixel area (PCA2), and the third pixel area (PCA3).

[0180] For each unit pixel area (PCAu), a second driving voltage line (PLv), one of the vertical initialization voltage lines, a common voltage line (EL), and a vertical reference voltage line (VRLv) may be sequentially arranged in the x direction. For each unit pixel area (PCAu), one of the first vertical initialization voltage line (VL1v), the second-first vertical initialization voltage line (VL21v), and the second-second vertical initialization voltage line (VL22v) may be arranged in the first pixel area (PCA1) and the second pixel area (PCA2). For example, the vertical conductive lines may be arranged in the following order in the x direction: a second drive voltage line (PLv), a first vertical initialization voltage line (VL1v), a common voltage line (EL), a vertical reference voltage line (VRLv), a second drive voltage line (PLv), a second-first vertical initialization voltage line (VL21v), a common voltage line (EL), a vertical reference voltage line (VRLv), a second drive voltage line (PLv), a second-second vertical initialization voltage line (VL22v), a common voltage line (EL), and a vertical reference voltage line (VRLv).

[0181] Figure 17a illustrates an example in which a second driving voltage line (PLv), a first vertical initialization voltage line (VL1v), a common voltage line (EL), and a vertical reference voltage line (VRLv) are sequentially arranged in the x direction in a unit pixel area (PCAu).

[0182] A second driving voltage line (PLv) may be arranged in the first pixel area (PCA1). The second driving voltage line (PLv) may include a main line (PLm2) extending in the y direction and a first area (145a), a second area (146a), and a third area (147a) protruding and extending from the main line (PLm2) in the x direction. The main line (PLm2) may overlap a data line (DL) located in the first pixel area (PCA1). The first area (145a) may overlap a first gate line (GWL) and a reference voltage line (VRL). An extension of the first area (145a) may overlap a first initialization voltage line (VL1), a second-first initialization voltage line (VL21), and a second-second initialization voltage line (VL22) located in a pixel area adjacent to the first pixel area (PCA1) in the y direction. The second region (146a) may overlap the first transistor (T1), the first capacitor (C1), and the second capacitor (C2). The third region (147a) may overlap the first initialization voltage line (VL1), the second-first initialization voltage line (VL21), and the second-second initialization voltage line (VL22). An extension of the third region (147a) may overlap the first gate line (GWL) and the reference voltage line (VRL) located in a pixel region adjacent to the first pixel region (PCA1) in the y direction. The second region (146a) of the second driving voltage line (PLv) may be electrically connected to the connection electrode (135) of the first pixel region (PCA1) through a contact hole (52) penetrating the fifth insulating layer (115). Accordingly, the second driving voltage line (PLv) can be electrically connected to the first driving voltage line (PLh). The driving voltage line (PL) can have a mesh structure in the display area (DA) including the first driving voltage line (PLh) and the second driving voltage line (PLv).

[0183] A first vertical initialization voltage line (VL1v) may be arranged in a first pixel area (PCA1) and a second pixel area (PCA2). The first vertical initialization voltage line (VL1v) may include a main line (VL1vm) extending in the y direction and a first area (145b), a second area (146b), a third area (147b), and a fourth area (148b) protruding and extending from the main line (VL1vm) in the x direction. The first area (145b), the third area (147b), and the fourth area (148b) may be located in the first pixel area (PCA1), and the second area (146b) may be located in the first pixel area (PCA1) and the second pixel area (PCA2).

[0184] The main line (VL1vm) may overlap the data line (DL) located in the second pixel area (PCA2). The first area (145b) may overlap the first gate line (GWL) and the reference voltage line (VRL) located in the first pixel area (PCA1). An extension of the first area (145b) may overlap the first initialization voltage line (VL1), the second-first initialization voltage line (VL21), and the second-second initialization voltage line (VL22) located in the pixel area adjacent to the first pixel area (PCA1) in the y direction. The second area (146b) may overlap the first transistor (T1), the first capacitor (C1), and the second capacitor (C2) located in the first pixel area (PCA1) and the second pixel area (PCA2). The third region (147b) may overlap the first initialization voltage line (VL1), the second-first initialization voltage line (VL21), and the second-second initialization voltage line (VL22) located in the first pixel region (PCA1). The extension of the third region (147a) may overlap the first gate line (GWL) and the reference voltage line (VRL) located in the pixel region adjacent to the first pixel region (PCA1) in the y direction.

[0185] The fourth region (148b) is located between the second region (146b) and the third region (147b), and can be electrically connected to the connection electrode (137) located in the first pixel region (PCA1) through a contact hole (53) penetrating the fifth insulating layer (115). Accordingly, the first vertical initialization voltage line (VL1v) is electrically connected to the first initialization voltage line (VL1), and the first initialization voltage line (VL1) can have a mesh structure in the display region (DA).

[0186] The shape of the connecting electrode (138) and / or the vertical initialization voltage lines of FIGS. 17b and 17c may be different from the shape of the connecting electrode (138) and / or the vertical initialization voltage lines illustrated in FIGS. 16 and 17a.

[0187] As illustrated in Fig. 17b, a second-second vertical initialization voltage line (VL22v) may be arranged in the first pixel area (PCA1) and the second pixel area (PCA2) of the unit pixel area (PCAu). The second-second vertical initialization voltage line (VL22v) may include a main line (VL22vm) extending in the y direction and a first area (145b), a second area (146b), a third area (147b), and a fourth area (148b) protruding and extending in the x direction from the main line (VL22vm). The first region (145b) and the third region (147b) may be located in the first pixel region (PCA1), the fourth region (148b) may be located in the second pixel region (PCA2), and the second region (146b) may be located in the first pixel region (PCA1) and the second pixel region (PCA2).

[0188] The main line (VL22vm) may overlap the data line (DL) located in the second pixel area (PCA2). The first area (145b) may overlap the first gate line (GWL) and the reference voltage line (VRL) located in the first pixel area (PCA1). An extension of the first area (145b) may overlap the first initialization voltage line (VL1), the second-first initialization voltage line (VL21), and the second-second initialization voltage line (VL22) located in the pixel area adjacent to the first pixel area (PCA1) in the y direction. The second area (146b) may overlap the first transistor (T1), the first capacitor (C1), and the second capacitor (C2) located in the first pixel area (PCA1) and the second pixel area (PCA2). The third region (147b) may overlap the first initialization voltage line (VL1), the second-first initialization voltage line (VL21), and the second-second initialization voltage line (VL22) located in the first pixel region (PCA1). The extension of the third region (147a) may overlap the first gate line (GWL) and the reference voltage line (VRL) located in the pixel region adjacent to the first pixel region (PCA1) in the y direction.

[0189] The fourth region (148b) can be electrically connected to the connection electrode (138) located in the second pixel region (PCA2) through the contact hole (53) penetrating the fifth insulating layer (115). The connection electrode (138) of the second pixel region (PCA2) can be electrically connected to the second-second initialization voltage line (VL22) through the contact hole (48b). Accordingly, the second-second vertical initialization voltage line (VL22v) is electrically connected to the second-second initialization voltage line (VL22), and the second-second initialization voltage line (VL22) can have a mesh structure in the display region (DA).

[0190] As illustrated in FIG. 17c, a second-first vertical initialization voltage line (VL21v) may be arranged in the first pixel area (PCA1) and the second pixel area (PCA2) of the unit pixel area (PCAu). The second-first vertical initialization voltage line (VL21v) may include a main line (VL21vm) extending in the y direction and a first area (145b), a second area (146b), a third area (147b), and a fourth area (148b) protruding and extending from the main line (VL21vm) in the x direction. The first area (145b), the third area (147b), and the fourth area (148b) may be located in the first pixel area (PCA1), and the second area (146b) may be located in the first pixel area (PCA1) and the second pixel area (PCA2).

[0191] The main line (VL21vm) may overlap the data line (DL) located in the second pixel area (PCA2). The first area (145b) may overlap the first gate line (GWL) and the reference voltage line (VRL) located in the first pixel area (PCA1). An extension of the first area (145b) may overlap the first initialization voltage line (VL1), the second-first initialization voltage line (VL21), and the second-second initialization voltage line (VL22) located in a pixel area adjacent to the first pixel area (PCA1) in the y direction. The second area (146b) may overlap the first transistor (T1), the first capacitor (C1), and the second capacitor (C2) located in the first pixel area (PCA1) and the second pixel area (PCA2). The third region (147b) may overlap the first initialization voltage line (VL1), the second-first initialization voltage line (VL21), and the second-second initialization voltage line (VL22) located in the first pixel region (PCA1). The extension of the third region (147a) may overlap the first gate line (GWL) and the reference voltage line (VRL) located in the pixel region adjacent to the first pixel region (PCA1) in the y direction.

[0192] The fourth region (148b) is located between the second region (146b) and the third region (147b), and can be electrically connected to the connection electrode (138) located in the first pixel region (PCA1) through a contact hole (53) penetrating the fifth insulating layer (115). The connection electrode (138) of the first pixel region (PCA1) can be electrically connected to the second-first initialization voltage line (VL21) through the contact hole (48a). Accordingly, the second-first vertical initialization voltage line (VL21v) is electrically connected to the second-first initialization voltage line (VL21), and the second-first initialization voltage line (VL21) can have a mesh structure in the display region (DA).

[0193] A common voltage line (EL) may be arranged in the second pixel area (PCA2) and the third pixel area (PCA3). The common voltage line (EL) may extend in the y direction and include a first area (145c) having a first width in the x direction, a second area (146c) having a second width narrower than the first width, and a third area (147c) having the first width. The first area (145c), the second area (146c), and the third area (147c) may overlap a data line (DL) located in the third pixel area (PCA3). The first area (145c) may overlap a first gate line (GWL), a third gate line (VRL), and a third gate line (GRL) located in the second pixel area (PCA2) and the third pixel area (PCA3). The third region (147c) may overlap the first transistor (T1), the first capacitor (C1), the second capacitor (C2), the fourth gate line (EML), the fifth gate line (EMBL), the second gate line (GIL), the first initialization voltage line (VL1), the second-first initialization voltage line (VL21), and the second-second initialization voltage line (VL22) located in the first pixel region (PCA1) and the second pixel region (PCA2).

[0194] A vertical reference voltage line (VRLv) may be arranged in the third pixel area (PCA3). The vertical reference voltage line (VRLv) may include a main line (VRLvm) extending in the y direction and a first area (145d), a second area (146d), and a third area (147d) protruding and extending from the main line (VRLvm) in the x direction. The first area (145d) may overlap the first gate line (GWL) and the third gate line (VRL). An extension of the first area (145d) may overlap the first initialization voltage line (VL1), the second-first initialization voltage line (VL21), and the second-second initialization voltage line (VL22) located in a pixel area adjacent to the third pixel area (PCA3) in the y direction. The second region (146d) may overlap the first transistor (T1), the first capacitor (C1), and the second capacitor (C2). The third region (147d) may overlap the first initialization voltage line (VL1), the second-first initialization voltage line (VL21), and the second-second initialization voltage line (VL22). An extension of the third region (147d) may overlap the first gate line (GWL) and the reference voltage line (VRL) located in a pixel region adjacent to the third pixel region (PCA3) in the y direction. The first region (145d) of the vertical reference voltage line (VRLv) may be electrically connected to the connection electrode (132) through a contact hole (54) penetrating the fifth insulating layer (115). Accordingly, the vertical reference voltage line (VRLv) is electrically connected to the reference voltage line (VRL), and the reference voltage line (VRL) may have a mesh structure in the display area (DA).

[0195] The corresponding connection electrodes (121, 122, 131, 132, 133, 134, 135, 136, 137, 138, 141) of each of the first pixel area (PCA1), the second pixel area (PCA2), and the third pixel area (PCA3) may have different shapes depending on the positions of the wires arranged in the pixel area.

[0196] A sixth insulating layer (116) is arranged over a fifth conductive layer (115), and an organic light-emitting diode (OLED) as a display element may be arranged over the sixth insulating layer (116) as shown in Fig. 18. Fig. 18 illustrates organic light-emitting diodes arranged on the unit pixel area illustrated in Fig. 17a.

[0197] In one embodiment, the first insulating layer (111), the second insulating layer (112), the third insulating layer (113), and the fourth insulating layer (114) may be inorganic insulating layers, and the fifth insulating layer (115) and the sixth insulating layer (116) may be organic insulating layers. The inorganic insulating layer may include an inorganic material including an oxide or a nitride. For example, the inorganic insulating layer may include at least one of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The organic insulating layer may include an organic material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0198] FIG. 19 illustrates organic light-emitting diodes, which are part of the pixels illustrated in FIG. 18. The organic light-emitting diode (OLED) may include a pixel electrode (211), a counter electrode (215), and an emission layer (213a) between the pixel electrode (211) and the counter electrode (215). FIG. 19 illustrates a pixel electrode (211) and an emission layer (213a) of a first pixel (PX1), a pixel electrode (211) and an emission layer (213b) of a second pixel (PX2), and a pixel electrode (211) and an emission layer (213c) of a third pixel (PX3). FIGS. 20 and 21 illustrate an organic light-emitting diode (OLED) including a pixel electrode (211), an emission layer (213a), and an emission layer (215) of a first pixel (PX1).

[0199] The pixel electrode (211) can be connected to the pixel circuit by being electrically connected to the lower connection electrode through the contact hole (61) of the sixth insulating layer (116). Referring to FIG. 19, the pixel electrode (211) of the first pixel (PX1) can be electrically connected to the first transistor (T1) by being electrically connected to the connection electrode (141) arranged in the first pixel area (PCA1). The pixel electrode (211) of the second pixel (PX2) can be electrically connected to the first transistor (T1) by being electrically connected to the connection electrode (141) arranged in the second pixel area (PCA2). The pixel electrode (211) of the third pixel (PX3) can be electrically connected to the first transistor (T1) by being electrically connected to the connection electrode (141) arranged in the third pixel area (PCA3).

[0200] In one embodiment, the pixel electrode (211) of the first pixel (PX1) and the pixel electrode (211) of the second pixel (PX2) may overlap the pixel circuit of the first pixel area (PCA1) and be arranged adjacent to each other in the y direction. The pixel electrode (211) of the third pixel (PX3) may overlap the pixel circuits of the second pixel area (PCA2) and the third pixel area (PCA3). The pixel electrode (211) of the first pixel (PX1) and the pixel electrode (211) of the second pixel (PX2) may each have an approximately square shape, and the pixel electrode (211) of the third pixel (PX3) may have a rectangular shape with a long side in the y direction.

[0201] A pixel definition layer (117) covering the edge of the pixel electrode (211) may be disposed on the sixth insulating layer (116). An opening (117OP) exposing a portion of the pixel electrode (211) and defining a light-emitting area may be defined in the pixel definition layer (117). The pixel definition layer (115) may be a single-layer or multi-layer organic insulating layer and / or inorganic insulating layer.

[0202] The counter electrode (215) can be formed integrally to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area (DA).

[0203] Fig. 22 is a schematic diagram of an equivalent circuit (PCa) of a pixel (PXa) according to one embodiment. Figs. 23 and 24 are schematic diagrams illustrating signals for explaining the operation of the pixel illustrated in Fig. 22.

[0204] The pixel (PXa) illustrated in FIG. 22 differs from the pixel (PX) illustrated in FIG. 4 in that at least the gate of the seventh transistor (T7) is connected to the sixth gate line (GBL) and supplied with the sixth gate signal (GB). In the display device (10) illustrated in FIG. 2, sixth gate lines (GBL) are further arranged in the pixel portion (11), and the gate driving circuit (13) can further generate the sixth gate signal (GB).

[0205] As illustrated in FIGS. 23 and 24, the pixel (PXa) can be driven for one first scan period (AS) and one second scan period (SS) during one frame. Hereinafter, the differences from the operation of the pixel (PX) described in FIGS. 4 to 7 will be described.

[0206] As illustrated in Fig. 23, the first scan period (AS) may include a first non-emission period (ND1) in which the pixel (PXa) does not emit light and a first emission period (DD1) in which the pixel (PXa) emits light. The first non-emission period (ND1) may include a first period (P1), a second period (P2), a third period (P3), and a fourth period (P4).

[0207] In the first period (P1), a second gate signal (GI) of an on voltage may be supplied (applied) to the second gate line (GIL), and a sixth gate signal (GB) of an on voltage may be supplied to the sixth gate line (GBL). In addition, a third gate signal (GR) of an on voltage may be supplied to the third gate line (GRL). The fourth transistor (T4) may be turned on by the second gate signal (GI), and the third transistor (T3) may be turned on by the third gate signal (GR). The second terminal of the first transistor (T1) may be initialized to the first initialization voltage (Vint) by the turned-on fourth transistor (T4). The first gate of the first transistor (T1) may be initialized to the reference voltage (Vref) by the turned-on third transistor (T3). The seventh transistor (T7) is turned on by the sixth gate signal (GB), and the pixel electrode of the organic light-emitting diode (OLED) can be initialized to the second initialization voltage (Vaint) by the turned-on seventh transistor (T7).

[0208] In the second period (P2), a third gate signal (GR) of an on voltage may be supplied to the third gate line (GRL), and a fourth gate signal (EM) may be supplied to the fourth gate line (EML). The third transistor (T3) may be turned on by the third gate signal (GR), and the fifth transistor (T5) may be turned on by the fourth gate signal (EM). Accordingly, a voltage corresponding to the threshold voltage (Vth) of the first transistor (T1) may be stored in the first capacitor (C1), so that the threshold voltage (Vth) of the first transistor (T1) may be compensated.

[0209] In the third period (P3), a first gate signal (GW) of an on voltage can be supplied to the first gate line (GWL). The second transistor (T2) is turned on by the first gate signal (GW). The turned-on second transistor (T2) can transmit the data signal (Vdata) from the data line (DL) to the first gate of the first transistor (T1). Accordingly, the first capacitor (C1) can be charged with a voltage corresponding to the threshold voltage (Vth) of the first transistor (T1) and the data signal (Vdata).

[0210] In the fourth period (P4), a second gate signal (GI) of an on voltage may be supplied (applied) to the second gate line (GIL), and a sixth gate signal (GB) of an on voltage may be supplied to the sixth gate line (GBL). The fourth transistor (T4) may be turned on by the second gate signal (GI), and a first initialization voltage (Vint) may be transmitted to the second terminal of the first transistor (T1) to the turned-on fourth transistor (T4). The seventh transistor (T7) may be turned on by the sixth gate signal (GB), and a second initialization voltage (Vaint) may be transmitted to a pixel electrode of an organic light-emitting diode (OLED) by the turned-on seventh transistor (T7).

[0211] In the first emission period (DD1), a fourth gate signal (EM) of an on voltage may be supplied to a fourth gate line (EML), and a fifth gate signal (EMB) of an on voltage may be supplied to a fifth gate line (EMBL). The fifth transistor (T5) is turned on by the fourth gate signal (EM), and a first driving voltage (ELVDD) may be supplied to a first terminal of the first transistor (T1) by the turned-on fifth transistor (T5). The sixth transistor (T6) is turned on by the fifth gate signal (EMB), and the first transistor (T1) outputs a driving current having a magnitude corresponding to a voltage corresponding to a data signal (Vdata) stored in the first capacitor (C1), and the organic light-emitting diode (OLED) can emit light with a brightness corresponding to the magnitude of the driving current.

[0212] As illustrated in Fig. 24, the second scan period (SS) may include a second non-emission period (ND2) in which the pixel (PXa) does not emit light and a second emission period (DD2) in which the pixel (PXa) emits light. The second non-emission period (ND2) may include a fifth period (P5) and a sixth period (P6). The second scan period (SS) may not include a compensation period corresponding to the second period (P2) of the first scan period (AS) and a writing period corresponding to the third period (P3).

[0213] In the fifth period (P5), a sixth gate signal (GB) of a voltage can be supplied to the sixth gate line (GBL). The seventh transistor (T7) is turned on by the sixth gate signal (GB), and the pixel electrode of the organic light-emitting diode (OLED) can be initialized to the second initialization voltage (Vaint) by the turned-on seventh transistor (T7).

[0214] In the sixth period (P6), a sixth gate signal (GB) of a voltage can be supplied to the sixth gate line (GBL). The seventh transistor (T7) is turned on by the sixth gate signal (GB), and the pixel electrode of the organic light-emitting diode (OLED) can be initialized to the second initialization voltage (Vaint) by the turned-on seventh transistor (T7).

[0215] In the second emission period (DD2), a fourth gate signal (EM) of an on voltage may be supplied to the fourth gate line (EML), and a fifth gate signal (EMB) of an on voltage may be supplied to the fifth gate line (EMBL). The fifth transistor (T5) is turned on by the fourth gate signal (EM), and a first driving voltage (ELVDD) may be supplied to the first terminal of the first transistor (T1) by the turned-on fifth transistor (T5). The sixth transistor (T6) is turned on by the fifth gate signal (EMB), and the first transistor (T1) outputs a driving current having a magnitude corresponding to the voltage stored in the first capacitor (C1), for example, a data signal (Vdata), and the organic light-emitting diode (OLED) may emit light with a brightness corresponding to the magnitude of the driving current (Id). The data signal (Vdata) stored in the first capacitor (C1) during the second emission period (DD2) may be a data signal supplied to the pixel and maintained during the third period (P3) of the first scan period (AS).

[0216] In each of the first emission period (DD1) and the second emission period (DD2), the timing of applying the turn-on voltage of the fifth gate signal (EMB) may be delayed by a predetermined time (DT) (e.g., a pre-designated or selectable time) from the timing of applying the turn-on voltage of the fourth gate signal (EM). In addition, the embodiments illustrated in FIGS. 22 to 24 perform the initialization of the pixel electrodes in the fifth period (P5) and the sixth period (P6), which correspond to the periods before and after the compensation period of the first scan period (AS) in the second scan period (SS), thereby minimizing the luminance deviation according to the driving speed even if one frame includes one or more second scan periods (SS). In addition, by performing the initialization of the driving transistor only in the first scan period (AS), the occurrence of a stain (mura) caused by a voltage drop of the first initialization voltage of the screen can be minimized.

[0217] In the embodiments illustrated in FIGS. 22 to 24, during one frame, the first gate signal (GW), the second gate signal (GI), and the third gate signal (GR) may be supplied only during the first scan period (AS), and the sixth gate signal (GB) may be supplied during the first scan period (AS) and the second scan period (SS). The fourth gate signal (EM) and the fifth gate signal (EMB) may be supplied during the first scan period (AS) and the second scan period (SS). That is, during one frame, the cycles of the first gate signal (GW), the second gate signal (GI), and the third gate signal (GR) may be one cycle, and the cycles of the fourth gate signal (EM), the fifth gate signal (EMB), and the sixth gate signal (GB) may be two cycles.

[0218] In another embodiment, the fourth period (P4) of the first scan period (AS) and the sixth period (P6) of the second scan period (SS) may be omitted.

[0219] Although not shown, in another embodiment, the second capacitor (C2) may be connected to a conductive line to which a voltage is applied at one-cycle intervals during one frame, in addition to the reference voltage line (VRL), or to a conductive line to which there is no voltage fluctuation during one frame. For example, the second capacitor (C2) may be connected between the first initialization voltage line (VL1) and the second node (N2), or between the second initialization voltage line (VL2) and the second node (N2). Or, as another example, as shown in FIG. 25, the second capacitor (C2) may be connected between the common voltage line (EL) to which the second driving voltage (ELVSS) is applied and the second node (N2).

[0220] Figures 26 and 27 are schematic diagrams of equivalent circuits (PCb and PCc) of pixels (PXb and PXc) according to one embodiment.

[0221] The pixel (PXb) illustrated in FIG. 26 differs from the pixel (PX) illustrated in FIG. 4 in that at least a second capacitor (C2) is connected between the driving voltage line (PL) and the second node (N2), and a third capacitor (C3) is added between the second node (N2) and the third node (N3). A first electrode of the third capacitor (C3) may be connected to the second node (N2), and a second electrode may be connected to the third node (N3). A second electrode of the third capacitor (C3) may be disposed above the first electrode of the third capacitor (C3) and may be electrically connected to a pixel electrode of an organic light-emitting diode (OLED). In one embodiment, the first electrode of the third capacitor (C3) and the second electrode (C22, FIG. 20) of the second capacitor (C2) are arranged on the same layer, and the second electrode of the third capacitor (C3) may be a part of the semiconductor layer (the third semiconductor layer (ACT3) of FIG. 13) of the sixth transistor (T6).

[0222] Even if the voltage of the second node (N2) fluctuates according to the variation of the first driving voltage (ELVDD), the voltage of the second node (N2) can be compensated by the parasitic capacitor (Coled) of the organic light-emitting diode (OLED) by placing the third capacitor (C3) between the second node (N2) and the third node (N3).

[0223] The pixel (PXb) illustrated in FIG. 26 can operate in a first scan period (AS) according to FIG. 6 and one or more second scan periods (SS) according to FIG. 7 during one frame.

[0224] The pixel (PXc) illustrated in FIG. 27 differs from the pixel (PXb) illustrated in FIG. 25 in that at least the gate of the seventh transistor (T7) is connected to the sixth gate line (GBL) and supplied with the sixth gate signal (GB). The pixel (PXc) illustrated in FIG. 27 can operate in the first scan period (AS) according to FIG. 23 and one or more second scan periods (SS) according to FIG. 24 during one frame.

[0225] Figures 28a to 29b are schematic cross-sectional views showing the structure of a display element according to one embodiment.

[0226] As a display element according to one embodiment, an organic light-emitting diode (OLED) may include a pixel electrode (211), a counter electrode (215), and an intermediate layer (213) between the pixel electrode (211) (first electrode, anode) and the counter electrode (215) (second electrode, cathode).

[0227] The pixel electrode (211) may include a light-transmitting conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The pixel electrode (211) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. For example, the pixel electrode (211) may have a three-layer structure of ITO / Ag / ITO.

[0228] The counter electrode (215) may be disposed on the intermediate layer (213). The counter electrode (215) may include a metal, alloy, electrically conductive compound, or any combination thereof having a low work function. For example, the counter electrode (205) may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The counter electrode (205) may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0229] The intermediate layer (213) may include a polymer or low-molecular organic material that emits light of a predetermined color. In addition to various organic materials, the intermediate layer (213) may also include metal-containing compounds such as organometallic compounds and inorganic materials such as quantum dots.

[0230] In one embodiment, the intermediate layer (213) may include a light-emitting layer and a first functional layer and a second functional layer below and above the light-emitting layer, respectively. The first functional layer may include, for example, a hole transport layer (HTL) or a hole transport layer and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer or the second functional layer may be omitted. The first functional layer and the second functional layer may be formed integrally to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area (DA).

[0231] In one embodiment, the intermediate layer (213) may include two or more emitting units sequentially stacked between the pixel electrode (211) and the counter electrode (215), and a charge generation layer (CGL) disposed between the two emitting units. When the intermediate layer (213) includes the emitting units and the charge generation layer (CGL), the organic light-emitting diode (OLED) may be a tandem light-emitting element. The organic light-emitting diode (OLED) may improve color purity and luminous efficiency by having a stacked structure of a plurality of emitting units.

[0232] One light-emitting unit may include a light-emitting layer and a first functional layer and a second functional layer above and below the light-emitting layer, respectively. The charge generation layer (CGL) may include a negative charge generation layer and a positive charge generation layer. The light-emitting efficiency of an organic light-emitting diode (OLED), which is a tandem light-emitting device having a plurality of light-emitting layers, can be further increased by the negative charge generation layer and the positive charge generation layer.

[0233] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0234] In one embodiment, as illustrated in FIG. 28A, an organic light-emitting diode (OLED) may include a first light-emitting unit (EU1) including a first light-emitting layer (EML1) that is sequentially stacked, and a second light-emitting unit (EU2) including a second light-emitting layer (EML2). A charge generation layer (CGL) may be provided between the first light-emitting unit (EU1) and the second light-emitting unit (EU2). For example, the organic light-emitting diode (OLED) may include a pixel electrode (211), a first light-emitting layer (EML1), a charge generation layer (CGL), a second light-emitting layer (EML2), and a counter electrode (215), which are sequentially stacked. A first functional layer and a second functional layer may be included below and above the first light-emitting layer (EML1), respectively. A first functional layer and a second functional layer may be included below and above the second light-emitting layer (EML2), respectively. The first light-emitting layer (EML1) may be a blue light-emitting layer, and the second light-emitting layer (EML2) may be a yellow light-emitting layer.

[0235] In one embodiment, as illustrated in FIG. 28b, an organic light-emitting diode (OLED) may include a first light-emitting unit (EU1) including a first light-emitting layer (EML1), a third light-emitting unit (EU3), and a second light-emitting unit (EU2) including a second light-emitting layer (EML2). A first charge generation layer (CGL1) may be provided between the first light-emitting unit (EU1) and the second light-emitting unit (EU2), and a second charge generation layer (CGL2) may be provided between the second light-emitting unit (EU2) and the third light-emitting unit (EU3). For example, an organic light-emitting diode (OLED) may include a pixel electrode (211), a first light-emitting layer (EML1), a first charge generation layer (CGL1), a second light-emitting layer (EML2), a second charge generation layer (CGL2), the first light-emitting layer (EML1), and a counter electrode (215) that are sequentially stacked. A first functional layer and a second functional layer may be included below and above the first light-emitting layer (EML1), respectively. A first functional layer and a second functional layer may be included below and above the second light-emitting layer (EML2), respectively. The first light-emitting layer (EML1) may be a blue light-emitting layer, and the second light-emitting layer (EML2) may be a yellow light-emitting layer.

[0236] In one embodiment, the organic light emitting diode (OLED) may further include a third light emitting layer (EML3) and / or a fourth light emitting layer (EML4) that directly contacts, in addition to the second light emitting layer (EML2), the second light emitting unit (EU2) below and / or above the second light emitting layer (EML2). Here, direct contact may mean that no other layer is disposed between the second light emitting layer (EML2) and the third light emitting layer (EML3) and / or between the second light emitting layer (EML2) and the fourth light emitting layer (EML4). The third light emitting layer (EML3) may be a red light emitting layer, and the fourth light emitting layer (EML4) may be a green light emitting layer.

[0237] For example, as illustrated in FIG. 28c, an organic light-emitting diode (OLED) may include a pixel electrode (211), a first light-emitting layer (EML1), a first charge generation layer (CGL1), a third light-emitting layer (EML3), a second light-emitting layer (EML2), a second charge generation layer (CGL2), a first light-emitting layer (EML1), and a counter electrode (215) that are sequentially stacked. As another example, as illustrated in FIG. 28d, an organic light-emitting diode (OLED) may include a pixel electrode (211), a first light-emitting layer (EML1), a first charge generation layer (CGL1), a third light-emitting layer (EML3), a second light-emitting layer (EML2), a fourth light-emitting layer (EML4), a second charge generation layer (CGL2), a first light-emitting layer (EML1), and a counter electrode (215) that are sequentially stacked.

[0238] Fig. 29a is a schematic cross-sectional view showing an example of the organic light-emitting diode of Fig. 28c, and Fig. 29b is a schematic cross-sectional view showing an example of the organic light-emitting diode of Fig. 28d.

[0239] Referring to FIG. 29a, an organic light-emitting diode (OLED) may include a first light-emitting unit (EU1), a second light-emitting unit (EU2), and a third light-emitting unit (EU3) that are sequentially stacked. A first charge generation layer (CGL1) may be provided between the first light-emitting unit (EU1) and the second light-emitting unit (EU2), and a second charge generation layer (CGL2) may be provided between the second light-emitting unit (EU2) and the third light-emitting unit (EU3). The first charge generation layer (CGL1) and the second charge generation layer (CGL2) may each include a negative charge generation layer (nCGL) and a positive charge generation layer (pCGL).

[0240] The first light-emitting unit (EU1) may include a blue light-emitting layer (BEML). The first light-emitting unit (EU1) may further include a hole injection layer (HIL) and a hole transport layer (HTL) between the pixel electrode (211) and the blue light-emitting layer (BEML). In one embodiment, a p-doped layer may further be included between the hole injection layer (HIL) and the hole transport layer (HTL). The p-doped layer may be formed by doping the hole injection layer (HIL) with a p-type doping material. In one embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue light-emitting layer (BEML) and the hole transport layer (HTL). The blue light auxiliary layer may increase the light output efficiency of the blue light-emitting layer (BEML). The blue light auxiliary layer may increase the light output efficiency of the blue light-emitting layer (BEML) by controlling a hole charge balance. The electron blocking layer may prevent electron injection into the hole transport layer (HTL). The buffer layer can compensate for the resonance distance according to the wavelength of light emitted from the light-emitting layer.

[0241] The second light-emitting unit (EU2) may include a yellow light-emitting layer (YEML) and a red light-emitting layer (REML) directly in contact with the yellow light-emitting layer (YEML) under the yellow light-emitting layer (YEML). The second light-emitting unit (EU2) may further include a hole transport layer (HTL) between the positive charge generation layer (pCGL) of the first charge generation layer (CGL1) and the red light-emitting layer (REML), and may further include an electron transport layer (ETL) between the yellow light-emitting layer (YEML) and the negative charge generation layer (nCGL) of the second charge generation layer (CGL2).

[0242] The third light-emitting unit (EU3) may include a blue light-emitting layer (BEML). The third light-emitting unit (EU3) may further include a hole transport layer (HTL) between the positive charge generation layer (pCGL) of the second charge generation layer (CGL2) and the blue light-emitting layer (BEML). The third light-emitting unit (EU3) may further include an electron transport layer (ETL) and an electron injection layer (EIL) between the blue light-emitting layer (BEML) and the counter electrode (215). The electron transport layer (ETL) may be a single layer or a multilayer. In one embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue light-emitting layer (BEML) and the hole transport layer (HTL). At least one of a hole blocking layer and a buffer layer may further be included between the blue light-emitting layer (BEML) and the electron transport layer (ETL). The hole blocking layer may prevent hole injection into the electron transport layer (ETL).

[0243] The organic light emitting diode (OLED) illustrated in FIG. 29b differs from the organic light emitting diode (OLED) illustrated in FIG. 29a in the stacked structure of the second light emitting unit (EU2), but otherwise has the same configuration. Referring to FIG. 29b, the second light emitting unit (EU2) may include a yellow light emitting layer (YEML), a red light emitting layer (REML) located below the yellow light emitting layer (YEML) and in direct contact with the yellow light emitting layer (YEML), and a green light emitting layer (GEML) located above the yellow light emitting layer (YEML) and in direct contact with the yellow light emitting layer (YEML). The second light-emitting unit (EU2) may further include a hole transport layer (HTL) between the positive charge generation layer (pCGL) of the first charge generation layer (CGL1) and the red light-emitting layer (REML), and may further include an electron transport layer (ETL) between the green light-emitting layer (GEML) and the negative charge generation layer (nCGL) of the second charge generation layer (CGL2).

[0244] Fig. 30 is a schematic cross-sectional view showing the structure of a pixel of a display device according to one embodiment.

[0245] Referring to FIG. 30, a display device may include a plurality of pixels. The plurality of pixels may include a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3). The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may each include a pixel electrode (211), a counter electrode (215), and an intermediate layer (213). In one embodiment, the first pixel (PX1) may be a red pixel, the second pixel (PX2) may be a green pixel, and the third pixel (PX3) may be a blue pixel. Here, the pixel includes an organic light-emitting diode (OLED) as a display element, and the organic light-emitting diode (OLED) of each pixel may be electrically connected to a pixel circuit.

[0246] The pixel electrode (211) can be independently provided for each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3).

[0247] The intermediate layer (213) of the organic light emitting diode (OLED) of each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may include a first light emitting unit (EU1), a second light emitting unit (EU2), which are sequentially stacked, and a charge generation layer (CGL) between the first light emitting unit (EU1) and the second light emitting unit (EU2). The charge generation layer (CGL) may include a negative charge generation layer (nCGL) and a positive charge generation layer (pCGL). The charge generation layer (CGL) may be a common layer formed continuously in the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3).

[0248] The first light emitting unit (EU1) of the first pixel (PX1) may include a hole injection layer (HIL), a hole transport layer (HTL), a red emission layer (REML), and an electron transport layer (ETL) sequentially stacked on the pixel electrode (201). The first light emitting unit (EU1) of the second pixel (PX2) may include a hole injection layer (HIL), a hole transport layer (HTL), a green emission layer (GEML), and an electron transport layer (ETL) sequentially stacked on the pixel electrode (211). The first light emitting unit (EU1) of the third pixel (PX3) may include a hole injection layer (HIL), a hole transport layer (HTL), a blue emission layer (BEML), and an electron transport layer (ETL) sequentially stacked on the pixel electrode (211). Each of the hole injection layer (HIL), hole transport layer (HTL) and electron transport layer (ETL) of the first light-emitting unit (EU1) may be a common layer formed continuously in the first pixel (PX1), the second pixel (PX2) and the third pixel (PX3).

[0249] The second light-emitting unit (EU2) of the first pixel (PX1) may include a hole transport layer (HTL), an auxiliary layer (AXL), a red light-emitting layer (REML), and an electron transport layer (ETL) sequentially stacked on a charge generation layer (CGL). The second light-emitting unit (EU2) of the second pixel (PX2) may include a hole transport layer (HTL), a green light-emitting layer (GEML), and an electron transport layer (ETL) sequentially stacked on a charge generation layer (CGL). The second light-emitting unit (EU2) of the third pixel (PX3) may include a hole transport layer (HTL), a blue light-emitting layer (BEML), and an electron transport layer (ETL) sequentially stacked on a charge generation layer (CGL). Each of the hole transport layer (HTL) and electron transport layer (ETL) of the second light-emitting units (EU1) may be a common layer formed continuously in the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3). In one embodiment, at least one of a hole blocking layer and a buffer layer may be further included between the light-emitting layer and the electron transport layer (ETL) in the second light-emitting unit (EU2) of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3).

[0250] The thickness (H1) of the red emitting layer (REML), the thickness (H2) of the green emitting layer (GEML), and the thickness (H3) of the blue emitting layer (BEML) can be determined according to the resonance distance. The auxiliary layer (AXL) is an additional layer added to adjust the resonance distance and may include a resonance auxiliary material. For example, the auxiliary layer (AXL) and the hole transport layer (HTL) may include the same material.

[0251] In FIG. 30, the auxiliary layer (AXL) is provided only in the first pixel (PX1), but the embodiment of the present invention is not limited thereto. For example, the auxiliary layer (AXL) may be provided in at least one of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) in order to match the resonance distances of each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3).

[0252] The display device may further include a capping layer (217) disposed on the outer side of the counter electrode (215). The capping layer (217) may serve to improve luminous efficiency by the principle of constructive interference. As a result, the light extraction efficiency of the organic light-emitting diode (OLED) may be increased, thereby improving the luminous efficiency of the organic light-emitting diode (OLED).

[0253] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and variations of the embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. In a display device including a plurality of pixels, Each of the above plurality of pixels, A first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; A second transistor connected to the first gate of the first transistor and the data line; A third transistor connected to the first gate of the first transistor and the first voltage line; A fourth transistor connected to the first terminal of the first transistor and the second voltage line; A first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and A second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor; A display device in which the first electrode of the second capacitor and the first voltage line are arranged on the same layer.

2. In paragraph 1, A display device, wherein the second electrode of the second capacitor is connected to the second gate of the first transistor.

3. In paragraph 1, The first electrode of the above first capacitor includes an upper electrode and a lower electrode, The upper electrode and the first gate of the first transistor are arranged on the same layer, The lower electrode and the first electrode of the second capacitor are arranged on the same layer, The display device, wherein the lower electrode is connected to the upper electrode.

4. In paragraph 1, A display device, wherein during one frame, a gate signal is supplied once to the gate of the third transistor, and a gate signal is supplied twice or more to the gate of the fourth transistor.

5. In the first paragraph, each of the plurality of pixels, A fifth transistor connected to the second terminal of the first transistor and the third voltage line; A sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and Further comprising a seventh transistor connected to the light emitting diode and the fourth voltage line; A display device in which the same gate signal is supplied to the gate of the fifth transistor and the gate of the seventh transistor.

6. In paragraph 5, A display device, wherein the timing at which the gate signal is applied to the gate of the fourth transistor is earlier than the timing at which the gate signal is applied to the gate of the sixth transistor.

7. In the first paragraph, each of the plurality of pixels, A fifth transistor connected to the second terminal of the first transistor and the third voltage line; A sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and Further comprising a seventh transistor connected to the light emitting diode and the fourth voltage line; A display device, wherein the gate signal supplied to the gate of the fifth transistor and the gate signal supplied to the gate of the seventh transistor are different.

8. In paragraph 7, A display device, wherein during one frame, a gate signal is supplied once to the gate of the fifth transistor, and a gate signal is supplied twice or more to the gate of the seventh transistor.

9. In paragraph 1, A frame includes a first scan period including a first non-emission period and a first emission period, and a second scan period including a second non-emission period and a second emission period, Each of the above plurality of pixels, Further comprising a fifth transistor connected to the second terminal of the first transistor and the third voltage line; The above first non-luminous period is, A writing period during which a first gate signal is applied to the gate of the second transistor; Before the above-mentioned writing period, a first period in which a second gate signal is applied to the gate of the fifth transistor and a third gate signal is applied to the gate of the third transistor; and A display device including a second period during which the third gate signal is applied to the gate of the third transistor and the fourth gate signal is applied to the gate of the fourth transistor, between the writing period and the first period.

10. In the above paragraph 9, The above second non-luminous period is, A display device, comprising a third period in which a second gate signal is applied to the gate of the fifth transistor.

11. In a display device including a plurality of pixels, Each of the above plurality of pixels, A first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; A second transistor connected to the first gate of the first transistor and the data line; A third transistor connected to the first gate of the first transistor and the first voltage line; A fourth transistor connected to the first terminal of the first transistor and the second voltage line; A fifth transistor connected to the second terminal of the first transistor and the light-emitting diode; A first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and A second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor; A display device, wherein the timing at which a gate signal is applied to the gate of the fourth transistor is earlier than the timing at which a gate signal is applied to the gate of the fifth transistor.

12. In paragraph 11, A display device, wherein the second electrode of the second capacitor is connected to the second gate of the first transistor.

13. In paragraph 11, The first electrode of the above first capacitor includes an upper electrode and a lower electrode, The upper electrode and the first gate of the first transistor are arranged on the same layer, The lower electrode and the first electrode of the second capacitor are arranged on the same layer, The display device, wherein the lower electrode is connected to the upper electrode.

14. In paragraph 11, A display device, wherein during one frame, a gate signal is supplied once to the gate of the third transistor, and a gate signal is supplied twice or more to the gate of the fourth transistor.

15. In the 11th paragraph, each of the plurality of pixels, A sixth transistor connected to the second terminal of the first transistor and the third voltage line; and Further comprising a seventh transistor connected to the light emitting diode and the fourth voltage line; A display device in which the same gate signal is supplied to the gate of the sixth transistor and the gate of the seventh transistor.

16. In the 11th paragraph, each of the plurality of pixels, A sixth transistor connected to the second terminal of the first transistor and the third voltage line; and Further comprising a seventh transistor connected to the light emitting diode and the fourth voltage line; A display device, wherein the gate signal supplied to the gate of the sixth transistor and the gate signal supplied to the gate of the seventh transistor are different.

17. In paragraph 16, A display device, wherein during one frame, a gate signal is supplied once to the gate of the sixth transistor, and a gate signal is supplied twice or more to the gate of the seventh transistor.

18. In a display device including a plurality of pixels, Each of the above plurality of pixels, A first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; A second transistor connected to the first gate of the first transistor and the data line; A third transistor connected to the first gate of the first transistor and the first voltage line; A fourth transistor connected to the first terminal of the first transistor and the second voltage line; A first capacitor including a first electrode connected to a first gate of the first transistor and a second electrode connected to a second terminal of the first transistor; A second capacitor including a first electrode connected to the second voltage line and a second electrode connected to the second terminal of the first transistor; and A display device comprising a third capacitor including a first electrode connected to a second terminal of the first transistor and a second electrode connected to one electrode of the light-emitting diode.

19. In paragraph 18, each of the plurality of pixels, A fifth transistor connected to the second terminal of the first transistor and the third voltage line; A sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and Further comprising a seventh transistor connected to the light emitting diode and the fourth voltage line; The same gate signal is supplied to the gate of the fifth transistor and the gate of the seventh transistor. A display device, wherein the timing at which the gate signal is applied to the gate of the fourth transistor is earlier than the timing at which the gate signal is applied to the gate of the sixth transistor.

20. In the first paragraph, each of the plurality of pixels, A fifth transistor connected to the second terminal of the first transistor and the third voltage line; A sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and Further comprising a seventh transistor connected to the light emitting diode and the fourth voltage line; The gate signal supplied to the gate of the fifth transistor and the gate signal supplied to the gate of the seventh transistor are different, A display device, wherein the timing at which the gate signal is applied to the gate of the fourth transistor is earlier than the timing at which the gate signal is applied to the gate of the sixth transistor.

21. In a display device including a plurality of pixels, Each of the above plurality of pixels, A first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; A second transistor connected to the first gate of the first transistor and the data line; A third transistor connected to the first gate of the first transistor and the first voltage line; A fourth transistor connected to the first terminal of the first transistor and the second voltage line; A fifth transistor connected to the second terminal of the first transistor and the first electrode of the light-emitting diode; A first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and A display device comprising a second capacitor including a first electrode connected to a second terminal of the first transistor and a second electrode connected to a second electrode of the light-emitting diode.

22. In paragraph 21, A display device, wherein the first electrode of the second capacitor is connected to the second gate of the first transistor.

23. In paragraph 21, A display device, wherein the first capacitor includes an upper electrode disposed on the same layer as the first gate of the first transistor and a lower electrode disposed on the same layer as the first electrode of the second capacitor and connected to the upper electrode.

24. A display device in claim 21, wherein during one frame, a gate signal is supplied to the gate of the third transistor once, and a gate signal is supplied to the gate of the fourth transistor twice or more.

25. In paragraph 21, each of the plurality of pixels, A sixth transistor connected to the second terminal of the first transistor and the third voltage line; and Further comprising a seventh transistor connected to the first electrode of the light-emitting diode and the fourth voltage line; A display device in which the same gate signal is supplied to the gate of the fifth transistor and the gate of the seventh transistor.

26. In paragraph 21, A display device, wherein the timing at which a gate signal is applied to the gate of the fourth transistor is earlier than the timing at which a gate signal is applied to the gate of the fifth transistor.

27. In paragraph 21, each of the plurality of pixels, A sixth transistor connected to the second terminal of the first transistor and the third voltage line; and Further comprising a seventh transistor connected to the first electrode of the light-emitting diode and the fourth voltage line; A display device, wherein the gate signal supplied to the gate of the sixth transistor and the gate signal supplied to the gate of the seventh transistor are different.

28. In paragraph 27, A display device, wherein during one frame, a gate signal is supplied once to the gate of the sixth transistor, and a gate signal is supplied twice or more to the gate of the seventh transistor.

29. In paragraph 21, A frame includes a first scan period including a first non-emission period and a first emission period, and a second scan period including a second non-emission period and a second emission period, Each of the above plurality of pixels, Further comprising a sixth transistor connected to the second terminal of the first transistor and the third voltage line; The above first non-luminous period is, A writing period during which a first gate signal is applied to the gate of the second transistor; Before the above-mentioned writing period, a first period in which a second gate signal is applied to the gate of the sixth transistor and a third gate signal is applied to the gate of the third transistor; and A display device including a second period during which the third gate signal is applied to the gate of the third transistor and the fourth gate signal is applied to the gate of the fourth transistor, between the writing period and the first period.

30. In the above paragraph 29, The above second non-luminous period is, A display device, comprising a third period in which a second gate signal is applied to the gate of the sixth transistor.

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