Display substrate and display device

Abstract

A display substrate (100) and a display device. The display substrate (100) comprises a shift register (120), comprising an input circuit (121), an output circuit (122), a first output pull-down circuit (124), and a second output pull-down circuit (129), wherein the input circuit (121) is configured to respond to a first driving signal on a control end of the input circuit (121) so as to write an input signal on an input end of the input circuit (121) into a first node (N1); the output circuit (122) is configured to respond to a signal on the first node (N1) so as to output a clock signal as a gate driving signal by means of an output end of the output circuit (122); an input end of the first output pull-down circuit (124) and an input end of the second output pull-down circuit (129) are separately connected to a first power supply voltage line (141); the first output pull-down circuit (124) is configured to reduce a fall time of a gate driving signal at a first end of a gate line by means of a first power supply voltage; the second output pull-down circuit (129) is configured to reduce a fall time of a gate driving signal at a second end of the gate line by means of the first power supply voltage. The display substrate (100) can reduce the bezel width while achieving a high resolution and a high refresh rate.

Description

Display substrate and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, the market has placed higher demands on low-cost, narrow-frame, and lightweight designs for display devices. Against this backdrop, Gate Driver on Array (GOA) technology for display substrates has emerged and has become a research hotspot for major manufacturers.

[0003] GOA technology integrates the gate driver circuit onto the display substrate with the pixel array. This allows the gate driver circuit to directly provide gate drive signals to the pixel array, eliminating the need for additional gate driver chips and corresponding binding structures. This reduces costs and border widths. Typically, GOA technology uses multiple cascaded shift registers to enable pixel arrays row by row, enabling display products to display colorful images.

[0004] Summary of the Invention

[0005] The embodiment of the present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a shift register, a clock signal line and a first power supply voltage line arranged on the base substrate, wherein the clock signal line is configured to provide a clock signal to the shift register, and the first power supply voltage line is configured to provide a first power supply voltage to the shift register; the shift register includes an input circuit, an output circuit, and a first output pull-down circuit, wherein the input circuit includes a control terminal, an input terminal and an output terminal, and the output circuit includes a control terminal, an input terminal and an output terminal, the output terminal of the input circuit and the control terminal of the output circuit are connected to a first node, and the input terminal of the output circuit is connected to the clock signal line; the input circuit is configured to respond to the first node on the control terminal of the input circuit. The first output pull-down circuit includes a control terminal, an input terminal, and an output terminal. The input terminal of the first output pull-down circuit is connected to a first power supply voltage line, and the output terminal of the first output pull-down circuit is connected to the output terminal of the output circuit. The first output pull-down circuit is configured to respond to a second drive signal at the control terminal of the first output pull-down circuit to reduce the fall time of the gate drive signal at the output terminal of the output circuit via the first power supply voltage. Thus, by reducing the fall time of the gate drive signal output by a single shift register, the display substrate can further reduce costs and border width by using a GOA circuit with an odd-even cross drive method while ensuring a higher resolution and refresh rate of the display substrate, making the product more competitive in the market.

[0006] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate and a shift register, a clock signal line, and a first power supply voltage line arranged on the base substrate, wherein the clock signal line is configured to provide a clock signal to the shift register, and the first power supply voltage line is configured to provide a first power supply voltage to the shift register; the shift register comprises an input circuit, an output circuit, and a first output pull-down circuit, the input circuit comprises a control terminal, an input terminal, and an output terminal, the output circuit comprises a control terminal, an input terminal, and an output terminal, the output terminal of the input circuit and the control terminal of the output circuit are connected to a first node, and the input terminal of the output circuit is connected to the clock signal line; the input circuit is configured to respond to a first drive signal on the control terminal of the input circuit The input signal on the input terminal of the input circuit is written into the first node, and the output circuit is configured to respond to the signal on the first node to output the clock signal on the clock signal line through the output terminal of the output circuit as a gate drive signal; the first output pull-down circuit includes a control terminal, an input terminal and an output terminal, the input terminal of the first output pull-down circuit is connected to the first power supply voltage line, the output terminal of the first output pull-down circuit is connected to the output terminal of the output circuit, and the first output pull-down circuit is configured to respond to the second drive signal on the control terminal of the first output pull-down circuit to reduce the falling time of the gate drive signal at the output terminal of the output circuit through the first power supply voltage, and the falling edge of the gate drive signal overlaps with the rising edge of the second drive signal.

[0007] For example, a display substrate provided by an embodiment of the present disclosure also includes: a gate line extending along a first direction; and a plurality of pixel rows arranged along a second direction intersecting the first direction, each of the pixel rows including a plurality of pixel units arranged along the first direction, the gate line being connected to the plurality of pixel units in the pixel row and providing the gate drive signal to the plurality of pixel units, the gate line including a first end and a second end located on both sides of the pixel row, the first end of the gate line being connected to the output end of the output circuit, the shift register also including a second output pull-down circuit including a control end, an input end and an output end, the input end of the second output pull-down circuit being connected to the first power supply voltage line, the second end of the gate line being connected to the output end of the second output pull-down circuit, the second output pull-down circuit being configured to respond to a third drive signal on the control end of the second output pull-down circuit, and to reduce the fall time of the gate drive signal at the second end through the first power supply voltage.

[0008] For example, in a display substrate provided by an embodiment of the present disclosure, the second driving signal and the third driving signal are the same.

[0009] For example, in a display substrate provided in an embodiment of the present disclosure, the base substrate includes a display area and a peripheral area, the peripheral area includes a first sub-peripheral area and a second sub-peripheral area located on both sides of the display area, the input circuit, the output circuit and the first output pull-down circuit of the shift register are located in one of the first sub-peripheral area and the second sub-peripheral area, and the second output pull-down circuit of the shift register is located in the other of the first sub-peripheral area and the second sub-peripheral area.

[0010] For example, in a display substrate provided in an embodiment of the present disclosure, the display substrate includes M shift registers and M gate lines, the M shift registers respectively provide gate drive signals for the M gate lines, the i-th shift register provides a gate drive signal for the i-th gate line, i is a positive integer greater than or equal to 1 and less than or equal to M, the 2n+1th shift register among the M shift registers is located in the first sub-peripheral area, the 2n+2th shift register is located in the second sub-peripheral area, and n is an integer greater than or equal to 0.

[0011] For example, in a display substrate provided in an embodiment of the present disclosure, the first sub-peripheral area includes a first register area and a 2j+1th register area, the second sub-peripheral area includes a second register area and a 2j+2th register area, the first register area and the second register area are relatively spaced apart, the 2j+1th register area and the 2j+2th register area are relatively spaced apart, the first register area is provided with an input circuit, an output circuit and a first output pull-down circuit of the first shift register and a second output pull-down circuit of the second shift register, and the second register area is provided with an input circuit, an output circuit and a first output pull-down circuit of the first shift register, and a second output pull-down circuit of the second shift register. The input circuit, output circuit and first output pull-down circuit of the second shift register and the second output pull-down circuit of the first shift register are set, the input circuit, output circuit and first output pull-down circuit of the 2j+1th shift register and the second output pull-down circuit of the 2j+2th shift register are set in the 2j+2th register area, and the input circuit, output circuit and first output pull-down circuit of the 2j+2th shift register and the second output pull-down circuit of the 2j+1th shift register are set, where j is a positive integer greater than or equal to 1.

[0012] For example, in a display substrate provided by an embodiment of the present disclosure, the first sub-peripheral area includes a first register area and a 2j+1th register area, the second sub-peripheral area includes a second register area and a 2j+2th register area, the first register area and the second register area are relatively spaced apart, the 2j+1th register area and the 2j+2th register area are relatively spaced apart, the first register area is provided with an input circuit, an output circuit, and a first output pull-down circuit of the first shift register, the second register area is provided with an input circuit, an output circuit, and a first output pull-down circuit of the second shift register, and the second output pull-down circuit of the first shift register, the 2j+1th register area is provided with an input circuit, an output circuit, and a first output pull-down circuit of the 2j+1th shift register, and the second output pull-down circuit of the 2jth shift register, the 2j+2th register area is provided with an input circuit, an output circuit, and a first output pull-down circuit of the 2j+2th shift register, and the second output pull-down circuit of the 2j+1th shift register, and j is a positive integer greater than or equal to 1.

[0013] For example, in the display substrate provided by an embodiment of the present disclosure, the second output pull-down circuit of the first shift register is arranged on a side of the second register region away from the 2j+2th shift register.

[0014] For example, in the display substrate provided in one embodiment of the present disclosure, the control end of the first output pull-down circuit of the mth shift register is electrically connected to the output end of the output circuit of the m+kth shift register, where m is a positive integer greater than or equal to 1, and k is a positive integer greater than or equal to 1.

[0015] For example, in a display substrate provided in an embodiment of the present disclosure, the display substrate includes p clock signal lines, and k=p / 2.

[0016] For example, in the display substrate provided in an embodiment of the present disclosure, the control end of the second output pull-down circuit of the mth shift register is electrically connected to the output end of the output circuit of the (m+k)th shift register.

[0017] For example, in a display substrate provided in an embodiment of the present disclosure, the input circuit includes an input transistor, the output circuit includes an output transistor, the first output pull-down circuit includes a first pull-down transistor, the input transistor includes a gate, a first electrode, and a second electrode, the output transistor includes a gate, a first electrode, and a second electrode, the first pull-down transistor includes a gate, a first electrode, and a second electrode, the second electrode of the input transistor and the gate of the output transistor are connected to a first node, the first electrode of the output transistor is connected to the clock signal line, the first electrode of the first pull-down transistor is connected to the first power supply voltage line, and the second electrode of the first pull-down transistor is connected to the second electrode of the output transistor.

[0018] For example, in the display substrate provided in one embodiment of the present disclosure, the 2n+1th shift register and the 2n+2th shift register are arranged with relative intervals; in the 2n+1th shift register, the orthographic projection of the first pull-down transistor on the base substrate is located on the side of the orthographic projection of the output transistor on the base substrate close to the 2n+2th shift register; in the 2n+2th shift register, the orthographic projection of the first pull-down transistor on the base substrate is located on the side of the orthographic projection of the output transistor on the base substrate close to the 2n+1th shift register.

[0019] For example, in the display substrate provided in one embodiment of the present disclosure, the second output pull-down circuit includes a second pull-down transistor, including a gate, a first electrode and a second electrode, the first electrode of the second pull-down transistor is connected to the first power supply voltage line, and the second electrode of the second pull-down transistor is connected to the second end of the gate line.

[0020] For example, in the display substrate provided in an embodiment of the present disclosure, the 2n+1th shift register and the 2n+2th shift register are arranged with relative intervals; the orthographic projection of the second pull-down transistor of the 2n+1th shift register on the substrate substrate is located between the orthographic projection of the output transistor of the 2n+2th shift register on the substrate substrate and the orthographic projection of the first pull-down transistor of the 2n+2th shift register on the substrate substrate; the orthographic projection of the second pull-down transistor of the 2n+2th shift register on the substrate substrate is located between the orthographic projection of the output transistor of the 2n+1th shift register on the substrate substrate and the orthographic projection of the first pull-down transistor of the 2n+1th shift register on the substrate substrate.

[0021] For example, in the display substrate provided in an embodiment of the present disclosure, the channel width-to-length ratio of the second pull-down transistor is greater than the channel width-to-length ratio of the first pull-down transistor.

[0022] For example, in a display substrate provided in an embodiment of the present disclosure, the channel width-to-length ratio of the first pull-down transistor is smaller than that of the output transistor, and the channel width-to-length ratio of the second pull-down transistor is larger than that of the output transistor.

[0023] For example, in a display substrate provided in an embodiment of the present disclosure, the shift register further includes a first control circuit, a second control circuit and a first noise reduction circuit, a second noise reduction circuit; the output end of the first control circuit and the output end of the second control circuit are connected to a second node, the control end and the input end of the first control circuit are connected to a second power supply voltage line, the input end of the second control circuit is connected to the first power supply voltage line, the control end of the second control circuit is connected to the first node, the first control circuit is configured to respond to a second power supply voltage on the second power supply voltage line, and pull up the potential of the second node through the second power supply voltage, and the second control circuit is configured to respond to a signal on the first node to pass The first noise reduction circuit and the second noise reduction circuit are connected to the second node, the input terminal of the first noise reduction circuit and the input terminal of the second noise reduction circuit are connected to the first power supply voltage line, the output terminal of the first noise reduction circuit is connected to the first node, and the output terminal of the second noise reduction circuit is connected to the output terminal of the output circuit. The first noise reduction circuit is configured to respond to a signal on the second node to reduce noise on the first node through the first power supply voltage, and the second noise reduction circuit is configured to respond to a signal on the second node to reduce noise on the output terminal of the output circuit through the first power supply voltage.

[0024] For example, in a display substrate provided in an embodiment of the present disclosure, the first control circuit includes a first control transistor, the second control circuit includes a second control transistor, the first noise reduction circuit includes the first noise reduction transistor, the second noise reduction circuit includes the second noise reduction transistor, the first control transistor includes a gate, a first electrode, and a second electrode, the second control transistor includes a gate, a first electrode, and a second electrode, the first noise reduction transistor includes a gate, a first electrode, and a second electrode, the second noise reduction transistor includes a gate, a first electrode, and a second electrode, the first electrode and the gate of the first control transistor are connected to the second power supply voltage line, the second electrode of the first control transistor and the second electrode of the second control transistor are connected to the second node, the gate of the second control transistor is connected to the first node, the first electrode of the second control transistor is connected to the first power supply voltage line, the gate of the first noise reduction transistor and the gate of the second noise reduction transistor are connected to the second node, the first electrode of the first noise reduction transistor and the first electrode of the second noise reduction transistor are connected to the first power supply voltage line, the second electrode of the first noise reduction transistor is connected to the first node, and the second electrode of the second noise reduction transistor is connected to the output end of the output circuit.

[0025] For example, in the display substrate provided in one embodiment of the present disclosure, the shift register further includes a clear circuit, including a control end, an input end, and an output end. The control end of the clear circuit is configured to respond to a fourth drive signal and clear the signal on the first node through a first power supply voltage drop.

[0026] For example, in a display substrate provided in an embodiment of the present disclosure, the clear circuit includes a clear transistor, including a gate, a first electrode and a second electrode. The first electrode of the clear transistor is connected to the first power supply voltage line, and the second electrode of the clear transistor is connected to the first node.

[0027] For example, in a display substrate provided in an embodiment of the present disclosure, the display substrate includes p clock signal lines, the control end of the clear circuit of the nth shift register is electrically connected to the output end of any one of the n+kth shift register to the n+p-1th shift register, and k=p / 2.

[0028] At least one embodiment of the present disclosure further provides a display device, comprising any one of the display substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0030] FIG1 is a schematic diagram of the coordination between a gate drive signal and a data drive signal;

[0031] FIG2 is a schematic diagram of a display substrate of a GOA using a double-sided driving method;

[0032] FIG3 is a schematic diagram of a display substrate of a GOA using an odd-even cross drive mode;

[0033] FIG4 is a schematic diagram of a shift register in a display substrate;

[0034] FIG5 shows a schematic diagram of a GOA circuit;

[0035] FIG6 is a schematic diagram of a display substrate provided in one embodiment of the present disclosure;

[0036] FIG7 is a schematic diagram of a shift register in a display substrate provided by an embodiment of the present disclosure;

[0037] FIG8 is a schematic diagram of a cascade connection of a shift register in a display substrate provided by an embodiment of the present disclosure;

[0038] FIG9 is a schematic diagram of cascading of shift registers in another display substrate provided by an embodiment of the present disclosure;

[0039] FIG10 is a timing diagram of a shift register in a display substrate provided by an embodiment of the present disclosure;

[0040] FIG11 is a partial layout diagram of a display substrate provided in one embodiment of the present disclosure;

[0041] FIG12A is a dimension design diagram of a shift register in a display substrate;

[0042] FIG12B is a dimension design diagram of a shift register in a display substrate provided by an embodiment of the present disclosure;

[0043] FIG13A is a diagram showing simulation results of a shift register according to an embodiment of the present disclosure;

[0044] FIG13B is a schematic diagram of gate drive signal selection points at different positions on a display substrate according to an embodiment of the present disclosure;

[0045] FIG14 is a schematic diagram of cascading of shift registers in another display substrate provided by an embodiment of the present disclosure;

[0046] FIG15 is a schematic diagram of cascading of shift registers in another display substrate provided by an embodiment of the present disclosure;

[0047] FIG16 is a schematic diagram of cascading of shift registers in another display substrate provided by an embodiment of the present disclosure;

[0048] FIG17 is a schematic diagram of cascading of shift registers in another display substrate provided by an embodiment of the present disclosure; and

[0049] FIG18 is a schematic diagram of a display device provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0051] Unless otherwise defined, the technical or scientific terms used in the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. In addition, when the number of a component or element is not specifically stated below in the embodiments of the present disclosure, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "a plurality" refers to at least two.

[0052] It should be noted that the transistors used in the embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Since the source and drain of the transistor are symmetrical, they are structurally indistinguishable and can therefore be replaced with each other. In the embodiments of the present disclosure, to distinguish the source and drain of the transistor, one of the source and drain is referred to as the first electrode, and the other of the source and drain is referred to as the second electrode. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type transistors and P-type transistors. When an N-type transistor is used, a high level is input to the gate, and the first and second electrodes are conductive; when a P-type transistor is used, a low level is input to the gate, and the first and second electrodes are conductive. The following embodiments are described using N-type transistors as an example, but the embodiments of the present disclosure include but are not limited to these. The transistors in the embodiments of the present disclosure may also be P-type transistors. It is understandable that replacing an N-type transistor with a P-type transistor is something that a person skilled in the art can easily think of without inventive effort, and therefore falls within the scope of protection of the embodiments of the present disclosure.

[0053] The GOA circuit can adopt a double-sided driving mode (head to head driving) and an odd-even interlace driving mode (interlace driving); the double-sided driving mode refers to setting two shift registers on both sides of the same pixel row, and providing gate drive signals to the pixel row from both ends of the pixel row; the odd-even interlace driving mode refers to setting a shift register on a single side of the same pixel row, so that the single side of the pixel row provides a gate drive signal to the pixel row, and the shift register corresponding to the odd pixel row is located on one side, and the shift register corresponding to the even pixel row is located on the other side.

[0054] Generally speaking, small-sized display devices (such as mobile phones) and medium-sized display devices with low refresh rates (such as tablets) use an odd-even cross drive method due to the small load on the gate lines; while medium-sized and large-sized display devices with high refresh rates (such as monitors and TVs) use a double-sided drive method due to the large load on the gate drive signal lines. This is because the gate drive signal lines of small-sized panels have a small load, and the waveform delay of the gate drive signal is small, so the rise time and fall time of the gate drive signal are also small. Therefore, the odd-even cross drive method can meet general needs and even meet the needs of high refresh rates. On the other hand, large-sized panels have a large load on the gate lines, and the waveform delay of the gate drive signal is large. If odd-even cross drive is used, it will be difficult to achieve a high refresh rate.

[0055] Specifically, Figure 1 is a schematic diagram of the mutual coordination of a gate drive signal and a data drive signal. As shown in Figure 1, the data drive signal must have a lag of a period of time relative to the gate drive signal, that is, the misshoot time t2 in Figure 1. It is generally required that the misshoot time t2 is greater than or equal to the maximum value of the gate drive signal fall time, that is, the maximum value of the gate drive signal fall time at each position on the gate line (near end, middle, far end, etc.). t3 is the unit time, which is determined by factors such as the resolution and refresh rate of the display substrate. The higher the resolution and refresh rate of the display substrate, the smaller the unit time t3. When the unit time t3 is a fixed value, that is, when the resolution and refresh rate of the display substrate are determined, t1 is the charging time. The longer the charging time t1, the higher the charging rate. If the charging rate is not enough, the display substrate will show abnormalities.

[0056] As shown in Figure 1, charging time t1 = unit time t3 - offset time t2, that is, t1 = t3 - t2. It can be seen from this that in order to ensure the charging rate, the charging time t1 should be as large as possible. Therefore, in display substrates with high resolution and high refresh rate, the falling time of the gate drive signal should be as small as possible, so that the offset time t2 can be small and the charging time t1 can be large. If a GOA circuit with a double-sided drive method is used, the load of the gate signal line phase is driven simultaneously by the shift registers on the left and right sides, and the load of a single shift register is halved, thereby reducing the falling time of the gate drive signal. If a GOA circuit with an odd-even cross drive method is used, the load of the gate signal line phase is driven by a single shift register, resulting in a longer falling time of the gate drive signal. Therefore, if a large-size display device uses a GOA circuit with an odd-even cross drive method, it is generally difficult to achieve a high refresh rate.

[0057] Figure 2 is a schematic diagram of a display substrate for a GOA using a dual-side drive method; Figure 3 is a schematic diagram of a display substrate for a GOA using an odd-even crossover drive method. As shown in Figures 2 and 3, each pixel row in Figure 2 is driven simultaneously by two shift registers located on the left and right sides. For example, the first pixel row is driven simultaneously by two shift registers G1 located on the left and right sides of the first pixel row, the second pixel row is driven simultaneously by two shift registers G2 located on the left and right sides of the second pixel row, and so on. In this case, the height occupied by each shift register G can be roughly equivalent to the height of a pixel. In this case, the width occupied by the shift register is a and the height is h1. The width a occupied by the shift register can be considered as the minimum value of the required border of the display substrate. Each pixel row in FIG3 is driven by only a single shift register; for example, the first shift register (on the left) drives the first pixel row, the third shift register (on the left) drives the third pixel row, and so on. The second shift register (on the right) drives the second pixel row, the fourth shift register (on the right) drives the fourth pixel row, and so on. At this time, the height h2 occupied by each shift register is roughly the height of two pixels, and the width occupied by the shift register is b, which can be considered as the minimum value of the required border of the display substrate. It can be seen that when the areas occupied by the two shift registers are not much different, the display substrate using the GOA of FIG3 using the odd-even cross drive method can greatly reduce the width b occupied by the corresponding shift register, that is, b < a, thereby reducing the required border width. Therefore, the GOA circuit using the odd-even cross drive method can reduce the number of shift registers, thereby having a lower cost, and can also reduce the border width, thus having great application value.

[0058] FIG. 4 is a schematic diagram showing a shift register in a display substrate. As shown in Figure 4, the shift register 10 includes an input transistor 11, an output transistor 12, a first control transistor 13, a second control transistor 14, a first noise reduction transistor 15, a second noise reduction transistor 16, a clear transistor 17 and a bootstrap capacitor Cb; the second electrode of the input transistor 11 and the gate of the output transistor 12 are connected to the first node N1, and the first electrode and gate of the input transistor 11 are connected to the pull-up signal; the first electrode of the output transistor 12 is connected to the clock signal; the gate and the first electrode of the first control transistor 13 are connected to a high potential, and the second electrode of the first control transistor 13 and the second electrode of the second control transistor 14 are connected to the second node N2; the gate of the first noise reduction transistor 15 and the gate of the second noise reduction transistor 16 are connected to the second node N2, the first electrode of the first noise reduction transistor 15 and the first electrode of the second noise reduction transistor 16 are connected to a low potential, the second electrode of the first noise reduction transistor 15 is connected to the first node N1, and the second electrode of the second noise reduction transistor 16 is connected to the second electrode of the output transistor 12; one end of the bootstrap capacitor Cb is connected to the first node N1, and the other end is connected to the second electrode of the output transistor 12.

[0059] As shown in FIG4 , the second electrode of the output transistor 12 is connected to one end of the gate line 20; the shift register 10 further includes the pull-down transistor 18, the output end of which is connected to the other end of the gate line 20. The display substrate can reduce the fall time of the gate drive signal on the gate line 20 from both ends of the gate line 20 via the output transistor 12 and the pull-down transistor 18. However, the pull-down transistor 18 can only pull down the gate drive signal at the far end of the gate line 20 (relative to the output end of the shift register), thereby reducing the fall time of the gate drive signal at the far end of the gate line 20. While the output transistor 12 can reduce the fall time of the gate drive signal at the near end of the gate line 20 to a certain extent, as the channel width-to-length ratio of the output transistor 12 increases, the parasitic capacitance of the output transistor 12 increases, causing its effect on reducing the fall time of the gate drive signal to reach saturation and unable to be further reduced.

[0060] FIG5 shows a schematic diagram of a GOA circuit. As shown in FIG5 , the GOA circuit includes several shift registers, including a first shift register 10A and a second shift register 10B. The input end of the output transistor 12 of the first shift register 10A is connected to the first clock signal line CK1, and the input end of the output transistor 12 of the second shift register 10B is connected to the second clock signal line CK2. With this arrangement, the parasitic capacitance Cgs of the output transistor 12 is loaded on the clock signal line. As the channel width-to-length ratio of the output transistor 12 increases, its on-state current increases, thereby reducing the fall time of the gate drive signal at the near end of the gate line 20. However, the parasitic capacitance Cgs of the output transistor 12 also increases, and the load on the clock signal line increases. Therefore, as the output transistor 12 increases, the fall time of the gate drive signal first decreases and then reaches saturation. Thereafter, it no longer decreases as the channel width-to-length ratio of the output transistor 12 increases, resulting in the gate drive signal fall time being unable to be further reduced. It can be seen that the fall time of the gate drive signal at the proximal end of the gate line will reach a certain limit value and cannot continue to fall, while the fall time of the gate drive signal at the distal end of the gate line can continue to decrease as the channel width-to-length ratio of the pull-down transistor increases, which will eventually cause the fall time of the gate drive signal at the distal end of the gate line to be much shorter than the fall time of the gate drive signal at the proximal end of the gate line. On the one hand, it will cause a large difference in the feed-through voltage between the proximal and distal ends of the pixel row, and there is a risk of poor display for the display substrate of the GOA circuit using a unilateral drive method; on the other hand, the above-mentioned misshoot time t2 is determined by the maximum value of the fall time of the gate drive signal at each point on the gate line, so unilaterally reducing the fall time of the gate drive signal at the distal end of the gate line is invalid. It should be noted that the input module 31 in Figure 5 may include the above-mentioned input transistor M1, and the maintenance module 32 in Figure 5 may include the above-mentioned first control transistor 13, the second control transistor 14, the first noise reduction transistor 15, and the second noise reduction transistor 16.

[0061] In this regard, an embodiment of the present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a shift register, a clock signal line, and a first power supply voltage line arranged on the base substrate. The clock signal line is configured to provide a clock signal to the shift register, and the first power supply voltage line is configured to provide a first power supply voltage to the shift register; the shift register includes an input circuit, an output circuit, and a first output pull-down circuit, the input circuit includes a control terminal, an input terminal, and an output terminal, the output circuit includes a control terminal, an input terminal, and an output terminal, the output terminal of the input circuit and the control terminal of the output circuit are connected to a first node, and the input terminal of the output circuit is connected to the clock signal line; the input circuit is configured to respond to the first node on the control terminal of the input circuit. The first output pull-down circuit includes a control terminal, an input terminal, and an output terminal. The input terminal of the first output pull-down circuit is connected to a first power supply voltage line, and the output terminal of the first output pull-down circuit is connected to the output terminal of the output circuit. The first output pull-down circuit is configured to respond to a second drive signal at the control terminal of the first output pull-down circuit to reduce the fall time of the gate drive signal at the output terminal of the output circuit via the first power supply voltage. Thus, by reducing the fall time of the gate drive signal output by a single shift register, the display substrate can further reduce costs and border width by using a GOA circuit with an odd-even cross drive method while ensuring a higher resolution and refresh rate of the display substrate, making the product more competitive in the market.

[0062] Hereinafter, the display substrate and the display device provided by the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0063] An embodiment of the present disclosure provides a display substrate. FIG6 is a schematic diagram of a display substrate provided by an embodiment of the present disclosure; FIG7 is a schematic diagram of a shift register in a display substrate provided by an embodiment of the present disclosure.

[0064] As shown in Figures 6 and 7, the display substrate 100 includes a base substrate 110 and a shift register 120, a clock signal line 130, and a first power supply voltage line 141 provided on the base substrate 110; the clock signal line 130 is configured to provide a clock signal to the shift register 120, and the first power supply voltage line 141 is configured to provide a first power supply voltage to the shift register 120; the shift register 120 includes an input circuit 121, an output circuit 122, and a first output pull-down circuit 124, the input circuit 121 includes a control terminal, an input terminal, and an output terminal, and the output circuit 122 includes a first output pull-down circuit 124. 22 includes a control end, an input end and an output end, the output end of the input circuit 121 and the control end of the output circuit 122 are connected to the first node N1, and the input end of the output circuit 122 is connected to the clock signal line 130; the input circuit 121 is configured to respond to the first drive signal on the control end of the input circuit 121 to write the input signal on the input end of the input circuit 121 into the first node N1, and the output circuit 122 is configured to respond to the signal on the first node N1 to output the clock signal on the clock signal line 130 as a gate drive signal through the output end of the output circuit 122.

[0065] The first output pull-down circuit 124 includes a control terminal, an input terminal, and an output terminal. The input terminal of the first output pull-down circuit 124 is connected to the first power supply voltage line 141, and the output terminal of the first output pull-down circuit 124 is connected to the output terminal of the output circuit 122. The first output pull-down circuit 124 is configured to respond to a second drive signal at the control terminal of the first output pull-down circuit 124 to reduce the falling time of the gate drive signal at the output terminal of the output circuit 122 by using the first power supply voltage, with the rising edge of the second drive signal and the falling edge of the gate drive signal overlapping in time. It should be noted that the input and output terminals of the aforementioned circuits merely represent examples of signal input and output and are not intended to limit the actual direction of current flow. The input and output terminals of the various circuits are interchangeable.

[0066] In the display substrate provided by the embodiment of the present disclosure, the shift register can reduce the fall time of the gate drive signal at the output end of the output circuit through the first output pull-down circuit, thereby reducing the fall time of the gate drive signal at the proximal end of the gate line corresponding to the shift register. This can reduce the misshoot time (the misshoot time t2 is determined by the maximum fall time of the gate drive signal at each point on the gate line) and increase the charging time. As a result, the display substrate can have a higher resolution and refresh rate (suitable for large-size products) while adopting a GOA circuit with an odd-even cross drive method to further reduce costs and reduce border width, making the product more competitive in the market.

[0067] In some examples, as shown in FIG7 , the display substrate 100 further includes a gate line 150 and a plurality of pixel rows 165; the gate line 150 extends along a first direction X, and the plurality of pixel rows 165 are arranged along a second direction Y intersecting the first direction X, and each pixel row 165 includes a plurality of pixel units 160 arranged along the first direction; the gate line 150 is connected to the plurality of pixel units 160 in the pixel row 165 and provides a gate drive signal to the plurality of pixel units 160; the gate line 150 includes a first end 150A and a second end 150B located on both sides of the pixel row 165, and the gate line 150 is connected to the plurality of pixel units 160 in the pixel row 165. The first end 150A is connected to the output end of the output circuit 122; the shift register 120 also includes a second output pull-down circuit 129, including a control end, an input end and an output end, the input end of the second output pull-down circuit 129 is connected to the first power supply voltage line 141, and the second end 150B of the gate line 150 is connected to the output end of the second output pull-down circuit 129. The second output pull-down circuit 129 is configured to respond to the third drive signal on the control end of the second output pull-down circuit 129, and reduce the fall time of the gate drive signal at the second end 150B through the first power supply voltage.

[0068] In this display substrate, the shift register can reduce the fall time of the gate drive signal at the near end (i.e., the first end) of the gate line near the output circuit and the far end (i.e., the second end) of the gate line far from the output circuit, respectively, through a first output pull-down circuit and a second output pull-down circuit. This reduces the fall time of the gate drive signal at various positions on the gate line, resulting in a shorter staggered time and a longer charging time for the multiple pixel units corresponding to the gate line. As a result, this display substrate can achieve higher resolution and refresh rate (suitable for large-size products) while also using a GOA circuit with an odd-even cross drive method to further reduce costs and border width, making the product more competitive in the market.

[0069] In some examples, as shown in FIG7 , the control end of the first output pull-down circuit 124 and the control end of the second output pull-down circuit 129 are connected to the same signal line Gn+4, i.e., the second drive signal and the third drive signal are the same. Thus, the display substrate can synchronously reduce the fall time of the gate drive signal at the near end (i.e., the first end) of the gate line close to the output circuit and the far end (i.e., the second end) of the gate line far from the output circuit through the first output pull-down circuit and the second output pull-down circuit. It should be noted that the aforementioned signal line Gn+4 can be the gate drive signal output by the n+4th shift register.

[0070] FIG8 is a schematic diagram of a cascade connection of shift registers in a display substrate provided in one embodiment of the present disclosure; FIG9 is a schematic diagram of a cascade connection of shift registers in another display substrate provided in one embodiment of the present disclosure. Each shift register in FIG8 shows only some of the ports of the input circuit, output circuit, first output pull-down circuit, and second output pull-down circuit, where G1 represents the control terminal of the input circuit 121, 3S represents the input terminal of the output circuit, 3D represents the output terminal of the output circuit, 4AG represents the control terminal of the first output pull-down circuit, 4BG represents the control terminal of the second output pull-down circuit, and 4BD represents the output terminal of the second output pull-down circuit. Each shift register in FIG9 shows only some of the ports of the first output pull-down circuit and the second output pull-down circuit, where M4A represents the first output pull-down circuit and M4B represents the second output pull-down circuit.

[0071] In some examples, as shown in Figures 6, 7, 8, and 9, the base substrate 110 includes a display area 112 and a peripheral area 114. The peripheral area 114 includes a first sub-peripheral area 114A and a second sub-peripheral area 114B located on either side of the display area 112. For example, the first sub-peripheral area 114A and the second sub-peripheral area 114B are located on the left and right sides of the display area 112. The input circuit 121, output circuit 122, and first output pull-down circuit 124 of the shift register 120 are located in one of the first sub-peripheral area 114A and the second sub-peripheral area 114B, and the second output pull-down circuit 129 of the shift register 120 is located in the other of the first sub-peripheral area 114A and the second sub-peripheral area 114B. Thus, the display substrate uses a GOA circuit with an odd-even cross drive method to further reduce costs and reduce border width.

[0072] For example, as shown in FIG. 6 , the peripheral region 114 of the base substrate 110 may further include a binding region 118 located below the display region 112 for binding with an external driver IC.

[0073] For example, as shown in Figures 8 and 9, the input circuit, output circuit and first output pull-down circuit of the first shift register 120 are located in the first sub-peripheral area 114A, and the second output pull-down circuit of the first shift register 120 is located in the second sub-peripheral area 114B; the input circuit, output circuit and first output pull-down circuit of the second shift register 120 are located in the second sub-peripheral area 114B, and the second output pull-down circuit of the second shift register 120 is located in the first sub-peripheral area 114A; the input circuit, output circuit and first output pull-down circuit of the third shift register 120 are located in the first sub-peripheral area 114A, and the second output pull-down circuit of the third shift register 120 is located in the second sub-peripheral area 114B; the input circuit, output circuit and first output pull-down circuit of the fourth shift register 120 are located in the second sub-peripheral area 114B, and the second output pull-down circuit of the fourth shift register 120 is located in the first sub-peripheral area 114A; and so on.

[0074] In some examples, as shown in Figures 6, 7, 8, and 9, the display substrate 100 includes M shift registers 120 and M gate lines 150. The M shift registers 120 provide gate drive signals for the M gate lines 150, respectively. The i-th shift register 120 provides a gate drive signal for the i-th gate line 150, where i is a positive integer greater than or equal to 1 and less than or equal to M. Among the M shift registers 120, the 2n+1-th shift register 120 is located in the first sub-peripheral area 114A, and the 2n+2-th shift register 120 is located in the second sub-peripheral area 114B, where n is an integer greater than or equal to 0. Thus, the display substrate can set the shift registers corresponding to the odd-numbered rows of gate lines in the first sub-peripheral area and the shift registers corresponding to the even-numbered rows of gate lines in the second sub-peripheral area, thereby realizing an odd-even cross drive mode.

[0075] In some examples, as shown in Figures 6, 7, 8, and 9, the first sub-peripheral area 114A includes a first register area 210 and a 2j+1th register area 210, and the second sub-peripheral area 114B includes a second register area 220 and a 2j+2th register area 220. The first register area 210 and the second register area 220 are relatively spaced apart, and the 2j+1th register area 210 and the 2j+2th register area 220 are relatively spaced apart. The first register area 210 is provided with the input circuit 121, the output circuit 122, and the first output pull-down circuit 124 of the first shift register 120, and the second output pull-down circuit 129 of the second shift register 120; the second register area 220 is provided with the The input circuit 121, output circuit 122, and first output pull-down circuit 124 of the two shift registers 120, as well as the second output pull-down circuit 129 of the first shift register 120, are arranged in the 2j+1th register region 210. The input circuit 121, output circuit 122, and first output pull-down circuit 124 of the 2j+1th shift register 120, as well as the second output pull-down circuit 129 of the 2j+2th shift register 120, are arranged in the 2j+2th register region 220. The input circuit 121, output circuit 122, and first output pull-down circuit 124 of the 2j+2th shift register 120, as well as the second output pull-down circuit 129 of the 2j+1th shift register 120, where j is a positive integer greater than or equal to 1. Thus, the display substrate can, while each shift register can reduce the fall time of the gate drive signal on the corresponding gate line from both ends of the gate line, cleverly utilize the area of ​​the peripheral region to improve integration.

[0076] In some examples, as shown in FIG6 and FIG7 , the control terminal of the first output pull-down circuit 124 of the mth shift register 120 is electrically connected to the output terminal of the output circuit 122 of the m+kth shift register 120, where m is a positive integer greater than or equal to 1, and k is a positive integer greater than or equal to 1. In other words, the first output pull-down circuit of the mth shift register can be controlled by the output signals of subsequent shift registers, which can save drive lines and improve integration.

[0077] In some examples, as shown in FIG6 and FIG7 , the display substrate 100 includes p clock signal lines 130 , k=p / 2, so that the falling edge of the gate driving signal overlaps with the rising edge of the second driving signal.

[0078] In some examples, as shown in FIG6 and FIG7 , the control terminal of the second output pull-down circuit 129 of the mth shift register 120 is electrically connected to the output terminal of the output circuit 122 of the (m+k)th shift register 120. In other words, the second output pull-down circuit of the mth shift register can be controlled by the output signals of subsequent shift registers, which can save drive lines and improve integration.

[0079] In some examples, as shown in Figures 6 and 7, the control end of the first output pull-down circuit 124 and the control end of the second output pull-down circuit 129 of the mth shift register 120 are both electrically connected to the output end of the output circuit 122 of the m+kth shift register 120.

[0080] In some examples, as shown in Figures 6 and 7, when m is an odd number, the control terminals of the first output pull-down circuit 124 and the second output pull-down circuit 129 of the m-th shift register 120 are both electrically connected to the output terminals of the output circuit 122 of the odd-numbered shift register 120. When m is an even number, the control terminals of the first output pull-down circuit 124 and the second output pull-down circuit 129 of the m-th shift register 120 are both electrically connected to the output terminals of the output circuit 122 of the even-numbered shift register 120. This arrangement allows for better wiring of the display substrate and improves integration.

[0081] In some examples, as shown in Figures 6 and 7, in the shift register 120, the input circuit 121 includes an input transistor M1, the output circuit 122 includes an output transistor M3, and the first output pull-down circuit 124 includes a first pull-down transistor M4A; the input transistor M1 includes a gate, a first electrode, and a second electrode, the output transistor M3 includes a gate, a first electrode, and a second electrode, and the first pull-down transistor M4A includes a gate, a first electrode, and a second electrode; the second electrode of the input transistor M1 and the gate of the output transistor M3 are connected to the first node N1, the first electrode of the output transistor M3 is connected to the clock signal line 130, the first electrode of the first pull-down transistor M4A is connected to the first power supply voltage line 141, and the second electrode of the first pull-down transistor M4A is connected to the second electrode of the output transistor M3.

[0082] In some examples, as shown in Figures 6 and 7, the second output pull-down circuit 129 includes a second pull-down transistor M4B, including a gate, a first electrode, and a second electrode; the first electrode of the second pull-down transistor M4B is connected to the first power supply voltage line 141, and the second electrode of the second pull-down transistor M4B is connected to the second end of the gate line 150.

[0083] In some examples, as shown in FIG6 and FIG7 , the shift register 120 further includes a bootstrap capacitor Cb; one end of the bootstrap capacitor Cb is connected to the first node N1 , and the other end of the bootstrap capacitor Cb is connected to the output end of the output transistor M3 .

[0084] In some examples, as shown in Figures 8 and 9, the input terminal 3S of the output transistor M3 of the first shift register 120 is connected to the first clock signal line 131, the output terminal 3D of the output transistor M3 of the first shift register 120 outputs the gate drive signal G1, and the gate 4AG of the first pull-down transistor M4A of the first shift register 120 is connected to the output terminal of the fifth shift register 120 to receive the gate drive signal G5; the second pull-down transistor M4B of the second shift register 120 is set in the first register area 210, the gate 4BG of the second pull-down transistor M4B of the second shift register 120 is connected to the output terminal of the sixth shift register 120 to receive the gate drive signal G6, and the drain 4BD of the second pull-down transistor M4B of the second shift register 120 is connected to the output terminal of the second shift register 120 to reduce the falling time of the gate drive signal at the far end of the second shift register 120.

[0085] In some examples, as shown in Figures 8 and 9, the input terminal 3S of the output transistor M3 of the second shift register 120 is connected to the second clock signal line 132, the output terminal 3D of the output transistor M3 of the second shift register 120 outputs the gate drive signal G2, and the gate 4AG of the first pull-down transistor M4A of the second shift register 120 is connected to the output terminal of the sixth shift register 120 to receive the gate drive signal G6; the second pull-down transistor M4B of the first shift register 120 is set in the second register area 220, the gate 4BG of the second pull-down transistor M4B of the first shift register 120 is connected to the output terminal of the fifth shift register 120 to receive the gate drive signal G5, and the drain 4BD of the second pull-down transistor M4B of the first shift register 120 is connected to the output terminal of the first shift register 120 to reduce the falling time of the gate drive signal at the far end of the first shift register 120.

[0086] In some examples, as shown in Figures 8 and 9, the input terminal 3S of the output transistor M3 of the third shift register 120 is connected to the first clock signal line 131, the output terminal 3D of the output transistor M3 of the third shift register 120 outputs the gate drive signal G1, and the gate 4AG of the first pull-down transistor M4A of the third shift register 120 is connected to the output terminal of the seventh shift register 120 to receive the gate drive signal G7; the second pull-down transistor M4B of the fourth shift register 120 is set in the first register area 210, the gate 4BG of the second pull-down transistor M4B of the fourth shift register 120 is connected to the output terminal of the eighth shift register 120 to receive the gate drive signal G8, and the drain 4BD of the second pull-down transistor M4B of the fourth shift register 120 is connected to the output terminal of the fourth shift register 120 to reduce the falling time of the gate drive signal at the far end of the fourth shift register 120.

[0087] In some examples, as shown in Figures 8 and 9, the input terminal 3S of the output transistor M3 of the 4th shift register 120 is connected to the second clock signal line 132, the output terminal 3D of the output transistor M3 of the 4th shift register 120 outputs the gate drive signal G2, and the gate 4AG of the first pull-down transistor M4A of the 4th shift register 120 is connected to the output terminal of the 8th shift register 120 to receive the gate drive signal G8; the second pull-down transistor M4B of the 3rd shift register 120 is set in the second register area 220, the gate 4BG of the second pull-down transistor M4B of the 3rd shift register 120 is connected to the output terminal of the 7th shift register 120 to receive the gate drive signal G7, and the drain 4BD of the second pull-down transistor M4B of the 3rd shift register 120 is connected to the output terminal of the 3rd shift register 120 to reduce the falling time of the gate drive signal at the far end of the 3rd shift register 120.

[0088] It should be noted that the above describes the cascade method of the first shift register to the fourth shift register; therefore, the shift registers provided in the embodiment of the present disclosure can be cascaded according to Figures 8 and 9 and the above-mentioned related descriptions, which will not be repeated here.

[0089] FIG10 is a timing diagram of a shift register in a display substrate provided by an embodiment of the present disclosure. As shown in FIG10 , in the input phase, the input transistor M1 responds to the drive signal on its gate, writes the signal inputted by its first pole to the first node N1, and simultaneously charges the bootstrap capacitor Cb; in the output phase, the output transistor M3 is configured to respond to the signal on the first node N1 to output the clock signal on the clock signal line 130 through the output end of the output transistor M3 as a gate drive signal; when the gate drive signal starts to fall, the first pull-down transistor M4A and the second pull-down transistor M4B are turned on, and the fall time of the gate drive signal is reduced from both ends (far end and near end) of the gate line by the first power supply voltage. It should be noted that CKm is the clock signal line connected to the output circuit of the mth shift register, and CKm+6 is the clock signal line connected to the output circuit of the m+6th shift register.

[0090] In some examples, as shown in Figures 6 and 7, the shift register 120 also includes a first control circuit 125, a second control circuit 126, a first noise reduction circuit 127 and a second noise reduction circuit 128; the output end of the first control circuit 125 and the output end of the second control circuit 126 are connected to the second node N2, the control end and the input end of the first control circuit 125 are connected to the second power supply voltage line 142, the input end of the second control circuit 126 is connected to the first power supply voltage line 141 to be configured to receive the first power supply voltage, and the control end of the second control circuit 126 is connected to the first node N1. The first control circuit 125 is configured to respond to a second power supply voltage on the second power supply voltage line 142 and pull up the potential of the second node N2 using the second power supply voltage. The second control circuit 126 is configured to respond to a signal on the first node N1 and pull down the potential of the second node N2 using the first power supply voltage. The control terminal of the first noise reduction circuit 127 and the control terminal of the second noise reduction circuit 128 are connected to the second node N2. The input terminal of the first noise reduction circuit 127 and the input terminal of the second noise reduction circuit 128 are connected to the first power supply voltage line 141 to be configured to receive the first power supply voltage. The output terminal of the first noise reduction circuit 127 is connected to the first node N1, and the output terminal of the second noise reduction circuit 128 is connected to the output terminal of the output circuit 122. The first noise reduction circuit 127 is configured to respond to a signal on the second node N2 to reduce the noise of the first node N1 using the first power supply voltage. The second noise reduction circuit 128 is configured to respond to a signal on the second node N2 to reduce the noise of the output terminal of the output circuit 122 using the first power supply voltage. It should be noted that the input end of the second control circuit, the input end of the first noise reduction circuit, and the input end of the second noise reduction circuit may also be connected to other signal lines loaded with the first power supply voltage to receive the first power supply voltage.

[0091] In some examples, as shown in FIG6 and FIG7, the first control circuit 125 includes a first control transistor M5, the second control circuit 126 includes a second control transistor M6, the first noise reduction circuit 127 includes a first noise reduction transistor M7, and the second noise reduction circuit 128 includes a second noise reduction transistor M8; the first control transistor M5 includes a gate, a first electrode, and a second electrode, the second control transistor M6 includes a gate, a first electrode, and a second electrode, the first noise reduction transistor M7 includes a gate, a first electrode, and a second electrode, and the second noise reduction transistor M8 includes a gate, a first electrode, and a second electrode; the first electrode and the gate of the first control transistor M5 are connected to the second power supply voltage line 14. 2, the second electrode of the first control transistor M5 and the second electrode of the second control transistor M6 are connected to the second node N2, the gate of the second control transistor M6 is connected to the first node N1, and the first electrode of the second control transistor M6 is connected to the first power supply voltage line 141; the gate of the first noise reduction transistor M7 and the gate of the second noise reduction transistor M8 are connected to the second node, the first electrode of the first noise reduction transistor M7 and the first electrode of the second noise reduction transistor M8 are connected to the first power supply voltage line 141, the second electrode of the first noise reduction transistor M7 is connected to the first node N1, and the second electrode of the second noise reduction transistor M8 is connected to the output end of the output circuit 122.

[0092] In some examples, as shown in FIG10 , when the potential on the first node N1 is at a high level, the second control transistor M6 is turned on, and the first power supply voltage on the first power supply voltage line 141 can be written into the second node N2, so that the second node N2 maintains a low level; when the potential on the first node N1 is at a low level, the second control transistor M6 is not turned on, and the second power supply voltage on the second power supply voltage line 142 is written into the second node N2 through the first control transistor M5, so that the point of the second node N2 is pulled high; at this time, the first noise reduction transistor M7 and the second noise reduction transistor M8 are turned on, and the first power supply voltage on the first power supply voltage line 141 reduces the potential on the first node N1 through the first noise reduction transistor M7, and reduces the potential on the output end of the output circuit 122 through the second noise reduction transistor M8.

[0093] In some examples, as shown in Figures 6 and 7, the shift register 120 further includes a clear circuit 123; the clear circuit 123 includes a control end, an input end, and an output end; the control end of the clear circuit 123 is configured to respond to the fourth driving signal and clear the signal on the first node N1 through the first power supply voltage drop.

[0094] In some examples, the fourth drive signal at the control terminal of the clear circuit 123 of the nth shift register 120 can be a signal at the output terminal of any one of the n+kth to n+p-1th shift registers. In other words, the control terminal of the clear circuit 123 of the nth shift register 120 can be electrically connected to the output terminal of any one of the n+kth to n+p-1th shift registers. This configuration can save drive lines and improve integration.

[0095] For example, as shown in FIG. 7 , the fourth driving signal on the control terminal of the clearing circuit 123 of the nth shift register 120 may be the signal on the output terminal of the (n+6)th shift register.

[0096] In some examples, as shown in Figures 6 and 7, the clearing circuit 123 includes a clearing transistor M2, including a gate, a first electrode and a second electrode. The first electrode of the clearing transistor M2 is configured to receive the first power supply voltage, and the second electrode of the clearing transistor M2 is connected to the first node N1.

[0097] Figure 11 is a partial layout diagram of a display substrate provided in accordance with an embodiment of the present disclosure. As shown in Figure 11 , the 2n+1th shift register 120 and the 2n+2th shift register 120 are spaced apart from each other, i.e., the 2n+1th shift register 120 and the 2n+2th shift register 120 are disposed on opposite sides of the display area 112 and are disposed opposite each other; where n is a positive integer greater than or equal to 0.

[0098] In some examples, as shown in FIG11 , in the 2n+1th shift register 120 , the orthographic projection of the first pull-down transistor M4A on the substrate substrate 110 is located on a side of the orthographic projection of the output transistor M3 on the substrate substrate 110 that is close to the 2n+2th shift register 120 ; in the 2n+2th shift register 120 , the orthographic projection of the first pull-down transistor M4A on the substrate substrate 110 is located on a side of the orthographic projection of the output transistor M3 on the substrate substrate 110 that is close to the 2n+1th shift register 120 .

[0099] In some examples, as shown in FIG11 , the orthographic projection of the second pull-down transistor M4B of the 2n+1th shift register 120 on the substrate 110 is located between the orthographic projection of the output transistor M3 of the 2n+2th shift register 120 on the substrate 110 and the orthographic projection of the first pull-down transistor M4A of the 2n+2th shift register 120 on the substrate 110; and the orthographic projection of the second pull-down transistor M4B of the 2n+2th shift register 120 on the substrate 110 is located between the orthographic projection of the output transistor M3 of the 2n+1th shift register 120 on the substrate 110 and the orthographic projection of the first pull-down transistor M4A of the 2n+1th shift register 120 on the substrate 110. Thus, the display substrate can facilitate cascading between shift registers, improve integration, and further reduce border width.

[0100] Figure 12A shows a dimensional design diagram of a shift register in a display substrate; Figure 12B shows a dimensional design diagram of a shift register in a display substrate according to an embodiment of the present disclosure. The shift register shown in Figure 12A includes only the second pull-down transistor M4B, which is the pull-down transistor at the far end of the gate line; the shift register shown in Figure 12B includes the first pull-down transistor M4A and the second pull-down transistor M4B.

[0101] As shown in Figures 12A and 12B, when the first power supply voltage is -10V and the second power supply voltage is 30V, the channel widths of the output transistors M3 in Figures 10A and 10B are both 2400 microns, the channel width of the second pull-down transistor M4B in Figure 10A is 4000 microns, and the channel width of the first pull-down transistor M4A in Figure 10B is 1500 microns, while the channel width of the second pull-down transistor M4B is 2500 microns. Thus, although the shift register shown in Figure 10B has an additional transistor, the overall width of the shift register can be kept constant or even reduced by reducing the channel width of the second pull-down transistor.

[0102] In some examples, as shown in FIG. 11 and FIG. 12B , the channel length of the first pull-down transistor M4A is less than the channel length of the output transistor M3 .

[0103] In some examples, as shown in FIG. 11 and FIG. 12B , the channel width-to-length ratio of the second pull-down transistor M4B is greater than the channel width-to-length ratio of the first pull-down transistor M4A, thereby increasing the shift register's ability to reduce the falling time of the gate drive signal at the far end of the gate line.

[0104] In some examples, as shown in FIG11 and FIG12B , the channel width-to-length ratio of the first pull-down transistor M4A is smaller than that of the output transistor M3 , and the channel width-to-length ratio of the second pull-down transistor M4B is larger than that of the output transistor M3 .

[0105] FIG13A is a diagram showing the simulation results of a shift register provided in an embodiment of the present disclosure; FIG13B is a schematic diagram showing the points of the gate drive signal provided in an embodiment of the present disclosure at different positions on the display substrate. The simulation of FIG13A is carried out under the conditions that the first power supply voltage is -10V and the second power supply voltage is 30V; the channel widths of the output transistor M3 and the second pull-down transistor M4B in the shift register in the comparative example in FIG13A can be referred to the relevant parameters of FIG12A; the channel widths of the output transistor M3, the first pull-down transistor M4A, and the second pull-down transistor M4B in the shift register in the embodiment in FIG13A can be referred to the relevant parameters of FIG12B. FIG13B shows a schematic diagram of the gate drive signal at different positions on the display substrate, wherein Gn_L is the proximal position of the gate line, Gn_B is the middle position of the gate line, Gn_C is the distal position of the gate line, Gn_M1 is the middle position between Gn_L and Gn_B points, and Gn_M2 is the middle position between Gn_C and Gn_B points.

[0106] As shown in Figure 13A, the comparative example adopts M4B with a larger channel width-to-length ratio to pull down the falling time of the gate drive signal due to the far end, so the gate drive signal is less at the Gn_C position falling time, but because the Gn_L position only has M3 to pull down, the gate drive signal falling time is now larger. As mentioned above, the effective value of the gate drive signal is the maximum value everywhere on the gate line, so the falling time of the gate drive signal at the far end of the gate line that is unilaterally reduced is invalid, and the falling time of the gate drive signal at the near end and the far end needs to be reduced simultaneously. On the contrary, the embodiment has added the first pull-down transistor M4A due to the near end, and after the falling time of the gate drive signal on the near end of the gate line that can be pulled down by M3 reaches saturation, M4A can continue to further pull down the falling time of the gate drive signal on the near end of the gate line, so the falling time of the gate drive signal on the near end of the gate line is reduced simultaneously, and matching can be achieved, so that the gate drive signal falling time can be effectively reduced.

[0107] Thus, the shift register provided by the disclosed embodiment, without increasing the layout area, adds a first pull-down transistor. After the fall time of the gate drive signal at the proximal end of the gate line pulled down by the output transistor reaches saturation, the first pull-down transistor can be used to further pull down the fall time of the gate drive signal at the proximal end of the gate line, effectively reducing the fall time of the gate drive signal. As a result, the display substrate can adopt a GOA design with an odd-even cross drive method (especially for large-size products), achieving a high refresh rate while having a narrow frame.

[0108] FIG14 is a schematic diagram of the cascade connection of shift registers in another display substrate provided in an embodiment of the present disclosure; FIG15 is a schematic diagram of the cascade connection of shift registers in another display substrate provided in an embodiment of the present disclosure. Each shift register in FIG14 shows only part of the ports of the input circuit, output circuit, first output pull-down circuit, and second output pull-down circuit, where G1 represents the control end of the input circuit 121, 3S represents the input end of the output circuit, 3D represents the output end of the output circuit, 4AG represents the control end of the first output pull-down circuit, 4BG represents the control end of the second output pull-down circuit, and 4BD represents the output end of the second output pull-down circuit. Each shift register in FIG15 shows only part of the ports of the first output pull-down circuit and the second output pull-down circuit, where M4A represents the first output pull-down circuit and M4B represents the second output pull-down circuit.

[0109] As shown in Figures 14 and 15 , the peripheral area includes a first sub-peripheral area 114A and a second sub-peripheral area 114B located on either side of the display area 112. For example, the first sub-peripheral area 114A and the second sub-peripheral area 114B are located on the left and right sides of the display area. The first sub-peripheral area 114A includes a first register area 210 and a 2j+1th register area 210, and the second sub-peripheral area 114B includes a second register area 220 and a 2j+2th register area 220. The first register area 210 and the second register area 220 are spaced apart from each other, and the 2j+1th register area 210 and the 2j+2nd register area 220 are spaced apart from each other.

[0110] As shown in Figures 14 and 15, the first register area 210 is configured to set the input circuit, output circuit and first output pull-down circuit of the first shift register 120, and the second register area 220 is configured to set the input circuit, output circuit and first output pull-down circuit of the second shift register 120 and the second output pull-down circuit of the first shift register 120; the 2j+1th register area 210 is configured to set the input circuit, output circuit and first output pull-down circuit of the 2j+1th shift register 120 and the second output pull-down circuit of the 2jth shift register 120, and the 2j+2th register area 220 is configured to set the input circuit, output circuit and first output pull-down circuit of the 2j+2th shift register 120 and the second output pull-down circuit of the 2j+1th shift register 120, where j is a positive integer greater than or equal to 1.

[0111] In simple terms, the first register region does not include the second output pull-down circuit (eg, M4B) of the second shift register. After the last shift register, a separate output pull-down circuit may be provided as the second output pull-down circuit of the last shift register.

[0112] FIG16 is a schematic diagram of a cascade connection of shift registers in another display substrate provided in an embodiment of the present disclosure; FIG17 is a schematic diagram of a cascade connection of shift registers in another display substrate provided in an embodiment of the present disclosure. Each shift register in FIG16 shows only part of the ports of the input circuit, output circuit, first output pull-down circuit, and second output pull-down circuit, where G1 represents the control end of the input circuit 121, 3S represents the input end of the output circuit, 3D represents the output end of the output circuit, 4AG represents the control end of the first output pull-down circuit, 4BG represents the control end of the second output pull-down circuit, and 4BD represents the output end of the second output pull-down circuit. Each shift register in FIG17 shows only part of the ports of the first output pull-down circuit and the second output pull-down circuit, where M4A represents the first output pull-down circuit and M4B represents the second output pull-down circuit.

[0113] As shown in Figures 16 and 17, the peripheral area includes a first sub-peripheral area 114A and a second sub-peripheral area 114B located on both sides of the display area 112. For example, the first sub-peripheral area 114A and the second sub-peripheral area 114B are located on the left and right sides of the display area 112. The first sub-peripheral area 114A includes a first register area 210 and a 2j+1th register area 210, and the second sub-peripheral area 114B includes a second register area 220 and a 2j+2th register area 220. The first register area 210 and the second register area 220 are spaced apart from each other, and the 2j+1th register area 210 and the 2j+2nd register area 220 are spaced apart from each other.

[0114] As shown in Figures 16 and 17, the first register region 210 is configured with the input circuit, output circuit, and first output pull-down circuit of the first shift register 120. The second register region 220 is configured with the input circuit, output circuit, and first output pull-down circuit of the second shift register 120, as well as the second output pull-down circuit of the first shift register 120. The 2j+1th register region 210 is configured with the input circuit, output circuit, and first output pull-down circuit of the 2j+1th shift register 120, as well as the second output pull-down circuit of the 2jth shift register 120. The 2j+2th register region 220 is configured with the input circuit, output circuit, and first output pull-down circuit of the 2j+2th shift register 120, as well as the second output pull-down circuit of the 2j+1th shift register 120. The second output pull-down circuit of the first shift register 120 is configured on the side of the second register region 220 away from the 2j+2th shift register. In this case, the last register region is not configured with a second output pull-down circuit.

[0115] At least one embodiment of the present disclosure further provides a display device. FIG18 is a schematic diagram of a display device provided in one embodiment of the present disclosure. As shown in FIG18 , the display device 500 includes a display substrate 100 provided in any of the above examples. Thus, the display device can achieve a higher resolution and refresh rate (suitable for large-size products) while also utilizing an odd-even cross-drive GOA circuit to further reduce costs and border width, making the product more competitive in the market.

[0116] For example, the display device may be an electronic product with a display function, such as a television, a monitor, an electronic picture frame, an electronic photo frame, a navigator, a notebook computer, a tablet computer, or a smart phone.

[0117] There are a few points to note:

[0118] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0119] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0120] The above are merely specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed herein should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate and a shift register, a clock signal line and a first power supply voltage line arranged on the base substrate; The gate line extends along the first direction; as well as A plurality of pixel rows are arranged along a second direction intersecting the first direction, each of the pixel rows comprising a plurality of pixel units arranged along the first direction, Wherein, the clock signal line is configured to provide a clock signal to the shift register, and the first power supply voltage line is configured to provide a first power supply voltage to the shift register; The shift register comprises an input circuit, an output circuit, and a first output pull-down circuit, wherein the input circuit comprises a control terminal, an input terminal, and an output terminal, the output circuit comprises a control terminal, an input terminal, and an output terminal, the output terminal of the input circuit and the control terminal of the output circuit are connected to a first node, and the input terminal of the output circuit is connected to the clock signal line; The input circuit is configured to respond to a first driving signal on a control terminal of the input circuit to write an input signal on an input terminal of the input circuit to the first node, and the output circuit is configured to respond to a signal on the first node to output a gate driving signal via an output terminal of the output circuit with the clock signal on the clock signal line; The first output pull-down circuit comprises a control terminal, an input terminal and an output terminal, the input terminal of the first output pull-down circuit is connected to a first power supply voltage line, the output terminal of the first output pull-down circuit is connected to the output terminal of the output circuit, and the first output pull-down circuit is configured to respond to a second driving signal on the control terminal of the first output pull-down circuit to reduce a falling time of the gate driving signal at the output terminal of the output circuit by the first power supply voltage; The gate line is connected to the plurality of pixel units in the pixel row and provides the gate driving signal to the plurality of pixel units, the gate line comprises a first end and a second end located at both sides of the pixel row, the first end of the gate line is connected to the output end of the output circuit, The shift register also includes a second output pull-down circuit, including a control end, an input end and an output end, the input end of the second output pull-down circuit is connected to the first power supply voltage line, the second end of the gate line is connected to the output end of the second output pull-down circuit, and the second output pull-down circuit is configured to respond to a third drive signal on the control end of the second output pull-down circuit, and reduce the falling time of the gate drive signal at the second end through the first power supply voltage.

2. The display substrate according to claim 1, wherein: The second driving signal is the same as the third driving signal.

3. The display substrate according to claim 1, wherein: The base substrate comprises a display area and a peripheral area, wherein the peripheral area comprises a first sub-peripheral area and a second sub-peripheral area located on both sides of the display area. The input circuit, the output circuit and the first output pull-down circuit of the shift register are located in one of the first sub-peripheral area and the second sub-peripheral area, and the second output pull-down circuit of the shift register is located in the other of the first sub-peripheral area and the second sub-peripheral area.

4. The display substrate according to claim 3, wherein: The display substrate comprises M shift registers and M gate lines, the M shift registers respectively provide gate drive signals for the M gate lines, the i-th shift register provides the gate drive signal for the i-th gate line, i is a positive integer greater than or equal to 1 and less than or equal to M, The 2n+1th shift register among the M shift registers is located in the first sub-peripheral area, and the 2n+2th shift register is located in the second sub-peripheral area, where n is an integer greater than or equal to 0.

5. The display substrate according to claim 4, wherein: The first sub-peripheral area includes a first register area and a 2j+1th register area, the second sub-peripheral area includes a second register area and a 2j+2th register area, the first register area and the second register area are arranged at a relative interval, and the 2j+1th register area and the 2j+2th register area are arranged at a relative interval, The first register region is provided with an input circuit, an output circuit, and a first output pull-down circuit of the first shift register, and a second output pull-down circuit of the second shift register; the second register region is provided with an input circuit, an output circuit, and a first output pull-down circuit of the second shift register, and a second output pull-down circuit of the first shift register; The 2j+1th register region is provided with an input circuit, an output circuit, and a first output pull-down circuit of the 2j+1th shift register and a second output pull-down circuit of the 2j+2th shift register, and the 2j+2th register region is provided with an input circuit, an output circuit, and a first output pull-down circuit of the 2j+2th shift register and a second output pull-down circuit of the 2j+1th shift register, j is a positive integer greater than or equal to 1.

6. The display substrate according to claim 4, wherein: The first sub-peripheral area includes a first register area and a 2j+1th register area, the second sub-peripheral area includes a second register area and a 2j+2th register area, the first register area and the second register area are arranged at a relative interval, and the 2j+1th register area and the 2j+2th register area are arranged at a relative interval, The first register region is provided with an input circuit, an output circuit and a first output pull-down circuit of the first shift register, and the second register region is provided with an input circuit, an output circuit and a first output pull-down circuit of the second shift register and a second output pull-down circuit of the first shift register, The 2j+1th register region is provided with an input circuit, an output circuit, and a first output pull-down circuit of the 2j+1th shift register, and a second output pull-down circuit of the 2jth shift register; the 2j+2th register region is provided with an input circuit, an output circuit, and a first output pull-down circuit of the 2j+2th shift register, and a second output pull-down circuit of the 2j+1th shift register; j is a positive integer greater than or equal to 1.

7. The display substrate according to claim 6, wherein: The second output pull-down circuit of the first shift register is arranged on a side of the second register region away from the 2j+2nd shift register.

8. The display substrate according to any one of claims 4 to 7, wherein: The control end of the first output pull-down circuit of the mth shift register is electrically connected to the output end of the output circuit of the m+kth shift register, where m is a positive integer greater than or equal to 1, and k is a positive integer greater than or equal to 1.

9. The display substrate according to claim 8, wherein: The display substrate includes p clock signal lines, and k=p / 2.

10. The display substrate according to claim 8, wherein: The control end of the second output pull-down circuit of the mth shift register is electrically connected to the output end of the output circuit of the (m+k)th shift register.

11. The display substrate according to any one of claims 4 to 7, wherein: The input circuit includes an input transistor, the output circuit includes an output transistor, the first output pull-down circuit includes a first pull-down transistor, The input transistor includes a gate, a first electrode and a second electrode, the output transistor includes a gate, a first electrode and a second electrode, and the first pull-down transistor includes a gate, a first electrode and a second electrode. The second electrode of the input transistor and the gate of the output transistor are connected to a first node, the first electrode of the output transistor is connected to the clock signal line, the first electrode of the first pull-down transistor is configured to receive a first power supply voltage, and the second electrode of the first pull-down transistor is connected to the second electrode of the output transistor.

12. The display substrate according to claim 11, wherein: The 2n+1th shift register and the 2n+2th shift register are arranged with relative intervals; In the 2n+1th shift register, the orthographic projection of the first pull-down transistor on the substrate is located on a side of the orthographic projection of the output transistor on the substrate close to the 2n+2th shift register; In the 2n+2nd shift register, the orthographic projection of the first pull-down transistor on the substrate is located on a side of the orthographic projection of the output transistor on the substrate close to the 2n+1st shift register.

13. The display substrate according to claim 11, wherein: The second output pull-down circuit includes a second pull-down transistor including a gate, a first electrode and a second electrode. A first electrode of the second pull-down transistor is configured to receive a first power supply voltage, and a second electrode of the second pull-down transistor is connected to the second end of the gate line.

14. The display substrate according to claim 13, wherein: The 2n+1th shift register and the 2n+2th shift register are arranged with relative intervals; The orthographic projection of the second pull-down transistor of the 2n+1th shift register on the substrate is located between the orthographic projection of the output transistor of the 2n+2th shift register on the substrate and the orthographic projection of the first pull-down transistor of the 2n+2th shift register on the substrate; The orthographic projection of the second pull-down transistor of the 2n+2th shift register on the substrate is located between the orthographic projection of the output transistor of the 2n+1th shift register on the substrate and the orthographic projection of the first pull-down transistor of the 2n+1th shift register on the substrate.

15. The display substrate according to claim 13, wherein: A channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor.

16. The display substrate according to claim 15, wherein: A channel width-to-length ratio of the first pull-down transistor is smaller than a channel width-to-length ratio of the output transistor, and a channel width-to-length ratio of the second pull-down transistor is larger than a channel width-to-length ratio of the output transistor.

17. The display substrate according to any one of claims 1 to 16, wherein: The shift register further includes a first control circuit, a second control circuit and a first noise reduction circuit and a second noise reduction circuit; The output terminal of the first control circuit and the output terminal of the second control circuit are connected to a second node, the control terminal and the input terminal of the first control circuit are connected to a second power supply voltage line, the input terminal of the second control circuit is configured to receive a first power supply voltage, and the control terminal of the second control circuit is connected to the first node. The first control circuit is configured to respond to a second power supply voltage on a second power supply voltage line and pull up the potential of the second node through the second power supply voltage, and the second control circuit is configured to respond to a signal on the first node to pull down the potential on the second node through the first power supply voltage; The control end of the first noise reduction circuit and the control end of the second noise reduction circuit are connected to the second node, the input end of the first noise reduction circuit and the input end of the second noise reduction circuit are configured to receive a first power supply voltage, the output end of the first noise reduction circuit is connected to the first node, and the output end of the second noise reduction circuit is connected to the output end of the output circuit, The first noise reduction circuit is configured to respond to a signal on the second node to reduce noise on the first node through the first power supply voltage, and the second noise reduction circuit is configured to respond to a signal on the second node to reduce noise on an output end of the output circuit through the first power supply voltage.

18. The display substrate according to claim 17, wherein: The first control circuit includes a first control transistor, the second control circuit includes a second control transistor, the first noise reduction circuit includes a first noise reduction transistor, the second noise reduction circuit includes a second noise reduction transistor, The first control transistor includes a gate, a first electrode and a second electrode, the second control transistor includes a gate, a first electrode and a second electrode, the first noise reduction transistor includes a gate, a first electrode and a second electrode, and the second noise reduction transistor includes a gate, a first electrode and a second electrode. The first electrode and the gate of the first control transistor are connected to the second power supply voltage line, the second electrode of the first control transistor and the second electrode of the second control transistor are connected to a second node, the gate of the second control transistor is connected to the first node, and the first electrode of the second control transistor is configured to receive a first power supply voltage. The gate of the first noise reduction transistor and the gate of the second noise reduction transistor are connected to the second node, the first electrode of the first noise reduction transistor and the first electrode of the second noise reduction transistor are configured to receive a first power supply voltage, the second electrode of the first noise reduction transistor is connected to the first node, and the second electrode of the second noise reduction transistor is connected to the output end of the output circuit.

19. The display substrate according to claim 17, wherein: The shift register further includes a clearing circuit, including a control terminal, an input terminal and an output terminal. The control end of the clearing circuit is configured to respond to a fourth driving signal and clear the signal on the first node by dropping a first power supply voltage.

20. The display substrate according to claim 19, wherein: The display substrate includes p clock signal lines, and the control end of the clear circuit of the nth shift register is electrically connected to the output end of any one of the n+kth to n+p-1th shift registers, where k=p / 2.

21. The display substrate according to claim 19, wherein: The clearing circuit includes a clearing transistor including a gate, a first electrode and a second electrode. The first electrode of the clearing transistor is configured to receive a first power supply voltage, and the second electrode of the clearing transistor is connected to the first node.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

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