Memory and manufacturing method therefor, and electronic device

Abstract

The present disclosure relates to the technical field of semiconductors, and relates to a memory and a manufacturing method therefor, and an electronic device, for use in solving the problem of how to reduce the parasitic capacitance of the memory. The memory comprises transistors (2), a word line (WL), and a bit line (BL); the word line (WL) extends in a direction perpendicular to a substrate (1); the transistors (2) each comprise a semiconductor layer (21) located on a side wall of the word line (WL), and a gate insulating layer (22) provided between the side wall of the word line (WL) and the semiconductor layer (21); the bit line (BL) comprises a bit line main body (111) and different first branches (112) corresponding to different transistors (2); the bit line main body (111) extends in a first direction parallel to the substrate (1); the first branches (112) extend towards the semiconductor layer (21) and are connected to the semiconductor layer (21). The present disclosure can reduce the parasitic capacitance of the memory, thereby further improving the performance of the memory.

Description

Memory and manufacturing method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on March 28, 2023, with application number 202310314393.2 and invention name “Memory, manufacturing method thereof, and electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a memory, a manufacturing method thereof, and an electronic device. Background Art

[0004] With the development of communication and digital technologies, people continue to pursue products with lower power consumption, lighter weight, and higher performance. Three-dimensional dynamic random access memory (3D-DRAM), which offers higher integration density and larger storage capacity, has gradually become a key research direction in memory. However, the traditional manufacturing processes currently used to produce 3D-DRAM are prone to generating large parasitic capacitance within the 3D-DRAM, leading to noise introduction issues. This hinders further improvements in 3D-DRAM structure and performance.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a memory, a method for manufacturing the same, and an electronic device.

[0007] According to some embodiments, the present disclosure provides a memory device. The memory device includes a word line, a transistor, and a bit line. The word line extends in a direction perpendicular to a substrate. The transistor includes a semiconductor layer located on or surrounding the sidewalls of the word line and a gate insulating layer disposed between the sidewalls of the word line and the semiconductor layer. The bit line includes a bit line body and different first branches corresponding to different transistors. The bit line body extends in a first direction parallel to the substrate. The first branches extend toward the semiconductor layer and are connected to the semiconductor layer.

[0008] According to some embodiments, the number of first branches corresponding to the same transistor in the bit line is two, and a first accommodating cavity is formed between the two first branches and the bit line body and the gate insulating layer. The memory further includes: a first insulating layer filled in the first accommodating cavity.

[0009] According to some embodiments, the first branch and the bit line body are formed by patterning a conductive film layer. The first branch and the bit line body have the same film thickness, which is a dimension in a direction perpendicular to the substrate.

[0010] According to some embodiments, the semiconductor layer includes two sub-layers extending along sidewalls of the word line, the two sub-layers are spaced apart in a first direction, and the two sub-layers are connected to the two first branches in a one-to-one correspondence.

[0011] According to some embodiments, the memory further includes a capacitor. The capacitor includes a first electrode connected to the semiconductor layer. The first electrode includes two second branches. The two second branches are respectively connected to the two sub-film layers of the semiconductor layer in a one-to-one correspondence.

[0012] In some embodiments, the first electrode further includes a first electrode body connecting the two second branches. The first electrode body and the second branches are arranged sequentially along a second direction, which is parallel to the substrate and intersects the first direction. A second accommodation cavity is formed between the first electrode body, the two second branches, and the gate insulating layer. The memory further includes a second insulating layer filling the second accommodation cavity.

[0013] According to some embodiments, the capacitor further includes a second electrode disposed between the first electrode and the second insulating layer, and a first dielectric layer surrounding a sidewall of the second electrode.

[0014] According to some embodiments, the capacitor further includes a second dielectric layer and a third electrode stacked on an outer surface of the first electrode, wherein the third electrode is connected to the second electrode.

[0015] According to some embodiments, there are multiple transistors, and the multiple transistors are distributed in one layer, or distributed in different layers stacked in a direction perpendicular to the substrate.

[0016] According to some embodiments, the present disclosure further provides a method for manufacturing a memory, comprising the following steps.

[0017] A conductive film layer is formed on the substrate.

[0018] The patterned conductive film layer forms a bit line. The bit line includes: a bit line body extending along a first direction parallel to the substrate, and a plurality of first branches arranged at intervals in the first direction.

[0019] Transistors and word lines are formed correspondingly at the extended ends of two adjacent first branches; wherein the word line extends in a direction perpendicular to the substrate; the transistor includes a semiconductor layer located on or surrounding the sidewalls of the word line and a gate insulating layer arranged between the sidewalls of the word line and the semiconductor layer; the first branch extends toward the semiconductor layer and is connected to the semiconductor layer.

[0020] According to some embodiments, a first accommodating cavity is formed between the two first branches corresponding to the same transistor, the bit line body, and the gate insulating layer. The manufacturing method further includes: filling the first accommodating cavity with an insulating material to form a first insulating layer.

[0021] According to some embodiments, the memory further includes a capacitor. The capacitor includes a first electrode. The manufacturing method further includes: forming the first electrode simultaneously with the bit line during patterning of the conductive film layer. The first electrode includes two second branches spaced apart in a first direction. The semiconductor layer is further connected to the two second branches.

[0022] According to some embodiments, the first electrode further includes a first electrode body connecting the two second branches. The first electrode body and the second branches are arranged sequentially along a second direction parallel to the substrate, and a second accommodating cavity is formed between the first electrode body, the two second branches, and the gate insulating layer. The manufacturing method further includes filling the second accommodating cavity with an insulating material to form a second insulating layer.

[0023] According to some embodiments, forming transistors and word lines corresponding to the extending ends of two adjacent first branches includes the following steps.

[0024] Before forming the first insulating layer and the second insulating layer, a sacrificial material is filled in the region between the first electrode body, the two second branches, the two first branches and the bit line body.

[0025] Part of the sacrificial material is removed to form an accommodation hole; the accommodation hole is used to define the formation area of ​​the transistor and the word line.

[0026] An initial semiconductor layer, a gate insulating layer and a word line are sequentially formed on the inner wall of the accommodating hole.

[0027] The remaining sacrificial material is removed to expose a first sidewall of the initial semiconductor layer facing the first electrode and a second sidewall of the initial semiconductor layer facing the bit line.

[0028] The initial semiconductor layer is etched based on the first sidewall and the second sidewall to expose the gate insulating layer, and the remaining initial semiconductor layer is formed into two sub-film layers spaced apart in the first direction, and both ends of each sub-film layer are respectively connected to the first branch and the second branch.

[0029] According to some embodiments, the memory manufacturing method further includes: forming a second electrode between the first electrode and the second insulating layer, and a first dielectric layer surrounding a sidewall of the second electrode.

[0030] According to some embodiments, the manufacturing method of the memory further includes: forming a first dielectric layer between the first electrode and the second insulating layer, while forming a second dielectric layer on the outer surface of the first electrode; forming a third electrode on the outer surface of the second dielectric layer while forming the second electrode between the first electrode and the second insulating layer, and connecting the third electrode to the second electrode.

[0031] According to some embodiments, the present disclosure further provides a memory on another aspect, comprising: a conductive film layer, a gate, a semiconductor layer, and a gate insulating layer. The conductive film layer comprises: a bit line region extending along the column direction, and a source region and a drain region sequentially distributed in the row direction toward the bit line region. The drain region is connected to the bit line region. There is a gap between the source region and the drain region. The gate is located between the source region and the drain region and extends in a direction perpendicular to the substrate. The semiconductor layer is arranged on the side wall of the gate. The gate insulating layer is arranged between the side wall of the gate and the semiconductor layer. At least one of the source region and the drain region includes two third branches, and the two third branches are simultaneously connected to the semiconductor layer.

[0032] According to some embodiments, the third branch has the same film thickness as that of the bit line region, where the film thickness is a dimension in a direction perpendicular to the substrate.

[0033] According to some embodiments, the semiconductor layer includes two spaced-apart subregions; the two subregions extend along the row direction on the gate sidewalls, and an extended end of any subregion is connected to an extended end of the third branch of the source region or the drain region.

[0034] According to some embodiments, the conductive film layer further includes a first electrode region, wherein the first electrode region, the source region, and the drain region are sequentially distributed in a row direction toward the bit line region, and the first electrode region is connected to the source region.

[0035] According to some embodiments, the source region includes two third branches, and the first electrode region includes two second branches, wherein the two second branches are connected to the two third branches of the source region in a one-to-one correspondence.

[0036] According to some embodiments, another aspect of the present disclosure provides an electronic device, comprising the memory as described in any of the above embodiments.

[0037] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0039] FIG1 is a schematic diagram of the structure of a memory provided in some embodiments; FIG1a is a schematic cross-sectional view of a memory shown in FIG1 at section C1; FIG1b is a schematic cross-sectional view of a memory shown in FIG1 at section C2; FIG1c is a schematic cross-sectional view of a memory shown in FIG1 at section C3;

[0040] FIG2 is a schematic flow chart of a method for manufacturing a memory provided in some embodiments;

[0041] FIG3 is a schematic flow chart of another method for manufacturing a memory provided in some embodiments;

[0042] FIG4 is a schematic diagram of a flow chart of step 30 provided in some embodiments;

[0043] FIG5 is a schematic diagram of a structure obtained after forming a first mask layer in some embodiments; FIG5a is a schematic cross-sectional view of a structure shown in FIG5 at section C1; FIG5b is a schematic cross-sectional view of a structure shown in FIG5 at section C2; FIG5c is a schematic cross-sectional view of a structure shown in FIG5 at section C3;

[0044] FIG6 is a schematic diagram of a structure obtained after forming an isolation layer in some embodiments; FIG6a is a schematic cross-sectional view of a structure shown in FIG6 at section C1; FIG6b is a schematic cross-sectional view of a structure shown in FIG6 at section C2; FIG6c is a schematic cross-sectional view of a structure shown in FIG6 at section C3;

[0045] FIG7 is a schematic diagram of a structure obtained after forming a second sacrificial layer in some embodiments; FIG7a is a schematic cross-sectional view of a structure shown in FIG7 at section C1; FIG7b is a schematic cross-sectional view of a structure shown in FIG7 at section C2; FIG7c is a schematic cross-sectional view of a structure shown in FIG7 at section C3;

[0046] FIG8 is a schematic diagram of a structure obtained after exposing the first electrode in some embodiments; FIG8a is a schematic cross-sectional view of a structure shown in FIG8 at section C1; FIG8b is a schematic cross-sectional view of a structure shown in FIG8 at section C4; FIG8c is a schematic cross-sectional view of a structure shown in FIG8 at section C3;

[0047] FIG9 is a schematic diagram of a structure obtained after forming a capacitor in some embodiments; FIG9a is a schematic cross-sectional view of a structure shown in FIG9 at section C1; FIG9b is a schematic cross-sectional view of a structure shown in FIG9 at section C4; FIG9c is a schematic cross-sectional view of a structure shown in FIG9 at section C3;

[0048] FIG10 is a schematic diagram of a structure obtained after forming an accommodating hole in some embodiments; FIG10a is a schematic cross-sectional view of a structure shown in FIG10 at section C1; FIG10b is a schematic cross-sectional view of a structure shown in FIG10 at section C2; FIG10c is a schematic cross-sectional view of a structure shown in FIG10 at section C3;

[0049] FIG11 is a schematic diagram of a structure obtained after word lines are formed in some embodiments; FIG11a is a schematic cross-sectional view of a structure shown in FIG11 at section C1; FIG11b is a schematic cross-sectional view of a structure shown in FIG11 at section C2; FIG11c is a schematic cross-sectional view of a structure shown in FIG11 at section C3;

[0050] FIG12 is a schematic diagram of a structure obtained after forming a sub-film layer of a semiconductor layer in some embodiments; FIG12a is a schematic cross-sectional view of a structure shown in FIG12 at section C1; FIG12b is a schematic cross-sectional view of a structure shown in FIG12 at section C2; FIG12c is a schematic cross-sectional view of a structure shown in FIG12 at section C3;

[0051] Figure 13 is a structural schematic diagram of another memory provided in some embodiments; Figure 13a is a cross-sectional schematic diagram of a memory shown in Figure 13 on the C1 section; Figure 13b is a cross-sectional schematic diagram of a memory shown in Figure 13 on the C2 section; Figure 13c is a cross-sectional schematic diagram of a memory shown in Figure 13 on the C3 section. DETAILED DESCRIPTION

[0052] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0054] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0055] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0056] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0057] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present disclosure.

[0058] Some embodiments of the present disclosure provide a memory. Referring to FIG. 1 and FIG. 1a, FIG. 1b, and FIG. 1c, the memory includes: a word line WL, a transistor 2, and a bit line BL. The word line WL extends in a direction perpendicular to the substrate 1 (e.g., the Z direction). The transistor 2 includes a semiconductor layer 21 located on or surrounding the sidewall of the word line WL and a gate insulating layer 22 disposed between the sidewall of the word line WL and the semiconductor layer 21. The bit line BL includes a bit line body 111 and different first branches 112 corresponding to different transistors 2. The bit line body 111 extends in a first direction parallel to the substrate 1 (e.g., the Y direction). The first branch 112 extends toward the semiconductor layer 21 and is connected to the semiconductor layer 21.

[0059] The semiconductor layer 21 surrounding the word line WL may be understood as not completely surrounding the word line WL, but rather surrounding a portion of the sidewalls of the word line WL, for example, laterally spaced apart and physically disconnected. For example, the semiconductor layer 21 may extend perpendicularly along the sidewalls of the word line WL and parallel to the extension direction of the first branches 112. The semiconductor layer 21 may not be disposed between two adjacent first branches 112 belonging to the same transistor 2.

[0060] In some embodiments, the memory includes one or more memory layers M stacked in a direction perpendicular to the substrate 1 (e.g., the Z direction). Accordingly, the number of transistors 2 is multiple. The multiple transistors 2 can be distributed in one memory layer M. Alternatively, the multiple transistors 2 can be distributed in different memory layers M stacked in a direction perpendicular to the substrate 1.

[0061] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0062] For example, each transistor 2 in each storage layer M can serve as a transistor of a corresponding storage unit, and the storage unit can be, for example, a 1T1C, 1T0C or 2T0C architecture. Taking the 1T1C architecture as an example, the storage unit can include a capacitor and a transistor connected to the capacitor. For example, in a 3D-DRAM, a plurality of storage cells can be distributed in an array in a plane parallel to the substrate 1 (for example, an XY plane), and periodically stacked in a direction perpendicular to the substrate 1 (for example, in the Z direction) to form a multi-layer storage layer M.

[0063] In some embodiments, please refer to Figure 1a for understanding. Figure 1a illustrates an embodiment in which two columns of memory cells share a bit line (BL). In this memory layer M, the bit line (BL) is parallel to the substrate 1 and extends along the Y direction. Multiple transistors 2 can be arranged in rows along the Y direction on both sides of the corresponding bit line (BL). This allows the memory cells to be arranged on both sides of the corresponding bit line (BL) (which can be understood as each transistor 2 being arranged in the two regions separated by the bit line (BL)).

[0064] In some embodiments, as shown in FIG1a , there are two first branches 112 corresponding to the same transistor 2 in the bit line BL, and a first accommodating cavity X1 is formed between the two first branches 112, the bit line body 111, and the gate insulating layer 22. The memory further includes a first insulating layer 31 filling the first accommodating cavity X1.

[0065] By way of example, the first insulating layer 31 includes but is not limited to a silicon oxide layer.

[0066] In the disclosed embodiment, the bit line BL includes a bit line body 111 and different first branches 112 corresponding to different transistors 2. The first branches 112 extend toward and connect to the semiconductor layer 21 of the transistor 2. The first insulating layer 31 can be provided in a first accommodating cavity X1 formed between the first branches 112, the bit line body 111, and the gate insulating layer 22. This effectively improves the isolation between the word line WL and the bit line BL, avoids a large relative area between the bit line BL and the semiconductor layer 21, and minimizes parasitic capacitance. This can further improve memory performance.

[0067] In some embodiments, referring to FIG. 1 a , the first branch 112 and the bitline body 111 are formed by patterning a conductive film layer. The first branch 112 and the bitline body 111 have the same film thickness, which is the dimension perpendicular to the substrate 1 (e.g., the Z direction).

[0068] Here, the first branch 112 of the bit line BL and the bit line body 111 are formed based on a patterning process of the same conductive film layer, which is beneficial for simplifying the manufacturing process of the memory and improving production efficiency.

[0069] For example, the conductive film layer may be a metal layer, such as a tungsten metal layer or a copper metal layer.

[0070] 1a and 1b , the semiconductor layer 21 includes two sub-layers 211 extending along the sidewalls of the word lines WL. The two sub-layers 211 are spaced apart in a first direction and are connected to the two first branches 112 in a one-to-one correspondence.

[0071] Here, the semiconductor layer 21 may at least serve as a channel layer of the transistor 2 in the corresponding memory cell.

[0072] For example, the sub-film layer 211 in the semiconductor layer 21 may be a metal oxide semiconductor layer, for example, a metal oxide semiconductor material including at least one of indium, gallium, zinc or tin.

[0073] In some examples, the sub-film layer 211 in the semiconductor layer 21 may be an indium gallium zinc oxide (IGZO) layer, but is not limited thereto.

[0074] In addition, the word line WL is a gate word line, which can be used as a memory word line WL and also serve as a gate of the transistor 2 in each corresponding memory cell, thereby controlling the on and off of the transistor 2.

[0075] For example, the material of the word line WL includes metal, such as metal tungsten or metal copper.

[0076] For example, the orthographic projection shape of the word line WL on the surface of the substrate 1 includes but is not limited to a rectangle. The rectangle mentioned here can be an ideal rectangle with right angles, or an approximate rectangle including etching deviations or transition rounded corners.

[0077] Illustratively, the gate insulating layer 22 includes, but is not limited to, a HK dielectric layer.

[0078] It should be noted that the semiconductor layers 21 arranged adjacent to each other in a direction perpendicular to the substrate 1 in each memory layer M can be manufactured by etching the same initial semiconductor layer, and the corresponding manufacturing method is detailed in the relevant description later in this specification. The disclosed embodiment can minimize unnecessary semiconductor material between the capacitor 4 and the bit line BL, thereby minimizing parasitic capacitance and further optimizing memory performance.

[0079] In some embodiments, referring to Figures 1, 1a, and 1c, the memory further includes a capacitor 4. Capacitor 4 includes a first electrode 41 connected to semiconductor layer 21. First electrode 41 includes a first electrode body 411 and two second branches 412. The two second branches 412 are connected to the two sub-membrane layers 211 of semiconductor layer 21 in a one-to-one correspondence.

[0080] In some embodiments, referring to Figures 1a and 1c, a first electrode body 411 in a first electrode 41 is connected to two second branches 412. The first electrode body 411 and the second branches 412 are arranged sequentially along a second direction (e.g., the X direction), which is parallel to the substrate 1 and intersects the first direction (e.g., the Y direction). A second accommodating cavity X2 is formed between the first electrode body 411, the two second branches 412, and the gate insulating layer 22. The memory further includes a second insulating layer 32 filling the second accommodating cavity X2.

[0081] By way of example, the second insulating layer 32 includes, but is not limited to, a silicon oxide layer.

[0082] In the disclosed embodiment, the first electrode 41 includes a first electrode body 411 and two second branches 412, with the second branches 412 extending toward and connected to the semiconductor layer 21 of the transistor 2. The second accommodating cavity X2 formed between the second branches 412, the first electrode body 411, and the gate insulating layer 22 can be used to provide the second insulating layer 32. This effectively improves the isolation between the word line WL and the first electrode 41 of the capacitor 4, and avoids a large relative area between the first electrode 41 of the capacitor 4 and the semiconductor layer 21, thereby minimizing parasitic capacitance and further improving memory performance.

[0083] In some embodiments, referring to FIG. 1 a and FIG. 1 c , the capacitor 4 further includes a second electrode 42 disposed between the first electrode 41 and the second insulating layer 32 , and a first dielectric layer 43 surrounding a sidewall of the second electrode 42 .

[0084] For example, the orthographic projection shape of the second electrode 42 on the surface of the substrate 1 includes but is not limited to a rectangle. The rectangle mentioned here can be an ideal rectangle with right angles, or an approximate rectangle including etching deviations or transition rounded corners.

[0085] 1 a and 1 c , the capacitor 4 further includes a second dielectric layer 44 and a third electrode 45 stacked on the outer surface of the first electrode 41 . The third electrode 45 is connected to the second electrode 42 .

[0086] For example, the first dielectric layer 43 and the second dielectric layer 44 may be formed of the same dielectric material and through the same deposition process.

[0087] For example, the first dielectric layer 43 and the second dielectric layer 44 include but are not limited to HK (high-K) dielectric layers, which are dielectric layers with a high dielectric constant K, for example, greater than 3.9.

[0088] In addition, the deposition processes mentioned above and below include but are not limited to atomic layer deposition (ALD) process, chemical vapor deposition (CVD) process, molecular layer deposition (MLD) process, etc.

[0089] For example, the second electrode 42 and the third electrode 45 may be made of the same conductive material and formed through the same deposition process.

[0090] By way of example, the second electrode 42 and the third electrode 45 include, but are not limited to, polysilicon.

[0091] It should be noted that, referring to Figures 1, 1a, and 1c, in some embodiments, in the same memory layer M, multiple second dielectric layers 44 of a column of capacitors 4 arranged along a first direction (e.g., the Y direction) can be connected as a whole, and multiple third electrodes 45 of the column of capacitors 4 can be connected as a whole. Furthermore, in some embodiments, in different memory layers M, multiple third electrodes 45 of capacitors 4 located on the same side of the bit line BL can be connected as a whole.

[0092] In addition, optionally, in different storage layers M of some embodiments, as shown in FIG. 1 c , the first dielectric layers 43 of the capacitors 4 that are adjacently arranged in a direction perpendicular to the substrate 1 (eg, the Z direction) are integrally connected.

[0093] Optionally, as shown in FIG. 1 c , in the storage layer M adjacent to the substrate 1 , the first dielectric layer 43 further extends and is located between the third electrode 45 and the substrate 1 .

[0094] It is worth mentioning that, to match the arrangement of the conductive elements (e.g., bit lines BL, word lines WL, first electrodes 41, second electrodes 42, and third electrodes 45) in the above-mentioned memory, the memory may further include other insulating layers in addition to the first insulating layer 31 and the second insulating layer 32, such as the third insulating layer 33 and the fourth insulating layer 34 in FIG. 1b, to meet the insulation requirements between adjacent conductive elements or between a conductive element and the outside. This embodiment of the present disclosure will not be discussed in detail.

[0095] Some embodiments of the present disclosure also provide a method for manufacturing a memory, which is used to prepare the memory in some of the above embodiments. The manufacturing method also has the technical advantages of the above memories.

[0096] Please refer to FIG. 2 and understand in combination with FIG. 1 , FIG. 1 a , FIG. 1 b and FIG. 1 c , the manufacturing method includes the following steps.

[0097] S10 , forming a conductive film layer on the substrate 1 .

[0098] S20 , patterning the conductive film layer to form a bit line BL. The bit line BL includes a bit line body 111 extending in a first direction (eg, Y direction) parallel to the substrate 1 , and a plurality of first branches 112 spaced apart in the first direction (eg, Y direction).

[0099] S30, a transistor 2 and a word line WL are formed correspondingly at the extended ends of two adjacent first branches 112; wherein the word line WL extends in a direction perpendicular to the substrate 1 (for example, in the Z direction); the transistor 2 includes a semiconductor layer 21 located on the sidewall of the word line WL and a gate insulating layer 22 arranged between the sidewall of the word line WL and the semiconductor layer 21; the first branch 112 extends toward the semiconductor layer 21 and is connected to the semiconductor layer 21.

[0100] In some embodiments, as shown in Figure 1a, a first accommodating cavity X1 is formed between two first branches 211 corresponding to the same transistor 2, the bit line body 111, and the gate insulating layer 22. Referring to Figure 3 and in conjunction with Figure 1a, the manufacturing method further includes S40.

[0101] S40 , filling the first receiving cavity X1 with insulating material to form a first insulating layer 31 .

[0102] In some embodiments, as understood in conjunction with Figures 1, 1a, and 1c, the memory device further includes a capacitor 4. Capacitor 4 includes a first electrode 41. The manufacturing method further includes: forming the first electrode 41 simultaneously with the bit line BL during patterning of the conductive film layer. The first electrode 41 includes two second branches 412 spaced apart in a first direction (e.g., the Y direction). The semiconductor layer 21 is further connected to the two second branches 412.

[0103] In some embodiments, as understood in conjunction with Figures 1, 1a, and 1c, the first electrode 41 further includes a first electrode body 411 connecting two second branches 412. The first electrode body 411 and the second branches 412 are sequentially arranged along a second direction (e.g., the X direction) parallel to the substrate 1, and a second accommodating cavity X2 is formed between the first electrode body 411, the two second branches 412, and the gate insulating layer 22. Referring to Figure 3 in conjunction with Figure 1a, the manufacturing method further includes S50.

[0104] S50 , filling the second receiving cavity X2 with insulating material to form a second insulating layer 32 .

[0105] In some embodiments, referring to FIG. 4 and in combination with FIG. 1 , FIG. 1 a , FIG. 1 b and FIG. 1 c , the transistor 2 and the word line WL are formed correspondingly at the extended ends of two adjacent first branches 112 in step S30 , including but not limited to the following steps.

[0106] S301 , before forming the first insulating layer 31 and the second insulating layer 32 , a sacrificial material is filled in a region between the first electrode body 411 , the two second branches 412 , the two first branches 112 and the bit line body 111 .

[0107] S302 , removing part of the sacrificial material to form an accommodation hole; the accommodation hole is used to define the formation area of ​​the transistor 2 and the word line WL.

[0108] S303 , an initial semiconductor layer, a gate insulating layer 22 and a word line WL are sequentially formed on the inner wall of the receiving hole.

[0109] S304 , removing the remaining sacrificial material to expose a first sidewall of the initial semiconductor layer facing the first electrode 41 and a second sidewall of the initial semiconductor layer facing the bit line BL.

[0110] S305, based on the first side wall and the second side wall, the initial semiconductor layer is etched until the gate insulation layer 22 is exposed, and the remaining initial semiconductor layer is formed into two sub-membrane layers 211 spaced apart in the first direction (for example, the Y direction), and the two ends of each sub-membrane layer 211 are respectively connected to the first branch 112 and the second branch 412.

[0111] In some embodiments, please refer to FIG. 1 , FIG. 1 a and FIG. 1 c to understand that the memory manufacturing method further includes S60 .

[0112] S60 , forming a second electrode 42 between the first electrode 41 and the second insulating layer 32 , and a first dielectric layer 43 surrounding the sidewalls of the second electrode 42 .

[0113] In some embodiments, please refer to FIG. 1 , FIG. 1 a and FIG. 1 c to understand that the memory manufacturing method further includes S601 and S602 .

[0114] S601 , forming a first dielectric layer 43 between the first electrode 41 and the second insulating layer 32 , and forming a second dielectric layer 44 on the outer surface of the first electrode 41 .

[0115] S602 , while forming the second electrode 42 between the first electrode 41 and the second insulating layer 32 , a third electrode 45 is formed on the outer surface of the second dielectric layer 44 and connected to the second electrode 42 .

[0116] It is understood that some of the steps in the above-mentioned memory manufacturing method are shown in sequence as indicated by the arrows in Figures 2, 3, and 4, but these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction for the execution of these steps, and they can be performed in other orders. Moreover, at least some of the steps in Figures 2, 3, and 4 may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily sequential, but can be performed simultaneously, in turn, or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0117] In order to more clearly illustrate the memory manufacturing methods in some of the above embodiments, the following embodiments exemplarily provide some possible specific implementations of some steps.

[0118] In step S10 , referring to FIG. 5 and FIG. 5 a , FIG. 5 b , and FIG. 5 c , multiple conductive film layers L1 and multiple first sacrificial layers L21 are stacked and alternately distributed along a direction perpendicular to the substrate 1 (eg, the Z direction) and are formed.

[0119] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0120] Illustratively, the conductive film layer L1 includes a metal layer, such as a metal tungsten layer.

[0121] Illustratively, the first sacrificial layer L21 includes, but is not limited to, a silicon nitride layer.

[0122] Here, the number of stacked conductive film layers L1 can be set based on the number of stacked memory layers M in the memory. Furthermore, the first sacrificial layer L21 can be located between adjacent conductive film layers L1 or on one side of the first and last conductive film layers L1. The number of first sacrificial layers L21 can match the number of stacked conductive film layers L1. Each conductive film layer L1 and each first sacrificial layer L21 can be formed using a deposition process.

[0123] In addition, after forming the alternating stack of multi-layer conductive film layers L1 and multi-layer first sacrificial layers L21, a first mask layer Y1, such as a photoresist layer and / or a hard mask layer, can be formed on the upper surface of the top first sacrificial layer L21, thereby facilitating the subsequent etching of each conductive film layer L1 and each first sacrificial layer L21 based on the mask pattern in the first mask layer Y1.

[0124] In step S20, referring to Figure 6 and Figures 6a, 6b, and 6c, an etching process is performed on the multi-layer conductive film layer L1 and the multi-layer first sacrificial layer L21 to form a bit line BL in the conductive film layer L1 and a plurality of conductive units 30 that are integrally connected to the bit line BL and arranged at intervals in a first direction (for example, the Y direction) to obtain an initial stacked structure A.

[0125] For example, the conductive film layer L1 and the first sacrificial layer L21 in the initial stacked structure A can be etched based on the pattern of the first mask layer Y1 to have the same pattern, such as shown in Figure 6a. The patterned conductive film layer L1 includes: a bit line BL extending along a column direction (e.g., the Y direction) and a plurality of conductive units 3 extending along the bit line BL; each conductive unit 3 extends along the X direction and is spaced apart in the Y direction. Optionally, the conductive units 3 are symmetrically distributed around the bit line BL.

[0126] 6 and 6a, 6b and 6c, after the initial stacked structure A is obtained, an isolation layer L3 is formed to cover the sidewalls of the initial stacked structure A and fill the spaces between adjacent conductive units 3.

[0127] By way of example, the material of the isolation layer L3 includes but is not limited to oxide, such as silicon oxide.

[0128] For example, the isolation layer L3 is formed by a deposition process, and the outline size of the isolation layer L3 can be determined to match the initial stacked structure A and the subsequent arrangement positions of the capacitors 4 .

[0129] It should be noted that, in some embodiments, the isolation layer L3 can be formed before removing the aforementioned first mask layer Y1. Thus, after forming the isolation layer L3, a grinding process can be used to remove the first mask layer Y1 and ensure that the surfaces of the isolation layer L3 and the top first sacrificial layer L21 are smooth. The grinding process includes, but is not limited to, chemical mechanical polishing (CMP).

[0130] 7 and 7a, 7b, and 7c, an etching process is performed on the initial stacked structure A to form a sacrificial trench X at one end of each conductive unit 3 close to the bit line BL, thereby obtaining a first branch 112 of the bit line BL located on the periphery of the sacrificial trench X, a first electrode 41, and a portion to be removed 03 located between the first branch 112 and the first electrode 41.

[0131] Here, the first electrode 41 includes a first electrode body 411 and two second branches 412. The portion to be removed 03 is located between and connected to the first branch 112 and the second branch 412, respectively, and is used to define the formation position of the sub-film layer 211 in the semiconductor layer 21.

[0132] For example, as shown in Figure 7a, the orthographic projection of the sacrificial groove X on the substrate 1 is in the shape of a strip, and the size of the corresponding area in the sacrificial groove X for forming the portion to be removed 03 in the first direction (for example, the Y direction) is larger than the size of other areas in the sacrificial groove X in the first direction (for example, the Y direction).

[0133] 7 and 7a, 7b, and 7c, a second sacrificial layer L22 is filled in the sacrificial groove X to obtain a stacked structure B.

[0134] Here, after the second sacrificial layer L22 is deposited into the sacrificial groove X, a CMP process can be used to polish the upper surface of the stacked structure B. In addition to the patterned conductive film layers L1 and the first sacrificial layers L21, the stacked structure B further includes an isolation layer L3 disposed on the sidewalls of the initial stacked structure A and the second sacrificial layer L22 filled into the sacrificial groove X.

[0135] For example, the material of the second sacrificial layer L22 is the same as that of the first sacrificial layer L21. The second sacrificial layer L22 includes but is not limited to a silicon nitride layer. Based on this, the second sacrificial layer L22 and the first sacrificial layer L21 can be subsequently etched using the same process.

[0136] It can be understood that the second sacrificial layer L22 here is the sacrificial material filled in the area between the first electrode body 411 , the two second branches 412 , the two first branches 112 and the bit line body 111 in step S301 .

[0137] In step S60 , referring to FIG8 and FIG8 a , FIG8 b , and FIG8 c , a second mask layer Y2 is formed on the upper surface of the stacked structure B. The second mask layer Y2 has an opening pattern for defining the formation position of the capacitor 4 .

[0138] The stacked structure B is etched once based on the second mask layer Y2 to remove the isolation layer L3, the second sacrificial layer L22 and the first sacrificial layer L21 exposed by the opening pattern, exposing the first electrode 41 (including the first electrode body 411 and part of the second branch 412).

[0139] In step S601, referring to FIG. 9 and FIG. 9a, FIG. 9b, and FIG. 9c, a dielectric material is deposited to form a first dielectric layer 43 conformally covering the inner surface of the first electrode 41 and the etched surface of the second sacrificial layer L22, and a second dielectric layer 44 conformally covering the outer surface of the first electrode 41.

[0140] Here, the first dielectric layer 43 covering the inner surface of the first electrode 41 and the second dielectric layer 44 covering the outer surface of the first electrode 41 are integrally connected.

[0141] For example, the first dielectric layer 43 and the second dielectric layer 44 can be formed simultaneously using a deposition process. The material of the first dielectric layer 43 and the second dielectric layer 44 includes HK dielectric material. The deposition thickness of the first dielectric layer 43 and the second dielectric layer 44 can be set to match the requirements.

[0142] For example, as shown in FIG9a , in the same storage layer M, multiple second dielectric layers 44 of a column of capacitors 4 arranged along a first direction (e.g., the Y direction) can be connected as a whole, and multiple third electrodes 45 of the column of capacitors 4 can be connected as a whole. Furthermore, the second dielectric layer 44 also extends to the etched surface of the isolation layer L3 (i.e., the sidewall of the third insulating layer 33).

[0143] For example, as shown in FIG9c , in different storage layers M, the first dielectric layers 43 of the capacitors 4 arranged adjacent to each other in a direction perpendicular to the substrate 1 (e.g., the Z direction) are integrally connected. Optionally, as shown in FIG9c , in the storage layer M adjacent to the substrate 1, the first dielectric layer 43 and the second dielectric layer 44 further extend to cover the surface of the substrate 1.

[0144] In step S602 , referring to FIG. 9 and FIG. 9 a , FIG. 9 b , and FIG. 9 c , a conductive material is deposited to form a second electrode 42 covering the first dielectric layer 43 and a third electrode 45 covering the second dielectric layer 44 , and the third electrode 45 is connected to the second electrode 42 .

[0145] By way of example, the materials of the second electrode 42 and the third electrode 45 include, but are not limited to, polysilicon.

[0146] For example, after the third electrode 45 is formed by a deposition process, the upper surface of the third electrode 45 may be polished by a CMP process.

[0147] 9a , multiple third electrodes 45 of a column of capacitors 4 in the same storage layer M may be connected as one. As shown in FIG9b , multiple third electrodes 45 of capacitors 4 on the same side of a bit line BL in different storage layers M may be connected as one.

[0148] As described above, after forming the capacitor 4, in step S302, referring to FIG10 and FIG10a, FIG10b, and FIG10c, the second sacrificial layer L22 is etched to remove part of the sacrificial material to form a receiving hole H. The receiving hole H is used to define the formation area of ​​the transistor 2 and the word line WL.

[0149] It is understood that the portion to be removed 03 mentioned in some of the aforementioned embodiments can be removed in this step to expose the corresponding sidewalls of the isolation layer L3. In this way, the receiving hole H is surrounded by the sidewalls of the second sacrificial layer L22 and the isolation layer L3 exposed after etching.

[0150] For example, the step of forming the aforementioned accommodation hole H can be performed in two steps. In the first step, the second sacrificial layer L22 is etched to form an initial accommodation hole. Furthermore, for example, before etching the second sacrificial layer L22, a mask layer (e.g., including a photoresist layer and / or a hard mask layer) can be formed on the upper surface of the corresponding structure to etch the second sacrificial layer L22 based on a mask pattern in the mask layer. In the second step, the portion to be removed O3 is etched away based on the initial accommodation hole to form the accommodation hole H.

[0151] Optionally, the portion to be removed 03 may be removed by etching using an isotropic etching process.

[0152] In step S303 , referring to FIG. 11 and FIG. 11 a , FIG. 11 b , and FIG. 11 c , an initial semiconductor layer 210 , a gate insulating layer 22 , and a word line WL are sequentially formed on the inner wall of the receiving hole H.

[0153] By way of example, the initial semiconductor layer 210 includes but is not limited to a metal oxide semiconductor layer, such as an IGZO layer.

[0154] For example, the initial semiconductor layer 210 may be formed by a deposition process, such as an ALD process.

[0155] Illustratively, the gate insulating layer 22 includes, but is not limited to, a HK dielectric layer.

[0156] For example, the gate insulating layer 22 may be formed by a deposition process, such as an ALD process.

[0157] For example, the word line WL extends in a direction perpendicular to the substrate 1 (eg, the Z direction), and the material of the word line WL includes but is not limited to metal tungsten.

[0158] For example, the word lines WL may be formed by a deposition process. After the word lines WL are formed by the deposition process, a CMP process may be used to grind the upper surface of the resulting structure to ensure that the exposed word lines WL have good surface quality.

[0159] In step S304, referring to FIG. 12 and FIG. 12a, FIG. 12b, and FIG. 12c, the remaining second sacrificial layer L22 and the first sacrificial layer L21 are removed to expose the first sidewall S1 of the initial semiconductor layer 210 facing the first electrode 41 and the second sidewall S2 of the initial semiconductor layer 210 facing the bit line BL.

[0160] Optionally, a mask layer (e.g., including a photoresist layer and / or a hard mask layer) may be formed on the upper surface of the structure obtained after forming the word line WL to etch and remove the remaining second sacrificial layer L22 and first sacrificial layer L21 based on the mask pattern in the mask layer.

[0161] Optionally, the remaining second sacrificial layer L22 and the remaining first sacrificial layer L21 may be removed by etching using an isotropic etching process.

[0162] In step S305, please refer to Figures 12, 12a, 12b, 12c and Figures 1, 1a, 1b, 1c to understand that the initial semiconductor layer 210 is etched based on the first side wall S1 and the second side wall S2 to expose the gate insulation layer 22, and the remaining initial semiconductor layer 210 in each storage layer M is formed into two sub-membrane layers 211 spaced apart in the first direction (for example, the Y direction), and the two ends of each sub-membrane layer 211 are respectively connected to the first branch 112 and the second branch 412.

[0163] For example, the initial semiconductor layer 330 may be etched using an isotropic etching process to form the sub-membrane layer 211 .

[0164] Here, after forming each sub-membrane layer 211 , a first accommodating cavity X1 is formed between the two first branches 112 corresponding to the same transistor 2 and the bit line body 111 and the gate insulating layer 22 , and a second accommodating cavity X2 is formed between the first electrode body 411 , the two second branches 412 and the gate insulating layer 22 .

[0165] In steps S40 and S50, referring to Figures 1 and 1a, 1b, and 1c, the remaining areas of the second sacrificial layer L22 and the first sacrificial layer L21 removed, as well as the etched areas of the initial semiconductor layer 330, are filled with an insulating material to form an insulating layer. This insulating material includes, but is not limited to, silicon oxide. This insulating layer includes: a first insulating layer 31 filled in the first accommodating cavity X1; a second insulating layer 32 filled in the second accommodating cavity X2; and the third and fourth insulating layers 33 and 34 shown in Figure 1b.

[0166] Here, the insulating layer may be formed by a deposition process. After the insulating layer is formed by the deposition process, the upper surface of the insulating layer may be polished by a CMP process to ensure that the upper surface of the insulating layer is flat and the upper surface of the word line WL is exposed with good surface quality.

[0167] It should be added that the "one-time etching process" mentioned in some of the above embodiments can be understood as: etching based on the pattern of the same mask layer to form the same pattern; and it is not limited to a specific etching method, for example, it can be implemented by dry etching, it can be implemented by wet etching, or it can be implemented by both dry etching and wet etching, etc.

[0168] In summary, in some embodiments of the present disclosure, the conductive unit 3 in the conductive film layer L1 is first patterned to form a sacrificial groove X, which can remove the redundant metal that may exist between the bit line BL and the word line WL and between the word line WL and the first electrode 41 of the capacitor 4 in the conductive film layer L1. Then, the second sacrificial layer L22 is backfilled in the sacrificial groove X, and the second sacrificial layer L22 can be patterned to form spaces for manufacturing the capacitor 4, the transistor 2 and the word line WL, respectively, to manufacture the capacitor 4, the transistor 2 and the word line WL. Finally, the remaining second sacrificial layer L22 and the first sacrificial layer L21 are replaced with an insulating layer. The embodiments of the present disclosure can greatly improve and optimize the improvement of parasitic capacitance and the removal of parasitic transistors in the memory.

[0169] Some embodiments of the present disclosure also provide a memory. Referring to Figure 13 and Figures 13a, 13b, and 13c, the memory includes: a conductive film layer L1, a gate 20, a semiconductor layer 21, and a gate insulating layer 22. The conductive film layer L1 includes: a bit line region BL' extending along the column direction (e.g., the Y direction), and a source region 23 and a drain region 24 sequentially distributed in the row direction (e.g., the X direction) toward the bit line region BL'. The drain region 24 is connected to the bit line region BL'. There is a gap between the source region 23 and the drain region 24. The gate 20 is located between the source region 23 and the drain region 24 and extends in a direction perpendicular to the substrate 1. The semiconductor layer 21 is arranged on the sidewall of the gate 20, for example, surrounding the sidewall of the gate 20. The gate insulating layer 22 is arranged between the sidewall of the gate 20 and the semiconductor layer 21. At least one of the source region 23 and the drain region 24 includes two third branches 231 , and the two third branches 231 are simultaneously connected to the semiconductor layer 21 .

[0170] Here, the gate 20 , the semiconductor layer 21 , the gate insulating layer 22 , the source region 23 , and the drain region 24 together constitute the transistor 2 .

[0171] In conjunction with the relevant descriptions in some of the foregoing embodiments, in some embodiments, the memory includes one or more memory layers M stacked in a direction perpendicular to the substrate 1 (e.g., the Z direction). Accordingly, the number of transistors 2 is multiple. The multiple transistors 2 can be distributed in one memory layer M. Alternatively, the multiple transistors 2 can be distributed in different memory layers M stacked in a direction perpendicular to the substrate 1.

[0172] For example, each transistor 2 in each storage layer M can serve as a transistor of a corresponding storage unit, and the storage unit can be, for example, a 1T1C, 1T0C or 2T0C architecture. Taking the 1T1C architecture as an example, the storage unit can include a capacitor and a transistor connected to the capacitor. For example, in a 3D-DRAM, a plurality of storage cells can be distributed in an array in a plane parallel to the substrate 1 (for example, an XY plane), and periodically stacked in a direction perpendicular to the substrate 1 (for example, in the Z direction) to form a multi-layer storage layer M.

[0173] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0174] For example, the conductive film layer L1 may be a metal layer, such as a tungsten metal layer or a copper metal layer.

[0175] For example, the material of the gate 20 includes metal, such as tungsten or copper.

[0176] For example, the orthographic projection shape of the gate 20 on the surface of the substrate 1 includes but is not limited to a rectangle. The rectangle mentioned here can be an ideal rectangle with right angles, or an approximate rectangle including etching deviations or transition rounded corners.

[0177] In the above embodiment, at least one of the source region 23 and the drain region 24 includes two third branches 231, and both third branches 231 are simultaneously connected to the semiconductor layer 21. Various implementations are possible. The following embodiment uses an example where both the source region 23 and the drain region 24 include two third branches 231. However, it is understood that it is also acceptable for only one of the source region 23 or the drain region 24 to include two third branches 231.

[0178] For example, as shown in FIG13a , a first accommodating cavity X1 is formed between the two third branches 231 of the drain region 24, and a second accommodating cavity X2 is formed between the two third branches 231 of the source region 23. The memory further includes: a first insulating layer 31 filled in the first accommodating cavity X1, and a second insulating layer 32 filled in the second accommodating cavity X2. In addition, the memory may also include other insulating layers in addition to the first insulating layer 31 and the second insulating layer 32, such as the third insulating layer 33 and the fourth insulating layer 34 in FIG13b , etc., to meet the insulation requirements between corresponding conductive elements or between conductive elements and the outside. This embodiment of the present disclosure will not be discussed one by one.

[0179] In some embodiments, referring to FIG. 13 a , the third branch 231 and the bit line region BL′ have the same film thickness, which is a dimension in a direction perpendicular to the substrate 1 (eg, the Z direction).

[0180] In some embodiments, please continue to refer to Figure 13a, the semiconductor layer 21 includes two sub-regions 211' spaced apart; the two sub-regions 211' extend along the row direction (for example, the X direction) on the side wall of the gate 20, and the extended end of any sub-region 211' is connected to the extended end of the third branch 231 of the source region 23 or the drain region 24.

[0181] Here, the semiconductor layer 21 may at least serve as a channel layer of the transistor 2 in the corresponding memory cell.

[0182] For example, the subregion 211 ′ in the semiconductor layer 21 may be a metal oxide semiconductor layer, for example, a metal oxide semiconductor material including at least one of indium, gallium, zinc, or tin.

[0183] In some examples, the sub-region 211 ′ in the semiconductor layer 21 may be an indium gallium zinc oxide (IGZO) layer, but is not limited thereto.

[0184] In some embodiments, referring to FIG. 13a , the memory device further includes a capacitor 4. The conductive film layer L1 further includes a first electrode region 41 ′. The first electrode region 41 ′, the source region 23 , and the drain region 24 are sequentially arranged in a row direction (e.g., the X direction) toward the bit line region BL′, and the first electrode region 41 ′ is connected to the source region 23 .

[0185] Alternatively, referring to FIG13 a , the source region 23 includes two third branches 231 , and the first electrode region 41 ′ includes two second branches 412 , wherein the two second branches 412 are connected to the two third branches 231 of the source region 23 in a one-to-one correspondence.

[0186] It should be noted that, in some embodiments, the capacitor 4 further includes a second electrode 42 disposed between the first electrode region 41 ′ and the second insulating layer 32 , and a first dielectric layer 43 surrounding the sidewalls of the second electrode 42 .

[0187] For example, the orthographic projection shape of the second electrode 42 on the surface of the substrate 1 includes but is not limited to a rectangle. The rectangle mentioned here can be an ideal rectangle with right angles, or an approximate rectangle including etching deviations or transition rounded corners.

[0188] 13a and 13c , the capacitor 4 further includes a second dielectric layer 44 and a third electrode 45 stacked on the outer surface of the first electrode region 41 ′. The third electrode 45 is connected to the second electrode 42 .

[0189] For example, the first dielectric layer 43 and the second dielectric layer 44 may be formed of the same dielectric material and through the same deposition process.

[0190] For example, the first dielectric layer 43 and the second dielectric layer 44 include but are not limited to HK (high-K) dielectric layers, which are dielectric layers with a high dielectric constant K, for example, greater than 3.9.

[0191] For example, the second electrode 42 and the third electrode 45 may be made of the same conductive material and formed through the same deposition process.

[0192] By way of example, the second electrode 42 and the third electrode 45 include, but are not limited to, polysilicon.

[0193] It can be understood that the memory in the above embodiment has a similar structure to the memory in some of the aforementioned embodiments. The manufacturing method of the memory can be adaptively carried out with reference to the manufacturing method of the aforementioned memory and will not be described in detail here.

[0194] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The electronic device may include a housing, a circuit board disposed within the housing, and a memory integrated on the circuit board. For the structure of the memory, please refer to the relevant description of some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited by the embodiments of the present disclosure.

[0195] In some embodiments, an external control device, such as a processor or actuator, coupled to the memory may also be integrated on the circuit board. For example, the electronic device may further include a processor integrated on the circuit board. The processor is coupled to the memory and can control read and write operations of the memory.

[0196] In some embodiments, the memory is 3D-DRAM.

[0197] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0198] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A memory, comprising: A word line extending in a direction perpendicular to the substrate; A transistor, comprising a semiconductor layer located at a sidewall of the word line and a gate insulating layer disposed between the sidewall of the word line and the semiconductor layer; A bit line including a bit line body and different first branches corresponding to different said transistors; The bit line body extends along a first direction parallel to the substrate; the first branch extends toward the semiconductor layer and is connected to the semiconductor layer.

2. The memory according to claim 1, wherein: The number of the first branches corresponding to the same transistor in the bit line is two, and a first accommodating cavity is formed between the two first branches and the bit line body and the gate insulating layer; The memory further includes: a first insulating layer filled in the first accommodation cavity.

3. The memory according to claim 2, wherein: The first branch and the bit line body are formed by patterning a conductive film layer; the first branch and the bit line body have the same film thickness, which is a dimension in a direction perpendicular to the substrate.

4. The memory according to claim 2 or 3, wherein: The semiconductor layer includes two sub-film layers respectively extending along the side walls of the word line; the two sub-film layers are spaced apart in the first direction, and the two sub-film layers are connected to the two first branches in a one-to-one correspondence.

5. The memory according to claim 4, wherein: It also includes capacitors; The capacitor includes a first electrode connected to the semiconductor layer; The first electrode includes two second branches; the two second branches are respectively connected to the two sub-film layers of the semiconductor layer in a one-to-one correspondence.

6. The memory according to claim 5, wherein: The first electrode further comprises a first electrode body connecting the two second branches; the first electrode body and the second branches are arranged in sequence along a second direction, the second direction is parallel to the substrate and intersects with the first direction; A second accommodating cavity is formed between the first electrode body, the two second branches and the gate insulating layer; The memory further includes: a second insulating layer filled in the second accommodation cavity.

7. The memory according to claim 6, wherein: The capacitor further includes a second electrode disposed between the first electrode and the second insulating layer, and a first dielectric layer surrounding a side wall of the second electrode.

8. The memory according to claim 7, wherein: The capacitor further includes a second dielectric layer and a third electrode stacked on the outer surface of the first electrode; the third electrode is connected to the second electrode.

9. The memory according to any one of claims 1 to 8, wherein: The number of the transistors is multiple; the multiple transistors are distributed in one layer, or distributed in different layers stacked in a direction perpendicular to the substrate.

10. A method for manufacturing a memory, comprising: forming a conductive film layer on a substrate; patterning the conductive film layer to form a bit line; The bit line comprises: a bit line body extending along a first direction parallel to the substrate, and a plurality of first branches arranged at intervals in the first direction; A transistor and a word line are formed correspondingly at the extended ends of two adjacent first branches; wherein the word line extends in a direction perpendicular to the substrate; the transistor includes a semiconductor layer located on the side wall of the word line and a gate insulating layer arranged between the side wall of the word line and the semiconductor layer; the first branch extends toward the semiconductor layer and is connected to the semiconductor layer.

11. The method for manufacturing a memory according to claim 10, wherein: A first accommodating cavity is formed between the two first branches corresponding to the same transistor, the bit line body, and the gate insulating layer; The manufacturing method further comprises: The first accommodating cavity is filled with insulating material to form a first insulating layer.

12. The method for manufacturing a memory according to claim 11, wherein: The memory further comprises a capacitor; the capacitor comprises a first electrode; The manufacturing method further comprises: When patterning the conductive film layer, the first electrode is formed synchronously with the bit line; the first electrode includes two second branches arranged at intervals in the first direction; Wherein, the semiconductor layer is also connected to two of the second branches correspondingly.

13. The method for manufacturing a memory according to claim 12, wherein: The first electrode further comprises a first electrode body connecting the two second branches; the first electrode body and the second branches are arranged in sequence along a second direction parallel to the substrate, and a second accommodation cavity is formed between the first electrode body, the two second branches and the gate insulating layer; The manufacturing method further comprises: The second accommodating cavity is filled with insulating material to form a second insulating layer.

14. The method for manufacturing a memory according to claim 13, wherein: The forming of transistors and word lines corresponding to the extending ends of two adjacent first branches includes: Before forming the first insulating layer and the second insulating layer, filling a sacrificial material in the first electrode body, the two second branches, and the region between the two first branches and the bit line body; Removing part of the sacrificial material to form a receiving hole; the receiving hole is used to define a formation area of ​​the transistor and the word line; forming an initial semiconductor layer, the gate insulating layer and the word line in sequence on the inner wall of the receiving hole; removing the remaining sacrificial material to expose a first side wall of the initial semiconductor layer facing the first electrode and a second side wall of the initial semiconductor layer facing the bit line; The initial semiconductor layer is etched based on the first side wall and the second side wall until the gate insulating layer is exposed, and the remaining initial semiconductor layer forms two sub-film layers spaced apart in the first direction, and both ends of each sub-film layer are respectively connected to the first branch and the second branch.

15. The method for manufacturing a memory according to claim 13, wherein: Also includes: A second electrode is formed between the first electrode and the second insulating layer, and a first dielectric layer surrounds a side wall of the second electrode.

16. The method for manufacturing a memory according to claim 15, wherein: Also includes: While forming the first dielectric layer between the first electrode and the second insulating layer, forming a second dielectric layer on the outer surface of the first electrode; While the second electrode is formed between the first electrode and the second insulating layer, a third electrode is formed on the outer surface of the second dielectric layer, and the third electrode is connected to the second electrode.

17. A memory comprising: The conductive film layer comprises: a bit line region extending along the column direction, and a source region and a drain region sequentially distributed in the row direction toward the bit line region; the drain region is connected to the bit line region, and there is a gap between the source region and the drain region; A gate, located between the source region and the drain region and extending in a direction perpendicular to the substrate; A semiconductor layer, disposed on a side wall of the gate; A gate insulating layer, disposed between the gate sidewall and the semiconductor layer; Wherein, at least one of the source region and the drain region includes two third branches, and the two third branches are connected to the semiconductor layer at the same time.

18. The memory according to claim 17, wherein: The third branch has the same film thickness as that of the bit line region, and the film thickness is a dimension in a direction perpendicular to the substrate.

19. The memory according to claim 17, wherein: The semiconductor layer includes two sub-regions spaced apart from each other; the two sub-regions extend along the row direction on the gate sidewall; and an extended end of any of the sub-regions is connected to an extended end of the third branch of the source region or the drain region.

20. The memory according to claim 17, wherein: The conductive film layer also includes a first electrode region; the first electrode region, the source region and the drain region are sequentially distributed in a row direction toward the bit line region; the first electrode region is connected to the source region.

21. The memory according to claim 20, wherein: The source region includes two third branches; the first electrode region includes two second branches; wherein the two second branches are connected to the two third branches of the source region in a one-to-one correspondence.

22. An electronic device comprising: The memory according to any one of claims 1 to 9 or the memory according to any one of claims 17 to 21.

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