Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of repeating units (100); each repeating unit (100) comprises a plurality of sub-pixels; each sub-pixel at least comprises a pixel driving circuit, a scanning signal line (30), and an auxiliary signal line (30A); each pixel driving circuit comprises a first electrode sheet (61) and at least one transistor; and the at least one transistor is connected to the first electrode sheet (61) by means of a connecting electrode. In a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer and a second conductive layer, the auxiliary signal lines (30A) and the first electrode sheets (61) are arranged in the first conductive layer, the scanning signal lines (30) and the connecting electrodes are arranged in the second conductive layer, the orthographic projections of the scanning signal lines (30) on a base plane are located within the range of the orthographic projections of the auxiliary signal lines (30A) on the base plane, and the scanning signal lines (30) are in lap joint with the auxiliary signal lines (30A).

Description

Display substrate, preparation method thereof and display device

[0001] The present application claims priority to PCT application No. PCT / CN2023 / 091560, filed on April 28, 2023, entitled "Display substrate, preparation method thereof and display device", the contents of which are hereby incorporated by reference into the present application. TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0003] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. With the continuous development of display technology, display devices using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0004] SUMMARY

[0005] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0006] In one aspect, the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, a scan signal line and an auxiliary signal line, the scan signal line being configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit comprising a storage capacitor and at least one transistor, the storage capacitor comprising at least a first plate, the at least one transistor being connected to the first plate through a connection electrode; in a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer disposed on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate, the auxiliary signal line and the first plate being disposed in the first conductive layer, the scan signal line and the connection electrode being disposed in the second conductive layer, a projection of the scan signal line on the substrate plane being within a range of a projection of the auxiliary signal line on the substrate plane, the scan signal line being overlapped with the auxiliary signal line.

[0007] In an exemplary embodiment, the storage capacitor further comprises a second plate, a footprint of the second plate on the substrate plane at least partially overlaps with a footprint of the first plate on the substrate plane; the at least one transistor comprises a second transistor, the second transistor comprises at least a second gate electrode, the second gate electrode is connected with the second plate through a plate via, a footprint of the second gate electrode on the substrate plane contains a footprint of the plate via on the substrate plane.

[0008] In an exemplary embodiment, the second transistor further comprises a second active layer, a first region of the second active layer is connected with a first power line through a power supply via, a second region of the second active layer is connected with the first plate through a connection electrode, the first power line is configured to provide a power signal to the pixel driving circuit, a footprint of the first power line on the substrate plane contains a footprint of the power supply via on the substrate plane.

[0009] In an exemplary embodiment, the second active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are integrally connected with each other, and / or the second active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are integrally connected with each other.

[0010] In an exemplary embodiment, the power supply via is shared by two adjacent sub-pixels in two adjacent repeating units in the pixel row direction, and / or the power supply via is shared by two adjacent sub-pixels in two adjacent repeating units in the pixel column direction.

[0011] In an exemplary embodiment, the connection electrode comprises a first connection electrode and a third connection electrode, the first connection electrode is connected with the first plate, the third connection electrode overlaps with the first connection electrode; the pixel driving circuit further comprises a fifth connection electrode, the fifth connection electrode is connected with the second region of the second active layer and the third connection electrode through a first overlap via; a first dimension of the first overlap via is greater than a second dimension of the first overlap via, the first dimension is a dimension of the first overlap via in the pixel row direction, and the second dimension is a dimension of the first overlap via in the pixel column direction.

[0012] In an exemplary embodiment, the power supply via and the first overlap via are not on a straight line extending along the pixel row direction.

[0013] In an exemplary embodiment, in the pixel column direction, the power supply via shared by two adjacent sub-pixels in two adjacent repeating units is located between two adjacent first overlap vias in the two adjacent repeating units.

[0014] In an example embodiment, the at least one transistor comprises a third transistor, the third transistor comprises at least a third active layer, a first region of the third active layer is connected with a compensation via and a compensation signal line, a second region of the third active layer is connected with the first plate through a connection electrode, the compensation signal line is configured to provide a compensation signal to the pixel driving circuit, and a footprint of the compensation signal line on the substrate plane contains a footprint of the compensation via on the substrate plane.

[0015] In an example embodiment, in at least one repeating unit, the third active layers of two sub-pixels adjacent in the pixel row direction are in an integrated structure connected with each other, and / or the third active layers of two sub-pixels adjacent in the pixel column direction are in an integrated structure connected with each other.

[0016] In an example embodiment, in at least one repeating unit, two sub-pixels adjacent in the pixel row direction share the compensation via, and / or two sub-pixels adjacent in the pixel column direction share the compensation via.

[0017] In an example embodiment, the connection electrode comprises a second connection electrode and a fourth connection electrode, the second connection electrode is connected with the first plate, and the fourth connection electrode is overlapped with the second connection electrode; the pixel driving circuit further comprises a sixth connection electrode, the sixth connection electrode is connected with the second region of the third active layer and the fourth connection electrode through a second overlapped via; a third dimension of the second overlapped via is smaller than a fourth dimension of the second overlapped via, the third dimension is a dimension of the second overlapped via in the pixel row direction, and the fourth dimension is a dimension of the second overlapped via in the pixel column direction.

[0018] In an example embodiment, the pixel driving circuit further comprises a first transistor, the first transistor comprises at least a first active layer, a first region of the first active layer is connected with a data via and a data signal line, the data signal line is configured to provide a data signal to the pixel driving circuit, and a footprint of the data signal line on the substrate plane contains a footprint of the data via on the substrate plane.

[0019] In an example embodiment, the pixel driving circuit comprises at least a first transistor and a third transistor, the first transistor comprises at least a first gate electrode, the third transistor comprises at least a third gate electrode, and the first gate electrode and the third gate electrode are connected with the scan signal line through a gate connection electrode respectively.

[0020] In an exemplary embodiment, in at least one repeating unit, the gate connection electrode, the first gate electrode and the third gate electrode of two sub-pixels adjacent in the pixel column direction are disposed in the same layer and are an integrated structure connected to each other.

[0021] In an exemplary embodiment, a projection of the gate connection electrode on the substrate plane at least partially overlaps with a projection of the scan signal line on the substrate plane, and the gate connection electrode is connected to the scan signal line through a gate connection via.

[0022] In an exemplary embodiment, in at least one repeating unit, the two sub-pixels adjacent in the pixel column direction share the gate connection electrode.

[0023] In an exemplary embodiment, in at least one repeating unit, the two sub-pixels adjacent in the pixel column direction share the gate connection via.

[0024] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0025] In yet another aspect, the present disclosure also provides a preparation method of a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, a scan signal line and an auxiliary signal line, the scan signal line being configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit comprising a storage capacitor and at least one transistor, the storage capacitor comprising at least a first electrode plate, the at least one transistor being connected to the first electrode plate through a connection electrode; the preparation method comprising:

[0026] forming a first conductive layer on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate, the auxiliary signal line and the first electrode plate being disposed in the first conductive layer, the scan signal line and the connection electrode being disposed in the second conductive layer, a projection of the scan signal line on the substrate plane being within a range of a projection of the auxiliary signal line on the substrate plane, and the scan signal line being overlapped with the auxiliary signal line.

[0027] In an exemplary embodiment, forming a first conductive layer on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate comprises:

[0028] sequentially depositing a first conductive thin film and a second conductive thin film;

[0029] adopting a patterning process of a half-tone mask plate, forming the scan signal line and the auxiliary signal line through a first etching process, and forming the first electrode plate and the connection electrode through a second etching process.

[0030] In an exemplary embodiment, the storage capacitor further comprises a second plate, a projection of the second plate on the substrate plane at least partially overlaps with a projection of the first plate on the substrate plane; the preparation method further comprises:

[0031] depositing a semiconductor thin film on a side of the second conductive layer away from the substrate;

[0032] using a half-tone mask plate, sequentially forming the second plate through an etching process and a conductorization process.

[0033] Other aspects can be apparent after reading the specification and the attached drawings. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0035] FIG. 1 is a structural schematic diagram of a display device;

[0036] FIG. 2 is a planar structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit in a repeat unit according to an exemplary embodiment of the present disclosure;

[0038] FIG. 4 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0039] FIGS. 5A to 5D are schematic diagrams of a display substrate after forming a first conductive layer and a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0040] FIGS. 6A to 6C are schematic diagrams of a display substrate after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure;

[0041] FIGS. 7A and 7B are schematic diagrams of a display substrate after forming a second insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0042] FIGS. 8A to 8C are schematic diagrams of a display substrate after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0043] FIG. 9 is a schematic diagram of a display substrate after forming a third insulating layer and a planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0044] FIGS. 10A and 10B are schematic diagrams of a display substrate after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0045] FIG. 11 is a schematic view of the display substrate according to an embodiment of the present disclosure.

[0046] Reference Signs: 10 - Substrate; 11 - First connection electrode; 12 - Second connection electrode; 13 - Third connection electrode; 14 - Fourth connection electrode; 15 - Fifth connection electrode; 16 - Sixth connection electrode; 21 - First active layer; 22 - Second active layer; 23 - Third active layer; 30 - Scan signal line; 30A - Auxiliary signal line; 31 - First gate electrode; 32 - Second gate electrode; 33 - Third gate electrode; 34 - Gate connection electrode; 51 - First power supply line; 52 - Data signal line; 53 - Compensation signal line; 60 - Storage capacitor; 61 - First plate; 62 - Second plate; 63 - First electrode; 64 - Anode connection electrode; 71 - First insulating layer; 72 - Second insulating layer; 100 - Repeat unit. DETAILED DESCRIPTION

[0047] In order to make the objects, technical solutions and advantages of the present disclosure clearer, below will be a detailed description of the embodiments of the present disclosure in combination with the drawings. The embodiments can be implemented in multiple different forms. One of ordinary skill in the art can easily understand that the means and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0048] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0049] In this specification, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among components, and are not used to denote the number in the sequence.

[0050] In this specification, in order to facilitate the description of the present specification and simplify the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0051] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0052] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0053] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit during operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other, and "source terminal" and "drain terminal" can be exchanged with each other.

[0054] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can transmit and receive an electrical signal between the connected components. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0055] In this specification, "parallel" means a state where an angle formed by two straight lines is -10° or more and 10° or less, and thus, an angle of -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is 80° or more and 100° or less, and thus, a state where an angle of 85° or more and 95° or less is also included.

[0056] In this specification, "film" and "layer" can be interchanged with each other. For example, "conductive layer" can be sometimes changed into "conductive film". Similarly, "insulating film" can be sometimes changed into "insulating layer".

[0057] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and the like are not strictly so, and can be an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, and deformation, and the like.

[0058] In this specification, "about" means not strictly limited to a boundary, and allows a range of values within a process and measurement error.

[0059] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the OLED display device can include a timing controller, a data driver, a scan driver, and a pixel array, the timing controller is connected to the data driver and the scan driver respectively, the data driver is connected to a plurality of data signal lines (D1 to Dn) respectively, and the scan driver is connected to a plurality of scan signal lines (S1 to Sm) respectively. The pixel array can include a plurality of sub-pixels Pxij, each sub-pixel Pxij can be connected to a corresponding data signal line and a corresponding scan signal line, i and j can be natural numbers. At least one sub-pixel Pxij can include at least a circuit unit and a display unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected to the scan signal line and the data signal line respectively, the display unit can include at least a light emitting device, the light emitting device is connected to the pixel driving circuit of the circuit unit, and the sub-pixel Pxij can refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and connected to the j-th data signal line. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data driver to the data driver, and can provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of pixels, n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals having on-pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner of sequentially transmitting the scan start signal provided in the form of an on-pulse to the next stage circuit under the control of the clock signal, m can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0060] The exemplary embodiments of the present disclosure provide a display substrate, comprising a plurality of repetitive units, at least one repetitive unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, a scan signal line configured to provide a scan signal to the pixel driving circuit, and an auxiliary signal line; the pixel driving circuit comprising a storage capacitor and at least one transistor, the storage capacitor comprising at least a first plate, the at least one transistor being connected to the first plate through a connection electrode; in a direction perpendicular to the display substrate, the display substrate comprising a first conductive layer disposed on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate, the auxiliary signal line and the first plate being disposed in the first conductive layer, the scan signal line and the connection electrode being disposed in the second conductive layer, a projection of the scan signal line on a plane of the substrate being within a range of a projection of the auxiliary signal line on the plane of the substrate, the scan signal line being overlapped with the auxiliary signal line.

[0061] In an exemplary embodiment, the storage capacitor further comprises a second plate, a projection of the second plate on the plane of the substrate at least partially overlapping with a projection of the first plate on the plane of the substrate; the at least one transistor comprises a second transistor, the second transistor comprising at least a second gate electrode, the second gate electrode being connected to the second plate through a plate via, a projection of the second gate electrode on the plane of the substrate containing a projection of the plate via on the plane of the substrate.

[0062] In an exemplary embodiment, the second transistor further comprises a second active layer, a first region of the second active layer being connected to a first power supply line through a power supply via, the first power supply line being configured to provide a power supply signal to the pixel driving circuit, a projection of the first power supply line on the plane of the substrate containing a projection of the power supply via on the plane of the substrate.

[0063] In an exemplary embodiment, the at least one transistor comprises a first transistor and a third transistor, the first transistor comprising at least a first gate electrode, the third transistor comprising at least a third gate electrode, the first gate electrode and the third gate electrode being connected to the scan signal line through a gate connection electrode respectively.

[0064] In an exemplary embodiment, the first transistor further comprises a first active layer, a first region of the first active layer being connected to a data signal line through a data via, the data signal line being configured to provide a data signal to the pixel driving circuit; a projection of the data signal line on the plane of the substrate containing a projection of the data via on the plane of the substrate.

[0065] In an example embodiment, the third transistor further includes a third active layer, a first region of the third active layer is connected with a compensation via and a compensation signal line, the compensation signal line is configured to provide a compensation signal to the pixel driving circuit; a projection of the compensation signal line on the substrate plane contains a projection of the compensation via on the substrate plane.

[0066] The display substrate of the present disclosure is illustrated below by some example embodiments.

[0067] FIG. 2 is a schematic diagram of a planar structure of a display substrate according to an example embodiment of the present disclosure. As shown in FIG. 2, in an example embodiment, in a direction parallel to the display substrate, the display substrate can include a plurality of repeating units 100, and at least one repeating unit 100 can include a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns. In an example embodiment, the repeating unit is a basic unit constituting the display substrate, and the display substrate is formed by repeating and continuously arranging the repeating units in at least one direction, i.e., the display substrate is formed by splicing a plurality of repeating units.

[0068] In an example embodiment, one repeating unit 100 can include four sub-pixels, and the four sub-pixels can include a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, a third sub-pixel P3 emitting third color light, and a fourth sub-pixel P4 emitting fourth color light. The four sub-pixels can be arranged in a square manner, which can effectively increase the aperture ratio and the area of the light transmission region.

[0069] In an example embodiment, in at least one repeating unit 100, the second sub-pixel P2 can be arranged on one side of the first sub-pixel P1 in a first direction X, the third sub-pixel P3 can be arranged on one side of the first sub-pixel P1 in a second direction Y, the fourth sub-pixel P4 can be arranged on one side of the third sub-pixel P3 in the first direction X, a plurality of sub-pixels arranged in the first direction X in sequence can be referred to as a pixel row, a plurality of sub-pixels arranged in the second direction Y in sequence can be referred to as a pixel column, and the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array. The first direction X and the second direction Y intersect.

[0070] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, the third sub-pixel P3 can be a white sub-pixel (W) emitting white light, and the fourth sub-pixel P4 can be a green sub-pixel (G) emitting green light. In some possible embodiments, the arrangement of RBWG can be adjusted according to actual needs, which is not specifically limited in the present disclosure.

[0071] In an example embodiment, in a direction perpendicular to the display substrate, the display substrate can include at least a driving circuit layer disposed on a base, a light emitting structure layer disposed on a side of the driving circuit layer away from the base. In at least one repeating unit, the driving circuit layer can include a plurality of circuit units, and the circuit units can include at least a pixel driving circuit. The pixel driving circuit can be connected to a scan signal line and a data signal line, and configured to receive a data voltage transmitted by the data signal line under control of the scan signal line, and output a corresponding current to a light emitting device.

[0072] In another example embodiment, in a direction perpendicular to the display substrate, the display substrate can include at least a driving circuit layer disposed on a base, a color film structure layer disposed on a side of the driving circuit layer away from the base, and a light emitting structure layer disposed on a side of the color film structure layer away from the base. In at least one repeating unit, the color film structure layer can include a plurality of color film units, and the color film units can include at least a color filter layer. The color filter layer can be configured to make a corresponding sub-pixel emit light of a required color.

[0073] In an example embodiment, the circuit unit in the present disclosure refers to an area divided according to the pixel driving circuit. The color film unit in the present disclosure refers to an area divided according to the color filter layer. The light emitting unit in the present disclosure refers to an area divided according to the light emitting device. The positions of the orthographic projection of the circuit unit on the base, the orthographic projection of the color filter layer on the base, and the orthographic projection of the light emitting unit on the base can be corresponding, or can be non-corresponding.

[0074] In an example embodiment of the present disclosure, the positions of the orthographic projection of the circuit unit on the base, the orthographic projection of the color filter layer on the base, and the orthographic projection of the light emitting unit on the base are substantially corresponding. The circuit unit, the color film unit, and the light emitting unit constitute a sub-pixel. In the following content, the sub-pixel is used to refer to the circuit unit, the color film unit, and the light emitting unit.

[0075] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit in one repeating unit in an example embodiment of the present disclosure. As shown in FIG. 3, at least one repeating unit can include four pixel driving circuits, and the four pixel driving circuits can be arranged in a square manner. The pixel driving circuit can be a 3T1C structure.

[0076] In the example embodiment, the at least one pixel driving circuit can include 3 transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and 1 storage capacitor C, and the pixel driving circuit is connected with a scan signal line 30, a first power supply line 51, a data signal line 52, and a compensation signal line 53, respectively.

[0077] In the example embodiment, each pixel driving circuit can include a first node N1 and a second node N2. The first node N1 is connected with a second electrode of the first transistor T1, a gate electrode of the second transistor T2, and a first terminal of the storage capacitor C, respectively. The second node N2 is connected with a second electrode of the second transistor T2, a second electrode of the third transistor T3, and a second terminal of the storage capacitor C, respectively.

[0078] In the example embodiment, the first terminal of the storage capacitor C is connected with the first node N1, and the second terminal of the storage capacitor C is connected with the second node N2. The storage capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0079] In the example embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0080] In the example embodiment, the gate electrode of the first transistor T1 is connected with the scan signal line 30, the first electrode of the first transistor T1 is connected with the data signal line 52, and the second electrode of the first transistor T1 is connected with the first node N1. When a conduction signal is applied to the scan signal line 30, the first transistor T1 inputs the data signal of the data signal line 52 to the gate electrode of the second transistor T2.

[0081] In the example embodiment, the gate electrode of the second transistor T2 is connected with the first node N1, the first electrode of the second transistor T2 is connected with the first power supply line 51, and the second electrode of the second transistor T2 is connected with the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode.

[0082] In the example embodiment, the gate electrode of the third transistor T3 is connected with the scan signal line 30, the first electrode of the third transistor T3 is connected with the compensation signal line 53, and the second electrode of the third transistor T3 is connected with the second node N2. When a conduction signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing to compensate the threshold voltage Vth.

[0083] In the example embodiment, in the pixel driving circuit of the at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected with the same scan signal line 30.

[0084] In an example embodiment, in the plurality of pixel driving circuits of the at least one pixel row, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30.

[0085] In an example embodiment, in the plurality of pixel driving circuits of the at least one repeating unit, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30.

[0086] In an example embodiment, the light emitting device EL can be an OLED including a first electrode, an organic light emitting layer, and a second electrode stacked, or can be a QLED including a first electrode, a quantum dot light emitting layer, and a second electrode stacked. The first electrode of the light emitting device EL is connected to the second node N2, the second electrode of the light emitting device EL is connected to the second power supply line VSS, and the light emitting device EL emits light of a corresponding brightness in response to the current of the second electrode of the second transistor T2. In an example embodiment, the first electrode can be an anode, and the second electrode can be a cathode; or, the first electrode can be a cathode, and the second electrode can be an anode.

[0087] In an example embodiment, the signal of the first power supply line 51 is a high-level signal continuously provided, and the signal of the second power supply line VSS is a low-level signal continuously provided.

[0088] In an example embodiment, the first transistor T1 to the third transistor T3 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the third transistor T3 can include P-type transistors and N-type transistors.

[0089] In an example embodiment, the first transistor T1 to the third transistor T3 can be low-temperature polysilicon thin film transistors, or can be oxide thin film transistors, or can be low-temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor uses oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low-temperature polysilicon thin film transistor and the oxide thin film transistor on one display substrate, i.e., an LTPO display substrate, can take advantage of both, can realize low-frequency driving, can reduce power consumption, and can improve display quality.

[0090] FIG. 4 is a schematic diagram of a structure of a display substrate according to an example embodiment of the present disclosure, illustrating a structure of four repeating units (16 sub-pixels) in a bottom emission display substrate. In the example embodiment, the four repeating units can include a first repeating unit Q1, a second repeating unit Q1, a third repeating unit Q3, and a fourth repeating unit Q4. The second repeating unit Q1 can be disposed on one side of the first repeating unit Q1 in a first direction X, the third repeating unit Q3 can be disposed on one side of the first repeating unit Q1 in a second direction Y, and the fourth repeating unit Q4 can be disposed on one side of the third repeating unit Q3 in the first direction X. At least one repeating unit can include four sub-pixels forming two pixel rows and two pixel columns. The four sub-pixels can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. The second sub-pixel P2 can be disposed on one side of the first sub-pixel P1 in the first direction X, the third sub-pixel P3 can be disposed on one side of the first sub-pixel P1 in the second direction Y, and the fourth sub-pixel P4 can be disposed on one side of the third sub-pixel P3 in the first direction X. The first direction X and the second direction Y intersect. A plurality of sub-pixels arranged in sequence along the first direction X can be referred to as a pixel row, and a plurality of sub-pixels arranged in sequence along the second direction Y can be referred to as a pixel column. A plurality of pixel rows and a plurality of pixel columns form a pixel array arranged in an array.

[0091] In the example embodiment, at least one sub-pixel can include a pixel driving circuit, a scan signal line 30, and an auxiliary signal line 30A. The scan signal line 30 and the auxiliary signal line 30A can have a linear shape with a main body portion extending along the first direction X (pixel row direction). The scan signal line 30 and the auxiliary signal line 30A can be disposed in the middle of the second direction Y (pixel column direction) of the repeating unit. The scan signal line 30 can be configured to provide a scan signal to the pixel driving circuit.

[0092] In the example embodiment, at least one pixel driving circuit can include a storage capacitor 60 and at least one transistor. The storage capacitor can include a first electrode plate, and the at least one transistor can be connected to the first electrode plate through a connection electrode. In a direction perpendicular to the display substrate, the display substrate can include at least a first conductive layer disposed on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate. The auxiliary signal line 30A and the first electrode plate can be disposed in the first conductive layer, and the scan signal line 30 and the connection electrode can be disposed in the second conductive layer. A normal projection of the scan signal line 30 on the substrate plane can be within a range of a normal projection of the auxiliary signal line 30A on the substrate plane. The scan signal line 30 and the auxiliary signal line 30A can be overlapped to form a signal line with a double-layer structure. In the example embodiment, the scan signal line 30 and the auxiliary signal line 30A are overlapped means that a surface of the auxiliary signal line 30A on a side away from the substrate is attached to a surface of the scan signal line 30 on a side close to the substrate.

[0093] In an example embodiment, the at least one transistor can include a second transistor T2, a second electrode of the second transistor T2 can be connected to the first electrode plate through a connection electrode, the connection electrode can include a first connection electrode and a third connection electrode, the first connection electrode is connected to the first electrode plate, and the third connection electrode is overlapped with the first connection electrode.

[0094] In an example embodiment, the storage capacitor can further include a second electrode plate, a footprint of the second electrode plate on the substrate plane at least partially overlaps with a footprint of the first electrode plate on the substrate plane. The second transistor T2 can include at least a second gate electrode 32, the second gate electrode 32 can be connected to the second electrode plate through an electrode plate via K1, and a footprint of the second gate electrode 32 on the substrate plane contains a footprint of the electrode plate via K1 on the substrate plane.

[0095] In an example embodiment, the second transistor T2 can further include a second active layer 22, a first region of the second active layer 22 is connected to the first power supply line 51 through a power supply via K2, the first power supply line 51 is configured to provide a power supply signal to the pixel driving circuit, and a footprint of the first power supply line 51 on the substrate plane contains a footprint of the power supply via K2 on the substrate plane.

[0096] In an example embodiment, the first regions of the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are connected to each other, and / or the first regions of the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are connected to each other.

[0097] In an example embodiment, the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integral structure connected to each other, and / or the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are an integral structure connected to each other.

[0098] In an example embodiment, the first regions of the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the first direction X share a power supply via K2, and / or the first regions of the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y share a power supply via K2.

[0099] In an example embodiment, the at least one transistor can include a third transistor T3, a second electrode of the third transistor T3 can be connected to the first electrode plate through a connection electrode, the connection electrode can include a second connection electrode and a fourth connection electrode, the second connection electrode is connected to the first electrode plate, and the fourth connection electrode is overlapped with the second connection electrode.

[0100] In an example embodiment, the third transistor T3 can at least include a third active layer 23, a first region of the third active layer 23 is connected with a compensation via K3 with a compensation signal line 53 configured to provide a compensation signal to the pixel driving circuit, a positive projection of the compensation signal line 53 on the substrate plane contains a positive projection of the compensation via K3 on the substrate plane.

[0101] In an example embodiment, in at least one repeating unit, the first regions of the third active layers 23 of two adjacent sub-pixels in the first direction X are connected with each other, and / or, the first regions of the third active layers 23 of two adjacent sub-pixels in the second direction Y are connected with each other.

[0102] In an example embodiment, in at least one repeating unit, the third active layers 23 of two adjacent sub-pixels in the first direction X are an integral structure connected with each other, and / or, the third active layers 23 of two adjacent sub-pixels in the second direction Y are an integral structure connected with each other.

[0103] In an example embodiment, in at least one repeating unit, the compensation vias K3 of two adjacent sub-pixels in the first direction X are shared, and / or, the compensation vias K3 of two adjacent sub-pixels in the second direction Y are shared.

[0104] In an example embodiment, the pixel driving circuit can further include a first transistor T1, the first transistor T1 can at least include a first active layer 21, a first region of the first active layer 21 is connected with a data via K4 with a data signal line 52 configured to provide a data signal to the pixel driving circuit, a positive projection of the data signal line 52 on the substrate plane contains a positive projection of the data via K4 on the substrate plane.

[0105] In an example embodiment, the first transistor T1 can further include a first gate electrode 31, the third transistor T3 can further include a third gate electrode 33, the first gate electrode 31 and the third gate electrode 33 are respectively connected with a scan signal line 30 through a gate connection electrode 34.

[0106] In an example embodiment, in the same sub-pixel, the first gate electrode 31, the third gate electrode 33 and the gate connection electrode 34 can be arranged in the same layer and are an integral structure connected with each other.

[0107] In an example embodiment, in at least one repeating unit, the first gate electrode 31, the third gate electrode 33 and the gate connection electrode 34 of two adjacent sub-pixels in the second direction Y can be arranged in the same layer and are an integral structure connected with each other.

[0108] In an example embodiment, the grid connection electrode 34 is connected to the scan signal line 30 through a grid connection via K5.

[0109] In an example embodiment, in at least one of the repeating units, two sub-pixels adjacent in the second direction Y share a grid connection electrode 34.

[0110] In an example embodiment, in at least one of the repeating units, two sub-pixels adjacent in the second direction Y share a grid connection via K5.

[0111] In an example embodiment, at least one of the repeating units can include one scan signal line 30, two first power supply lines 51, four data signal lines 52, and one compensation signal line 53, which are respectively connected to the pixel driving circuit in the corresponding sub-pixel. In an example embodiment, the shapes of the first power supply line 51, the data signal line 52, and the compensation signal line 53 can be linear shapes with main body portions extending along the second direction Y (the pixel column direction), one compensation signal line 53 can be located in the middle of the first direction X of the repeating unit, two first power supply lines 51 can be located on both sides of the first direction X of the repeating unit, four data signal lines 52 and the compensation signal line 53 can be located between the two first power supply lines 51, two of the four data signal lines 52 can be located on one side of one first power supply line 51 close to the compensation signal line 53, the other two of the four data signal lines 52 can be located on one side of the other first power supply line 51 close to the compensation signal line 53, and the storage capacitor 60 in the pixel driving circuit can be located between the data signal line 52 and the compensation signal line 53. In this way, one scan signal line 30 extending along the first direction X defines two pixel rows, one compensation signal line 53 extending along the second direction Y can define two pixel columns, and the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 forming one repeating unit.

[0112] In the exemplary embodiments, the two adjacent sub-pixels in the two adjacent repeating units in the first direction X refer to, in the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the second sub-pixel of the first repeating unit Q1 and the first sub-pixel of the second repeating unit Q2 are the two adjacent sub-pixels in the first direction X, and the fourth sub-pixel of the first repeating unit Q1 and the third sub-pixel of the second repeating unit Q2 are the two adjacent sub-pixels in the first direction X. The two adjacent sub-pixels in the two adjacent repeating units in the second direction Y refer to, in the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel of the first repeating unit Q1 and the first sub-pixel of the third repeating unit Q3 are the two adjacent sub-pixels in the second direction Y, and the fourth sub-pixel of the first repeating unit Q1 and the second sub-pixel of the third repeating unit Q3 are the two adjacent sub-pixels in the second direction Y.

[0113] In the exemplary embodiments, in the direction perpendicular to the display substrate, the display substrate can include a first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer sequentially arranged on the base, the auxiliary signal line 30A and the first plate of the storage capacitor 60 can be arranged in the first conductive layer, the scan signal line 30 can be arranged in the second conductive layer, the first active layer 21, the second active layer 22, the third active layer 23, and the second plate of the storage capacitor 60 can be arranged in the semiconductor layer, and the first gate electrode 31, the second gate electrode 32, the third gate electrode 33, the gate connection electrode 34, the first power supply line 51, the data signal line 52, and the compensation signal line 53 can be arranged in the third conductive layer.

[0114] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes, for metal materials, inorganic materials or transparent conductive materials, deposition of a film layer, coating photoresist on the film layer, mask exposure, development, etching, stripping of photoresist and the like, and for organic materials, coating of organic materials, mask exposure and development and the like. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate prepared by deposition, coating or other processes. If the "thin film" does not need to be subjected to the patterning process during the entire preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be subjected to the patterning process during the entire preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0115] In the exemplary embodiments, taking four repeating units (the first repeating unit Q1, the second repeating unit Q2, the third repeating unit Q3 and the fourth repeating unit Q4) as an example, the preparation process of the display substrate can include the following operations.

[0116] (1) Forming the first conductive layer and the second conductive layer pattern. In the exemplary embodiments, forming the first conductive layer and the second conductive layer pattern can include: sequentially depositing a first conductive thin film and a second conductive thin film on a substrate, patterning the first conductive thin film and the second conductive thin film by a patterning process, and forming the first conductive layer and the second conductive layer pattern on the substrate, as shown in FIGS. 5A, 5B, 5C and 5D, FIG. 5B is a schematic view of the first conductive layer in FIG. 5A, FIG. 5C is a schematic view of the second conductive layer in FIG. 5A, and FIG. 5D is a sectional view of A-A in FIG. 5A. In the exemplary embodiments, the first conductive layer can be referred to as a first transparent (1ITO) layer, and the second conductive layer can be referred to as a shading (SHL) layer.

[0117] As shown in FIGS. 5A, 5B and 5C, the first conductive layer of each sub-pixel in each repeating unit can at least include the first connection electrode 11, the second connection electrode 12, the auxiliary signal line 30A and the first plate 61 of the storage capacitor, and the second conductive layer of each sub-pixel in each repeating unit can at least include the third connection electrode 13, the fourth connection electrode 14 and the scanning signal line 30.

[0118] In an exemplary embodiment, the shape of the first plate 61 can be rectangular, the corner of the rectangular shape can be provided with a chamfer, the first plate 61 can serve as one transparent plate of the transparent storage capacitor, and the first plate 61 is configured to form the transparent storage capacitor with the second plate formed subsequently.

[0119] In an exemplary embodiment, the first connection electrode 11 and the third connection electrode 13 can be located on one side of the first plate 61 in the second direction Y, and the second connection electrode 12 and the fourth connection electrode 14 can be located on the other side of the first plate 61 in the second direction Y.

[0120] In an exemplary embodiment, in one repeating unit, the first connection electrode 11 and the third connection electrode 13 in the first sub-pixel P1 and the second sub-pixel P2 can be provided on the side opposite to the second direction Y of the first plate 61, and the second connection electrode 12 and the fourth connection electrode 14 can be provided on the side of the first plate 61 in the second direction Y. In the third sub-pixel P3 and the fourth sub-pixel P4, the first connection electrode 11 and the third connection electrode 13 can be provided on the side of the first plate 61 in the second direction Y, and the second connection electrode 12 and the fourth connection electrode 14 can be provided on the side opposite to the second direction Y of the first plate 61.

[0121] In an exemplary embodiment, the shape of the first connection electrode 11 and the third connection electrode 13 can be block-shaped (such as rectangular), and the orthographic projection of the third connection electrode 13 on the substrate completely overlaps the orthographic projection of the first connection electrode 11 on the substrate. The first end of the first connection electrode 11 is connected with the first plate 61, and the second end of the first connection electrode 11 extends away from the first plate 61. The third connection electrode 13 is directly overlapped with the first connection electrode 11, and the third connection electrode 13 is configured to be connected with the fifth connection electrode formed subsequently on one hand, and to shield light from the second transistor on the other hand, so as to reduce the light intensity on the second transistor, reduce the leakage current of the second transistor, and thus reduce the influence of light on the characteristics of the second transistor.

[0122] In the example embodiment, the second connection electrode 12 and the fourth connection electrode 14 can have a block shape (e.g., a rectangular shape), and a normal projection of the fourth connection electrode 14 on the substrate completely overlaps a normal projection of the second connection electrode 12 on the substrate. The first end of the second connection electrode 12 is connected to the first plate 61, and the second end of the second connection electrode 12 extends away from the first plate 61. The fourth connection electrode 14 directly overlaps the second connection electrode 12, and the fourth connection electrode 14 is configured to be connected to a sixth connection electrode to be formed later.

[0123] In the example embodiment, the first connection electrode 11, the second connection electrode 12, and the first plate 61 of each sub-pixel can be an integrated structure connected to each other.

[0124] In the example embodiment, the scan signal line 30 and the auxiliary signal line 30A can have a linear shape with a main body portion extending along the first direction X, and can be disposed at the middle of the second direction Y of the repeating unit, i.e., between the first sub-pixel P1 and the second sub-pixel P2 and between the third sub-pixel P3 and the fourth sub-pixel P4. The scan signal line 30 is configured to simultaneously control the on or off of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0125] In the example embodiment, the patterning of the first conductive film and the second conductive film by the patterning process can include: after sequentially depositing the first conductive film and the second conductive film, coating a layer of photoresist on the second conductive film, exposing the photoresist using a half-tone mask, after development, the photoresist forms a fully exposed area, a partially exposed area and an unexposed area, the photoresist in the fully exposed area is removed, exposing the surface of the second conductive film in the fully exposed area, the photoresist in the partially exposed area is partially removed, the photoresist in the partially exposed area has a first thickness, the photoresist in the unexposed area has no change, the photoresist in the unexposed area has a second thickness, the first thickness is less than the second thickness. The unexposed area is the area where the third connection electrode 13, the fourth connection electrode 14 and the scan signal line 30 are located, and the partially exposed area is the area where the first plate 61 is located. Subsequently, by a first etching process, the first conductive film and the second conductive film in the fully exposed area are etched away to form the scan signal line 30 and the auxiliary signal line 30A pattern, the orthographic projection of the scan signal line 30 on the base plane is within the orthographic projection of the auxiliary signal line 30A on the base plane, and the scan signal line 30 is overlapped with the auxiliary signal line 30A, that is, the surface of the scan signal line 30 close to the base side is attached to the surface of the auxiliary signal line 30A away from the base side. Subsequently, the photoresist in the partially exposed area is removed by an ashing process to expose the surface of the second conductive film in the partially exposed area, and the unexposed area is still covered with photoresist. Subsequently, by a second etching process, the second conductive film in the partially exposed area is etched away to expose the first conductive film to form the first connection electrode 11, the second connection electrode 12, the third connection electrode 13, the fourth connection electrode 14 and the first plate 61 pattern, the orthographic projection of the third connection electrode 13 on the base completely overlaps the orthographic projection of the first connection electrode 11 on the base, and the third connection electrode 13 is directly overlapped with the first connection electrode 11, the orthographic projection of the fourth connection electrode 14 on the base completely overlaps the orthographic projection of the second connection electrode 12 on the base, and the fourth connection electrode 14 is directly overlapped with the second connection electrode 12. Finally, the remaining photoresist is stripped.

[0126] As shown in FIG. 5D, through the present patterning process, the first conductive layer and the second conductive layer disposed on the side of the first conductive layer away from the substrate 10 are formed on the substrate 10, the first conductive layer can at least include the first connecting electrode 11, the second connecting electrode 12, the auxiliary signal line 30A and the first plate 61, and the second conductive layer can at least include the third connecting electrode 13, the fourth connecting electrode 14 and the scan signal line 30, the orthographic projection of the third connecting electrode 13 on the substrate completely overlaps the orthographic projection of the first connecting electrode 11 on the substrate, and the third connecting electrode 13 directly overlaps the first connecting electrode 11, the orthographic projection of the fourth connecting electrode 14 on the substrate completely overlaps the orthographic projection of the second connecting electrode 12 on the substrate, and the fourth connecting electrode 14 directly overlaps the second connecting electrode 12.

[0127] In the example embodiment, the scan signal line 30 and the auxiliary signal line 30A form a double-layer signal line structure, which can effectively reduce the resistance of the scan signal line, reduce the voltage drop of the scan signal, and improve the display performance.

[0128] In the example embodiment, the material of the first conductive layer can be a transparent conductive material, such as indium tin oxide ITO or indium zinc oxide IZO, etc., and the material of the second conductive layer can be a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0129] In the example embodiment, in at least one repeating unit, the positions of each pattern in the first conductive layer and the second conductive layer in the first sub-pixel P1 and the positions of each pattern in the first conductive layer and the second conductive layer in the third sub-pixel P3 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of each pattern in the first conductive layer and the second conductive layer in the second sub-pixel P2 and the positions of each pattern in the first conductive layer and the second conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of each pattern in the first conductive layer and the second conductive layer in the first sub-pixel P1 and the positions of each pattern in the first conductive layer and the second conductive layer in the second sub-pixel P2 can be substantially mirror-symmetric with respect to a vertical reference line, and the positions of each pattern in the first conductive layer and the second conductive layer in the third sub-pixel P3 and the positions of each pattern in the first conductive layer and the second conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to a vertical reference line. The horizontal reference line can be a straight line extending along the first direction X and bisecting the repeating unit in the second direction Y, and the vertical reference line can be a straight line extending along the second direction Y and bisecting the repeating unit in the first direction X.

[0130] (2) forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern can include: on a substrate on which the aforementioned pattern is formed, sequentially depositing a first insulating thin film and a semiconductor thin film, patterning the semiconductor thin film by a patterning process, forming a first insulating layer covering the first conductive layer and the second conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIGS. 6A, 6B and 6C, FIG. 6B is a schematic view of the semiconductor layer in FIG. 6A, and FIG. 6C is a sectional view in A-A direction of FIG. 6A.

[0131] In an exemplary embodiment, the semiconductor layer of each sub-pixel in each repeating unit can at least include a first active layer 21, a second active layer 22, a third active layer 23, and a second plate 62 of a storage capacitor, the first active layer 21 can serve as an active layer of the first transistor T1, the second active layer 22 can serve as an active layer of the second transistor T2, the third active layer 23 can serve as an active layer of the third transistor T3, and the second plate 62 can serve as another transparent plate of the transparent storage capacitor, and the second plate 62 is configured to form a transparent storage capacitor with the first plate 61.

[0132] In an exemplary embodiment, the first active layer 21 and the third active layer 23 can be disposed on the side of the first plate 61 of the sub-pixel close to the scan signal line 30, and the second active layer 22 can be disposed on the side of the first plate 61 of the sub-pixel away from the scan signal line 30.

[0133] In an exemplary embodiment, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region.

[0134] In an exemplary embodiment, the first region of the first active layer 21 of each sub-pixel is disposed on the side away from the first plate 61, the second region of the first active layer 21 is disposed on the side close to the first plate 61, and is connected with the second plate 62.

[0135] In an exemplary embodiment, the first region of the second active layer 22 of each sub-pixel is disposed on the side away from the first plate 61, the first region of the second active layer 22 has no overlap with the normal projection of the third connection electrode 13 of the sub-pixel on the substrate, the second region of the second active layer 22 is disposed on the side close to the first plate 61, and the normal projection of the second region and the channel region of the second active layer 22 on the substrate at least partially overlaps with the normal projection of the third connection electrode 13 on the substrate, so that the third connection electrode 13 as a shielding layer can shield the channel region of the second transistor T2, avoid the influence of light on the channel, and ensure the electrical performance of the second transistor T2.

[0136] In the example embodiment, the first regions of the second active layers 22 of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X can be connected to each other, so that the second transistors of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X share the first regions of the second active layers. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the first region of the second active layer 22 of the second sub-pixel P2 in the first repeating unit Q1 and the first region of the second active layer 22 of the first sub-pixel P1 in the second repeating unit Q2 are connected to each other. The first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 are connected to each other. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3 and the first region of the second active layer 22 of the first sub-pixel P1 in the fourth repeating unit Q4 are connected to each other. The first region of the second active layer 22 of the fourth sub-pixel P4 in the third repeating unit Q3 and the first region of the second active layer 22 of the third sub-pixel P3 in the fourth repeating unit Q4 are connected to each other.

[0137] In the example embodiment, the first regions of the second active layers 22 of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X are an integral structure connected to each other.

[0138] In the example embodiment, the first regions of the second active layers 22 of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y can be connected to each other, so that the second transistors of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the first regions of the second active layers. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the first region of the second active layer 22 of the third sub-pixel P3 in the first repeating unit Q1 and the first region of the second active layer 22 of the first sub-pixel P1 in the third repeating unit Q3 can be connected to each other, and the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3 can be connected to each other. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 and the first region of the second active layer 22 of the first sub-pixel P1 in the fourth repeating unit Q4 can be connected to each other, and the first region of the second active layer 22 of the fourth sub-pixel P4 in the second repeating unit Q2 and the first region of the second active layer 22 of the second sub-pixel P2 in the fourth repeating unit Q4 can be connected to each other.

[0139] In an exemplary embodiment, the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y can be an integrated structure connected to each other.

[0140] In an exemplary embodiment, the first region of the second active layer 22 of adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y can be connected to each other. For example, the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1, the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2, the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3, and the first region of the second active layer 22 of the first sub-pixel P1 in the fourth repeating unit Q4 can be connected to each other.

[0141] In an exemplary embodiment, the second active layer 22 of adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y can be an integrated structure connected to each other. The present disclosure can not only effectively reduce the number of vias, but also reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, and simplify the manufacturing process and reduce production costs by reducing the number of vias, thereby improving product yield.

[0142] In an exemplary embodiment, the first region of the third active layer 23 of each sub-pixel is disposed on the side away from the first plate 61, the second region of the third active layer 23 is disposed on the side close to the first plate 61, and the orthogonal projection of the second region of the third active layer 23 on the substrate at least partially overlaps with the orthogonal projection of the fourth connection electrode 14 of the sub-pixel on the substrate.

[0143] In an exemplary embodiment, in at least one repeating unit, the first region of the third active layer 23 in the first sub-pixel P1 and the first region of the third active layer 23 in the second sub-pixel P2 can be connected to each other, and the first region of the third active layer 23 in the third sub-pixel P3 and the first region of the third active layer 23 in the fourth sub-pixel P4 can be connected to each other, that is, the first regions of the third active layers 23 of adjacent two sub-pixels in one pixel row are connected to each other, so that the third transistors of adjacent two sub-pixels in one pixel row share the first region of the third active layer.

[0144] In an exemplary embodiment, the third active layer 23 in the first sub-pixel P1 and the third active layer 23 in the second sub-pixel P2 can be an integrated structure connected to each other, and the third active layer 23 in the third sub-pixel P3 and the third active layer 23 in the fourth sub-pixel P4 can be an integrated structure connected to each other, that is, the third active layers 23 of adjacent two sub-pixels in one pixel row are an integrated structure connected to each other.

[0145] In the example embodiment, in at least one repeating unit, the first region of the third active layer 23 in the first sub-pixel P1 and the first region of the third active layer 23 in the third sub-pixel P3 can be connected to each other, and the first region of the third active layer 23 in the second sub-pixel P2 and the first region of the third active layer 23 in the fourth sub-pixel P4 can be connected to each other, that is, the first regions of the third active layers 23 of the adjacent two sub-pixels in one pixel column are connected to each other, and thus the third transistors of the adjacent two sub-pixels in one pixel column share the first region of the third active layer.

[0146] In the example embodiment, the third active layer 23 in the first sub-pixel P1 and the third active layer 23 in the third sub-pixel P3 can be an integrated structure connected to each other, and the third active layer 23 in the second sub-pixel P2 and the third active layer 23 in the fourth sub-pixel P4 can be an integrated structure connected to each other, that is, the third active layers 23 of the adjacent two sub-pixels in one pixel column are an integrated structure connected to each other.

[0147] In the example embodiment, in at least one repeating unit, the first regions of the third active layers 23 of the adjacent sub-pixels can be connected to each other. For example, the first regions of the third active layers 23 of the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4 can be connected to each other.

[0148] In the example embodiment, in at least one repeating unit, the third active layers 23 of the adjacent sub-pixels can be an integrated structure connected to each other. By arranging the third transistors of the adjacent sub-pixels to share the first region of the third active layer, the number of vias can be effectively reduced, the occupied area of the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, and the production process can be simplified, the production cost can be reduced, and the product yield can be improved.

[0149] In the example embodiment, the second plate 62 can be in a rectangular shape, and the corners of the rectangular shape can be chamfered and arranged between the second active layer 22 and the third active layer 23 of the sub-pixel. The orthographic projection of the second plate 62 on the substrate and the orthographic projection of the first plate 61 on the substrate at least partially overlap, the second plate 62 can serve as another transparent plate of the transparent storage capacitor, and the first plate 61 and the second plate 62 form the transparent storage capacitor.

[0150] In the example embodiment, the second plate 62 and the first active layer 21 of each sub-pixel can be an integrated structure connected to each other.

[0151] In the example embodiment, in each sub-pixel, the area of the overlapping region in the orthographic projection of the first plate 61 on the substrate and the orthographic projection of the second plate 62 on the substrate can be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0152] In the example embodiment, the patterning of the semiconductor layer by the patterning process can include: after the semiconductor layer is deposited, a layer of photoresist is coated on the semiconductor layer, the photoresist is exposed using a half-tone mask, after development, the photoresist forms a fully exposed area, a partially exposed area and an unexposed area, the photoresist in the fully exposed area is removed, the fully exposed area exposes the surface of the semiconductor layer, the photoresist in the partially exposed area is partially removed, the photoresist in the partially exposed area has a first thickness, the photoresist in the unexposed area is unchanged, the photoresist in the unexposed area has a second thickness, the first thickness is less than the second thickness. The unexposed area is the channel region of each active layer, and the partially exposed area is the area that needs to be processed to be conductive. Subsequently, the semiconductor layer in the fully exposed area is etched away by an etching process to form the patterns of the first active layer 21, the second active layer 22, the third active layer 23 and the second plate 62. Subsequently, the photoresist in the partially exposed area is removed by a gray ash process, so that the partially exposed area exposes the semiconductor layer, and the unexposed area still covers the photoresist, i.e. the channel region of each active layer covers the photoresist, and the area outside the channel region is exposed. Subsequently, the semiconductor layer in the partially exposed area is processed to be conductive to form the conductive second plate 62 and the conductive first and second regions of each active layer. Finally, the remaining photoresist is stripped.

[0153] As shown in FIG. 6C, through this patterning process, the first insulating layer 71 covering the first conductive layer and the second conductive layer, and the semiconductor layer disposed on the side of the first insulating layer 71 away from the substrate 10 are formed. The semiconductor layer can at least include the second active layer 22, the third active layer 23 and the second plate 62, the orthographic projection of the second plate 62 on the substrate at least partially overlaps the orthographic projection of the first plate 61 on the substrate, and the first plate 61 and the second plate 62 form a transparent storage capacitor.

[0154] In the example embodiment, the semiconductor layer can be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0155] In the example embodiment, in at least one repeating unit, the positions of each pattern in the semiconductor layer in the first sub-pixel P1 can be substantially mirror-symmetrical relative to the horizontal reference line with the positions of each pattern in the semiconductor layer in the third sub-pixel P3, the positions of each pattern in the semiconductor layer in the second sub-pixel P2 can be substantially mirror-symmetrical relative to the horizontal reference line with the positions of each pattern in the semiconductor layer in the fourth sub-pixel P4, the positions of each pattern in the semiconductor layer in the first sub-pixel P1 can be substantially mirror-symmetrical relative to the vertical reference line with the positions of each pattern in the semiconductor layer in the second sub-pixel P2, and the positions of each pattern in the semiconductor layer in the third sub-pixel P3 can be substantially mirror-symmetrical relative to the vertical reference line with the positions of each pattern in the semiconductor layer in the fourth sub-pixel P4.

[0156] (3) Forming a second insulating layer pattern. In the example embodiment, forming the second insulating layer pattern can include: depositing a second insulating thin film on the substrate on which the aforementioned pattern is formed, and patterning the second insulating thin film by a patterning process to form the second insulating layer pattern covering the semiconductor layer, the second insulating layer being provided with a plurality of vias, as shown in FIGS. 7A and 7B, FIG. 7B being a sectional view along A-A direction in FIG. 7A.

[0157] In the example embodiment, the plurality of vias of each sub-pixel in each repeating unit at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, and a seventh via V7.

[0158] In the example embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer 21 on the substrate, the second insulating layer in the first via V1 is etched away to expose the surface of the first region of the first active layer 21, and the first via V1 is configured to allow the data signal line formed subsequently to pass through the via while connecting with the first region of the first active layer 21. In the example embodiment, the first via V1 can serve as a data via of the present disclosure.

[0159] In the example embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the first region of the second active layer 22 on the substrate, the second insulating layer in the second via V2 is etched away to expose the surface of the first region of the second active layer 22, and the second via V2 is configured to allow the first power supply line formed subsequently to pass through the via while connecting with the first region of the second active layer 22. In the example embodiment, the second via V2 can serve as a power supply via of the present disclosure.

[0160] In the example embodiment, the first regions of the second active layers 22 of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X are connected to each other, so that the two adjacent sub-pixels in the two adjacent repeating units in the first direction X can share the same second via V2. For example, the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 can share the same second via V2. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 can share the same second via V2.

[0161] In the example embodiment, the first regions of the second active layers 22 of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y are connected to each other, so that the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y can share the same second via V2. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 can share the same second via V2. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 can share the same second via V2.

[0162] In the example embodiment, the adjacent sub-pixels in the adjacent repeating units in the first direction X and the second direction Y share the same second via V2, i.e., the four adjacent sub-pixels in the adjacent repeating units share the same second via V2. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are two adjacent sub-pixels, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the second sub-pixel P2 of the third repeating unit Q3 and the first sub-pixel P1 of the fourth repeating unit Q4 are two adjacent sub-pixels, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q3 are two adjacent sub-pixels, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 of the second repeating unit Q2 and the first sub-pixel P1 of the fourth repeating unit Q4 are two adjacent sub-pixels, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3 and the first sub-pixel P1 of the fourth repeating unit Q4 share the same second via V2. The present disclosure can effectively reduce the number of vias, reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, and simplify the manufacturing process, reduce production costs, and improve product yield by arranging the four adjacent sub-pixels in the adjacent repeating units to share the same second via V2.

[0163] In the example embodiment, the third via V3 has a projection on the substrate within the projection of the second region of the second active layer 22 and the third connection electrode 13 on the substrate. The third via V3 is a via of the transfer structure, including a shallow half-hole in which the second insulating layer is etched away to expose the surface of the second region of the second active layer 22, and a deep half-hole in which the first insulating layer and the second insulating layer are etched away to expose the surface of the third connection electrode 13, so that the two half-holes of the via of the transfer structure simultaneously expose the second region of the second active layer 22 and the third connection electrode 13. The third via V3 is configured to allow the fifth connection electrode formed subsequently to connect to the second region of the second active layer 22 and the third connection electrode 13 through the via. The third via V3 can serve as the first bridging via of the present disclosure.

[0164] In the example embodiment, the first dimension L1 of the third via V3 can be greater than the second dimension L2 of the third via V3, the first dimension L1 being the dimension of the third via V3 in the first direction X, and the second dimension L2 being the dimension of the third via V3 in the second direction Y.

[0165] In the example embodiment, the second via V2 and the third via V3 are not on a straight line extending along the first direction X.

[0166] In the example embodiment, in the second direction Y, the second via V2 shared by the two adjacent sub-pixels in the two adjacent repeating units can be located between the two third vias V3 in the two adjacent repeating units.

[0167] In the example embodiment, the fourth via V4 has a projection on the substrate within the projection of the first region of the third active layer 23 on the substrate. The second insulating layer in the fourth via V4 is etched away to expose the surface of the first region of the third active layer 23. The fourth via V4 is configured to allow the compensation signal line formed subsequently to connect to the first region of the third active layer 23 through the via. In the example embodiment, the fourth via V4 can serve as the compensation via of the present disclosure.

[0168] In the example embodiment, since the first regions of the third active layer 23 of the two adjacent sub-pixels in the first direction X in one repeating unit are connected to each other, the two adjacent sub-pixels in the first direction X can share the same fourth via V4.

[0169] In the example embodiment, since the first regions of the third active layer 23 of the two adjacent sub-pixels in the second direction Y in one repeating unit are connected to each other, the two adjacent sub-pixels in the second direction Y can share the same fourth via V4.

[0170] In the example embodiment, the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4 in the repeating unit can share the same fourth via V4 because the first regions of the third active layers of the four sub-pixels in the repeating unit are connected to each other. By providing the fourth via V4 shared by adjacent sub-pixels, the number of vias can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, the manufacturing process can be simplified, the production cost can be reduced, and the product yield can be improved.

[0171] In the example embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the second region of the third active layer 23 and the fourth connection electrode 14 on the substrate. The fifth via V5 is a via of the switching structure, including a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the second region of the third active layer 23. The first insulating layer and the second insulating layer in the deep half-hole are etched away, exposing the surface of the fourth connection electrode 14, so that the via of the switching structure composed of the two half-holes simultaneously exposes the second region of the third active layer 23 and the fourth connection electrode 14. The fifth via V5 is configured to allow the sixth connection electrode formed subsequently to connect to the second region of the third active layer 23 and the fourth connection electrode 14 through the via. The fifth via V5 can serve as a second lap joint via of the present disclosure.

[0172] In the example embodiment, the third dimension L3 of the fifth via V5 can be smaller than the fourth dimension L4 of the fifth via V5. The third dimension L3 is the dimension of the first direction X of the fifth via V5, and the fourth dimension L4 is the dimension of the second direction Y of the fifth via V5.

[0173] In the example embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the orthographic projection of the second plate 62 on the substrate. The second insulating layer in the sixth via V6 is etched away, exposing the surface of the second plate 62. The sixth via V6 is configured to allow the second gate electrode formed subsequently to connect to the second plate 62 through the via. In the example embodiment, the sixth via V6 can serve as a plate via of the present disclosure.

[0174] In the example embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the orthographic projection of the scan signal line 30 on the substrate. The first insulating layer and the second insulating layer in the seventh via V7 are etched away, exposing the surface of the scan signal line 30. The seventh via V7 is configured to allow the gate connection electrode formed subsequently to connect to the scan signal line 30 through the via. In the example embodiment, the seventh via V7 serves as a gate connection via of the present embodiment.

[0175] In the example embodiment, in at least one repeating unit, the first sub-pixel P1 and the third sub-pixel P3 can share one seventh via V7, and the second sub-pixel P2 and the fourth sub-pixel P4 can share one seventh via V7, that is, two sub-pixels adjacent in the second direction Y share one seventh via V7. By setting two adjacent sub-pixels to share one seventh via V7, the number of vias can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, and the manufacturing process can be simplified, the production cost can be reduced, and the product yield can be improved.

[0176] As shown in FIG. 7B, by the present patterning process, a second insulating layer 72 covering the semiconductor layer is formed, and the second insulating layer 72 is provided with at least a fifth via V5, a sixth via V6, and a seventh via V7. The fifth via V5 includes a shallow half-hole and a deep half-hole, the second insulating layer 72 in the shallow half-hole is etched away to expose the surface of the third active layer 23, and the first insulating layer 71 and the second insulating layer 72 in the deep half-hole are etched away to expose the surface of the fourth connection electrode 14, so that the fifth via V5 of the transfer structure composed of two half-holes simultaneously exposes the third active layer 23 and the fourth connection electrode 14. The second insulating layer 72 in the sixth via V6 is etched away to expose the surface of the second plate 62. The first insulating layer 71 and the second insulating layer 72 in the seventh via V7 are etched away to expose the surface of the scanning signal line 30.

[0177] (4) Forming a third conductive layer pattern. In the example embodiment, forming the third conductive layer pattern can include: depositing a third conductive film on the substrate on which the aforementioned patterns are formed, and patterning the third conductive film by a patterning process to form a third conductive layer pattern on the second insulating layer, as shown in FIGS. 8A, 8B, and 8C, FIG. 8B is a schematic view of the third conductive layer in FIG. 8A, and FIG. 8C is a cross-sectional view in the direction of A-A in FIG. 8A. In the example embodiment, the third conductive layer can be referred to as a gate metal (GT) layer.

[0178] In the example embodiment, the third conductive layer of each sub-pixel in each repeating unit can include at least a fifth connection electrode 15, a sixth connection electrode 16, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, and a gate connection electrode 34.

[0179] In the example embodiment, the fifth connection electrode 15 can have a block shape (such as a rectangular shape), and can be arranged on the side of the second plate 62 away from the scanning signal line 30. The fifth connection electrode 15 is connected to the second region of the second active layer 22 and the third connection electrode 13 through the third via V3.

[0180] In the example embodiment, the orthogonal projection of the fifth connection electrode 15 on the substrate can contain the orthogonal projection of the third via hole V3 on the substrate.

[0181] In the example embodiment, since the fifth connection electrode 15 is connected to the second region of the second active layer 22 and the third connection electrode 13 at the same time, the third connection electrode 13 is connected to the first connection electrode 11, and the first connection electrode 11 is connected to the first plate 61, the fifth connection electrode 15 makes the second plate of the second transistor and the first plate 61 have the same potential. In the example embodiment, the fifth connection electrode 15 is configured to be connected to the anode connection electrode formed later.

[0182] In the example embodiment, the shape of the sixth connection electrode 16 can be a block shape (such as a rectangle), which can be arranged on the side of the second plate 62 close to the scan signal line 30, and the sixth connection electrode 16 is connected to the second region of the third active layer 23 and the fourth connection electrode 14 at the same time through the fifth via hole V5.

[0183] In the example embodiment, the orthogonal projection of the sixth connection electrode 16 on the substrate can contain the orthogonal projection of the fifth via hole V5 on the substrate.

[0184] In the example embodiment, since the sixth connection electrode 16 is connected to the second region of the third active layer 23 and the fourth connection electrode 14 at the same time, the fourth connection electrode 14 is connected to the second connection electrode 12, and the second connection electrode 12 is connected to the first plate 61, the sixth connection electrode 16 makes the second plate of the third transistor and the first plate 61 have the same potential.

[0185] In the example embodiment, the fifth connection electrode 15 and the sixth connection electrode 16 realize the connection between the second plate of the second transistor, the second plate of the third transistor, and the first plate 61 (the second end of the storage capacitor), form the second node in the pixel driving circuit, and thus the first plate 61 has the potential of the second node in the pixel driving circuit.

[0186] In the example embodiment, the shape of the gate connection electrode 34 can be a strip shape extending along the first direction X, which can be arranged in the middle of the second direction Y of the repeating unit, i.e., between the first sub-pixel P1 and the second sub-pixel P2 and the third sub-pixel P3 and the fourth sub-pixel P4, the orthogonal projection of the gate connection electrode 34 on the substrate at least partially overlaps the orthogonal projection of the scan signal line 30 on the substrate, and the gate connection electrode 34 is connected to the scan signal line 30 through the seventh via hole V7. In the example embodiment, the orthogonal projection of the gate connection electrode 34 on the substrate can contain the orthogonal projection of the seventh via hole V7 (gate connection via hole) on the substrate.

[0187] In the example embodiment, in at least one repeating unit, the first sub-pixel P1 and the third sub-pixel P3 can share one gate connection electrode 34, and the second sub-pixel P2 and the fourth sub-pixel P4 can share one gate connection electrode 34, that is, two adjacent sub-pixels in the second direction Y can share one gate connection electrode 34. By arranging that two adjacent sub-pixels share one gate connection electrode 34, the number of connection electrodes can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, and the manufacturing process can be simplified, the production cost can be reduced, and the product yield can be improved.

[0188] In the example embodiment, the first gate electrode 31 can have a strip shape extending along the second direction Y, can be arranged on the side of the gate connection electrode 34 close to the first active layer 21, the first end of the first gate electrode 31 is connected with the gate connection electrode 34, the second end of the first gate electrode 31 extends towards the first active layer 21, and the orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer 21 on the substrate. In the example embodiment, the first gate electrode 31 can serve as the gate electrode of the first transistor T1, and can control the conduction or disconnection of the first transistor T1.

[0189] In the example embodiment, the first gate electrode 31 and the gate connection electrode 34 can be an integrated structure connected with each other. Since two adjacent sub-pixels share one gate connection electrode 34, the gate connection electrode 34 and the first gate electrode 31 of the two adjacent sub-pixels are an integrated structure connected with each other. For example, the gate connection electrode 34, the first gate electrode 31 of the first sub-pixel P1 and the first gate electrode 31 of the third sub-pixel P3 are an integrated structure connected with each other. For another example, the gate connection electrode 34, the first gate electrode 31 of the second sub-pixel P2 and the first gate electrode 31 of the fourth sub-pixel P4 are an integrated structure connected with each other.

[0190] In the example embodiment, the second gate electrode 32 can have a strip shape extending along the second direction Y, the first end of the second gate electrode 32 is connected with the second plate 62 through the sixth via V6, the second end of the second gate electrode 32 extends towards the second active layer 22, and the orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate. In the example embodiment, the second gate electrode 32 can serve as the gate electrode of the second transistor T2, and can control the conduction or disconnection of the second transistor T2.

[0191] In the example embodiment, the orthographic projection of the second gate electrode 32 on the substrate can include the orthographic projection of the sixth via V6 (plate via) on the substrate.

[0192] In the example embodiment, since the second gate electrode 32 is connected with the second plate 62, and the second plate 62 is connected with the second region of the first active layer 21, the second electrode of the first transistor T1, the gate electrode of the second transistor T2 and the second plate 62 (the first terminal of the storage capacitor) have the same potential, forming the first node in the pixel driving circuit, and the second plate 62 has the potential of the first node in the pixel driving circuit.

[0193] In the example embodiment, since the first plate 61 has the potential of the second node in the pixel driving circuit, and the second plate 62 has the potential of the first node in the pixel driving circuit, the first plate 61 with the potential of the second node and the second plate 62 with the potential of the first node form the storage capacitor.

[0194] In the example embodiment, since the first plate 61 is made of transparent conductive material, and the second plate 62 is made of transparent metal oxide, the storage capacitor is a transparent capacitor.

[0195] In the example embodiment, the third gate electrode 33 can be in the shape of a strip extending along the second direction Y, and can be arranged on the side of the gate connecting electrode 34 close to the third active layer 23, the first end of the third gate electrode 33 is connected with the gate connecting electrode 34, the second end of the third gate electrode 33 extends towards the third active layer 23, and the orthographic projection of the third gate electrode 33 on the substrate at least partially overlaps with the orthographic projection of the third active layer 23 on the substrate. In the example embodiment, the third gate electrode 33 can serve as the gate electrode of the third transistor T3, and can control the on or off of the third transistor T3.

[0196] In the example embodiment, the third gate electrode 33 and the gate connecting electrode 34 can be an integrated structure connected with each other. Since two adjacent sub-pixels share one gate connecting electrode 34, the gate connecting electrode 34 and the third gate electrodes 33 of the two adjacent sub-pixels are an integrated structure connected with each other. For example, the gate connecting electrode 34, the third gate electrode 33 of the first sub-pixel P1 and the third gate electrode 33 of the third sub-pixel P3 are an integrated structure connected with each other. For another example, the gate connecting electrode 34, the third gate electrode 33 of the second sub-pixel P2 and the third gate electrode 33 of the fourth sub-pixel P4 are an integrated structure connected with each other.

[0197] In the example embodiment, the gate connecting electrode 34 and the first gate electrode 31 and the third gate electrode 33 of the two adjacent sub-pixels are in an integrated structure connected with each other. For example, the gate connecting electrode 34, the first gate electrode 31 and the third gate electrode 33 of the first sub-pixel P1, and the first gate electrode 31 and the third gate electrode 33 of the third sub-pixel P3 are in an integrated structure connected with each other. For another example, the gate connecting electrode 34, the first gate electrode 31 and the third gate electrode 33 of the second sub-pixel P2, and the first gate electrode 31 and the third gate electrode 33 of the fourth sub-pixel P4 are in an integrated structure connected with each other.

[0198] In the example embodiment, since the gate connecting electrode 34 is connected with the scan signal line 30, in one sub-pixel, one scan signal line 30 is connected with the first gate electrode 31 and the third gate electrode 33 at the same time, so that the scan signal line 30 can control the turn-on or turn-off of the first transistor T1 and the third transistor T3 in one sub-pixel.

[0199] In the example embodiment, in one pixel row, one scan signal line 30 is connected with all the first gate electrodes 31 and all the third gate electrodes 33 in multiple sub-pixels through the gate connecting electrode 34 at the same time, so that the scan signal line 30 can control the turn-on or turn-off of all the first transistors T1 and all the third transistors T3 in one pixel row.

[0200] In the example embodiment, in one repeating unit, one scan signal line 30 is connected with all the first gate electrodes 31 and all the third gate electrodes 33 in multiple sub-pixels through the gate connecting electrode 34 at the same time, so that the scan signal line 30 can control the turn-on or turn-off of all the first transistors T1 and all the third transistors T3 in the repeating unit at the same time.

[0201] In the example embodiment, the second conductive layer of each repeating unit in the display substrate can further include two first power lines 51, four data signal lines 52, and one compensation signal line 53.

[0202] In the example embodiment, the shapes of the first power line 51, the data signal line 52, and the compensation signal line 53 can be straight lines or broken lines with the main body part extending along the second direction Y, the compensation signal line 53 can be located in the middle of the first direction X of the repeating unit, the first first power line 51 can be located on the side opposite to the first direction X of the repeating unit, the second first power line 51 can be located on the side of the first direction X of the repeating unit, two of the four data signal lines 52 can be located between the first first power line 51 and the compensation signal line 53, and the other two of the four data signal lines 52 can be located between the second first power line 51 and the compensation signal line 53.

[0203] In the example embodiment, the first power line 51 and the compensation signal line 53 can define a first pixel column, and two data signal lines 52 are arranged in the first pixel column. The second power line 51 and the compensation signal line 53 can define a second pixel column, and two data signal lines 52 are arranged in the second pixel column.

[0204] In the example embodiment, the four data signal lines 52 can include a first data signal line and a second data signal line arranged in the first pixel column, a third data signal line and a fourth data signal line arranged in the second pixel column. The first data signal line can be arranged on one side of the first power line 51 in the first direction X, the second data signal line can be arranged on one side of the first data signal line in the first direction X, and the first electrode plate 61 and the second electrode plate 62 can be located between the second data signal line and the compensation signal line 53. The fourth data signal line can be arranged on the opposite side of the second power line 51 in the first direction X, the third data signal line can be arranged on the opposite side of the fourth data signal line in the first direction X, and the first electrode plate 61 and the second electrode plate 62 can be located between the compensation signal line 53 and the third data signal line.

[0205] In the example embodiment, two adjacent repeating units in the first direction X can share the same first power line 51. For example, the first repeating unit Q1 and the second repeating unit Q2 can share the same first power line 51. The third repeating unit Q3 and the fourth repeating unit Q4 can share the same first power line 51. By arranging adjacent repeating units to share the same first power line, the number of signal lines and the number of vias can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, and the display resolution can be improved.

[0206] In the example embodiment, the first power line 51 can be connected to the first region of the second active layer 22 through the second via V2, so that the first power line 51 writes the first power signal to the first electrode of the second transistor T2.

[0207] In the example embodiment, the orthogonal projection of the first power line 51 on the substrate can contain the orthogonal projection of the second via V2 (power via) on the substrate.

[0208] In the example embodiment, in each repeating unit, the first power line 51 of the first pixel column can simultaneously provide the first power signal to the pixel driving circuit in the first sub-pixel P1 and the third sub-pixel P3, and the first power line 51 of the second pixel column can simultaneously provide the first power signal to the pixel driving circuit in the second sub-pixel P2 and the fourth sub-pixel P4, so that the first power line 51 in one repeating unit is a one-to-two structure. The present disclosure shows that by designing the first power line as a one-to-two structure, the number of signal lines is saved, the occupied space is reduced, the structure is simple, the layout is reasonable, the layout space is fully utilized, the space utilization is improved, the pixel aperture rate is increased, and the display resolution is improved.

[0209] In the example embodiment, the two first power lines 51 in one repeating unit are symmetrically arranged with respect to the compensation signal line 53, and the second transistor T2 of the first pixel column is symmetrically arranged with respect to the compensation signal line 53 with the second transistor T2 of the second pixel column. The symmetric structure of the present disclosure can ensure that the voltage drop of the first power line to the second transistor T2 is substantially the same, thereby ensuring display uniformity.

[0210] In the example embodiment, the data signal line 52 can be connected to the first region of the first active layer through the first via V1, thereby realizing that the data signal line 52 writes the data signal to the first electrode of the first transistor T1.

[0211] In the example embodiment, the orthogonal projection of the data signal line 52 on the substrate can include the orthogonal projection of the first via V1 (data via) on the substrate.

[0212] In the example embodiment, the four data signal lines 52 can include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. In each repeating unit, the first data signal line can be connected to the first region of the first active layer of the first sub-pixel P1 through the first via V1, the second data signal line can be connected to the first region of the first active layer in the third sub-pixel P3 through the first via V1, the third data signal line can be connected to the first region of the first active layer in the fourth sub-pixel P4 through the first via V1, and the fourth data signal line can be connected to the first region of the first active layer in the second sub-pixel P2 through the first via V1.

[0213] In the example embodiment, the compensation signal line 53 can be connected to the first region of the third active layer 23 through the fourth via V4, thereby realizing that the compensation signal line 53 writes the compensation signal to the first electrode of the third transistor T3.

[0214] In the example embodiment, the orthogonal projection of the compensation signal line 53 on the substrate can include the orthogonal projection of the fourth via V4 (compensation via) on the substrate.

[0215] In the example embodiment, since the first regions of the third active layers of the four sub-pixels in the repeating unit are connected to each other, the four sub-pixels share the same fourth via V4, and thus share the same compensation signal line 53, that is, the four pixel driving circuits in one repeating unit share one compensation signal line 53, and the compensation signal line 53 in one repeating unit is a one-to-four structure. The present disclosure shows that by designing the compensation signal line as a one-to-four structure, the number of signal lines is saved, the occupied space is reduced, the structure is simple, the layout is reasonable, the layout space is fully utilized, the space utilization rate is improved, the pixel aperture rate is increased, and the display resolution is improved.

[0216] In the example embodiment, the compensation signal line 53 is arranged between the first pixel column and the second pixel column, and the third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are symmetrically arranged with respect to the compensation signal line 53. The symmetric structure of the present disclosure can ensure that the RC delay of the compensation signal writing into the third transistor T3 is substantially the same, and the display uniformity is ensured.

[0217] In the example embodiment, the first power supply line 51, the data signal line 52, and the compensation signal line 53 can be non-equal-width broken lines. The use of variable-width broken lines can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance.

[0218] In the example embodiment, in at least one repeating unit, the positions of the two first power supply lines 51 can be substantially mirror-symmetric with respect to the vertical reference line, and the positions of the two data signal lines 52 located on the side opposite to the first direction X of the compensation signal line 53 and the positions of the two data signal lines 52 located on the side of the first direction X of the compensation signal line 53 can be substantially mirror-symmetric with respect to the vertical reference line.

[0219] In the example embodiment, in at least one repeating unit, the positions of the various patterns in the third conductive layer in the first sub-pixel P1 and the positions of the various patterns in the third conductive layer in the third sub-pixel P3 can be substantially mirror-symmetric with respect to the horizontal reference line, the positions of the various patterns in the third conductive layer in the second sub-pixel P2 and the positions of the various patterns in the third conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to the horizontal reference line, the positions of the various patterns in the third conductive layer in the first sub-pixel P1 and the positions of the various patterns in the third conductive layer in the second sub-pixel P2 can be substantially mirror-symmetric with respect to the vertical reference line, and the positions of the various patterns in the third conductive layer in the third sub-pixel P3 and the positions of the various patterns in the third conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to the vertical reference line.

[0220] As shown in FIG. 8C, the third conductive layer is formed on the second insulating layer 72 by the present patterning process, and the third conductive layer at least includes the sixth connecting electrode 16, the second gate electrode 32 and the gate connecting electrode 34. The sixth connecting electrode 16 is connected with the third active layer 23 and the fourth connecting electrode 14 through the fifth via V5, the second gate electrode 32 is connected with the second plate 62 through the sixth via V6, and the gate connecting electrode 34 is connected with the scanning signal line 30 through the seventh via V7.

[0221] In the exemplary embodiments, the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0222] (5) Forming a third insulating layer and a planar layer pattern. In the exemplary embodiments, forming the third insulating layer and the planar layer pattern can include: on the substrate on which the aforementioned pattern is formed, first depositing a third insulating film, then coating a planar film, and patterning the planar film and the third insulating film by a patterning process to form the third insulating layer covering the third conductive layer and the planar layer pattern disposed on the third insulating layer, and the planar layer is provided with a plurality of vias, as shown in FIG. 9.

[0223] In the exemplary embodiments, the via of each sub-pixel in each repeating unit at least includes an eleventh via V11.

[0224] In the exemplary embodiments, the orthographic projection of the eleventh via V11 on the substrate is within the range of the orthographic projection of the fifth connecting electrode 15 on the substrate, the third insulating layer and the planar layer in the eleventh via V11 are etched away to expose the surface of the fifth connecting electrode 15, and the eleventh via V11 is configured to enable the anode connecting electrode formed subsequently to be connected with the fifth connecting electrode 15 through the via.

[0225] In the exemplary embodiments, the present process uses a one-time patterning process to form the vias on the third insulating layer and the planar layer at the same time, i.e., the third insulating layer and the planar layer share a one-time half-tone or gray-tone mask (MASK) process, effectively reducing the number of times of the patterning process.

[0226] (6) Forming a fourth conductive layer pattern. In the exemplary embodiments, forming the fourth conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a fourth conductive film, and patterning the fourth conductive film by a patterning process to form the fourth conductive layer pattern on the color film layer, as shown in FIG. 10A and FIG. 10B, and FIG. 10B is a schematic diagram of the fourth conductive layer in FIG. 10A. In the exemplary embodiments, the fourth conductive layer can be referred to as a second transparent (2ITO) layer.

[0227] In an example embodiment, the fourth conductive layer of each sub-pixel in each repeating unit can include at least the first electrode 63 and the anode connecting electrode 64.

[0228] In an example embodiment, the first electrode 63 can have a rectangular shape, and the corner of the rectangular shape can be provided with a chamfer, a groove or a protrusion, and the orthographic projection of the first electrode 63 on the substrate at least partially overlaps the orthographic projection of the second plate 62 on the substrate.

[0229] In an example embodiment, the anode connecting electrode 64 can have a block shape (e.g., a rectangular shape), and can be located on the side of the first electrode 63 away from the scan signal line 30. The first end of the anode connecting electrode 64 is connected to the first electrode 63, and the second end of the anode connecting electrode 64 extends away from the scan signal line 30 and is connected to the fifth connecting electrode 15 through the eleventh via V11.

[0230] In an example embodiment, in at least one sub-pixel, the anode connecting electrode 64 and the first electrode 63 can be an integrated structure connected to each other.

[0231] In an example embodiment, in at least one repeating unit, the four first electrodes 63 can be arranged in a square shape. The upper left first electrode is connected to the pixel driving circuit in the first sub-pixel P1, the upper right first electrode is connected to the pixel driving circuit in the second sub-pixel P2, the lower left first electrode is connected to the pixel driving circuit in the third sub-pixel P3, and the lower right first electrode is connected to the pixel driving circuit in the fourth sub-pixel P4. In some possible implementations, the first electrode can serve as the anode of the light emitting device, and the arrangement of the first electrode can be adjusted according to actual needs, which is not limited in the present disclosure.

[0232] In an example embodiment, the material of the first conductive layer can be a transparent conductive material, such as indium tin oxide ITO or indium zinc oxide IZO.

[0233] In an example embodiment, the first electrode 63 can also serve as an auxiliary capacitor of the storage capacitor. Since the first electrode 63 is connected to the anode connecting electrode 64, and the anode connecting electrode 64 is connected to the first plate 61 through the fifth connecting electrode 15, the third connecting electrode 13 and the first connecting electrode 11, the first electrode 63 has the potential of the second node in the pixel driving circuit, so that the first electrode 63 with the potential of the second node and the second plate 62 with the potential of the first node form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. The present disclosure utilizes the first electrode to form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel, which can effectively increase the capacitance value of the storage capacitor on the one hand, and can reduce the plate area while ensuring the capacitance value of the storage capacitor on the other hand, thereby effectively reducing the occupied area.

[0234] (7) Forming a pixel definition layer. In an example embodiment, forming the pixel definition layer pattern can include: on the substrate on which the aforementioned pattern is formed, applying a pixel definition film, patterning the pixel definition film by a patterning process, and forming the pixel definition layer covering the fourth conductive layer, as shown in FIG. 11.

[0235] In an example embodiment, a pixel opening PK is formed on the pixel definition layer of each sub-pixel in each repeating unit, the pixel definition film in the pixel opening PK is removed, and part of the surface of the first electrode 63 is exposed, and the orthographic projection of the pixel opening PK on the substrate is within the orthographic projection of the first electrode 63 on the substrate.

[0236] In an example embodiment, the shape of the pixel opening PK can be similar to the shape of the first electrode 63 in a plane parallel to the substrate, and the cross-sectional shape of the pixel opening PK can be rectangular or trapezoidal, etc. in a plane perpendicular to the substrate.

[0237] In an example embodiment, the shape of the pixel opening can include any one or more of the following: triangular, rectangular, trapezoidal, parallelogram, pentagon, hexagon, circular, and elliptical.

[0238] In an example embodiment, the shapes of the pixel openings of the four sub-pixels in the repeating unit can be the same or different. The areas of the pixel openings of the four sub-pixels can be the same or different.

[0239] In an example embodiment, the shapes and areas of the pixel openings of the four sub-pixels in the repeating unit can be different to adapt to the transmittance of different sub-pixel filters, so that the light emitting devices of the four sub-pixels can emit the same brightness at different currents, maximize the life of the light emitting devices of the four sub-pixels, and ensure the product life.

[0240] In an example embodiment, at least one partition groove M can also be provided on the pixel definition layer of each repeating unit, the shape of the partition groove M can be a strip shape extending along the second direction Y, and the partition groove M can be arranged between the pixel openings PK adjacent in the first direction X. For example, the partition groove M can be arranged between the pixel opening PK of the first sub-pixel P1 and the pixel opening PK of the second sub-pixel P2. For another example, the partition groove M can be arranged between the pixel opening PK of the third sub-pixel P3 and the pixel opening PK of the fourth sub-pixel P4. In an example embodiment, the partition groove M is configured to cut off the organic light emitting layer formed subsequently, block the lateral propagation path of the hole type carrier, eliminate lateral leakage, and eliminate lateral cross talk of the sub-pixels.

[0241] In the exemplary embodiments, the pixel definition layer can be made of polyimide, acrylic, polyethylene terephthalate, or the like.

[0242] (8) Forming the organic light-emitting layer and the cathode pattern. In the exemplary embodiments, forming the organic light-emitting layer and the cathode pattern can include: first forming the organic light-emitting layer pattern, the organic light-emitting layer being connected to the first electrode 63 through the pixel opening PK. Then forming the second electrode, the second electrode being connected to the organic light-emitting layer. In the exemplary embodiments, the second electrode can serve as the cathode of the light-emitting device.

[0243] In the exemplary embodiments, the organic light-emitting layer can include a light-emitting layer (EML), and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In the exemplary embodiments, the organic light-emitting layer can be formed by fine metal mask (FMM) or open mask evaporation, or by an inkjet process.

[0244] (8) Forming the encapsulation structure layer pattern. In the exemplary embodiments, forming the encapsulation structure layer pattern can include: first depositing a first inorganic thin film using an open mask to form a first encapsulation layer. Then, using an inkjet printing process to inkjet print an organic material on the first encapsulation layer, and after curing the film, a second encapsulation layer is formed. Then, depositing a second inorganic thin film using an open mask to form a third encapsulation layer, the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer forming the encapsulation structure layer. The first encapsulation layer and the third encapsulation layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbon nitride (SiCN), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer. The second encapsulation layer can be made of a resin material, forming a stacked structure of inorganic material / organic material / inorganic material, with the organic material layer being disposed between the two inorganic material layers, so as to prevent external water vapor from entering the light-emitting structure layer.

[0245] Thus far, the preparation of the display substrate of the exemplary embodiments of the present disclosure is completed. The display substrate can include a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the substrate. In a direction perpendicular to the display substrate, the driving circuit layer can include, sequentially disposed on the substrate, a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, and a planarization layer. The light-emitting structure layer can include a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode. The encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together.

[0246] In the example embodiment, for the display substrate including the color film structure layer, after the third conductive layer is formed, the third insulating layer is formed first, then the red color film layer, the green color film layer and the blue color film layer are sequentially formed, and then the planarization layer is formed, which will not be described here.

[0247] In the example embodiment, the substrate can be a flexible substrate or can be a rigid substrate. The rigid substrate can be one or more of, but not limited to, glass, quartz, and the flexible substrate can be one or more of, but not limited to, polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl acid ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In the example embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer stacked, the materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET) or a surface treated polymer soft film and the like, the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx) and the like, for improving the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0248] In the example embodiment, the first insulating layer, the second insulating layer and the third insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, multiple layers or a composite layer. The planarization layer can be an organic material such as resin and the like.

[0249] The structure shown in the disclosure and its preparation process is only an example, in the example embodiment, the corresponding structure can be changed and the patterning process can be increased or reduced, which is not limited in the disclosure.

[0250] The display substrate of the bottom emission structure provided by the example embodiment of the disclosure optimizes the structure of the pixel driving circuit, can effectively reduce the occupied area of the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution.

[0251] The display substrate of the example embodiment of the disclosure is formed synchronously in one patterning process through the first conductive layer and the second conductive layer, the scanning signal line and the auxiliary signal line form a double-layer structure of the signal line structure, which can effectively reduce the resistance of the scanning signal line, reduce the voltage drop of the scanning signal, and improve the display performance.

[0252] The display substrate provided by the embodiment of the present disclosure forms a semiconductor layer through a patterning process of a half-tone mask plate, and completes the conductorization process while forming the semiconductor layer, thereby reducing the process, improving the conductorization process effect, and adopting a via hole lapping mode. Compared with the existing structure in which the conductorization process is performed after the via hole is formed, the present disclosure not only effectively reduces the size of the via hole, effectively reduces the occupied area of the via hole connection structure, effectively reduces the occupied area of the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution, but also reduces the number of processes, effectively improves the production efficiency, effectively reduces the production cost, and maximizes the product yield.

[0253] The display substrate provided by the embodiment of the present disclosure forms a semiconductor layer through a patterning process of a half-tone mask plate, and completes the conductorization process while forming the semiconductor layer, thereby reducing the process, improving the conductorization process effect, and adopting a via hole lapping mode. Compared with the existing structure in which the conductorization process is performed after the via hole is formed, the present disclosure not only effectively reduces the size of the via hole, effectively reduces the occupied area of the via hole connection structure, effectively reduces the occupied area of the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution, but also reduces the number of processes, effectively improves the production efficiency, effectively reduces the production cost, and maximizes the product yield.

[0254] The display substrate provided by the embodiment of the present disclosure forms a semiconductor layer through a patterning process of a half-tone mask plate, and completes the conductorization process while forming the semiconductor layer, thereby reducing the process, improving the conductorization process effect, and adopting a via hole lapping mode. Compared with the existing structure in which the conductorization process is performed after the via hole is formed, the present disclosure not only effectively reduces the size of the via hole, effectively reduces the occupied area of the via hole connection structure, effectively reduces the occupied area of the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution, but also reduces the number of processes, effectively improves the production efficiency, effectively reduces the production cost, and maximizes the product yield.

[0255] The display substrate provided by the embodiment of the present disclosure forms a semiconductor layer through a patterning process of a half-tone mask plate, and completes the conductorization process while forming the semiconductor layer, thereby reducing the process, improving the conductorization process effect, and adopting a via hole lapping mode. Compared with the existing structure in which the conductorization process is performed after the via hole is formed, the present disclosure not only effectively reduces the size of the via hole, effectively reduces the occupied area of the via hole connection structure, effectively reduces the occupied area of the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution, but also reduces the number of processes, effectively improves the production efficiency, effectively reduces the production cost, and maximizes the product yield.

[0256] The display substrate provided by the embodiments of the present disclosure can make light pass through the transparent storage capacitor composed of the transparent conductive layer and the transparent semiconductor layer, so that the storage capacitor can be arranged in the pixel opening, which can effectively increase the capacitance of the storage capacitor and the pixel opening rate.

[0257] The transistor of the display substrate has a top gate structure, high Ion, high opening rate and good electrical stability, which is beneficial to achieve good driving effect and improve the reliability of the display substrate.

[0258] The display substrate can effectively increase the pixel opening rate and improve the display effect by arranging the sub-pixels in a square manner and using a first power line structure of a non-network structure, which is more suitable for display of the display type.

[0259] The preparation process of the present disclosure can be well compatible with the existing preparation process, and has the advantages of simple process implementation, easy implementation, high production efficiency, low production cost and high yield.

[0260] In the example embodiments, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), etc., which is not limited herein.

[0261] The example embodiments of the present disclosure also provide a preparation method of a display substrate for preparing the aforementioned display substrate. In the example embodiments, the display substrate includes a plurality of repeating units, at least one repeating unit includes a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel includes a pixel driving circuit, a scanning signal line and an auxiliary signal line, the scanning signal line is configured to provide a scanning signal to the pixel driving circuit; the pixel driving circuit includes a storage capacitor and at least one transistor, the storage capacitor includes at least a first electrode plate, and the at least one transistor is connected to the first electrode plate through a connection electrode; the preparation method includes:

[0262] forming a first conductive layer and a second conductive layer disposed on a side of the first conductive layer away from the substrate, the auxiliary signal line and the first electrode plate are disposed in the first conductive layer, the scanning signal line and the connection electrode are disposed in the second conductive layer, the orthographic projection of the scanning signal line on the substrate plane is within the range of the orthographic projection of the auxiliary signal line on the substrate plane, and the scanning signal line is overlapped with the auxiliary signal line.

[0263] In an exemplary embodiment, forming a first conductive layer on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate comprises:

[0264] sequentially depositing a first conductive film and a second conductive film;

[0265] using a patterning process of a half-tone mask plate, forming the scanning signal line and the auxiliary signal line by a first etching process, and forming the first plate and the connecting electrode by a second etching process.

[0266] In an exemplary embodiment, the storage capacitor further comprises a second plate, a normal projection of the second plate on the substrate plane at least partially overlaps with a normal projection of the first plate on the substrate plane; and the preparation method further comprises:

[0267] depositing a semiconductor film on a side of the second conductive layer away from the substrate;

[0268] using a patterning process of a half-tone mask plate, sequentially forming the second plate by an etching process and a conductorization process.

[0269] The present disclosure also provides a display device comprising the display substrate of the foregoing embodiments. The display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0270] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not limiting. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, and omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, a scanning signal line and an auxiliary signal line, the scanning signal line being configured to provide a scanning signal to the pixel driving circuit; the pixel driving circuit comprising a storage capacitor and at least one transistor, the storage capacitor comprising at least a first electrode plate, the at least one transistor being connected to the first electrode plate via a connecting electrode; in a direction perpendicular to the display substrate, the display substrate comprising a first conductive layer arranged on a substrate and a second conductive layer arranged on a side of the first conductive layer away from the substrate, the auxiliary signal line and the first electrode plate being arranged in the first conductive layer, the scanning signal line and the connecting electrode being arranged in the second conductive layer, the orthographic projection of the scanning signal line on the substrate plane being within the range of the orthographic projection of the auxiliary signal line on the substrate plane, and the scanning signal line being overlapped with the auxiliary signal line.

2. The display substrate according to claim 1, wherein: The storage capacitor also includes a second electrode plate, and the orthographic projection of the second electrode plate on the substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the substrate plane; the at least one transistor includes a second transistor, and the second transistor includes at least a second gate electrode, and the second gate electrode is connected to the second electrode plate through a plate via, and the orthographic projection of the second gate electrode on the substrate plane includes the orthographic projection of the plate via on the substrate plane.

3. The display substrate according to claim 2, wherein: The second transistor also includes a second active layer, a first area of ​​the second active layer is connected to a first power line through a power via, a second area of ​​the second active layer is connected to the first electrode through a connecting electrode, the first power line is configured to provide a power signal to the pixel driving circuit, and an orthographic projection of the first power line on the substrate plane includes an orthographic projection of the power via on the substrate plane.

4. The display substrate according to claim 3, wherein: The second active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are interconnected as an integrated structure, and / or the second active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are interconnected as an integrated structure.

5. The display substrate according to claim 3, wherein: Two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power via hole, and / or two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power via hole.

6. The display substrate according to claim 3, wherein: The connecting electrode includes a first connecting electrode and a third connecting electrode, the first connecting electrode is connected to the first electrode plate, and the third connecting electrode is overlapped with the first connecting electrode; the pixel driving circuit also includes a fifth connecting electrode, and the fifth connecting electrode is simultaneously connected to the second area of ​​the second active layer and the third connecting electrode through a first overlapping via hole; the first size of the first overlapping via hole is larger than the second size of the first overlapping via hole, the first size is the size of the first overlapping via hole in the pixel row direction, and the second size is the size of the first overlapping via hole in the pixel column direction.

7. The display substrate according to claim 6, wherein: The power via and the first overlapping via are not on a straight line extending along the direction of the pixel row.

8. The display substrate according to claim 6, wherein: In the pixel column direction, the power via hole shared by two adjacent sub-pixels in two adjacent repeating units is located between two adjacent first overlapping via holes in two adjacent repeating units.

9. The display substrate according to claim 1, wherein: The at least one transistor includes a third transistor, the third transistor includes at least a third active layer, a first area of ​​the third active layer is connected to a compensation signal line through a compensation via, a second area of ​​the third active layer is connected to the first electrode plate through a connecting electrode, the compensation signal line is configured to provide a compensation signal to the pixel driving circuit, and an orthographic projection of the compensation signal line on the substrate plane includes an orthographic projection of the compensation via on the substrate plane.

10. The display substrate according to claim 9, wherein: In at least one repeating unit, the third active layers of two adjacent sub-pixels in the pixel row direction are interconnected as an integrated structure, and / or the third active layers of two adjacent sub-pixels in the pixel column direction are interconnected as an integrated structure.

11. The display substrate according to claim 9, wherein: In at least one repeating unit, two adjacent sub-pixels in the pixel row direction share the compensation via hole, and / or two adjacent sub-pixels in the pixel column direction share the compensation via hole.

12. The display substrate according to claim 9, wherein: The connecting electrode includes a second connecting electrode and a fourth connecting electrode, the second connecting electrode is connected to the first electrode plate, and the fourth connecting electrode is overlapped with the second connecting electrode; the pixel driving circuit also includes a sixth connecting electrode, and the sixth connecting electrode is simultaneously connected to the second area of ​​the third active layer and the fourth connecting electrode through a second overlapping via hole; the third size of the second overlapping via hole is smaller than the fourth size of the second overlapping via hole, the third size is the size of the second overlapping via hole in the pixel row direction, and the fourth size is the size of the second overlapping via hole in the pixel column direction.

13. The display substrate according to claim 9, wherein: The pixel driving circuit also includes a first transistor, the first transistor includes at least a first active layer, a first area of ​​the first active layer is connected to a data signal line through a data via, the data signal line is configured to provide a data signal to the pixel driving circuit, and the orthographic projection of the data signal line on the substrate plane includes the orthographic projection of the data via on the substrate plane.

14. The display substrate according to any one of claims 1 to 13, wherein: The pixel driving circuit includes at least a first transistor and a third transistor, the first transistor includes at least a first gate electrode, the third transistor includes at least a third gate electrode, and the first gate electrode and the third gate electrode are respectively connected to the scanning signal line through gate connecting electrodes.

15. The display substrate according to claim 14, wherein: In at least one repeating unit, the gate connection electrode, the first gate electrode and the third gate electrode of two sub-pixels adjacent to each other in the pixel column direction are arranged in the same layer and are an integrated structure connected to each other.

16. The display substrate according to claim 14, wherein: The orthographic projection of the gate connection electrode on the substrate plane at least partially overlaps with the orthographic projection of the scan signal line on the substrate plane, and the gate connection electrode is connected to the scan signal line through a gate connection via.

17. The display substrate according to claim 16, wherein: In at least one repeating unit, two sub-pixels adjacent to each other in the pixel column direction share the gate connection electrode.

18. The display substrate according to claim 16, wherein: In at least one repeating unit, two adjacent sub-pixels in the pixel column direction share the gate connection via hole.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A method for preparing a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, a scanning signal line and an auxiliary signal line, the scanning signal line being configured to provide a scanning signal to the pixel driving circuit; the pixel driving circuit comprising a storage capacitor and at least one transistor, the storage capacitor comprising at least a first electrode plate, the at least one transistor being connected to the first electrode plate via a connecting electrode; the preparation method comprising: A first conductive layer and a second conductive layer arranged on a side of the first conductive layer away from the substrate are formed on a substrate, the auxiliary signal line and the first electrode are arranged in the first conductive layer, the scanning signal line and the connecting electrode are arranged in the second conductive layer, the orthographic projection of the scanning signal line on the substrate plane is located within the range of the orthographic projection of the auxiliary signal line on the substrate plane, and the scanning signal line is overlapped with the auxiliary signal line.

21. The display substrate according to claim 20, wherein: A first conductive layer and a second conductive layer disposed on a side of the first conductive layer away from the substrate are formed on a substrate, comprising: Depositing a first conductive film and a second conductive film in sequence; The scanning signal line and the auxiliary signal line are formed by a first etching process using a half-tone mask patterning process, and the first electrode plate and the connecting electrode are formed by a second etching process.

22. The display substrate according to claim 20, wherein: The storage capacitor further includes a second electrode plate, the orthographic projection of the second electrode plate on the substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the substrate plane; The preparation method further comprises: Depositing a semiconductor thin film on a side of the second conductive layer away from the substrate; The second electrode plate is formed by adopting a patterning process of a half-tone mask plate and sequentially performing an etching process and a conductor treatment process.

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