Display substrate, display panel, and display apparatus

Abstract

Provided in the present disclosure is a display substrate, comprising: a base substrate, which has an effective display area and a virtual area surrounding the effective display area, wherein the virtual area comprises at least one first virtual sub-area arranged in a first direction with the effective display area; a plurality of effective gate lines, which are located in the effective display area and extend in the first direction, wherein at least one end part of at least one effective gate line extends into the first virtual sub-area on the same side; and at least one virtual data line, which is located in the first virtual sub-are and extends in a second direction, wherein the first direction intersects with the second direction, and the orthographic projection of the end part, which is located in the first virtual sub-area, of the at least one effective gate line on the base substrate does not overlap with the orthographic projection of any virtual data line on the base substrate. Further provided in the embodiments of the present disclosure are a display panel and a display apparatus.

Description

Display substrate, display panel, and display device Technical Field

[0001] The present invention relates to the field of display, and in particular to a display substrate, a display panel and a display device. Background Art

[0002] The basic structure of a thin film transistor-liquid crystal display (TFT-LCD) generally includes an array substrate and an opposing substrate, as well as liquid crystal (LC) disposed between the array substrate and the opposing substrate. Various drive circuits and signal traces for display driving are disposed on the array substrate, and the structural design of the array substrate directly affects product performance.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, the display substrate comprising:

[0005] A base substrate having an active display area and a virtual area surrounding the active display area, wherein the virtual area includes at least one first virtual sub-area arranged in a first direction with respect to the active display area;

[0006] a plurality of effective gate lines, located in the effective display area and extending along a first direction, wherein at least one end portion of at least one of the effective gate lines extends into the first virtual sub-area on the same side;

[0007] at least one virtual data line, located in the first virtual sub-region and extending along a second direction, wherein the first direction intersects the second direction;

[0008] An orthographic projection of an end portion of at least one of the effective gate lines located in the first virtual sub-region on the base substrate does not overlap with an orthographic projection of any of the virtual data lines on the base substrate.

[0009] In some embodiments, the virtual area includes two first virtual sub-areas, and the two first virtual sub-areas are respectively located on two opposite sides of the active display area in the first direction;

[0010] Two ends of at least one of the active gate lines extend into the first dummy sub-regions on corresponding sides respectively.

[0011] In some embodiments, at least one of the effective gate lines extends to an end portion in the first virtual sub-region and is located on a side of the virtual data line farthest from the effective display region in the first virtual sub-region where the end portion is located.

[0012] In some embodiments, the number of the virtual data lines in the first virtual sub-area is greater than or equal to 2;

[0013] At least one of the effective gate lines extends to an end portion within the first virtual sub-region and is located between two of the virtual data lines that are farthest from the effective display region within the first virtual sub-region where the end portion is located, and a portion of the virtual data line that is farthest from the effective display region within the first virtual sub-region where the end portion is located and is arranged opposite to the end portion in the first direction protrudes toward a side away from the effective display region.

[0014] In some embodiments, the virtual area includes two first virtual sub-areas, the two first virtual sub-areas are respectively located on opposite sides of the active display area in the first direction, the base substrate further includes a peripheral area surrounding the virtual area, the peripheral area includes: two first peripheral sub-areas respectively located on one side of the two first virtual sub-areas away from the active display area, and the first gate driving circuit and the second gate driving circuit are respectively disposed in the two first peripheral sub-areas;

[0015] The plurality of effective gate lines located in the effective display area include: a plurality of first gate lines and a plurality of second gate lines, wherein the first gate lines and the second gate lines are alternately arranged along the second direction;

[0016] The first gate line is close to an end portion of the first gate driving circuit, is located on a side of the virtual data line that is farthest from the effective display area in the first virtual sub-area where the end portion is located, and is away from the effective display area, and is connected to a corresponding driving signal output terminal in the first gate driving circuit;

[0017] The second gate line is close to the end of the second gate driving circuit, is located on the side of the virtual data line farthest away from the effective display area in the first virtual sub-area where the end is located, and is away from the effective display area, and is connected to the corresponding driving signal output end in the second gate driving circuit.

[0018] In some embodiments, the number of the virtual data lines in the first virtual sub-area is greater than or equal to 2;

[0019] The first gate line is close to an end portion of the second gate driving circuit and is located between two of the virtual data lines that are farthest from the effective display area in the first virtual sub-region where the end portion is located, and a portion of the virtual data line that is farthest from the effective display area in the first virtual sub-region where the end portion is located and is arranged opposite to the end portion in the first direction protrudes toward a side away from the effective display area;

[0020] The second gate line is close to the end of the second gate driving circuit. The second gate line is close to the end of the first gate driving circuit and is located between the two virtual data lines farthest from the effective display area in the first virtual sub-area where the end is located, and a portion of the virtual data line farthest from the effective display area in the first virtual sub-area where the end is located that is opposite to the end in the first direction protrudes toward the side away from the effective display area.

[0021] In some embodiments, the virtual area includes two first virtual sub-areas, the two first virtual sub-areas are respectively located on opposite sides of the active display area in the first direction, the base substrate further includes a peripheral area surrounding the virtual area, the peripheral area includes: two first peripheral sub-areas respectively located on one side of the two first virtual sub-areas away from the active display area, and the first gate driving circuit and the second gate driving circuit are respectively disposed in the two first peripheral sub-areas;

[0022] The effective gate line is close to an end of the first gate driving circuit, is located on a side of the virtual data line that is farthest from the effective display area in the first virtual sub-area where the end is located, and is away from the effective display area, and is connected to a corresponding driving signal output terminal in the first gate driving circuit;

[0023] The effective gate line is close to the end of the second gate driving circuit, is located on the side of the virtual data line farthest away from the effective display area in the first virtual sub-area where the end is located, and is away from the effective display area, and is connected to the corresponding driving signal output end in the second gate driving circuit.

[0024] In some embodiments, the display substrate further comprises: a common voltage wiring line, the common voltage wiring line being located in the dummy area;

[0025] The effective gate line and the common voltage wiring are arranged in the same layer.

[0026] In some embodiments, the effective gate line extends to an end portion in the first virtual sub-region, and a distance in the first direction between the end portion and any virtual data line in the first virtual sub-region is greater than or equal to 7 μm and less than or equal to 20 μm.

[0027] In some embodiments, the display substrate further comprises:

[0028] a common voltage wiring line located in the virtual area;

[0029] a plurality of effective data lines, located in the effective display area, the effective data lines extending along the second direction, and the effective data lines being insulated from the common voltage wiring;

[0030] The number of the virtual data lines in the first virtual sub-area is greater than or equal to 2, the virtual data lines are connected to the common voltage wiring, and at least two of the virtual data lines are not in contact with each other.

[0031] In some embodiments, the display substrate further comprises:

[0032] A first conductive connection structure is located at a side of the end of the virtual data line away from the base substrate;

[0033] The virtual data line is connected to the common voltage wiring through the first conductive connection structure, and the first conductive connection structure includes a first part and a second part connected to each other. The first part is connected to the corresponding virtual data line, and the second part is connected to the common voltage wiring.

[0034] In some embodiments, the virtual area further includes: two second virtual sub-areas located on opposite sides of the active display area in the second direction;

[0035] The common voltage wiring includes: two second common voltage sub-lines respectively located in two second virtual sub-areas, and the two second common voltage sub-lines extend along the first direction;

[0036] Two ends of the virtual data line are respectively connected to two second common voltage sub-lines through corresponding first conductive connection structures.

[0037] In some embodiments, orthographic projections of two ends of the dummy data line on the base substrate overlap with orthographic projections of two second common voltage sub-lines on the base substrate.

[0038] In some embodiments, the two ends of the virtual data line are respectively a first end and a second end;

[0039] First ends of at least two virtual data lines located in the same first virtual sub-region are connected to different parts of the same first conductive connection structure;

[0040] The second ends of at least two virtual data lines located in the same first virtual sub-region are connected to different parts of the same first conductive connection structure.

[0041] In some embodiments, the display substrate further comprises:

[0042] a gate insulating layer located on a side of the common voltage wiring away from the base substrate; and the dummy data line located on a side of the gate insulating layer away from the base substrate.

[0043] a planarization layer, located on a side of the virtual data line away from the substrate;

[0044] a pixel electrode layer, located on a side of the planarization layer away from the base substrate, and comprising a plurality of pixel electrodes;

[0045] a passivation layer, located on a side of the pixel electrode layer away from the base substrate;

[0046] The first conductive connection structure is located on a side of the passivation layer away from the base substrate, the first part is connected to the virtual data line through a via hole on the passivation layer that exposes the surface of the virtual data line, and the second part is connected to the common voltage wiring through a via hole on the passivation layer, the planarization layer and the gate insulation layer that exposes the surface of the common voltage wiring.

[0047] In some embodiments, a common electrode is provided on a side of the effective data line away from the base substrate;

[0048] A portion on the common electrode serves as the first conductive connection structure.

[0049] In some embodiments, the base substrate further includes a peripheral region surrounding the virtual region, the peripheral region including: a first peripheral sub-region located on a side of the first virtual sub-region away from the effective display region, a gate drive circuit being disposed in the first peripheral sub-region, and at least one end of the effective gate line being connected to the corresponding drive signal output terminal in the gate drive circuit via a corresponding second conductive connection structure;

[0050] The common voltage wiring includes: a first common voltage sub-line located in the first dummy sub-region, the first common voltage sub-line extending along the second direction, and the first common voltage sub-line located between the effective gate line and the gate driving circuit;

[0051] The portion of the first common voltage sub-line that is opposite to the end of the effective gate line in the first direction is a avoidance portion, and the orthographic projection of the second conductive connection structure on the base substrate does not overlap with the orthographic projection of the avoidance portion on the base substrate.

[0052] In some embodiments, the common voltage wiring is provided on the same layer as the effective gate line;

[0053] The second conductive connection structure is arranged in the same layer as the effective data line and the dummy data line.

[0054] In some embodiments, the base substrate further includes a peripheral region surrounding the dummy region, the peripheral region including: a binding sub-region, a first peripheral sub-region, and a first corner sub-region, the binding sub-region is located on one side of the active display region in the second direction, the first peripheral sub-region is located on a side of the first dummy sub-region away from the active display region, and the first corner sub-region is located between the binding sub-region and the first peripheral sub-region;

[0055] A plurality of test terminals are provided in the first corner sub-area, a plurality of test lines are provided in the first peripheral sub-area, and one end of the test line close to the binding sub-area extends into the first corner sub-area and is connected to the corresponding test terminals;

[0056] A plurality of first electrostatic release units are provided in the first corner sub-area, and a portion of the test line located in the first corner sub-area is connected to a corresponding first electrostatic release unit via a corresponding third conductive connection structure;

[0057] The test terminal and the test line connected thereto share the first electrostatic discharge unit.

[0058] In some embodiments, the first electrostatic discharge unit includes: a first transistor and a second transistor;

[0059] The gate of the first transistor and the first electrode of the first transistor are connected to the corresponding third conductive connection structure, and the second electrode of the first transistor is connected to a common voltage wiring;

[0060] The gate electrode of the second transistor and the second electrode of the second transistor are connected to the common voltage wiring, and the first electrode of the second transistor is connected to the corresponding third conductive connection structure.

[0061] In some embodiments, the peripheral area further includes: a binding opposite sub-area and a second corner sub-area, the binding opposite sub-area and the binding sub-area are respectively located on opposite sides of the effective display area in the second direction, and the second corner sub-area is located between the binding opposite sub-area and the first peripheral sub-area;

[0062] A plurality of second electrostatic discharge units are provided in the second corner sub-region, an end of the test line close to the binding opposite sub-region extends into the second corner sub-region, and a portion of the test line located in the second corner sub-region is connected to a corresponding second electrostatic discharge unit via a corresponding fourth conductive connection structure;

[0063] The test terminal and the test line connected thereto share the second electrostatic discharge unit.

[0064] In some embodiments, the second electrostatic discharge unit includes: a third transistor and a fourth transistor;

[0065] The gate electrode of the third transistor and the first electrode of the third transistor are connected to the corresponding fourth conductive connection structure, and the second electrode of the third transistor is connected to the common voltage wiring;

[0066] The gate electrode of the fourth transistor and the second electrode of the fourth transistor are connected to the common voltage wiring, and the first electrode of the fourth transistor is connected to the corresponding fourth conductive connection structure.

[0067] In some embodiments, the test line and the common voltage wiring are arranged on the same layer;

[0068] The third conductive connection structure, the fourth conductive connection structure and the virtual data line are arranged in the same layer.

[0069] In a second aspect, an embodiment of the present disclosure provides a display panel, comprising: the display substrate provided in the above second aspect and an opposing substrate arranged opposite to the display substrate.

[0070] In a third aspect, an embodiment of the present disclosure provides a display device, comprising: the display panel and the source driver chip as improved in the second aspect;

[0071] The source driver chip is connected to the effective data line, and the source driver chip is used to provide a data voltage to the effective data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] FIG1 is a schematic top view of a display substrate provided by an embodiment of the present disclosure;

[0073] 2A and 2B are two schematic top views of an embodiment of the present disclosure in which one end of an effective gate line is located within a first virtual sub-region on the same side;

[0074] FIG3A is another schematic top view of a display substrate provided in an embodiment of the present disclosure;

[0075] FIG3B is another schematic top view of a display substrate provided in an embodiment of the present disclosure;

[0076] 4A to 4D are respectively microscopic images of region A, region B, region C, and region D in FIG1 ;

[0077] FIG5 is a schematic cross-sectional view taken along the PP' line in FIG4A;

[0078] FIG6 is a schematic diagram of the circuit structure of an effective pixel unit located in the effective display area according to an embodiment of the present disclosure;

[0079] FIG7 is a top view schematically showing a plurality of virtual data lines located in the same first virtual sub-region connected to a common voltage wiring in the related art;

[0080] FIG8 is another schematic top view of a display substrate provided in an embodiment of the present disclosure;

[0081] FIG9 is a schematic top view of a test terminal in the related art;

[0082] FIG10 is a schematic top view of a test terminal according to an embodiment of the present disclosure;

[0083] FIG11 is a schematic diagram of a circuit structure of a first electrostatic release unit in an embodiment of the present disclosure;

[0084] FIG12 is a schematic diagram of a circuit structure of a second electrostatic release unit in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0085] In order to enable those skilled in the art to better understand the technical solution of the present invention, a display substrate, a display panel and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

[0086] Many specific details of the present disclosure are described below, such as component structures, materials, dimensions, processing techniques, and technologies, to provide a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be implemented without following these specific details.

[0087] The terms "first", "second" and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms "include" or "comprise" and similar terms mean that the elements or objects preceding the term include the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms "coupled" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical coupling, whether direct or indirect.

[0088] The description of structure A surrounding structure B used in the embodiments of the present disclosure means that structure A is located outside structure B and surrounds at least a portion of structure B. For example, structure A surrounds one side, two sides, or multiple sides of structure B, and does not limit structure A to surrounding structure B in a full circle (360°).

[0089] As used in the embodiments of the present disclosure, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean that the difference from the stated value is within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5%.

[0090] In addition, in the expression of the range M to N in the embodiment of the present disclosure, the limited range includes two endpoint values, M and N.

[0091] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the coupling mode of the drain and source of each transistor can be interchangeable. Therefore, the drain and source of each transistor in the embodiments of the present disclosure are actually the same. Here, only in order to distinguish the two poles of the transistor other than the control electrode (i.e., the gate), one of the poles is called the drain and the other is called the source. In the following description, one of the source and drain of the same transistor is called the first pole, and the other is called the second pole.

[0092] The two structures described in the embodiments of the present disclosure are arranged in the same layer, which means that the two structures are formed by patterning the same material film layer; that is, the two structures can be simultaneously produced by patterning the same material film layer, and the two structures arranged in the same layer can be directly connected or disconnected from each other. The patterning process of the material film layer in the present disclosure generally includes the steps of photoresist coating, exposure, development, film etching, and photoresist stripping. If the material film to be patterned is a photoresist material, the patterning process can achieve patterning of the material film through the steps of exposure and development.

[0093] Through research, it was found that the effective gate line located in the effective display area of ​​the display substrate is a linear structure, and static electricity on the linear structure often accumulates at the end. Therefore, the location where static electricity accumulation and discharge occurs on the effective gate line is generally at the end of the effective gate line, and when static electricity accumulation and discharge occur at the end of the effective gate line, it is easy to cause damage to the structure near the end. In particular, when the end of the effective gate line overlaps with the virtual data line located in the virtual area of ​​the display substrate in a direction perpendicular to the base substrate, once the end of the effective gate line breaks through the gate insulating layer due to static electricity accumulation and discharge, it will cause the effective gate line and the virtual data line to be shorted (short); and because the virtual data line is electrically connected to the common voltage wiring, the common voltage will be loaded on the effective gate line shorted with the virtual data line, thereby causing the effective pixel unit connected to the effective gate line to have poor display. In order to effectively improve the above technical problems, the present disclosure provides a display substrate.

[0094] Figure 1 is a top view schematic diagram of a display substrate provided by an embodiment of the present disclosure, and Figures 2A and 2B are two top view schematic diagrams respectively showing that one end of an effective gate line is located in a first virtual sub-area on the same side in an embodiment of the present disclosure; Figure 3A is another top view schematic diagram of a display substrate provided by an embodiment of the present disclosure; Figure 3B is another top view schematic diagram of a display substrate provided by an embodiment of the present disclosure; Figures 4A to 4D are respectively microscope images of area A, area B, area C and area D in Figure 1; Figure 5 is a cross-sectional schematic diagram along the P-P' direction in Figure 4A; Figure 6 is a circuit structure schematic diagram of an effective pixel unit located in the effective display area in an embodiment of the present disclosure; Figure 7 is a top view schematic diagram of a plurality of virtual data lines located in the same first virtual sub-area connected to a common voltage wiring in the related art; as shown in Figures 1 to 7, the display substrate includes: a base substrate 1, a plurality of effective gate lines 9, and at least one virtual data line 6.

[0095] The base substrate 1 includes an active display area (AA) 2 and a dummy area surrounding the active display area 2. The dummy area 3 includes at least one first dummy sub-area 31 arranged along a first direction X with the active display area 2. The active gate lines 9 are located within the active display area 2 and extend along a first direction. At least one end of at least one active gate line 9 extends into the first dummy sub-area 31 on the same side. The dummy data lines 6 are located within the first dummy sub-area 31 and extend along a second direction, with the first direction intersecting the second direction. The orthographic projection of the end of at least one active gate line 9 located within the first dummy sub-area on the base substrate 1 does not overlap with the orthographic projection of any dummy data line 6 on the base substrate 1.

[0096] In the present disclosure, the positional relationship between the effective gate line 9 and the virtual data line 6 is designed as described above, and the orthographic projection of the end portion of at least one effective gate line 9 located in the first virtual sub-region on the substrate 1 does not overlap with the orthographic projection of any virtual data line 6 on the substrate 1. At this time, even if the end portion of the effective gate line 9 located in the first virtual sub-region 31 breaks through the gate insulating layer due to electrostatic accumulation and discharge, since the end portion is staggered with the virtual data line 6, the problem of short circuit between the effective gate line 9 and the virtual data line 6 can be effectively reduced or even completely avoided.

[0097] In some embodiments, a common voltage wiring 5 is further provided in the virtual area 3 of the display substrate, and an effective data line 7 is further provided in the effective display area 2 . The effective data line 7 extends along the second direction Y and is insulated from the common voltage wiring 5 .

[0098] In the display substrate, based on considerations such as the manufacturing process, a dummy area will be set on the periphery of the AA area, and some dummy structures, such as dummy data lines 6, will be set in the dummy area. Unlike the effective data lines 7 located in the AA area, which are loaded with display data voltages, the dummy data lines 6 located in the dummy area are generally loaded with a common voltage. Specifically, the effective data lines 7 will extend to the peripheral area 4 outside the dummy area 3 (specifically the binding sub-area 42, which will be described in detail later) for electrical connection with the source driver chip subsequently bound to the binding sub-area 42, thereby receiving the display data voltage output by the source driver chip; the dummy data lines 6 will extend to connect to the common voltage wiring 5 to receive the common voltage provided by the common voltage wiring 5.

[0099] In some embodiments, the virtual area 3 includes two first virtual sub-areas 31, which are respectively located on opposite sides of the effective display area 2 in the first direction X; the two ends of the effective gate line 9 respectively extend into the first virtual sub-areas 31 on the same side.

[0100] 2A and 2B , in the case shown in FIG2A , the effective gate line 9 extends to an end portion within the first virtual sub-region 31, located on a side of a virtual data line 6 that is farthest from the effective display area 2 within the first virtual sub-region 31 where the effective gate line 9 is located. In the case shown in FIG2B , the effective gate line 9 extends to an end portion within the first virtual sub-region 31, located between two virtual data lines 6 that are farthest from the effective display area 2 within the first virtual sub-region 31 where the effective gate line 9 is located, and a portion Q of the virtual data line that is farthest from the effective display area 2 within the first virtual sub-region 31 where the effective gate line 9 is located, which is opposite to the end portion in the first direction X, protrudes toward the side away from the effective display area 2 to bypass the end portion. Through the above design, on the one hand, the end portion of the effective gate line 9 can be staggered with the virtual data line 6; on the other hand, the end portion of the effective gate line 9 can be as close as possible to the location of the gate drive circuit (see below) to facilitate connection to the corresponding drive signal output terminal within the gate drive circuit.

[0101] Of course, the two situations in FIG. 2A and FIG. 2B are merely two different examples in the embodiment of the present disclosure, and they do not limit the technical solution of the present disclosure.

[0102] In some embodiments, the effective gate line 9 extends to an end portion within the first dummy sub-region 31, and a distance in the first direction X (e.g., distance L in FIG. 2A and FIG. 2B ) between the effective gate line 9 and any dummy data line 6 within the first dummy sub-region 31 where the effective gate line 9 extends is greater than or equal to 7 μm and less than or equal to 20 μm, for example, 7 μm, 10 μm, 13 μm, 16 μm, 20 μm, etc.

[0103] It should be noted that the distance between the “end” and the virtual data line 6 in the first direction in this disclosure refers to the minimum distance between the orthographic projection of the edge position of the end on the base substrate 1 and the orthographic projection of the virtual data line 6 on the base substrate 1 .

[0104] 3A and 4A to 4D, in some embodiments, the virtual area 3 includes two first virtual sub-areas 31, and the two first virtual sub-areas 31 are respectively located on opposite sides of the effective display area 2 in the first direction X. The substrate 1 also includes a peripheral area 4 surrounding the virtual area 3, and the peripheral area 4 includes: two first peripheral sub-areas 41 respectively located on the side of the two first virtual sub-areas 31 away from the effective display area 2, and the first gate driving circuit GOA1 and the second gate driving circuit GOA2 are respectively provided in the two first peripheral sub-areas 41; the multiple effective gate lines 9 located in the effective display area 2 include: multiple first gate lines 9a and multiple second gate lines 9b, the first gate lines 9a and the second gate lines 9b are respectively provided. The line 9a and the second gate line 9b are alternately arranged along the second direction Y; the first gate line 9a is close to the end of the first gate drive circuit GOA1, and is located on the side away from the effective display area 2 of a virtual data line 6 in the first virtual sub-area 31 where the end is located, and is connected to the corresponding drive signal output end in the first gate drive circuit GOA1; the second gate line 9b is close to the end of the second gate drive circuit GOA2, and is located on the side away from the effective display area 2 of a virtual data line 6 in the first virtual sub-area 31 where the end is located, and is connected to the corresponding drive signal output end in the second gate drive circuit GOA2.

[0105] In some embodiments, the first gate line 9a is close to the end of the second gate drive circuit GOA2, and is located between the two virtual data lines 6 farthest from the effective display area 2 in the first virtual sub-area 31 where the end is located, and a portion Q on a virtual data line farthest from the effective display area 2 in the first virtual sub-area 31 where the end is located, which is arranged opposite to the end in the first direction X, protrudes toward the side away from the effective display area 2.

[0106] The second gate line 9b is close to the end of the second gate drive circuit GOA2. The second gate line 9b is close to the end of the first gate drive circuit GOA1, and is located between the two virtual data lines 6 farthest from the effective display area 2 in the first virtual sub-area 31 where the end is located, and a portion Q on a virtual data line farthest from the effective display area 2 in the first virtual sub-area 31 where the end is located, which is arranged opposite to the end in the first direction X, protrudes toward the side away from the effective display area 2.

[0107] In the embodiment of the present disclosure, the first gate line 9a can be the effective gate line 9 located at an odd position in the effective display area 2, and the second gate line 9b can be the effective gate line 9 located at an even position in the effective display area 2; or, the first gate line 9a can be the effective gate line 9 located at an even position in the effective display area 2, and the second gate line 9b can be the effective gate line 9 located at an odd position in the effective display area 2. In the case shown in Figure 3A, the first gate line 9a is connected to the first gate circuit, and the second gate line 9b is connected to the second gate drive circuit GOA2. The first gate drive circuit GOA1 and the second gate drive circuit GOA2 alternately drive the effective gate lines 9.

[0108] 4A to 4D , exemplarily, a first virtual gate line 13 (a first virtual gate line is exemplarily shown in the figure) and a second virtual gate line 11 (two second virtual gate lines are exemplarily shown in the figure) are respectively provided in the two second virtual sub-areas 32. As an example, a first virtual gate line 13 (the specific number can be designed as needed) is provided in the second virtual sub-area 32 on the side of the first effective gate line 9 away from the second effective gate line 9, and a second virtual gate line 11 (the specific number can be designed as needed) is provided in the second virtual sub-area 32 on the side of the last effective gate line 9 away from the second-to-last effective gate line 9; the first virtual gate line 13 can extend into the first virtual sub-area 31 to be connected to the common voltage wiring 5, and a common voltage can be loaded on the first virtual gate line 13; the second virtual gate line 11 can be connected to the corresponding first gate drive circuit GOA1 and / or the second gate drive circuit GOA2 through the corresponding conductive connection structure 12 to receive the gate drive signal provided by the first gate drive circuit GOA1 and / or the second gate drive circuit GOA2.

[0109] Referring to FIG3B , unlike the manner in which the first gate drive circuit GOA1 and the second gate drive circuit GOA2 alternately drive the effective gate line 9 as shown in FIG3A , in the situation shown in FIG3B , each effective gate line 9 can be driven by the first gate drive circuit GOA1 and the second gate drive circuit GOA2 at the same time, that is, the effective gate line 9 can be driven on both sides. Such a design is conducive to improving the speed of loading the gate drive signal on the effective gate line 9.

[0110] Specifically, the virtual area 3 includes two first virtual sub-areas 31, and the two first virtual sub-areas 31 are respectively located on opposite sides of the effective display area 2 in the first direction X. The base substrate 1 also includes a peripheral area 4 surrounding the virtual area 3, and the peripheral area 4 includes: two first peripheral sub-areas 41 respectively located on one side of the two first virtual sub-areas 31 away from the effective display area 2, and the first gate drive circuit GOA1 and the second gate drive circuit GOA2 are respectively disposed in the two first peripheral sub-areas 41;

[0111] Each effective gate line 9 is close to the end of the first gate drive circuit GOA1, and is located on the side away from the effective display area 2 of a virtual data line 6 in the first virtual sub-area 31 where the end is located, and is connected to the corresponding drive signal output end in the first gate drive circuit GOA1; each effective gate line 9 is close to the end of the second gate drive circuit GOA2, and is located on the side away from the effective display area 2 of a virtual data line 6 in the first virtual sub-area 31 where the end is located, and is connected to the corresponding drive signal output end in the second gate drive circuit GOA2.

[0112] Continuing to refer to FIG. 3A and FIG. 3B , in some embodiments, the end of the effective gate line 9 can be connected to the corresponding signal output end in the corresponding gate drive circuit through the corresponding second conductive connection structure 10. For further description of the second conductive connection structure 10, please refer to the following content.

[0113] As shown in FIG7 , in the related art, the ends on the same side of multiple virtual data lines 06 located in the same virtual sub-region are connected together in the first virtual sub-region 031 to form a common end DP. This common end DP is then connected to the common voltage wiring 05 using a conductive connection structure 801, thereby electrically connecting each virtual data line 06 to the common voltage wiring 05. However, in actual applications, it has been found that the virtual data line 06 is an overall linear structure, and static electricity tends to accumulate at the ends of a linear structure. Directly connecting the ends on the same side of multiple virtual data lines 06 to form a common end DP increases the amount of static electricity accumulated at the common end DP, making it prone to static electricity accumulation and discharge. This static electricity accumulation and discharge at the common end DP can easily cause damage to surrounding structures (e.g., the common voltage wiring and the insulation layer).

[0114] Referring to Figures 1 and 3A to 4D, in order to effectively improve the above-mentioned technical problems, in the embodiment of the present disclosure, while the virtual data line 6 is extended to be connected to the common voltage wiring 5, at least two virtual data lines 6 are not in contact with each other, so as to avoid the static electricity on two or even more virtual data lines 6 from gathering together, thereby effectively reducing the risk of static electricity accumulation and discharge on the virtual data line 6.

[0115] It should be noted that FIG1 exemplarily illustrates a case where the virtual area 3 includes two first virtual sub-areas 31, the two first virtual sub-areas 31 being located on opposite sides of the active display area 2 in the first direction X, and each first virtual sub-area 31 including two virtual data lines 6. In the present disclosure, the virtual area 3 may also include only one first virtual area 3, and the one first virtual area 3 being located on one side of the active display area 2 in the first direction X. This case also falls within the scope of protection of the present disclosure.

[0116] In the embodiment of the present disclosure, a plurality of effective gate lines 9 are provided in the effective display area 2, and the effective gate lines 9 extend along the first direction X. The plurality of effective gate lines 9 and the plurality of effective data lines 7 define a plurality of effective pixel units. As shown in FIG6 , the effective pixel unit includes a thin film transistor T and a pixel electrode PIX. The control electrode of the thin film transistor T is connected to the corresponding effective gate line 9, the first electrode of the thin film transistor T is connected to the corresponding effective data line 7, and the second electrode of the thin film transistor T is connected to the pixel electrode PIX.

[0117] In some embodiments, the effective gate line 9 and the common voltage wiring 5 are provided in the same layer; the effective data line 7 and the dummy data line 6 are provided in the same layer.

[0118] Referring to Figures 1 to 3, in some embodiments, the display substrate further includes: a first conductive connection structure 8, the first conductive connection structure 8 is located on the side of the virtual data line 6 away from the base substrate 1; the virtual data line 6 is connected to the common voltage wiring 5 through the corresponding first conductive connection structure 8, the first conductive connection structure 8 includes a first part 81 and a second part 82 connected to each other, the first part 81 is connected to the corresponding virtual data line 6, and the second part 82 is connected to the common voltage wiring 5.

[0119] In some embodiments, the orthographic projection of the first conductive connection structure 8 on the base substrate 1 is completely located within the orthographic projection of the common voltage wiring 5 on the base substrate 1 .

[0120] In some embodiments, as shown in Figure 1, the virtual area 3 also includes: two second virtual sub-areas 32 located on opposite sides of the effective display area 2 in the second direction Y; the common voltage wiring 5 includes: two second common voltage sub-lines 52 respectively located in the two second virtual sub-areas 32, and the two second common voltage sub-lines 52 extend along the first direction X; both ends of the virtual data line 6 are respectively connected to the two second common voltage sub-lines 52 through corresponding first conductive connection structures 8.

[0121] In some embodiments, the orthographic projections of the two ends of the dummy data line 6 on the base substrate 1 overlap with the orthographic projections of the two second common voltage sub-lines 52 on the base substrate 1. In this case, the ends of the dummy data line 6 extend directly to the area where the second common voltage sub-lines 52 are located. The ends of the dummy data line 6 are close to the second common voltage sub-lines 52, which helps reduce the resistance between the ends of the dummy data line 6 and the second common voltage sub-lines 52.

[0122] In some embodiments, the two ends of the virtual data line 6 are respectively the first end and the second end (for example, the lower end of the virtual data line 6 in the accompanying drawings is the first end, and the upper end is the second end); as shown in Figures 4A and 4B, the first ends of all virtual data lines 6 located in the same first virtual sub-area 31 are connected to different parts on the same first conductive connection structure 8a; as shown in Figures 4C and 4D, the second ends of all virtual data lines 6 located in the same first virtual sub-area 31 are connected to different parts on the same first conductive connection structure 8b.

[0123] That is to say, the first ends of all virtual data lines 6 located in the same first virtual sub-area 31 correspond to the same first conductive connection structure 8a, and the second ends of all virtual data lines 6 located in the same first virtual sub-area 31 correspond to the same first conductive connection structure 8b; such a design can effectively reduce the number of first conductive connection structures 8 that need to be arranged, thereby simplifying the product structure.

[0124] In some embodiments, the display substrate further comprises: a gate insulating layer GI, a planarization layer PLN, a pixel electrode layer (not shown), and a passivation layer PVX. The gate insulating layer GI is located on a side of the common voltage wiring 5 and the effective gate line 9 away from the base substrate 1; the virtual data line 6 and the effective data line 7 are located on a side of the gate insulating layer GI away from the base substrate 1; the planarization layer PLN is located on a side of the virtual data line 6 away from the base substrate 1; the pixel electrode layer is located on a side of the planarization layer PLN away from the base substrate 1, and the pixel electrode layer includes a plurality of pixel electrodes PIX; the passivation layer PVX is located on a side of the pixel electrode layer away from the base substrate 1; a first conductive connection structure 8 is located on a side of the passivation layer PVX away from the base substrate 1, a first portion of the first conductive connection structure 8 is connected to (contacts) the virtual data line 6 through a via hole on the passivation layer PVX that is connected to the corresponding virtual data line 6, and a second portion of the first conductive connection structure 8 is connected to (contacts) the common voltage wiring 5 through a via hole on the passivation layer PVX, the planarization layer PLN, and the gate insulating layer GI that is connected to the common voltage wiring 5.

[0125] In some embodiments, a common electrode COM is provided on the side of the effective data line 7 away from the base substrate 1; part of the structure of the common electrode COM is reused as the first conductive connection structure 8. In the embodiment of the present disclosure, by using part of the common electrode as the first conductive connection structure 8, it is beneficial to simplify the product structure. Accordingly, the display substrate can be an array substrate in any one of the liquid crystal display panels of the Fringe Field Switching (FFS) type, the Advanced Super Dimension Switch (ADS) type, and the High Advanced Super Dimension Switch (HADS) type.

[0126] Optionally, the common voltage wiring 5 includes: a first common voltage sub-line 51 located within the first virtual sub-region 31, the first common voltage sub-line 51 extending along the second direction Y, and located between the effective gate line 9 and the gate drive circuit; a portion of the first common voltage sub-line 51 that directly opposes the end of the effective gate line 9 in the first direction X, forming a avoidance portion 51a; and an orthographic projection of the second conductive connection structure 10 on the base substrate 1 does not overlap with an orthographic projection of the avoidance portion 51a on the base substrate 1. Referring to Figures 3A and 3B and Figures 4A to 4D, the second conductive connection structure 10 is essentially a winding that bypasses the areas where the avoidance portions 51a are located.

[0127] In some embodiments, the second conductive connection structure 10 is disposed in the same layer as the effective data line 7 and the dummy data line 6 .

[0128] In the embodiment of the present disclosure, the portion of the first common voltage sub-line 51 that directly faces the end of the effective gate line 9 in the first direction X specifically refers to the portion of the first common voltage sub-line 51 that is covered by the end of the effective gate line 9 when projected onto the first common voltage sub-line 51 along the first direction X. The width of the end of the effective gate line 9 in the second direction Y is equal to or substantially equal to the width of a avoidance portion of the first common voltage sub-line 51 that the end of the effective gate line 9 directly faces in the second direction Y.

[0129] As can be seen from the accompanying drawings, the first common voltage sub-line 51 and the effective gate line 9 are both large pieces of metal, which are prone to accumulate charge during the process. In the subsequent process, there is a certain probability that the end of the effective gate line 9 will discharge electrostatically toward the part (avoidance part) facing the first common voltage sub-line 51, which can easily cause damage to the structure in the area where the avoidance part 51a is located. For example, if electrostatic discharge occurs at the end of the effective gate line 9, the part of the gate insulating layer GI located in the area where the avoidance part 51a is located will be broken down, and the second conductive connection structure 10 will just pass through the area where the avoidance part is located. At this time, it is easy for the second conductive connection structure 10 to short-circuit with the avoidance part 51a, which will cause the effective gate line 9 connected to the second conductive connection structure 10 to short-circuit with the common voltage wiring 5, and then cause the effective pixel unit connected to the effective gate line 9 to display poorly.

[0130] It should be noted that when the above-mentioned second virtual gate line 11 is provided on the display substrate, the portion of the first common voltage sub-line 51 that is opposite to the end of the second virtual gate line 11 in the first direction X also serves as the avoidance portion 51a, and the positive projection of the conductive connection structure 12 for connecting the end of the second virtual gate line 11 and the corresponding gate drive circuit on the base substrate 1 may also not overlap with the positive projection of the avoidance portion 51a on the base substrate 1.

[0131] Figure 8 is another top view schematic diagram of the display substrate provided by an embodiment of the present disclosure. As shown in Figure 8, in some embodiments, the base substrate 1 also includes a peripheral area 4 surrounding the virtual area 3, and the peripheral area 4 includes: a bonding sub-area, a first peripheral sub-area 41 and a first corner sub-area 44. The binding sub-area 42 is located on one side of the effective display area 2 in the second direction Y, the first peripheral sub-area 41 is located on the side of the first virtual sub-area 31 away from the effective display area 2, and the first corner sub-area 44 is located between the binding sub-area 42 and the first peripheral sub-area 41.

[0132] A plurality of test terminals 71 (CT pads) are provided in the first corner sub-area 44, and a plurality of test lines 72 are provided in the first peripheral sub-area 41. The end of the test line 72 close to the binding sub-area 42 extends into the first corner sub-area 44 and is connected to the corresponding test terminal 71; a plurality of first electrostatic release units 74 are provided in the first corner sub-area, and the part of the test line 72 located in the first corner sub-area 44 is connected to the corresponding first electrostatic release unit 74 through the corresponding third conductive connection structure 7573. The test terminal 71 and the test line 72 connected thereto share the first electrostatic release unit 74.

[0133] A plurality of connection terminals 81 are provided within the binding sub-region 42 for binding a source driver chip (not shown) and a flexible circuit board (not shown) within the binding sub-region 42. The source driver chip can be used to provide display data voltages to the effective data lines 7. Furthermore, a MUX circuit (not shown) can be provided within the binding sub-region 42 and between the effective data lines 7 and the source driver chip. The provision of the MUX circuit helps reduce the number of output channels of the source driver chip.

[0134] FIG9 is a top view schematic diagram of the test terminal in the related art. As shown in FIG9 , in the related art, in order to enable the test terminal 71 to have an electrostatic discharge function, an electrostatic discharge unit 80 is generally provided between two adjacent test terminals 71, such as an electrostatic discharge unit composed of a transistor. However, as can be seen from FIG9 , due to the small spacing between adjacent test terminals 71, the electrostatic discharge unit 80 must be prepared within the small spacing space. On the one hand, it requires a high alignment accuracy during the process, and the production yield of the production line is relatively low. On the other hand, it requires that the size of the electrostatic discharge unit 80 itself should also be designed to be small (for example, the electrostatic discharge unit is a small-sized transistor). At this time, the electrostatic discharge unit 80 is prone to conductorization, and the adjacent test terminals 71 are short-circuited, and the test terminals 71 cannot be used for normal testing.

[0135] FIG10 is a schematic top view of a test terminal in an embodiment of the present disclosure. As shown in FIG10 , to effectively improve the above-mentioned technical problems, in the disclosed embodiment, a first electrostatic discharge unit 74 is configured for the portion of the test line 72 located in the first corner sub-area 44, so that the portion of the test line 72 located in the first corner sub-area 44 has better electrostatic discharge capability. Moreover, because the portion of the test line 72 located in the first corner sub-area 44 is connected to the corresponding test terminal 71, the first electrostatic discharge unit 74 can also enable the test terminal 71 connected to the portion of the corresponding test line 72 located in the first corner sub-area 44 to have better electrostatic discharge capability. In other words, the test terminal 71 and the test line 72 to which it is connected can share the first electrostatic discharge unit 74. Therefore, there is no need to set an electrostatic discharge unit between the connected test terminals 71, and the above-mentioned technical problems existing in the related art shown in FIG9 can be effectively solved or alleviated.

[0136] In some embodiments, the peripheral area 4 further includes: a binding opposing sub-area 43 and a second corner sub-area 45, wherein the binding opposing sub-area 43 and the binding sub-area 42 are respectively located on opposite sides of the effective display area 2 in the second direction Y, and the second corner sub-area is located between the binding opposing sub-area 43 and the first peripheral sub-area 41; a plurality of second electrostatic discharge units 76 are provided in the second corner sub-area 45, and an end of the test line 72 near the binding opposing sub-area 43 extends into the second corner sub-area 45, and the portion of the test line 72 located in the second corner sub-area 45 is connected to the corresponding second electrostatic discharge unit 76 via the corresponding fourth conductive connection structure 75; the test terminal 71 and the test line 72 to which it is connected share the second electrostatic discharge unit 76. By providing the second electrostatic discharge unit 76, the electrostatic discharge capability of the test line 72 and the test terminal 71 can be further improved.

[0137] In some embodiments, the test line 72 is disposed on the same layer as the common voltage wiring 5 ; the third conductive connection structure 73 , the fourth conductive connection structure 75 and the dummy data line 6 are disposed on the same layer.

[0138] Figure 11 is a schematic diagram of a circuit structure of the first electrostatic release unit in an embodiment of the present disclosure. As shown in Figure 11, in some embodiments, the first electrostatic release unit 74 includes: a first transistor T1 and a second transistor T2; the gate of the first transistor T1 and the first electrode of the first transistor T1 are connected to the corresponding third conductive connection structure, and the second electrode of the first transistor T1 is connected to the common voltage wiring 5; the gate of the second transistor T2 and the second electrode of the second transistor T2 are connected to the common voltage wiring 5, and the first electrode of the second transistor T2 is connected to the corresponding third conductive connection structure 73.

[0139] Figure 12 is a schematic diagram of a circuit structure of the second electrostatic release unit in an embodiment of the present disclosure. As shown in Figure 12, in some embodiments, the second electrostatic release unit 76 includes: a third transistor T3 and a fourth transistor T4; the gate of the third transistor T3 and the first electrode of the third transistor T3 are connected to the corresponding fourth conductive connection structure 75, and the second electrode of the third transistor T3 is connected to the common voltage wiring 5; the gate of the fourth transistor T4 and the second electrode of the fourth transistor T4 are connected to the common voltage wiring 5, and the first electrode of the fourth transistor T4 is connected to the corresponding fourth conductive connection structure 75.

[0140] Of course, the first electrostatic release unit 74 and the second electrostatic release unit 76 in the embodiment of the present disclosure are not limited to the structure composed of two transistors shown in Figures 11 and 12. Those skilled in the art should know that any structure with an electrostatic release function can be used as the first electrostatic release unit 74 or the second electrostatic release unit 76 in the present disclosure.

[0141] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes: a display substrate and an opposing substrate arranged opposite to the display substrate, wherein the display substrate can adopt the display substrate provided in the previous embodiment.

[0142] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel, wherein the display panel adopts the display panel provided in the previous embodiment; the display device may also include a driving module for driving the display panel to display.

[0143] Optionally, the driving module includes: a source driver chip; the source driver chip is connected to the effective data line, and the source driver chip is used to provide a data voltage to the effective data line.

[0144] The display device in the embodiments of the present disclosure may specifically be an electronic tag, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a mobile internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), a personal computer (PC), a television (TV), a mobile phone, an electronic photo frame, a navigation system, an ATM, an kiosks, and other display products or components with a display function.

[0145] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, wherein: include: A substrate having an effective display area and a virtual area surrounding the effective display area, wherein the virtual area includes at least one first virtual sub-area arranged in a first direction with the effective display area; A plurality of effective gate lines are located in the effective display area and extend along a first direction, and at least one end of at least one of the effective gate lines extends into the first virtual sub-area on the same side; at least one virtual data line, located in the first virtual sub-region and extending along a second direction, wherein the first direction intersects the second direction; An orthographic projection of an end portion of at least one of the effective gate lines located in the first virtual sub-region on the substrate does not overlap with an orthographic projection of any of the virtual data lines on the substrate.

2. The display substrate according to claim 1, wherein: The virtual area includes two first virtual sub-areas, and the two first virtual sub-areas are respectively located at two opposite sides of the effective display area in the first direction; Two ends of at least one of the effective gate lines extend into the first virtual sub-region on the corresponding side respectively.

3. The display substrate according to claim 1 or 2, wherein: At least one of the effective gate lines extends to an end portion in the first virtual sub-region and is located at a side of the virtual data line farthest from the effective display region in the first virtual sub-region where the end portion is located, away from the effective display region.

4. The display substrate according to claim 1 or 2, wherein: The number of the virtual data lines in the first virtual sub-area is greater than or equal to 2; At least one of the effective gate lines extends to an end portion within the first virtual sub-region and is located between two of the virtual data lines that are farthest from the effective display region within the first virtual sub-region where the end portion is located, and a portion of a virtual data line that is farthest from the effective display region within the first virtual sub-region where the end portion is located and is arranged opposite to the end portion in the first direction protrudes toward a side away from the effective display region.

5. The display substrate according to claim 1 or 2, wherein: The virtual area includes two first virtual sub-areas, the two first virtual sub-areas are respectively located at two opposite sides of the effective display area in the first direction, the substrate further includes a peripheral area surrounding the virtual area, the peripheral area includes: two first peripheral sub-areas respectively located at one side of the two first virtual sub-areas away from the effective display area, and the first gate driving circuit and the second gate driving circuit are respectively arranged in the two first peripheral sub-areas; The plurality of effective gate lines located in the effective display area include: a plurality of first gate lines and a plurality of second gate lines, wherein the first gate lines and the second gate lines are alternately arranged along the second direction; The first gate line is close to an end of the first gate driving circuit, is located on a side of the virtual data line farthest from the effective display area in the first virtual sub-area where the end is located, and is away from the effective display area, and is connected to a corresponding driving signal output terminal in the first gate driving circuit; The second gate line is close to the end of the second gate driving circuit, located on the side of the virtual data line farthest from the effective display area in the first virtual sub-area where the end is located, away from the effective display area, and is connected to the corresponding driving signal output terminal in the second gate driving circuit.

6. The display substrate according to claim 5, wherein: The number of the virtual data lines in the first virtual sub-area is greater than or equal to 2; The first gate line is close to an end of the second gate driving circuit and is located between two virtual data lines in the first virtual sub-region where the end is located and is farthest from the effective display region, and a portion of a virtual data line in the first virtual sub-region where the end is located and is farthest from the effective display region and is arranged opposite to the end in the first direction, protrudes toward a side away from the effective display region; The second gate line is close to the end of the second gate driving circuit. The second gate line is close to the end of the first gate driving circuit, and is located between two virtual data lines farthest from the effective display area in the first virtual sub-area where the end is located, and a portion of the virtual data line farthest from the effective display area in the first virtual sub-area where the end is located, which is arranged opposite to the end in the first direction, protrudes toward the side away from the effective display area.

7. The display substrate according to claim 1 or 2, wherein: The virtual area includes two first virtual sub-areas, the two first virtual sub-areas are respectively located at two opposite sides of the effective display area in the first direction, the substrate further includes a peripheral area surrounding the virtual area, the peripheral area includes: two first peripheral sub-areas respectively located at one side of the two first virtual sub-areas away from the effective display area, and the first gate driving circuit and the second gate driving circuit are respectively arranged in the two first peripheral sub-areas; The effective gate line is close to the end of the first gate driving circuit, is located on a side of the virtual data line farthest from the effective display area in the first virtual sub-area where the end is located, away from the effective display area, and is connected to the corresponding driving signal output terminal in the first gate driving circuit; The effective gate line is close to the end of the second gate driving circuit, is located on the side of the virtual data line farthest from the effective display area in the first virtual sub-area where the end is located, and is away from the effective display area, and is connected to the corresponding driving signal output terminal in the second gate driving circuit.

8. The display substrate according to any one of claims 1 to 7, wherein: The display substrate further includes: a common voltage wiring line, the common voltage wiring line being located in the dummy area; The effective gate line is arranged in the same layer as the common voltage wiring line.

9. The display substrate according to any one of claims 1 to 8, wherein: The effective gate line extends to an end portion in the first virtual sub-region, and a distance between the end portion and any one of the virtual data lines in the first virtual sub-region in the first direction is greater than or equal to 7 μm and less than or equal to 20 μm.

10. The display substrate according to any one of claims 1 to 7, wherein: The display substrate further comprises: A common voltage wiring line is located in the virtual area; A plurality of effective data lines are located in the effective display area, the effective data lines extend along a second direction, and the effective data lines are insulated from the common voltage wiring; The number of the virtual data lines in the first virtual sub-area is greater than or equal to 2, the virtual data lines are connected to the common voltage wiring, and at least two of the virtual data lines are not in contact with each other.

11. The display substrate according to claim 10, wherein: Also includes: A first conductive connection structure is located at a side of the end of the virtual data line away from the substrate; The virtual data line is connected to the common voltage wiring through the first conductive connection structure, and the first conductive connection structure includes a first part and a second part connected to each other, the first part is connected to the corresponding virtual data line, and the second part is connected to the common voltage wiring.

12. The display substrate according to claim 11, wherein: The virtual area further includes: two second virtual sub-areas located on opposite sides of the effective display area in the second direction; The common voltage wiring includes: two second common voltage sub-lines respectively located in two second virtual sub-areas, and the two second common voltage sub-lines extend along the first direction; Two ends of the virtual data line are respectively connected to two of the second common voltage sub-lines through the corresponding first conductive connection structures.

13. The display substrate according to claim 12, wherein: The orthographic projections of two ends of the virtual data line on the base substrate overlap with the orthographic projections of two second common voltage sub-lines on the base substrate respectively.

14. The display substrate according to claim 12 or 13, wherein: The two ends of the virtual data line are respectively a first end and a second end; The first ends of at least two of the virtual data lines located in the same first virtual sub-region are connected to different parts of the same first conductive connection structure; The second ends of at least two of the virtual data lines located in the same first virtual sub-region are connected to different parts of the same first conductive connection structure.

15. The display substrate according to any one of claims 11 to 14, wherein: Also includes: The gate insulating layer is located on a side of the common voltage wiring away from the base substrate; the virtual data line is located on a side of the gate insulating layer away from the base substrate; A planarization layer, located on a side of the virtual data line away from the substrate; A pixel electrode layer, located on a side of the planarization layer away from the base substrate, comprising a plurality of pixel electrodes; A passivation layer, located on a side of the pixel electrode layer away from the base substrate; The first conductive connection structure is located on a side of the passivation layer away from the base substrate, the first part is connected to the virtual data line through a via hole on the passivation layer that exposes the surface of the virtual data line, and the second part is connected to the common voltage wiring through a via hole on the passivation layer, the planarization layer and the gate insulation layer that exposes the surface of the common voltage wiring.

16. The display substrate according to any one of claims 11 to 15, wherein: A common electrode is provided on a side of the effective data line away from the base substrate; A portion on the common electrode serves as the first conductive connection structure.

17. The display substrate according to any one of claims 1 to 16, wherein: The substrate also includes a peripheral area surrounding the virtual area, the peripheral area including: a first peripheral sub-area located at a side of the first virtual sub-area away from the effective display area, a gate driving circuit is arranged in the first peripheral sub-area, and at least one end of the effective gate line is connected to the corresponding driving signal output terminal in the gate driving circuit through a corresponding second conductive connection structure; The common voltage wiring includes: a first common voltage sub-line located in the first virtual sub-area, the first common voltage sub-line extending along the second direction, and the first common voltage sub-line located between the effective gate line and the gate driving circuit; The portion of the first common voltage sub-line that is opposite to the end of the effective gate line in the first direction is a avoidance portion, and the orthographic projection of the second conductive connection structure on the base substrate does not overlap with the orthographic projection of the avoidance portion on the base substrate.

18. The display substrate according to claim 17, wherein: The common voltage wiring is arranged in the same layer as the effective gate line; The second conductive connection structure is arranged in the same layer as the effective data line and the virtual data line.

19. The display substrate according to any one of claims 1 to 18, wherein: The substrate further comprises a peripheral region surrounding the virtual region, the peripheral region comprising: a binding sub-region, a first peripheral sub-region and a first corner sub-region, the binding sub-region is located at one side of the effective display region in the second direction, the first peripheral sub-region is located at a side of the first virtual sub-region away from the effective display region, and the first corner sub-region is located between the binding sub-region and the first peripheral sub-region; A plurality of test terminals are arranged in the first corner sub-area, a plurality of test wires are arranged in the first peripheral sub-area, and one end of the test wire close to the binding sub-area extends into the first corner sub-area and is connected to the corresponding test terminals; A plurality of first electrostatic release units are arranged in the first corner sub-area, and a portion of the test line located in the first corner sub-area is connected to a corresponding first electrostatic release unit through a corresponding third conductive connection structure; The test terminal and the test line connected thereto share the first electrostatic release unit.

20. The display substrate according to claim 19, wherein: The first electrostatic release unit includes: a first transistor and a second transistor; The gate of the first transistor and the first electrode of the first transistor are connected to the corresponding third conductive connection structure, and the second electrode of the first transistor is connected to a common voltage wiring; The gate of the second transistor and the second electrode of the second transistor are connected to the common voltage wiring, and the first electrode of the second transistor is connected to the corresponding third conductive connection structure.

21. The display substrate according to claim 19 or 20, wherein: The peripheral area further includes: a binding opposite sub-area and a second corner sub-area, the binding opposite sub-area and the binding sub-area are respectively located at two opposite sides of the effective display area in the second direction, and the second corner sub-area is located between the binding opposite sub-area and the first peripheral sub-area; A plurality of second electrostatic release units are arranged in the second corner sub-area, an end of the test line close to the binding opposite sub-area extends into the second corner sub-area, and a portion of the test line located in the second corner sub-area is connected to the corresponding second electrostatic release unit through a corresponding fourth conductive connection structure; The test terminal and the test line connected thereto share the second electrostatic release unit.

22. The display substrate according to claim 21, wherein: The second electrostatic discharge unit includes: a third transistor and a fourth transistor; The gate of the third transistor and the first electrode of the third transistor are connected to the corresponding fourth conductive connection structure, and the second electrode of the third transistor is connected to a common voltage wiring; The gate electrode of the fourth transistor and the second electrode of the fourth transistor are connected to the common voltage wiring, and the first electrode of the fourth transistor is connected to the corresponding fourth conductive connection structure.

23. The display substrate according to claim 21 or 22, wherein: The test line is arranged on the same layer as the common voltage wiring; The third conductive connection structure, the fourth conductive connection structure and the virtual data line are arranged in the same layer.

24. A display panel, wherein: include: A display substrate as claimed in any one of claims 1 to 23, and an opposing substrate arranged opposite to the display substrate.

25. A display device, wherein: include: The display panel and the source driver chip as described in claim 24; The source driver chip is connected to the effective data line, and the source driver chip is used to provide a data voltage to the effective data line.

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