Display substrate and display apparatus

Abstract

A display substrate, comprising a base substrate, a driving circuit layer and a light-emitting structure layer. The driving circuit layer is located in a first display area and comprises a plurality of first circuit units and a plurality of second circuit units. Each first circuit unit comprises a first pixel circuit, and a scanning line and a first data line that are electrically connected to the first pixel circuit. Each second circuit unit comprises an invalid pixel circuit, and the scanning line and an invalid data line that are electrically connected to the invalid pixel circuit. The display substrate satisfies at least one of the following: the overlapping area of the scanning lines and the first pixel circuits in the first circuit units is larger than the overlapping area of the scanning lines and the invalid pixel circuits in the second circuit units, and the overlapping area of the scanning lines and the first data lines in the first circuit units is larger than the overlapping area of the scanning lines and the invalid data lines in the second circuit units.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on May 31, 2023, with application number 202310639739.6 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. Under-display camera technology is a new technology designed to increase the screen-to-body ratio of displays.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display substrate and a display device.

[0007] In one aspect, embodiments of the present disclosure provide a display substrate comprising: a substrate, a driving circuit layer, and a light-emitting structure layer. The driving circuit layer is located in a first display area and includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns. The plurality of circuit units include at least a plurality of first circuit units and a plurality of second circuit units. The first circuit unit includes a first pixel circuit, a scan line electrically connected to the first pixel circuit and extending in a first direction, and a first data line electrically connected to the second direction. At least one second circuit unit includes an inactive pixel circuit, a scan line electrically connected to the inactive pixel circuit, and an inactive data line extending in a second direction. The first direction intersects the second direction. The light-emitting structure layer is located on a side of the driving circuit layer away from the substrate and includes a plurality of first light-emitting elements located in the first display area, with at least one first pixel circuit electrically connected to at least one first light-emitting element. The display substrate satisfies at least one of the following conditions: the overlap area of ​​the scan line with the first pixel circuit in the first circuit unit is greater than the overlap area with the inactive pixel circuit in the second circuit unit; and the overlap area of ​​the scan line with the first data line in the first circuit unit is greater than the overlap area with the inactive data line in the second circuit unit.

[0008] In some exemplary embodiments, orthographic projections of the scan line and the invalid data line in the second circuit unit on the substrate do not overlap.

[0009] In some exemplary embodiments, in a unit column where the second circuit unit is located, a plurality of the invalid data lines are arranged in sequence along the second direction, a first break is provided between adjacent invalid data lines in the second direction, and the length of the scan line along the second direction is less than the length of the first break along the second direction.

[0010] In some example embodiments, the inactive data line in the second circuit unit is electrically connected to a second voltage line extending along the second direction and transmitting a first voltage signal.

[0011] In some exemplary embodiments, in a direction perpendicular to the display substrate, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate. The scan line is located in the first conductive layer, the inactive data line and the first data line are located in the fifth conductive layer, and the second voltage line is located in the third conductive layer.

[0012] In some exemplary embodiments, the inactive data line in the second circuit unit is electrically connected to a third voltage line extending along the first direction and transmitting a second voltage signal.

[0013] In some exemplary embodiments, the driving circuit layer also includes: a fourth voltage line extending along the second direction and transmitting the second voltage signal, the fourth voltage line being located on a side of the third voltage line away from the substrate and electrically connected to the third voltage line; the invalid data line and the fourth voltage line are in the same layer structure.

[0014] In some exemplary embodiments, in a direction perpendicular to the display substrate, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate. The third voltage line is located in the fourth conductive layer, and the inactive data line and the fourth voltage line are located in the fifth conductive layer.

[0015] In some exemplary embodiments, each of the first pixel circuit and the invalid pixel circuit includes at least: a driving transistor, a data writing transistor, and a threshold compensation transistor; the gates of the data writing transistor and the threshold compensation transistor of the first pixel circuit and the invalid pixel circuit are electrically connected to the scan line. A first electrode of the data writing transistor of the first pixel circuit is electrically connected to the first data line, and a second electrode of the data writing transistor of the first pixel circuit is electrically connected to the first electrode of the driving transistor of the first pixel circuit; a first electrode of the threshold compensation transistor of the first pixel circuit is electrically connected to the gate of the driving transistor of the first pixel circuit, and a second electrode of the threshold compensation transistor of the first pixel circuit is electrically connected to the second electrode of the driving transistor of the first pixel circuit. A first electrode of the data writing transistor of the invalid pixel circuit is electrically connected to the invalid data line, and a second electrode of the data writing transistor of the invalid pixel circuit is electrically connected to the first electrode of the driving transistor of the invalid pixel circuit; a first electrode of the threshold compensation transistor of the invalid pixel circuit is electrically connected to the gate of the driving transistor of the invalid pixel circuit, and a second electrode of the threshold compensation transistor of the invalid pixel circuit is electrically connected to the second electrode of the driving transistor of the invalid pixel circuit. The display substrate satisfies at least one of the following: the threshold compensation transistor of the first pixel circuit is a dual-gate structure, and the threshold compensation transistor of the invalid pixel circuit is a single-gate structure; the length of the gate of the data writing transistor of the first pixel circuit along the second direction is greater than the length of the gate of the data writing transistor of the invalid pixel circuit along the second direction.

[0016] In some exemplary embodiments, gates of the data writing transistors and the threshold compensation transistors in the first pixel circuit and the invalid pixel circuit are connected to the scan line in an integrated structure.

[0017] In some exemplary embodiments, the first pixel circuit and the deactivation pixel circuit each include: a driving transistor, a first reset transistor, a threshold compensation transistor, and a storage capacitor. The gate electrode of the driving transistor of the first pixel circuit, the second electrode of the first reset transistor, the first electrode of the threshold compensation transistor, and the first plate of the storage capacitor are electrically connected to a second connection electrode; the orthographic projection of the second connection electrode on the substrate partially overlaps with the orthographic projection of the scan line on the substrate. The gate electrode of the driving transistor of the deactivation pixel circuit and the first plate of the storage capacitor are electrically connected to a ninth connection electrode, and the second electrode of the first reset transistor and the first electrode of the threshold compensation transistor of the deactivation pixel circuit are electrically connected to a tenth connection electrode. The ninth and tenth connection electrodes are located on either side of the scan line and do not overlap with the orthographic projection of the scan line on the substrate.

[0018] In some exemplary embodiments, the ninth connection electrode and the tenth connection electrode are both electrically connected to a second voltage line extending along the second direction and transmitting a first voltage signal.

[0019] In some exemplary embodiments, the first pixel circuit further includes: a first shielding electrode, the first shielding electrode being located on a side of the second connecting electrode away from the substrate, the orthographic projection of the first shielding electrode on the substrate overlapping the orthographic projection of the second connecting electrode on the substrate. The inactive pixel circuit further includes: a second shielding electrode, the second shielding electrode being located on a side of the ninth connecting electrode and the tenth connecting electrode away from the substrate, the orthographic projection of the second shielding electrode on the substrate overlapping the orthographic projections of the ninth connecting electrode and the tenth connecting electrode on the substrate.

[0020] In some exemplary embodiments, the first pixel circuit further includes: a first shielding electrode, the first shielding electrode being located on a side of the second connecting electrode away from the substrate, the orthographic projection of the first shielding electrode on the substrate overlapping the orthographic projection of the second connecting electrode on the substrate. The inactive pixel circuit further includes: a third shielding electrode and a fourth shielding electrode, the third shielding electrode and the fourth shielding electrode being located on a side of the ninth connecting electrode and the tenth connecting electrode away from the substrate, the orthographic projection of the third shielding electrode on the substrate overlapping the orthographic projection of the ninth connecting electrode on the substrate, the orthographic projection of the fourth shielding electrode on the substrate overlapping the orthographic projection of the tenth connecting electrode on the substrate, and the orthographic projections of the third shielding electrode and the fourth shielding electrode on the substrate not overlapping the orthographic projection of the scan line on the substrate.

[0021] In some exemplary embodiments, the third shielding electrode is electrically connected to a third voltage line extending along the first direction and transmitting a second voltage signal; the fourth shielding electrode is electrically connected to a second voltage line extending along the second direction and transmitting a first voltage signal, and the first voltage signal is greater than the second voltage signal.

[0022] In some exemplary embodiments, the plurality of circuit units further include: a plurality of second pixel circuits; at least one of the second pixel circuits and the inactive pixel circuit are located in the same unit column. The substrate further includes: a second display area located at least one side of the first display area; the light-emitting structure layer further includes: a plurality of second light-emitting elements located in the second display area. At least one of the second pixel circuits is electrically connected to at least one second light-emitting element via a conductive connection line.

[0023] On the other hand, an embodiment of the present disclosure provides a display device comprising the display substrate as described above, and a sensor located on the non-display surface side of the display substrate; the orthographic projection of the sensor on the display substrate at least partially overlaps with the second display area of ​​the display substrate.

[0024] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0025] Summary of the Figures

[0026] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0027] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0028] FIG2 is a schematic planar structural diagram of a display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0029] FIG3 is a schematic diagram of a partial structure of a display substrate according to at least one embodiment of the present disclosure;

[0030] FIG4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0031] FIG5 is a partial plan view of a first display area according to at least one embodiment of the present disclosure;

[0032] FIG6 is a schematic plan view of the display substrate after the semiconductor layer is formed in FIG5 ;

[0033] FIG7A is a schematic plan view of the display substrate after the first conductive layer is formed in FIG5 ;

[0034] FIG7B is a schematic diagram of the first conductive layer in FIG7A ;

[0035] FIG8A is a schematic plan view of the display substrate after the second conductive layer is formed in FIG5 ;

[0036] FIG8B is a schematic diagram of the second conductive layer in FIG8A ;

[0037] FIG9 is a schematic plan view of the display substrate after the third insulating layer is formed in FIG5 ;

[0038] FIG10A is a schematic plan view of the display substrate after the third conductive layer is formed in FIG5 ;

[0039] FIG10B is a schematic diagram of the third conductive layer in FIG10A ;

[0040] FIG11 is a schematic plan view of the display substrate after the fifth insulating layer is formed in FIG5 ;

[0041] FIG12A is a schematic plan view of the display substrate after the fourth conductive layer is formed in FIG5 ;

[0042] FIG12B is a schematic diagram of the fourth conductive layer in FIG12A;

[0043] FIG13 is a schematic plan view of the display substrate after the sixth insulating layer is formed in FIG5 ;

[0044] FIG14A is a schematic plan view of the display substrate after the fifth conductive layer is formed in FIG5 ;

[0045] FIG14B is a schematic diagram of the fifth conductive layer in FIG14A;

[0046] FIG15 is a schematic plan view of the display substrate after the seventh insulating layer is formed in FIG5 ;

[0047] FIG16A is a schematic plan view of the display substrate after the first connection layer is formed in FIG5 ;

[0048] FIG16B is a schematic diagram of the first connection layer in FIG16A;

[0049] FIG17 is a schematic plan view of the display substrate after the eighth insulating layer is formed in FIG5 ;

[0050] FIG18A is a schematic plan view of the display substrate after the second connection layer is formed in FIG5 ;

[0051] FIG18B is a schematic diagram of the second connection layer in FIG18A;

[0052] FIG19 is a schematic plan view of the display substrate after the ninth insulating layer is formed in FIG5 ;

[0053] FIG20A is a schematic plan view of the display substrate after the third connection layer is formed in FIG5 ;

[0054] FIG20B is a schematic diagram of the third connection layer in FIG20A;

[0055] FIG21 is a schematic plan view of the display substrate after the tenth insulating layer is formed in FIG5 ;

[0056] FIG22A is a schematic plan view of the display substrate after the anode layer is formed in FIG5 ;

[0057] FIG22B is a schematic diagram of the anode layer in FIG22A ;

[0058] FIG23 is another partial schematic plan view of the driving circuit layer of the first display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0059] FIG24A is a schematic plan view of the display substrate after the third conductive layer is formed in FIG23;

[0060] FIG24B is a schematic diagram of the third conductive layer in FIG24A ;

[0061] FIG25A is a schematic plan view of the display substrate after the fourth conductive layer is formed in FIG23;

[0062] FIG25B is a schematic diagram of the fourth conductive layer in FIG25A;

[0063] FIG26 is another partial schematic plan view of the driving circuit layer of the first display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0064] FIG27A is a schematic plan view of the display substrate after the third conductive layer is formed in FIG26 ;

[0065] FIG27B is a schematic diagram of the third conductive layer in FIG27A ;

[0066] FIG28 is a schematic plan view of the display substrate after the fourth conductive layer is formed in FIG26;

[0067] FIG29 is another partial schematic plan view of the driving circuit layer of the first display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0068] FIG30 is a schematic diagram of the first conductive layer in FIG29;

[0069] FIG31 is another partial schematic plan view of a driving circuit layer in the first display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0070] FIG32 is another partial schematic plan view of the driving circuit layer of the first display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0071] FIG33A is a schematic plan view of the display substrate after the third conductive layer is formed in FIG32;

[0072] FIG33B is a schematic diagram of the third conductive layer in FIG33A ;

[0073] FIG34 is a schematic diagram of the fourth conductive layer in FIG32;

[0074] FIG35 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0075] Details

[0076] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0077] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0078] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0079] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0080] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0081] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0082] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0083] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0084] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0085] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0086] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0087] FIG1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, as shown in FIG1 , the display substrate may include: a display area AA and a peripheral area BB surrounding the periphery of the display area AA. The display area AA of the display substrate may include: a first display area A1 and a second display area A2; the first display area A1 may at least partially surround the second display area A2. For example, the second display area A2 may be located in the top center of the display area AA, and the first display area A1 may surround the second display area A2. However, this embodiment is not limited to this. For example, the second display area A2 may be located in other positions such as the upper left corner or the upper right corner of the display area, and the first display area A1 may surround at least one side of the second display area A2.

[0088] In some examples, as shown in FIG1 , the display area AA may be a rectangle, such as a rounded rectangle. The second display area A2 may be a circle or an ellipse. However, this embodiment is not limited thereto. For example, the second display area A2 may be a rectangle, a semicircle, a pentagon, or other shapes.

[0089] In some examples, as shown in Figure 1, the second display area A2 can be a light-transmitting display area, and can also be called a full display with camera (FDC) area under the screen, which is configured to display images and transmit light; the first display area A1 can be a normal display area, which is configured to display images. For example, the orthographic projection of the sensor (such as hardware such as a camera) on the display substrate can be located in the second display area A2 of the display substrate. In some examples, as shown in Figure 1, the second display area A2 can be circular, and the size of the orthographic projection of the sensor on the display substrate can be less than or equal to the size of the second display area A2. However, this embodiment is not limited to this. In other examples, the second display area A2 can be rectangular, and the size of the orthographic projection of the sensor on the display substrate can be less than or equal to the size of the inscribed circle of the second display area A2.

[0090] In some examples, as shown in FIG1 , the ratio of the resolution of the second display area A2 to the resolution of the first display area A1 can be approximately 0.8 to 1.2. Alternatively, the resolution of the second display area A2 can be substantially the same as the resolution of the first display area A1. This embodiment is not limited thereto.

[0091] Figure 2 is a schematic diagram of the planar structure of the display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2, the display area may include multiple pixel units P, and at least one pixel unit P may include a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 and a fourth subpixel P4 that emit a third color light. In some examples, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 and the fourth subpixel P4 may be green subpixels (G) that emit green light.

[0092] In some examples, each sub-pixel may include a circuit unit and a light-emitting element. The circuit unit may include at least a pixel circuit. The pixel circuit is respectively connected to a scan line, a data line, and a light-emitting control line. The pixel circuit may be configured to receive a data voltage transmitted by the data line and output a corresponding current to the light-emitting element under the control of the scan line and the light-emitting control line. The light-emitting element in at least one sub-pixel is respectively connected to the pixel circuit of the sub-pixel in which it is located. The light-emitting element is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel in which it is located.

[0093] In some examples, a pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin-film transistor, and C refers to a capacitor. The number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0094] In some examples, the multiple transistors in the pixel circuit can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield. In other examples, the multiple transistors in the pixel circuit can include P-type transistors and N-type transistors.

[0095] In some examples, multiple transistors in the pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0096] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0097] In some examples, the shape of the light-emitting element can be a rectangle, a rhombus, a pentagon, or a hexagon. The light-emitting elements of the four sub-pixels of a pixel unit can be arranged horizontally, vertically, or in a square. However, this embodiment is not limited to this. In other examples, a pixel unit can include three sub-pixels, and the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern.

[0098] In some implementations, in order to improve the light transmittance of the second display area A2, only a light-emitting element may be provided in the second display area A2, and the pixel circuit that drives the light-emitting element of the second display area A2 may be provided in the first display area A1. That is, the light transmittance of the second display area A2 is improved by separately providing the light-emitting element and the pixel circuit. In this implementation, the light-emitting element of the second display area is electrically connected to the pixel circuit of the first display area through a transparent conductive line, and the transparent conductive line overlaps with other signal lines (such as a scan line). For example, the parasitic capacitance generated by the overlap of the transparent conductive line and the scan line will cause the load of the scan line to increase, resulting in a reduction in the charging time of the pixel circuit, and it is easy for poor display to occur laterally (for example, along the first direction X) on both sides of the second display area. For example, the display brightness of the second display area is lower than the display brightness of the adjacent area; the display brightness of the first display area close to the second display area is lower than the display brightness of the first display area away from the second display area.

[0099] The present embodiment provides a display substrate and a display device, which can improve lateral display defects of the display substrate.

[0100] This embodiment provides a display substrate comprising: a substrate, a driving circuit layer, and a light-emitting structure layer. The driving circuit layer is located in a first display area and includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. The plurality of circuit units include at least a plurality of first circuit units and a plurality of second circuit units. The first circuit unit includes a first pixel circuit, a scan line electrically connected to the first pixel circuit and extending along a first direction, and a first data line electrically connected to the second direction. The second circuit unit includes an inactive pixel circuit, the scan line electrically connected to the inactive pixel circuit, and an inactive data line extending along the second direction. The first direction intersects the second direction. For example, the first direction and the second direction are perpendicular to each other. The display substrate satisfies at least one of the following conditions: the overlap area of ​​the scan line with the first pixel circuit in the first circuit unit is greater than the overlap area with the inactive pixel circuit in the second circuit unit; and the overlap area of ​​the scan line with the first data line in the first circuit unit is greater than the overlap area with the inactive data line in the second circuit unit. The light-emitting structure layer is located on a side of the driving circuit layer away from the substrate and includes a plurality of first light-emitting elements located in the first display area, with at least one first pixel circuit electrically connected to at least one first light-emitting element.

[0101] In some examples, the overlapping area of ​​the scan line with the first pixel circuit in the first circuit unit may be greater than the overlapping area with the invalid pixel circuit in the second circuit unit. Alternatively, the overlapping area of ​​the scan line with the first data line in the first circuit unit may be greater than the overlapping area with the invalid data line in the second circuit unit. Alternatively, the overlapping area of ​​the scan line with the first pixel circuit in the first circuit unit may be greater than the overlapping area with the invalid pixel circuit in the second circuit unit; furthermore, the overlapping area of ​​the scan line with the first data line in the first circuit unit may be greater than the overlapping area with the invalid data line in the second circuit unit. This embodiment is not limited to this.

[0102] The display substrate provided in this embodiment can reduce the load of the scan line by reducing the overlapping area of ​​the scan line and the invalid pixel circuit or invalid data line in the second circuit unit, thereby improving the horizontal display defects of the display substrate.

[0103] In some exemplary embodiments, the orthographic projections of the scan lines and invalid data lines in the second circuit unit onto the substrate may not overlap. The orthographic projections of the scan lines and first data lines in the first circuit unit onto the substrate may partially overlap. In some examples, in a cell column where the second circuit unit is located, multiple invalid data lines may be arranged sequentially along the second direction, with a first break provided between adjacent invalid data lines in the second direction. The length of the scan lines along the second direction may be less than the length of the first break along the second direction. This example reduces the load on the scan lines by reducing the overlapping area between the invalid data lines and the scan lines.

[0104] In some exemplary embodiments, the first pixel circuit and the invalid pixel circuit may each include at least: a driving transistor, a data writing transistor, and a threshold compensation transistor. The gates of the data writing transistor and the threshold compensation transistor of the first pixel circuit and the invalid pixel circuit are electrically connected to the scan line. The first electrode of the data writing transistor of the first pixel circuit is electrically connected to the first data line, and the second electrode of the data writing transistor of the first pixel circuit is electrically connected to the first electrode of the driving transistor of the first pixel circuit; the first electrode of the threshold compensation transistor of the first pixel circuit is electrically connected to the gate of the driving transistor of the first pixel circuit, and the second electrode of the threshold compensation transistor of the first pixel circuit is electrically connected to the second electrode of the driving transistor of the first pixel circuit. The first electrode of the data writing transistor of the invalid pixel circuit is electrically connected to the invalid data line, and the second electrode of the data writing transistor of the invalid pixel circuit is electrically connected to the first electrode of the driving transistor of the invalid pixel circuit; the first electrode of the threshold compensation transistor of the invalid pixel circuit is electrically connected to the gate of the driving transistor of the invalid pixel circuit, and the second electrode of the threshold compensation transistor of the invalid pixel circuit is electrically connected to the second electrode of the driving transistor of the invalid pixel circuit. The display substrate may satisfy at least one of the following conditions: the threshold compensation transistor of the first pixel circuit has a dual-gate structure, and the threshold compensation transistor of the inactive pixel circuit has a single-gate structure; and the gate length of the data write transistor of the first pixel circuit along the second direction is greater than the gate length of the data write transistor of the inactive pixel circuit along the second direction. In this example, by reducing the gate size of at least one of the threshold compensation transistor and the data write transistor of the inactive pixel circuit, the overlap area between the scan line and the inactive pixel circuit can be reduced, thereby reducing the load on the scan line and reducing the parasitic capacitance of the scan line.

[0105] In some exemplary embodiments, the first pixel circuit and the invalid pixel circuit may each include: a driving transistor, a first reset transistor, a threshold compensation transistor, and a storage capacitor. The gate electrode of the driving transistor of the first pixel circuit, the second electrode of the first reset transistor, the first electrode of the threshold compensation transistor, and the first plate of the storage capacitor are electrically connected to the second connecting electrode. The orthographic projection of the second connecting electrode on the substrate partially overlaps with the orthographic projection of the scan line on the substrate. The gate electrode of the driving transistor of the invalid pixel circuit and the first plate of the storage capacitor are electrically connected to the ninth connecting electrode, the second electrode of the first reset transistor of the invalid pixel circuit and the first electrode of the threshold compensation transistor are electrically connected to the tenth connecting electrode, and the ninth connecting electrode and the tenth connecting electrode are located on both sides of the scan line and do not overlap with the orthographic projection of the scan line on the substrate. In this example, the connecting electrode connected to the first node of the invalid pixel circuit (i.e., the connection node of the gate electrode of the driving transistor, the second electrode of the first reset transistor, the first electrode of the threshold compensation transistor, and the first plate of the storage capacitor) is set to be disconnected at the scan line and does not overlap with the scan line, thereby reducing the overlapping area between the invalid pixel circuit and the scan line and reducing the load of the scan line.

[0106] In some exemplary embodiments, the first pixel circuit may further include: a first shielding electrode, the first shielding electrode being located on a side of the second connecting electrode away from the substrate, the first shielding electrode's orthographic projection on the substrate overlapping the second connecting electrode's orthographic projection on the substrate. The inactive pixel circuit may further include: a third shielding electrode and a fourth shielding electrode, the third shielding electrode and the fourth shielding electrode being located on a side of the ninth connecting electrode and the tenth connecting electrode away from the substrate; the orthographic projection of the third shielding electrode on the substrate overlapping the ninth connecting electrode's orthographic projection on the substrate, the orthographic projection of the fourth shielding electrode on the substrate overlapping the tenth connecting electrode's orthographic projection on the substrate, the orthographic projections of the third shielding electrode and the fourth shielding electrode on the substrate not overlapping the orthographic projections of the scan line on the substrate. In this example, the shielding electrode that shields the first node of the inactive pixel circuit (i.e., the connection node of the gate of the driving transistor, the second electrode of the first reset transistor, the first electrode of the threshold compensation transistor, and the first plate of the storage capacitor) is set to be disconnected at the scan line so as not to overlap with the scan line, thereby further reducing the overlapping area between the inactive pixel circuit and the scan line and reducing the load on the scan line.

[0107] The solution of this embodiment is illustrated below through some examples.

[0108] Figure 3 is a schematic diagram of a partial structure of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the display substrate may include at least: a plurality of pixel circuits and a plurality of first light-emitting elements 53 located in a first display area A1; and a plurality of second light-emitting elements 54 located in a second display area A2. The plurality of pixel circuits in the first display area A1 may include: a plurality of first pixel circuits 51, a plurality of second pixel circuits 52, and a plurality of inactive pixel circuits 55.

[0109] In some examples, as shown in FIG2 , at least one first pixel circuit 51 among the plurality of first pixel circuits 51 can be electrically connected to at least one first light-emitting element 53 among the plurality of first light-emitting elements 53, and the orthographic projection of the at least one first pixel circuit 51 on the substrate can at least partially overlap with the orthographic projection of the at least one first light-emitting element 53 on the substrate. The first pixel circuit 51 can be configured to provide a drive signal to the connected first light-emitting element 53 to drive the corresponding first light-emitting element 53 to emit light. For example, the plurality of first pixel circuits 51 and the plurality of first light-emitting elements 53 can have a one-to-one relationship, or a one-to-many relationship.

[0110] In some examples, as shown in FIG3 , at least one second pixel circuit 52 among the plurality of second pixel circuits 52 can be electrically connected to at least one second light-emitting element 54 among the plurality of second light-emitting elements 54 via a conductive connection line 41. The second pixel circuit 52 can be configured to provide a drive signal to the connected second light-emitting element 54 to drive the corresponding second light-emitting element 54 to emit light. For example, the plurality of second pixel circuits 52 and the plurality of second light-emitting elements 54 can have a one-to-one relationship, or a one-to-many relationship. Since the second light-emitting elements 54 and the second pixel circuits 52 are located in different areas, the orthographic projection of at least one second pixel circuit 52 on the substrate and the orthographic projection of at least one second light-emitting element 54 on the substrate may not overlap.

[0111] In some examples, the light-emitting area of ​​a single second light-emitting element 54 can be smaller than the light-emitting area of ​​a single first light-emitting element 53. That is, the light-emitting area of ​​the first light-emitting element 53 can be larger than the light-emitting area of ​​the second light-emitting element 54. The light-emitting area of ​​a single light-emitting element can correspond to the area of ​​the pixel opening of the pixel definition layer. In some examples, in the second display area A2, a light-transmitting area can be provided between adjacent second light-emitting elements 54. For example, multiple light-transmitting areas can be connected to each other to form a continuous light-transmitting area separated by multiple second light-emitting elements 54. The conductive connecting line 41 is made of a transparent conductive material to maximize the light transmittance of the light-transmitting area.

[0112] In some examples, as shown in FIG3 , a plurality of second pixel circuits 52 may be arranged at intervals between a plurality of first pixel circuits 51, and a plurality of invalid pixel circuits 55 may be arranged at intervals between a plurality of first pixel circuits 51. For example, a plurality of first pixel circuits 51 may be arranged between two adjacent second pixel circuits 52 in the first direction X, and a plurality of first pixel circuits 51 may be arranged between two adjacent invalid pixel circuits 55. This example, by providing the invalid pixel circuit 55, can help improve the uniformity of components of multiple film layers in the etching process. For example, the invalid pixel circuit 55 can have substantially the same structure as the second pixel circuit 52 in its row or column, except that it is not electrically connected to any light-emitting element.

[0113] In some examples, because the first display area A1 is provided with not only the first pixel circuit 51 electrically connected to the first light-emitting element 53 but also the second pixel circuit 52 electrically connected to the second light-emitting element 54, the number of pixel circuits in the first display area A1 is greater than the number of first light-emitting elements 53. In some examples, the area for providing the newly added pixel circuits (including the second pixel circuit 52 and the inactive pixel circuit 55) can be obtained by reducing the size of the first pixel circuit 51 in the first direction X. For example, the size of the pixel circuit in the first direction X can be smaller than the size of the first light-emitting element in the first direction X.

[0114] In some examples, each of the original a columns of pixel circuits can be compressed along the first direction X to create space for an additional column of pixel circuits, and the space occupied by the a column of pixel circuits before compression and the a+1 column of pixel circuits after compression can be the same. Wherein, a can be an integer greater than 1. In this example, a can be equal to 2. However, this embodiment is not limited to this. For example, a can be 3 or 4, etc.

[0115] In some examples, the second pixel circuit 52 and the invalid pixel circuit 55 may be provided in the first display area A1 on both sides (e.g., left and right) of the second display area A2 along the first direction X, and the second pixel circuit and the invalid pixel circuit may not be provided in the first display area A on both sides (e.g., upper and lower) of the second display area A2 along the second direction Y, or only the invalid pixel circuit may be provided. This embodiment is not limited to this.

[0116] FIG4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this example may have a 7T1C structure. In some examples, as shown in FIG4 , the pixel circuit of this example may include: first transistors T1 to T7. The pixel circuit may be electrically connected to a scan line GL, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.

[0117] In some examples, as shown in FIG4 , the first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL can be configured to provide a scan signal SCAN to the pixel circuit, the data line DL can be configured to provide a data signal to the pixel circuit, the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset signal RESET2 to the pixel circuit.

[0118] In some examples, in a row of pixel circuits, the second reset control line RST2 can be connected to the scan line GL to be input with the scan signal SCAN. That is, the second reset signal RESET2(n) received by the pixel circuit in the nth row is the scan signal SCAN(n) received by the pixel circuit in the nth row. However, this embodiment is not limited to this. For example, the second reset control signal line RST2 can be input with a second reset control signal RESET2 that is different from the scan signal SCAN. In some examples, in the pixel circuit in the nth row, the first reset control line RST1 can be connected to the scan line GL of the pixel circuit in the n-1th row to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be achieved.

[0119] In some examples, as shown in FIG4 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 may also be referred to as a driving transistor. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The first transistor T1 may also be referred to as a first reset transistor and is configured to reset the gate of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan line GL, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3. The second transistor T2 may also be referred to as a threshold compensation transistor. The gate of the fourth transistor T4 is electrically connected to the scan line GL, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. The fourth transistor T4 may also be referred to as a data write transistor. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The fifth transistor T5 may also be referred to as a first emission control transistor. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The sixth transistor T6 may also be referred to as a second emission control transistor. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The seventh transistor T7 may also be referred to as a second reset transistor and is configured to reset the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1. The cathode of the light-emitting element EL is electrically connected to the second power line PL2.

[0120] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3 and the second transistor T2, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3, the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light-emitting element EL.

[0121] The following describes the operation process of the pixel circuit shown in Figure 4. The description is made by taking the pixel circuit shown in Figure 4 as an example in which all of the multiple transistors included are P-type transistors.

[0122] In some examples, during a frame display period, the operation process of the pixel circuit may include: a first stage, a second stage, and a third stage. In this example, the second reset control line RST2 and the scan line GL transmit the same signal as an example for description.

[0123] The first phase is called the reset phase. The first reset control signal RESET1 provided by the first reset control line RST1 is low, turning on the first reset transistor T1. The first initial signal provided by the first initial signal line INIT1 is supplied to the first node N1, initializing the first node N1 and clearing the existing data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is high, and the emission control signal EM provided by the emission control line EML is high, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the light-emitting element EL does not emit light.

[0124] The second phase is called the data writing phase or the threshold compensation phase. The scan signal SCAN provided by the scan line GL is a low-level signal, the first reset control signal RESET1 provided by the first reset control line RST1, and the emission control signal EM provided by the emission control line EML are both high-level signals, and the data line DL outputs a data signal. During this phase, since the first electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on. The scan signal SCAN is a low-level signal, turning on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on, causing the data voltage Vdata output by the data line DL to be provided to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is then charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, allowing the second initialization signal (i.e., anode reset signal) provided by the second initialization signal line INIT2 to be supplied to the anode of the light-emitting element EL, thereby initializing (resetting) the anode of the light-emitting element EL and clearing the pre-stored voltage therein, completing the initialization and ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, turning off the first transistor T1. The emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0125] The third phase is called the light-emitting phase. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The first voltage signal VDD output by the first power line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0126] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2=K×[VDD-Vdata] 2 ;

[0127] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0128] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0129] Figure 5 is a partial plan view of the first display area of ​​at least one embodiment of the present disclosure. In this example, multiple circuit units arranged in sequence along the first direction X can be called a unit row, and multiple circuit units arranged in sequence along the second direction Y can be called a unit column.

[0130] In some examples, as shown in FIG5 , the first display area may include at least: a substrate, and a driving circuit layer, a conductive connection layer, and a light-emitting structure layer sequentially arranged on the substrate. The driving circuit layer may include at least: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of invalid pixel circuits. The circuit structures of the first pixel circuit, the second pixel circuit, and the invalid pixel circuit may all be 7T1C structures as shown in FIG4 . The conductive connection layer may include at least a plurality of conductive connection lines, and the conductive connection lines may be configured to extend to the second display area to electrically connect the corresponding second pixel circuit and the second light-emitting element located in the second display area. The light-emitting structure layer may include at least: a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area, and the plurality of first light-emitting elements may be electrically connected to the plurality of first pixel circuits.

[0131] 5 to 22B , the structure of the first display area of ​​the display substrate of this example is described by way of example through the preparation process of the display substrate.

[0132] The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0133] As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0134] In some examples, as shown in Figures 6 to 21, the first display area may include: a first circuit area A11 and a second circuit area A12 arranged at intervals along the first direction X. The first circuit area A11 may be provided with a plurality of unit columns (for example, two unit columns), and the second circuit area A12 may be provided with one unit column. The plurality of unit columns of the first circuit area A11 may include a plurality of first circuit units, and each first circuit unit may include at least: a first pixel circuit and a scan line and a first data line electrically connected to the first pixel circuit. The first pixel circuit may include: a first transistor 11 to a seventh transistor 17 and a storage capacitor 18. A unit column of the second circuit area A12 may include a plurality of second circuit units, and at least one second circuit unit may include: an invalid pixel circuit and a scan line and an invalid data line electrically connected to the invalid pixel circuit. The invalid pixel circuit may include: a first transistor 21 to a seventh transistor 27 and a storage capacitor 28.

[0135] In this example, circuit units arranged in two rows and six columns (e.g., including columns N-1 to N+4, and rows M and M+1) are used as an example. The circuit units in columns N-1, N, N+2, and N+3 include a plurality of first circuit units, while the circuit units in columns N+1 and N+4 include a plurality of second circuit units. The following describes the structure of the first circuit unit in row M of column N and the second circuit unit in row M of column N+1 as an example.

[0136] In some examples, the preparation process of the display substrate may include the following operations.

[0137] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0138] (2) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer disposed on the substrate.

[0139] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the semiconductor layer may include, for example, polycrystalline silicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, doped with impurities, and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as the source electrode or drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this. In other examples, the material of the semiconductor layer may include amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), and the like. This embodiment may be applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0140] FIG6 is a schematic plan view of the display substrate after the semiconductor layer is formed in FIG5 . In some examples, as shown in FIG6 , the semiconductor layer of the first circuit unit may include at least: active layers of multiple transistors of the first pixel circuit (e.g., including the first active layer 110 of the first transistor of the first pixel circuit in the current row, the second active layer 120 of the second transistor, the third active layer 130 of the third transistor, the fourth active layer 140 of the fourth transistor, the fifth active layer 150 of the fifth transistor, the sixth active layer 160 of the sixth transistor, and the seventh active layer 170 of the seventh transistor of the first pixel circuit in the previous row). The active layers of the seven transistors of the first pixel circuit may be an interconnected integrated structure.

[0141] In some examples, as shown in FIG6 , the semiconductor layer of the second circuit unit may include at least active layers of multiple transistors of the invalid pixel circuit (e.g., a first active layer 210 of a first transistor of the invalid pixel circuit of the current row, a second active layer 220 of a second transistor, a third active layer 230 of a third transistor, a fourth active layer 240 of a fourth transistor, a fifth active layer 250 of a fifth transistor, a sixth active layer 260 of a sixth transistor, and a seventh active layer 270 of a seventh transistor of the invalid pixel circuit of the previous row). The active layers of the seven transistors of the invalid pixel circuit may be an interconnected integrated structure.

[0142] In some examples, as shown in FIG6 , in a unit row, the active layers of the pixel circuits in the 2i-1th circuit unit and the 2ith circuit unit can be interconnected as an integrated structure, where i is an integer greater than 0. For example, the first active layer of the first pixel circuit in the circuit unit in the Mth row and N-1th column (i.e., the first circuit unit) and the first active layer 110 of the first pixel circuit in the circuit unit in the Mth row and Nth column (i.e., the first circuit unit) can be interconnected as an integrated structure. The first active layer 110 of the inactive pixel circuit in the circuit unit in the Mth row and N+1th column (i.e., the second circuit unit) and the first active layer of the first pixel circuit in the circuit unit in the Mth column and N+2th column (i.e., the first circuit unit) can be interconnected as an integrated structure.

[0143] In some examples, as shown in FIG6 , in a unit row, the active layers of the pixel circuits in the 2i-th circuit unit and the 2i+1-th circuit unit may be interconnected as an integrated structure, where i is an integer greater than 0. For example, the seventh active layer 170 of the first pixel unit in the circuit unit in the M-th row and N-th column (i.e., the first circuit unit) and the seventh active layer 270 of the inactive pixel circuit in the circuit unit in the M-th row and N+1-th column (i.e., the second circuit unit) may be interconnected as an integrated structure.

[0144] The arrangement of the active layer of the pixel circuit in the first display area of ​​this example can facilitate a compact arrangement of the pixel circuit, thereby saving space.

[0145] In some examples, as shown in FIG6 , the first active layers 110 and 210 may be approximately n-shaped, the second active layers 120 and 220, the sixth active layers 160 and 260, and the seventh active layer 270 may be approximately L-shaped, the third active layers 130 and 230 may be approximately Ω-shaped, and the fourth active layers 140 and 240 and the fifth active layers 150 and 250 may be approximately I-shaped. The seventh active layer 170 may be approximately zigzag-shaped. This embodiment is not limited thereto.

[0146] In some examples, the first region of the fourth active layer 140 and the first region of the fifth active layer 150 of the first pixel circuit can be provided separately. The first region of the first active layer 110 of the first pixel circuit can be connected to the first region of the first active layer of an adjacent pixel circuit on the opposite side of the first direction X, and the second region can also serve as the first region of the second active layer 120. The first region of the third active layer 130 can also serve as the second region of the fourth active layer 140 and the second region of the fifth active layer 150; the second region of the third active layer 130 can also serve as the second region of the second active layer 120 and the first region of the sixth active layer 160; and the second region of the sixth active layer 160 can also serve as the first region of the seventh active layer 170. The first region of the seventh active layer 170 can be connected to the first region of the seventh active layer of an adjacent pixel circuit along the first direction X. The structure of the active layer of the inactive pixel circuit is similar to that of the first pixel circuit and is therefore not further described here.

[0147] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The first conductive film is patterned through a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer.

[0148] FIG7A is a plan view schematic diagram of the display substrate after the first conductive layer is formed in FIG5 . FIG7B is a schematic diagram of the first conductive layer in FIG7A . In some examples, as shown in FIG7A and FIG7B , the first conductive layer of the first circuit unit may include at least: gates of multiple transistors of the first pixel circuit (e.g., gates of the first transistor 11 to the sixth transistor 16 of the first pixel circuit in the current row, and the gate of the seventh transistor of the first pixel circuit in the previous row), as well as a first plate 181 of the storage capacitor, a first reset control line (e.g., a first reset control line RST1(m) or RST1(m+1)), a scan line (e.g., a scan line GL(m) or GL(m+1)), and a light emitting control line (e.g., a light emitting control line EML(m) or EML(m+1)).

[0149] In some examples, as shown in Figures 7A and 7B, the first conductive layer of the second circuit unit may include at least: gates of multiple transistors of the invalid pixel circuit (for example, the gates of the first transistor 21 to the sixth transistor 26 of the invalid pixel circuit of this row, the first plate 281 of the storage capacitor, and the gate of the seventh transistor 27 of the invalid pixel circuit of the previous row), a first reset control line (for example, the first reset control line RST1(m) or RST1(m+1)), a scan line (for example, the scan line GL(m) or GL(m+1)), and a light-emitting control line (for example, the light-emitting control line EML(m) or EML(m+1)).

[0150] The following description takes the first reset control line RST1(m), the scan line GL(m) and the light-emitting control line EML(m) as an example. The structures of the first reset control line RST1(m+1), the scan line GL(m+1) and the light-emitting control line EML(m+1) are similar, so they are not repeated here.

[0151] In some examples, the scan line GL(m) is located on one side of the first reset control line RST1(m) in the second direction Y. The emission control line EML(m) is located on one side of the scan line GL(m) in the second direction Y. The first plate 181 of the storage capacitor of the first pixel circuit and the first plate 281 of the storage capacitor of the inactive pixel circuit in the Mth row can be arranged alternately along the first direction X and located between the emission control line EML(m) and the scan line GL(m) in the second direction Y.

[0152] In some examples, the shape of the first reset control line RST1(m) can be roughly a straight line extending along the first direction X. In the first circuit unit, the area where the first reset control line RST1(m) overlaps with the first active layer of the first transistor 11 of the first pixel circuit of the current row can serve as the gate of the first transistor 11 of the dual-gate structure, and the area where the first reset control line RST1(m) overlaps with the seventh active layer of the seventh transistor of the first pixel circuit of the previous row can serve as the gate of the seventh transistor. In the second circuit unit, the area where the first reset control line RST1(m) overlaps with the first active layer of the first transistor 21 of the invalid pixel circuit of the current row can serve as the gate of the first transistor 21 of the dual-gate structure, and the area where the first reset control line RST1(m) overlaps with the seventh active layer of the seventh transistor of the invalid pixel circuit of the previous row can serve as the gate of the seventh transistor.

[0153] In some examples, the shape of the scan line GL(m) can be roughly a straight line with the main portion extending along the first direction X. The length of the scan line GL(m) along the second direction Y can be recorded as L1. In the first circuit unit, the area where the scan line GL(m) overlaps with the second active layer of the second transistor 12 of the first pixel circuit of this row can serve as the first gate of the second transistor 12 of the dual-gate structure, and the area where the scan line GL(m) overlaps with the fourth active layer of the fourth transistor 14 of the first pixel circuit of this row can serve as the gate of the fourth transistor 14. In the second circuit unit, the area where the scan line GL(m) overlaps with the second active layer of the second transistor 22 of the invalid pixel circuit of this row can serve as the first gate of the second transistor 22 of the dual-gate structure, and the area where the scan line GL(m) overlaps with the fourth active layer of the fourth transistor 24 of the invalid pixel circuit of this row can serve as the gate of the fourth transistor 24.

[0154] In some examples, within the first circuit unit, a first protrusion 191 may be provided on a side of the scan line GL(m) away from the first reset control line RST1(m). The shape of the first protrusion 191 may be substantially rectangular. The first end of the first protrusion 191 is connected to the scan line GL(m), and the second end of the first protrusion 191 extends toward the first plate 181 of the storage capacitor. The area where the first protrusion 191 overlaps with the second active layer of the second transistor 12 of the first pixel circuit of this row may serve as the second gate of the second transistor 12 of the dual-gate structure. The scan line GL(m) and the first protrusion 191 may be an integral structure connected to each other.

[0155] In some examples, within the first circuit unit, a second protrusion 192 may be provided on a side of the scan line GL(m) away from the first reset control line RST1(m). The shape of the second protrusion 192 may be substantially rectangular. The first end of the second protrusion 192 is connected to the scan line GL(m), and the second end of the second protrusion 192 extends toward the first plate 181 of the storage capacitor. The region where the second protrusion 192 overlaps with the fourth active layer of the fourth transistor 14 of the first pixel circuit of the row may serve as the gate of the fourth transistor 14. The second protrusion 192 and the first protrusion 191 may be spaced apart along the first direction X. The length of the first protrusion 191 along the second direction Y may be greater than the length of the second protrusion 192 along the second direction Y. The length of the first protrusion 191 along the first direction X may be less than the length of the second protrusion 192 along the first direction X. The scan line GL(m) and the second protrusion 192 may be an integrated structure connected to each other. In this example, the second protrusion 192 can increase the size of the gate of the fourth transistor 14 along the second direction Y and the size of the channel region of the fourth transistor 14 , thereby ensuring the data writing performance of the first pixel circuit.

[0156] In some examples, within the second circuit unit, a third protrusion 193 may be provided on a side of the scan line GL(m) away from the first reset control line RST1(m). The shape of the third protrusion 193 may be approximately rectangular. The first end of the third protrusion 193 is connected to the scan line GL(m), and the second end of the third protrusion 193 extends toward the first electrode 281 of the storage capacitor. The area where the third protrusion 193 overlaps with the second active layer of the second transistor 22 of the invalid pixel circuit of this row can serve as the second gate of the second transistor 22 of the dual-gate structure. The scan line GL(m) and the third protrusion 193 may be an integral structure connected to each other. The shape and size of the third protrusion 193 may be approximately the same as the shape and size of the first protrusion 191.

[0157] In some examples, within the second circuit unit, a fourth protrusion 194 may be provided on a side of the scan line GL(m) away from the first reset control line RST1(m). The fourth protrusion 194 may be substantially rectangular in shape. A first end of the fourth protrusion 194 is connected to the scan line GL(m), and a second end of the fourth protrusion 194 extends toward the first plate 281 of the storage capacitor. The region where the fourth protrusion 194 overlaps with the fourth active layer of the fourth transistor 24 in the inactive pixel circuit of the row may serve as the gate of the fourth transistor 24. The fourth protrusion 194 and the third protrusion 193 may be spaced apart along the first direction X. The length of the third protrusion 193 along the second direction Y may be greater than the length of the fourth protrusion 194 along the second direction Y. The length of the third protrusion 193 along the first direction X may be less than the length of the fourth protrusion 194 along the first direction X. The shape and size of the fourth protrusion 194 may be substantially the same as those of the second protrusion 192. The scan line GL(m) and the fourth protrusion 194 may be an integrated structure connected to each other.

[0158] In some examples, within the first circuit unit, the first plate 181 of the storage capacitor of the first pixel circuit can be substantially rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first plate 181 on the substrate can at least partially overlap with the orthographic projection of the third active layer of the third transistor 13 on the substrate. The first plate 181 can simultaneously serve as the first electrode (i.e., the lower plate) of the storage capacitor of the first pixel circuit and the gate of the third transistor 13.

[0159] In some examples, within the second circuit unit, the shape of the first plate 281 of the storage capacitor of the deactivated pixel circuit can be substantially rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first plate 281 on the substrate can at least partially overlap with the orthographic projection of the third active layer of the third transistor 23 on the substrate. The first plate 281 can simultaneously serve as the first electrode (i.e., the lower plate) of the storage capacitor of the deactivated pixel circuit and the gate of the third transistor 23.

[0160] In some examples, the shape of the emission control line EML(m) can be substantially a straight line extending along the first direction X. Within the first circuit unit, the area where the emission control line EML(m) overlaps with the fifth active layer of the fifth transistor 15 of the first pixel circuit in the same row can serve as the gate of the fifth transistor 15, and the area where the emission control line EML(m) overlaps with the sixth active layer of the sixth transistor 16 of the first pixel circuit in the same row can serve as the gate of the sixth transistor 16. Within the second circuit unit, the area where the emission control line EML(m) overlaps with the fifth active layer of the fifth transistor 25 of the inactive pixel circuit in the same row can serve as the gate of the fifth transistor 25, and the area where the emission control line EML(m) overlaps with the sixth active layer of the sixth transistor 26 of the inactive pixel circuit in the same row can serve as the gate of the sixth transistor 26.

[0161] In some examples, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield. The semiconductor layer in the area blocked by the first conductive layer can form the channel region of the seven transistors of the first pixel circuit and the seven transistors of the invalid pixel circuit, and the semiconductor layer in the area not blocked by the first conductive layer is conductorized, that is, the first and second areas of the seven transistors of the first pixel circuit and the first and second areas of the seven transistors of the invalid pixel circuit can all be conductorized.

[0162] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second conductive film is patterned through a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer.

[0163] Figure 8A is a planar schematic diagram of the display substrate after the second conductive layer is formed in Figure 5. Figure 8B is a schematic diagram of the second conductive layer in Figure 8A. In some examples, as shown in Figures 8A and 8B, the second conductive layer of the first circuit unit may include at least: a second plate 182 of the storage capacitor of the first pixel circuit, a first initial signal line (e.g., a first initial signal line INIT1(m) or INIT1(m+1)), and a second initial signal line (e.g., a second initial signal line INIT2(m-1) or INIT2(m)). The second conductive layer of the second circuit unit may include at least: a second plate 282 of the storage capacitor of the inactive pixel circuit, a first initial signal line (e.g., a first initial signal line INIT1(m) or INIT1(m+1)), and a second initial signal line (e.g., a second initial signal line INIT2(m-1) or INIT2(m)).

[0164] The following description takes the first initial signal line INIT1(m) and the second initial signal line INIT2(m-1) as examples. The structures of the first initial signal line INIT1(m+1) and the second initial signal line INIT2(m) are similar and thus will not be repeated here.

[0165] In some examples, the orthographic projection of the second initial signal line INIT2(m-1) on the substrate is located on a side of the first reset control line RST1(m) in the opposite direction of the second direction Y. The first initial signal line INIT1(m) may be located on a side of the second initial signal line INIT2(m-1) in the second direction Y. The second plate 182 of the storage capacitor of the first pixel circuit and the second plate 282 of the storage capacitor of the inactive pixel circuit of the Mth row may be arranged alternately along the first direction X and located on a side of the first initial signal line INIT1(m) in the second direction Y.

[0166] In some examples, the second initial signal line INIT2(m-1) and the first initial signal line INIT1(m) may be shaped substantially as straight lines with main portions extending along the first direction X. The length of the main portion of the second initial signal line INIT2(m-1) along the second direction Y may be greater than the length of the main portion of the first initial signal line INIT1(m) along the second direction Y.

[0167] In some examples, within the first circuit unit and the second circuit unit, a fifth protrusion 195 may be provided on a side of the first initial signal line INIT1(m) adjacent to the second initial signal line INIT2(m-1). The shape of the fifth protrusion 195 may be substantially rectangular. A first end of the fifth protrusion 195 is connected to the first initial signal line INIT1(m), and a second end of the fifth protrusion 195 extends toward the second initial signal line INIT2(m-1). For example, the fifth protrusion 195 may be located between the first region of the first active layer and the first region of the adjacent seventh active layer. The fifth protrusion 195 and the first initial signal line INIT1(m) may be an integrally connected structure.

[0168] In some examples, within the first circuit unit and the second circuit unit, a sixth protrusion 196 may be provided on a side of the first initial signal line INIT1(m) away from the second initial signal line INIT2(m-1). The shape of the sixth protrusion 196 may be substantially rectangular. The sixth protrusion 196 and the fifth protrusion 195 may be spaced apart along the first direction X. The length of the sixth protrusion 196 along the first direction X may be less than the length of the fifth protrusion 195 along the first direction X. The first end of the sixth protrusion 196 is connected to the first initial signal line INIT1(m), and the second end of the sixth protrusion 196 extends toward the second plate 182 or 282 of the storage capacitor. For example, the sixth protrusion 196 may be located between the first region of the second active layer and the first region of the fourth active layer of the first pixel circuit (or inactive pixel circuit). The sixth protrusion 196 and the first initial signal line INIT1(m) may be an integral structure connected to each other. In this example, the provision of the sixth protrusion 196 helps shield the fourth transistor from the effects of other signals.

[0169] In some examples, within the first circuit unit, the second plate 182 of the storage capacitor of the first pixel circuit can partially overlap with the orthographic projection of the first plate 181 on the substrate. The second plate 182 can have a first opening, which can be substantially rectangular, and the orthographic projection of the first opening on the substrate can be located within the orthographic projection of the first plate 181 on the substrate. The first plate of the storage capacitor of the first pixel circuit can serve as a first electrode of the storage capacitor, and the second plate of the storage capacitor can serve as a second electrode of the storage capacitor.

[0170] In some examples, within the second circuit unit, the second plate 282 of the storage capacitor of the inactive pixel circuit can partially overlap with the orthographic projection of the first plate 281 on the substrate. The second plate 282 can have a second opening, which can be substantially rectangular, and the orthographic projection of the second opening on the substrate can be located within the orthographic projection of the first plate 281 on the substrate. The first plate of the storage capacitor of the inactive pixel circuit can serve as the first electrode of the storage capacitor, and the second plate of the storage capacitor can serve as the second electrode of the storage capacitor.

[0171] In some examples, the second plate 282 (or 182) may be provided with a plate connection line 183 on one side of the first direction X or on the side opposite to the first direction X. The first end of the plate connection line 183 may be connected to the second plate of the circuit unit, and the second end may be connected to the second plate of the adjacent circuit unit after extending along the first direction X or the opposite direction of the first direction X, so that the second plates of adjacent circuit units on a unit row can be connected to each other. For example, the second plate 182 of the first pixel circuit in the first circuit unit can be connected to the second plate 282 of the invalid pixel circuit via the plate connection line 183. In some examples, the plate connection line 183 and the second plates 182 and 282 may be an integrated structure connected to each other. The second plates (including second plates 182 and 282) of the integrated structure of multiple circuit units in this example can be reused as horizontal lines extending along the first direction X for transmitting the first voltage signal. This not only ensures that the multiple second plates in a unit row have the same potential, but also reduces the voltage drop of the first voltage signal, which is beneficial to improving the uniformity of the display substrate and ensuring the display effect.

[0172] (5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate having the aforementioned pattern formed thereon, and the third insulating film is patterned by a patterning process to form a third insulating layer. The third insulating layer of each circuit unit is provided with a plurality of vias. In some examples, the third insulating layer may also be referred to as an interlayer insulating layer.

[0173] FIG9 is a schematic plan view of the display substrate after the third insulating layer is formed in FIG5 . In some examples, as shown in FIG9 , the plurality of vias of the first circuit unit may include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a twelfth via V12, a fourteenth via V14, and a sixteenth via V16. The plurality of vias of the second circuit unit may include at least a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a thirteenth via V13, a fifteenth via V15, and a seventeenth via V17. For example, the first via V1 may be located at the junction of the N-1th column circuit unit and the Nth column circuit unit, the seventeenth via V17 may be located at the junction of the Nth column circuit unit and the N+1th column circuit unit, and the seventh via V7 may be located at the junction of the N+1th column circuit unit and the N+2th column circuit unit.

[0174] In some examples, the third insulating layer, the second insulating layer, and the first insulating layer within the first through eleventh vias V1 to V11 can be removed to expose a portion of the surface of the semiconductor layer. The third insulating layer and the second insulating layer within the twelfth through thirteenth vias V12 and V13 can be removed to expose a portion of the surface of the first conductive layer. The third insulating layer within the fourteenth through seventeenth vias V14 to V17 can be removed to expose a portion of the surface of the second conductive layer.

[0175] (6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate having the aforementioned pattern, and the third conductive film is patterned using a patterning process to form a third conductive layer disposed on the third insulating layer. In some examples, the third conductive layer may also be referred to as a first source / drain metal layer.

[0176] FIG10A is a plan view schematic diagram of the display substrate after the third conductive layer is formed in FIG5 . FIG10B is a schematic diagram of the third conductive layer in FIG10A . In some examples, as shown in FIG10A and FIG10B , the third conductive layer of the first circuit unit may include at least: a plurality of connection electrodes of the first pixel circuit (for example, including the first connection electrode 301, the second connection electrode 302, the third connection electrode 303, and the fourth connection electrode 304), and a first voltage line 31. The third conductive layer of the second circuit unit may include at least: a plurality of connection electrodes of the inactive pixel circuit (for example, including the fifth connection electrode 305, the sixth connection electrode 306, the seventh connection electrode 307, and the eighth connection electrode 308), and a second voltage line 32.

[0177] In some examples, the shape of the first connection electrode 301 can be substantially a strip shape extending along the first direction X. One end of the first connection electrode 301 can be electrically connected to the first region of the first active layer of the first pixel circuit through the first via hole V1, and the other end can be electrically connected to the first initial signal line INIT1(m) through the sixteenth via hole V16.

[0178] In some examples, the second connection electrode 302 may be shaped substantially like a strip extending along the second direction Y. One end of the second connection electrode 302 may be electrically connected to the first region of the second active layer of the first pixel circuit through a second via hole V2, and the other end may be electrically connected to the first plate 181 of the storage capacitor of the first pixel circuit through a twelfth via hole V12.

[0179] In some examples, the third connection electrode 303 may be substantially rectangular in shape. The third connection electrode 303 may be electrically connected to the first region of the fourth active layer of the first pixel circuit through a third via hole V3.

[0180] In some examples, the fourth connection electrode 304 may be substantially rectangular in shape. The fourth connection electrode 304 may be electrically connected to the second region of the sixth active layer of the first pixel circuit through the fifth via hole V5.

[0181] In some examples, the shape of the first voltage line 31 can be substantially a zigzag line with a main portion extending along the second direction Y. The first voltage line 31 can be electrically connected to the second electrode plate 182 of the first pixel circuit through the fourteenth via V14, and can also be electrically connected to the first region of the fifth active layer of the first pixel circuit through the fourth via V4.

[0182] In some examples, the fifth connection electrode 305 may be shaped substantially like a strip extending along the second direction Y. One end of the fifth connection electrode 305 may be electrically connected to the second initial signal line INIT2(m) through a seventeenth via hole V17, and the other end may be electrically connected to the first region of the seventh active layer of the first pixel circuit in the previous row through a sixth via hole V6.

[0183] In some examples, the shape of the sixth connection electrode 306 can be substantially a strip shape extending along the second direction Y. One end of the sixth connection electrode 306 can be electrically connected to the first region of the second active layer of the inactive pixel circuit through the eighth via hole V8, and the other end can be electrically connected to the first electrode plate 281 of the inactive pixel circuit through the thirteenth via hole V13.

[0184] In some examples, the shape of the seventh connection electrode 307 may be substantially rectangular. The seventh connection electrode 307 may be electrically connected to the first region of the fourth active layer of the inactive pixel circuit through a ninth via hole V9.

[0185] In some examples, the eighth connection electrode 308 may be substantially rectangular in shape. The eighth connection electrode 308 may be electrically connected to the second region of the sixth active layer of the inactive pixel circuit through the eleventh via hole V11.

[0186] In some examples, the second voltage line 32 can be shaped substantially like a zigzag line with a main portion extending along the second direction Y. The second voltage line 32 can be electrically connected to the second electrode plate 282 of the inactive pixel circuit through the fifteenth via hole V15, and can also be electrically connected to the first region of the fifth active layer of the inactive pixel circuit through the tenth via hole V10. The second voltage line 32 and the seventh connection electrode 307 can be an integral structure connected to each other.

[0187] (7) Forming a fourth insulating layer and a fifth insulating layer. In some examples, a fourth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and then a fifth insulating film is coated. The fifth insulating film and the fourth insulating film are patterned in sequence using a patterning process to form the fourth insulating layer and the fifth insulating layer. The fourth insulating layer and the fifth insulating layer of each circuit unit may be provided with a plurality of vias. In some examples, the fourth insulating layer may also be referred to as a passivation layer, and the fifth insulating layer may also be referred to as a first planarization layer.

[0188] Figure 11 is a schematic plan view of the display substrate after the fifth insulating layer is formed in Figure 5. In some examples, as shown in Figure 11, the plurality of vias of the first circuit unit may include at least a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23. The plurality of vias of the second circuit unit may include at least a twenty-fourth via V24, a twenty-fifth via V25, and a twenty-sixth via V26. The fifth and fourth insulating layers within the twenty-first through twenty-sixth vias V21 through V26 may be removed, exposing a portion of the surface of the third conductive layer.

[0189] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a second source / drain metal layer.

[0190] FIG12A is a planar schematic diagram of the display substrate after the fourth conductive layer is formed in FIG5 . FIG12B is a schematic diagram of the fourth conductive layer in FIG12A . In some examples, as shown in FIG12A and FIG12B , the fourth conductive layer of the first circuit unit may include at least: a plurality of connecting electrodes of the first pixel circuit (for example, including the eleventh connecting electrode 311 and the twelfth connecting electrode 312 ), and a first shielding electrode 321 of the first pixel circuit. The fourth conductive layer of the second circuit unit may include at least: a plurality of connecting electrodes of the inactive pixel circuit (for example, including the thirteenth connecting electrode 313 and the fourteenth connecting electrode 314 ), and a second shielding electrode 322 of the inactive pixel circuit.

[0191] In some examples, the eleventh connection electrode 311 may be substantially rectangular, and the corners of the rectangle may be chamfered. The eleventh connection electrode 311 may be electrically connected to the third connection electrode 303 of the first pixel circuit through the twenty-first via hole V21 to achieve electrical connection with the fourth transistor of the first pixel circuit.

[0192] In some examples, the twelfth connection electrode 312 may be substantially rectangular, with chamfered corners. The twelfth connection electrode 312 may be electrically connected to the fourth connection electrode 304 of the first pixel circuit through the twenty-second via hole V22 to achieve electrical connection to the sixth transistor of the first pixel circuit.

[0193] In some examples, the thirteenth connection electrode 313 can be substantially rectangular, and the corners of the rectangle can be chamfered. The thirteenth connection electrode 313 can be electrically connected to the seventh connection electrode 307 of the deactivated pixel circuit through the twenty-fourth via V24, thereby electrically connecting to the fourth transistor of the deactivated pixel circuit. Since the seventh connection electrode 307 and the second voltage line 32 are interconnected as an integrated structure, the thirteenth connection electrode 313 is also electrically connected to the second voltage line 32.

[0194] In some examples, the shape of the fourteenth connection electrode 314 can be substantially rectangular, and the corners of the rectangle can be chamfered. The fourteenth connection electrode 314 can be electrically connected to the eighth connection electrode 308 of the invalid pixel circuit through the twenty-fifth via hole V25 to achieve electrical connection with the sixth transistor of the invalid pixel circuit.

[0195] In some examples, the shape of the first shielding electrode 321 can be roughly a broken line extending along the second direction Y. The first shielding electrode 321 can be electrically connected to the first voltage line 31 through the twenty-third via V23. The positive projection of the first shielding electrode 321 on the substrate can cover the positive projection of the second connection electrode 302 on the substrate. Since the second connection electrode 302 is connected to the second area of ​​the first active layer of the first pixel circuit, the first area of ​​the second active layer, the gate of the third transistor and the first plate of the storage capacitor, the second connection electrode 302 can serve as the first node of the first pixel circuit. The first shielding electrode 321 is electrically connected to the first voltage line 31, and can realize the transmission of a constant first voltage signal. By shielding the influence of other signals in the first pixel circuit on the first node, it can avoid other signals (such as data voltage jump) from affecting the voltage of the first node of the first pixel circuit, and can improve the display effect.

[0196] In some examples, the second shielding electrode 322 can be shaped substantially like a zigzag line extending along the second direction Y. The second shielding electrode 322 can be electrically connected to the second voltage line 32 through the twenty-sixth via V26. The orthographic projection of the second shielding electrode 322 on the substrate can cover the orthographic projection of the sixth connection electrode 306 on the substrate. The second shielding electrode 322 can shield the first node of the inactive pixel circuit from the effects of other signals in the inactive pixel circuit.

[0197] In some examples, a third voltage line 33 may be provided between adjacent cell rows. The third voltage line 33 may be shaped like a zigzag line with a main portion extending along the first direction X. The third voltage line 33 may be located on one side of the twelfth connecting electrode 312 and the fourteenth connecting electrode 314 in the second direction Y. A plurality of first connection blocks 33-1 may be provided on the side of the third voltage line 33 away from the twelfth connecting electrode 312 and the fourteenth connecting electrode 314. The first connection blocks 33-1 may be generally rectangular in shape. The first end of each first connection block 33-1 is connected to the third voltage line 33, and the second end may extend into a circuit cell along the second direction Y. The plurality of first connection blocks 33-1 may be spaced apart along the first direction X. The plurality of first connection blocks 33-1 and the third connection line 33 may be interconnected as an integral structure. The first connection block 33-1 may be configured to subsequently be electrically connected to a fourth voltage line extending along the second direction Y. In this example, the provision of the third voltage line forms a transverse transmission path for the second voltage signal.

[0198] (9) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the sixth insulating film is patterned using a patterning process to form the sixth insulating layer. The sixth insulating layer of each circuit unit can be provided with a plurality of vias. In some examples, the sixth insulating layer can also be referred to as a second planar layer.

[0199] Figure 13 is a schematic plan view of the display substrate after the sixth insulating layer is formed in Figure 5. In some examples, as shown in Figure 13, the plurality of vias of the first circuit unit may include at least a 31st via V31, a 32nd via V32, and a 33rd via V33. The plurality of vias of the second circuit unit may include at least a 34th via V34, a 35th via V35, and a 36th via V36. The sixth insulating layer within the 31st through 36th vias V31 to V36 may be removed, exposing a portion of the surface of the fourth conductive layer.

[0200] (10) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the fifth conductive film is patterned using a patterning process to form a fifth conductive layer disposed on the sixth insulating layer. In some examples, the fifth conductive layer may also be referred to as a third source / drain metal layer.

[0201] Figure 14A is a schematic plan view of the display substrate after the fifth conductive layer is formed in Figure 5. Figure 14B is a schematic view of the fifth conductive layer in Figure 14A. In some examples, as shown in Figures 14A and 14B, the fifth conductive layer of the first circuit unit may include at least a fifteenth connecting electrode 315, a fourth voltage line 34, and a first data line 36. The fifth conductive layer of the second circuit unit may include at least a sixteenth connecting electrode 316, a fourth voltage line 34, and an inactive data line 35.

[0202] In some examples, the shape of the fifteenth connection electrode 315 can be substantially rectangular, and the corners of the rectangle can be chamfered. The fifteenth connection electrode 315 can be electrically connected to the twelfth connection electrode 312 through the thirty-third via hole V33 to achieve electrical connection with the second region of the sixth active layer of the first pixel circuit.

[0203] In some examples, the shape of the sixteenth connection electrode 316 can be substantially rectangular, and the corners of the rectangle can be chamfered. The sixteenth connection electrode 315 can be electrically connected to the fourteenth connection electrode 314 through the thirty-sixth via hole V36 to achieve electrical connection with the second region of the sixth active layer of the inactive pixel circuit.

[0204] In some examples, the shape of the fourth voltage line 34 can be roughly a zigzag shape with the main portion extending along the second direction Y. The fourth voltage line 34 in the first circuit unit can be electrically connected to the first connection block 33-1 through the thirty-first via V31, thereby achieving electrical connection with the third voltage line 33. The fourth voltage line 34 in the second circuit unit can be electrically connected to the first connection block 33-1 through the thirty-fourth via V34, thereby achieving electrical connection with the third voltage line 33. In this example, the third voltage line 33 extending along the first direction X and the fourth voltage line 34 extending along the second direction Y of the main portion are interconnected to form a mesh structure for transmitting the second voltage signal. This can not only effectively reduce the transmission voltage drop of the second voltage signal, but also improve the uniformity of the second voltage signal in the display substrate.

[0205] In some examples, the shape of the first data line 36 can be substantially a zigzag shape with a main portion extending along the second direction Y. The first data line 36 can be electrically connected to the eleventh connection electrode 311 through the thirty-second via hole V32 to achieve electrical connection with the fourth transistor of the first pixel circuit, and is configured to provide a data signal to the first pixel circuit.

[0206] In some examples, the shape of the invalid data line 35 can be roughly a strip structure with a main portion extending along the second direction Y. In a unit column where the second circuit unit is located, multiple invalid data lines 35 can be arranged in sequence along the second direction Y. A first break K1 is provided between adjacent invalid data lines 35. The invalid data line 35 can have a first end 351 and a second end 352. The first end 351 of the invalid data line 35 can be electrically connected to the fourth transistor of the invalid pixel circuit through the thirty-fifth via V35 in a second circuit unit, and the second end 352 can extend in the opposite direction of the second direction Y to an adjacent second circuit unit. The first end 351 and the second end 352 of the invalid data line 35 can be adjacent to different scan lines. For example, the first end 351 of an invalid data line 35 is adjacent to the scan line GL(m+1), and the second end is adjacent to the scan line GL(m).

[0207] In some examples, a first break K1 is provided between the first end 351 of an invalid data line 35 and the second end 352 of an adjacent invalid data line 35. For example, the orthographic projection of the scan line GL(m) on the substrate may pass through the first break K1. The length of the main portion of the scan line GL(m) along the second direction Y may be less than the length of the first break K1 along the second direction Y. By providing the first break K1, the orthographic projection of the invalid data line 35 on the substrate does not overlap with the orthographic projection of the scan line on the substrate (as shown by the dotted box in FIG. 14A ).

[0208] In this example, the invalid data line 35 can be electrically connected to the second voltage line 32 transmitting the first voltage signal via the thirteenth connecting electrode 313 and the seventh connecting electrode 307, thereby preventing floating wiring from affecting circuit stability. Furthermore, a first break is provided between adjacent invalid data lines 35, disconnecting the invalid data line at the scan line location. This reduces overlap between the scan line and the invalid data line of the invalid pixel circuit within the second circuit unit, thereby reducing the load on the scan line and helping to improve lateral display defects on the display substrate. Because the invalid pixel circuit is not electrically connected to any light-emitting element, its connection to the second voltage line via the invalid data line does not affect the normal display of the display substrate.

[0209] At this point, a driving circuit layer can be formed in the first display area of ​​the display substrate. For example, the driving circuit layer may include: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, and a fifth conductive layer disposed on the substrate. In some examples, after forming the fifth conductive layer, the second display area may include the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer stacked on the substrate.

[0210] (11) Forming a seventh insulating layer and a first connecting layer. In some examples, a seventh insulating film is coated on the substrate on which the aforementioned pattern is formed, and the seventh insulating film is patterned using a patterning process to form a seventh insulating layer; then, a first transparent conductive film is deposited, and the first transparent conductive film is patterned using a patterning process to form a first connecting layer disposed on the seventh insulating layer. The seventh insulating layer of each circuit unit may be provided with a via. In some examples, the seventh insulating layer may also be referred to as a third planar layer.

[0211] Figure 15 is a schematic plan view of the display substrate after forming the seventh insulating layer in Figure 5. In some examples, as shown in Figure 15, the via holes of the first circuit unit may include at least a forty-first via hole V41. The via holes of the second circuit unit may include at least a forty-second via hole V42.

[0212] FIG16A is a schematic plan view of the display substrate after the first connection layer is formed in FIG5 . FIG16B is a schematic view of the first connection layer in FIG16 . In some examples, as shown in FIG16A and FIG16B , the first connection layer of the first circuit unit may include at least a first anode connection electrode 401. The first connection layer of the second circuit unit may include at least a first ineffective connection electrode 402. The first anode connection electrode 401 may be electrically connected to the fifteenth connection electrode 315 via a forty-first via hole V41. The first ineffective connection electrode 402 may be electrically connected to the sixteenth connection electrode 316 via a forty-second via hole V42.

[0213] (12) Forming an eighth insulating layer and a second connecting layer. In some examples, an eighth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the eighth insulating film is patterned using a patterning process to form an eighth insulating layer; subsequently, a second transparent conductive film is deposited, and the second transparent conductive film is patterned using a patterning process to form a second connecting layer disposed on the eighth insulating layer. The eighth insulating layer of each circuit unit may be provided with a via. In some examples, the eighth insulating layer may also be referred to as a fourth planar layer.

[0214] Figure 17 is a schematic plan view of the display substrate after the eighth insulating layer is formed in Figure 5. In some examples, as shown in Figure 17, the via holes of the first circuit unit may include at least a forty-third via hole V43. The via holes of the second circuit unit may include at least a forty-fourth via hole V44.

[0215] Figure 18A is a schematic plan view of the display substrate after the second connection layer is formed in Figure 5. Figure 18B is a schematic view of the second connection layer in Figure 18A. In some examples, as shown in Figures 18A and 18B, the second connection layer of the first circuit unit may include at least a second anode connection electrode 403. The second connection layer of the second circuit unit may include at least a second ineffective connection electrode 404. The second anode connection electrode 403 may be electrically connected to the first anode connection electrode 401 through a forty-third via V43. The second ineffective connection electrode 404 may be electrically connected to the first ineffective connection electrode 401 through a forty-fourth via V44.

[0216] (13) Forming a ninth insulating layer, a third connecting layer, and a tenth insulating layer. In some examples, a ninth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the ninth insulating film is patterned using a patterning process to form a ninth insulating layer; then, a third transparent conductive film is deposited, and the third transparent conductive film is patterned using a patterning process to form a third connecting layer disposed on the ninth insulating layer; then, a tenth insulating film is coated, and the tenth insulating film is patterned using a patterning process to form a tenth insulating layer. The ninth insulating layer of each circuit unit may be provided with a via. The tenth insulating layer of each first circuit unit may be provided with a via. In some examples, the ninth insulating layer may also be referred to as a fifth flat layer, and the tenth insulating layer may also be referred to as a sixth flat layer.

[0217] Figure 19 is a schematic plan view of the display substrate after the ninth insulating layer is formed in Figure 5. In some examples, as shown in Figure 19, the via holes of the first circuit unit may include at least a forty-fifth via hole V45. The via holes of the second circuit unit may include at least a forty-sixth via hole V46.

[0218] Figure 20A is a schematic plan view of the display substrate after the third connection layer is formed in Figure 5. Figure 20B is a schematic view of the third connection layer in Figure 20A. In some examples, as shown in Figures 20A and 20B, the third connection layer of the first circuit unit may include at least a third anode connection electrode 405. The third connection layer of the second circuit unit may include at least a third ineffective connection electrode 406. The third anode connection electrode 405 may be electrically connected to the second anode connection electrode 403 via a forty-fifth via hole V45. The third ineffective connection electrode 406 may be electrically connected to the second ineffective connection electrode 404 via a forty-sixth via hole V46.

[0219] FIG21 is a schematic plan view of the display substrate after the tenth insulating layer is formed in FIG5 . In some examples, as shown in FIG21 , the vias of the first circuit unit may include at least a forty-seventh via V47. Since the inactive pixel circuits of the second circuit unit do not need to be electrically connected to the light-emitting element, the tenth insulating layer of the second circuit unit may not have any vias.

[0220] In the second circuit unit of this example, by providing the first invalid connection electrode, the second invalid connection electrode and the third invalid connection electrode, the pattern uniformity of the first connection layer, the second connection layer and the third connection layer can be ensured, which is beneficial to the preparation of the film layer.

[0221] At this point, the conductive connection layer of the display substrate can be formed. The conductive connection layer of this example may include: a first connection layer, a second connection layer, and a third connection layer. In some examples, after forming the tenth insulating layer, the second display area may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, a first connection layer, an eighth insulating layer, a second connection layer, a ninth insulating layer, a third connection layer, and a tenth insulating layer stacked on the substrate. However, this embodiment is not limited to this. In other examples, the conductive connection layer of the display substrate may include one or two connection layers.

[0222] (14) Forming a light-emitting structure layer. In some examples, an anode film is deposited on a substrate forming the aforementioned pattern, and the anode film is patterned using a patterning process to form an anode layer; subsequently, a pixel definition film is coated on the substrate forming the aforementioned pattern, and a pixel definition layer is formed by masking, exposing, and developing processes. The pixel definition layer is formed with a plurality of pixel openings exposing the anode layer (for example, including a first pixel opening OP1, a second pixel opening OP2, a third pixel opening OP3, and a fourth pixel opening OP4 as shown in FIG5 ). Subsequently, an organic light-emitting layer is formed in the aforementioned pixel openings, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned using a patterning process to form a cathode layer, and the cathode layer is electrically connected to the organic light-emitting layer.

[0223] Figure 22A is a plan view schematic diagram of the display substrate after the anode layer is formed in Figure 5. Figure 22B is a schematic diagram of the anode layer in Figure 22A. In some examples, as shown in Figures 22A and 22B, the anode layer of the first display area may include: multiple anodes (e.g., a first anode 411, a second anode 412, a third anode 413, and a fourth anode 414). The first anode 411 can be electrically connected to the first pixel circuit in the M-th row, N+2 column circuit unit; the second anode 412 can be electrically connected to the first pixel circuit in the M+1-th row, N+2 column circuit unit; the third anode 413 can be electrically connected to the first pixel circuit in the M-th row, N column circuit unit; and the fourth anode 414 can be electrically connected to the first pixel circuit in the M-th row, N+3 column circuit unit. The inactive pixel circuit in the second circuit unit is not electrically connected to the anode of the light-emitting element.

[0224] In some examples, the orthographic projection of the anode layer on the substrate can cover the orthographic projection of the first fracture on the substrate. Using the anode layer to block the first fracture can improve the appearance visibility and avoid affecting the appearance visual uniformity.

[0225] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The fifth to tenth insulating layers can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer can be made of a reflective material such as metal, and the cathode layer can be made of a transparent conductive material. However, this embodiment is not limited to this.

[0226] The structure of the display substrate and its fabrication process in this embodiment are merely illustrative. In some examples, the structure can be modified and patterning processes can be added or removed based on actual needs. For example, the fourth or fifth insulating layer can be omitted, or the number of conductive connection layers can be reduced. This embodiment is not limited to these.

[0227] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to realize, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0228] The display substrate provided in this example can reduce the overlapping area between the invalid data lines connected to the invalid pixel circuit and the scan line by setting a first break between adjacent invalid data lines in the first display area, where the first break corresponds to the position of the scan line, and electrically connecting the invalid data line to the second voltage line that transmits the first voltage signal, thereby reducing the load on the scan line and helping to improve the lateral display defects of the display substrate.

[0229] In some examples, the load of the scan line in this example may be approximately 10.146fF. In a solution without only breaking the invalid data line, the load of the scan line may be approximately 10.157fF. This example can reduce the load of the scan line to a certain extent.

[0230] Figure 23 is another partial schematic plan view of the driving circuit layer of the first display area of ​​the display substrate according to at least one embodiment of the present disclosure. Figure 24A is a schematic plan view of the display substrate after the third conductive layer is formed in Figure 23. Figure 24B is a schematic diagram of the third conductive layer in Figure 24A. Figure 25A is a schematic plan view of the display substrate after the fourth conductive layer is formed in Figure 23. Figure 25B is a schematic diagram of the fourth conductive layer in Figure 25A.

[0231] In some examples, as shown in Figures 23 to 26, the driving circuit layer of the first display area may include at least: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, and a fifth conductive layer, disposed on a substrate. The description of the semiconductor layer to the third insulating layer of the driving circuit layer of this example can refer to the description of the previous embodiment, and thus is not repeated here.

[0232] In some examples, as shown in Figures 24A and 24B, the third conductive layer of the first circuit unit may include at least: a plurality of connection electrodes of the first pixel circuit (for example, a first connection electrode 301, a second connection electrode 302, a third connection electrode 303, and a fourth connection electrode 304), and a first voltage line 31. The third conductive layer of the second circuit unit may include at least: a plurality of connection electrodes of the inactive pixel circuit (for example, a fifth connection electrode 305, a sixth connection electrode 306, a seventh connection electrode 307, and an eighth connection electrode 308), and a second voltage line 32. The seventh connection electrode 307 is independently provided and not connected to the second voltage line 32.

[0233] In some examples, as shown in Figures 25A and 25B, the fourth conductive layer of the first circuit unit may include at least: a plurality of connection electrodes of the first pixel circuit (for example, including the eleventh connection electrode 311 and the twelfth connection electrode 312), and a first shielding electrode 321 of the first pixel circuit. The fourth conductive layer of the second circuit unit may include at least: a plurality of connection electrodes of the inactive pixel circuit (for example, including the thirteenth connection electrode 313 and the fourteenth connection electrode 314), and a second shielding electrode 322 of the inactive pixel circuit.

[0234] In some examples, a third voltage line 33 may be provided between adjacent cell rows. The third voltage line 33 may be shaped like a zigzag line with a main portion extending along the first direction X. A plurality of first connection blocks 33-1 and a plurality of second connection blocks 33-2 may be provided on a side of the third voltage line 33 away from the twelfth connection electrode 312 and the fourteenth connection electrode 314. The first connection blocks 33-1 and the second connection blocks 33-2 may be spaced apart along the first direction X. The first end of the second connection block 33-2 is connected to the third voltage line 33, and the second end extends along the second direction Y into a second circuit unit and is connected to the thirteenth connection electrode 313. The third voltage line 33, the first connection block 33-1, the second connection block 33-2, and the thirteenth connection electrode 313 may be an integrated structure connected to each other. Since the thirteenth connection electrode 313 is electrically connected to the fourth transistor of the deactivated pixel circuit, the fourth transistor of the deactivated pixel circuit can receive the second voltage signal by electrically connecting the thirteenth connection electrode 313 to the third voltage line 33.

[0235] In some examples, as shown in FIG23 , the fifth conductive layer of the first circuit unit may include at least a fourth voltage line 34 and a first data line 36. The fifth conductive layer of the second circuit unit may include at least a fourth voltage line 34 and an invalid data line 35. In a cell column where the second circuit unit is located, multiple invalid data lines 35 may be arranged sequentially along the second direction Y. A first break is provided between adjacent invalid data lines 35 (as indicated by the dotted line in FIG23 ).

[0236] In this example, the invalid data line 35 can be electrically connected to the thirteenth connection electrode 313 to achieve electrical connection to the third voltage line 33 and receive the second voltage signal. A first break is provided between adjacent invalid data lines 35, so that the invalid data line is disconnected at the scan line position. This can reduce overlap between the scan line and the invalid data line of the invalid pixel circuit in the second circuit unit, thereby reducing the load on the scan line and helping to improve lateral display defects of the display substrate.

[0237] The remaining structures of the display substrate of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0238] Figure 26 is another partial schematic plan view of the driving circuit layer in the first display area of ​​the display substrate of at least one embodiment of the present disclosure. Figure 27A is a schematic plan view of the display substrate after the third conductive layer is formed in Figure 26. Figure 27B is a schematic diagram of the third conductive layer in Figure 27A. Figure 28 is a schematic plan view of the display substrate after the fourth conductive layer is formed in Figure 26.

[0239] In some examples, as shown in Figures 26 to 28, the driving circuit layer of the first display area may include at least: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, and a fifth conductive layer, disposed on a substrate. The description of the semiconductor layer to the third insulating layer of the driving circuit layer of this example can be referred to the description of the previous embodiment, and thus will not be repeated here.

[0240] In some examples, as shown in Figures 27A and 27B, the third conductive layer of the first circuit unit may include at least: a plurality of connection electrodes of the first pixel circuit (for example, including the first connection electrode 301, the second connection electrode 302, the third connection electrode 303, and the fourth connection electrode 304), and a first voltage line 31. The third conductive layer of the second circuit unit may include at least: a plurality of connection electrodes of the inactive pixel circuit (for example, including the fifth connection electrode 305, the seventh connection electrode 307, the eighth connection electrode 308, the ninth connection electrode 309, and the tenth connection electrode 310), and a second voltage line 32.

[0241] In some examples, the ninth connecting electrode 309 can be electrically connected to the first region of the second active layer of the invalid pixel circuit; the tenth connecting electrode 310 can be electrically connected to the first plate of the storage capacitor of the invalid pixel circuit. The ninth connecting electrode 309 and the tenth connecting electrode 310 can be electrically connected to the second voltage line 32. For example, the ninth connecting electrode 309, the tenth connecting electrode 310 and the second voltage line 32 can be an integrated structure connected to each other. The ninth connecting electrode 309 can be located on the side of the scan line GL(m) in the opposite direction of the second direction Y, and the tenth connecting electrode 310 can be located on the side of the scan line GL(m) in the second direction Y. The orthographic projections of the ninth connecting electrode 309 and the tenth connecting electrode 310 on the substrate do not overlap with the orthographic projections of the scan line GL(m) on the substrate.

[0242] In some examples, as shown in FIG28 , the fourth conductive layer of the first circuit unit may include at least: a plurality of connecting electrodes of the first pixel circuit (for example, including the eleventh connecting electrode and the twelfth connecting electrode), and a first shielding electrode 321 of the first pixel circuit. The fourth conductive layer of the second circuit unit may include at least: a plurality of connecting electrodes of the invalid pixel circuit (for example, including the thirteenth connecting electrode and the fourteenth connecting electrode), and a second shielding electrode 322 of the invalid pixel circuit. A third voltage line 33 may be provided between adjacent unit rows. The description of the fourth conductive layer of this example can refer to the description of the embodiment shown in FIG5 , so it will not be repeated here.

[0243] In some examples, as shown in FIG26 , the fifth conductive layer of the first circuit unit may include at least a fourth voltage line 34 and a first data line 36. The fifth conductive layer of the second circuit unit may include at least a fourth voltage line 34 and an invalid data line 35. The fourth voltage line 34, the first data line 36, and the invalid data line 35 may all extend along the second direction Y. The orthographic projection of the invalid data line 35 on the substrate may overlap with the orthographic projection of the scan line on the substrate.

[0244] In the second circuit unit of this example, the connection electrodes electrically connected to the first node of the inactive pixel circuit are distributed on both sides of the scan line to avoid overlapping with the scan line. This reduces the overlap area between the inactive pixel circuit and the scan line, thereby lowering the load on the scan line and helping to improve lateral display defects on the display substrate. In some examples, the load on the scan line of this example can be approximately 9.8735 fF, which can reduce the load on the scan line compared to traditional designs.

[0245] In other examples, based on the structure of the display substrate of this example, the invalid data line located in the fifth conductive layer may not overlap with the positive projection of the scanning line on the substrate. For example, the invalid data line may be electrically connected to the second voltage line (as shown in the embodiment of Figure 5) or the third voltage line (as shown in the embodiment of Figure 23).

[0246] The rest of the structure and preparation process of the display substrate of this example can be referred to the description of the aforementioned embodiment, so they will not be described again here.

[0247] Figure 29 is another partial schematic plan view of the driving circuit layer in the first display region of a display substrate according to at least one embodiment of the present disclosure. Figure 29 only illustrates the semiconductor layer and the first conductive layer, omitting the remaining film layers. Figure 30 is a schematic view of the first conductive layer in Figure 29.

[0248] In some examples, as shown in Figures 29 and 30, the first conductive layer of the first circuit unit may include at least: the gates of multiple transistors of the first pixel circuit (for example, the gates of the first transistor 11 to the sixth transistor 16 of the first pixel circuit in the current row and the gate of the seventh transistor of the first pixel circuit in the previous row), as well as the first plate 181 of the storage capacitor, a first reset control line (for example, the first reset control line RST1(m) or RST1(m+1)), a scan line (for example, the scan line GL(m) or GL(m+1)), and an emission control line (for example, the emission control line EML(m) or EML(m+1)). In some examples, within the first circuit unit, a first protrusion 191 and a second protrusion 192 may be provided on a side of the scan line GL(m) away from the first reset control line RST1(m). The second transistor 12 of the first pixel circuit has a dual-gate structure.

[0249] In some examples, the first conductive layer of the second circuit unit may include at least: gates of multiple transistors of the invalid pixel circuit (for example, the gates of the first transistor 21 to the sixth transistor 26 of the invalid pixel circuit in the current row, the first plate 281 of the storage capacitor, and the gate of the seventh transistor 27 of the invalid pixel circuit in the previous row), a first reset control line (for example, the first reset control line RST1(m) or RST1(m+1)), a scan line (for example, the scan line GL(m) or GL(m+1)), and a light-emitting control line (for example, the light-emitting control line EML(m) or EML(m+1)). In the second circuit unit, no protrusion is provided on the side of the scan line GL(m) away from the first reset control line RST1(m). The second transistor 22 of the invalid pixel circuit has a single-gate structure. The length of the gate of the fourth transistor 24 of the invalid pixel circuit along the second direction Y may be less than the length of the gate of the fourth transistor 14 of the first pixel circuit along the second direction Y.

[0250] The display substrate of this example reduces the parasitic capacitance of the scan lines in the second circuit unit by reducing their dimensions, thereby lowering the load on the scan lines and helping to improve lateral display defects on the display substrate. In some examples, the load on the scan lines of this example can be approximately 8.9955 fF, which is significantly lower than conventional designs.

[0251] In other examples, the load on the scan line can be reduced by setting only the length of the gate of the fourth transistor 24 of the inactive pixel circuit along the second direction Y to be shorter than the length of the gate of the fourth transistor 14 of the first pixel circuit along the second direction Y. Alternatively, the load on the scan line can be reduced by setting only the second transistor 12 of the first pixel circuit to a dual-gate structure and the second transistor 22 of the inactive pixel circuit to a single-gate structure.

[0252] In other examples, the display substrate of this example can be combined with the design of the aforementioned embodiment. For example, based on the display substrate of this example, the invalid data line of the invalid pixel circuit does not overlap with the scan line and is electrically connected to the second voltage line or the third voltage line.

[0253] The rest of the structure and preparation process of the display substrate of this example can be referred to the description of the aforementioned embodiment, so they will not be described again here.

[0254] Figure 31 is another partial schematic plan view of the driving circuit layer of the first display region of the display substrate of at least one embodiment of the present disclosure. Figure 31 illustrates the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer, with the remaining film layers omitted.

[0255] In some examples, as shown in FIG31 , the second transistor of the first pixel circuit of the first circuit unit has a dual-gate structure. The second transistor 22 of the inactive pixel circuit of the second circuit unit has a single-gate structure. The length of the gate of the fourth transistor 24 of the inactive pixel circuit along the second direction Y can be less than the length of the gate of the fourth transistor of the first pixel circuit along the second direction Y.

[0256] In some examples, as shown in FIG31 , the third conductive layer of the second circuit unit may include at least: a ninth connecting electrode 309 and a tenth connecting electrode 310 of the inactive pixel circuit, and a second voltage line 32. The ninth connecting electrode 309 may be electrically connected to the first region of the second active layer of the inactive pixel circuit; the tenth connecting electrode 310 may be electrically connected to the first plate of the storage capacitor of the inactive pixel circuit. The ninth connecting electrode 309 and the tenth connecting electrode 310 may be electrically connected to the second voltage line 32. The ninth connecting electrode 309 may be located on a side of the scan line GL(m) in the opposite direction of the second direction Y, and the tenth connecting electrode 310 may be located on a side of the scan line GL(m) in the second direction Y. The orthographic projections of the ninth connecting electrode 309 and the tenth connecting electrode 310 on the substrate do not overlap with the orthographic projection of the scan line GL(m) on the substrate.

[0257] In the second circuit unit of this example, the connection electrodes electrically connected to the first node of the inactive pixel circuit are distributed on both sides of the scan line to avoid overlapping with the scan line, thereby reducing the overlap area between the inactive pixel circuit and the scan line. Furthermore, by reducing the size of the scan line in the second circuit unit, the parasitic capacitance of the scan line is reduced, thereby reducing the load on the scan line and helping to improve lateral display defects on the display substrate. In some examples, the load on the scan line of this example can be approximately 8.7025 fF, which can reduce the load on the scan line compared to traditional designs.

[0258] In other examples, the display substrate of this example can be combined with the design of the aforementioned embodiment. For example, based on the display substrate of this example, the invalid data line of the invalid pixel circuit does not overlap with the scan line and is electrically connected to the second voltage line or the third voltage line.

[0259] The rest of the structure and preparation process of the display substrate of this example can be referred to the description of the aforementioned embodiment, so they will not be described again here.

[0260] Figure 32 is another partial schematic plan view of the driving circuit layer in the first display area of ​​the display substrate according to at least one embodiment of the present disclosure. Figure 33A is a schematic plan view of the display substrate after the third conductive layer is formed in Figure 32. Figure 33B is a schematic view of the third conductive layer in Figure 33A. Figure 34 is a schematic view of the fourth conductive layer in Figure 32.

[0261] In some examples, as shown in Figures 32 to 34, the driving circuit layer of the first display area may include at least: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, and a fifth conductive layer, disposed on a substrate. The description of the semiconductor layer to the third insulating layer of the driving circuit layer of this example can be referred to the description of the previous embodiment, and thus will not be repeated here.

[0262] In some examples, as shown in Figures 33A and 33B, the third conductive layer of the first circuit unit may include at least: the third conductive layer of the first circuit unit may include at least: a plurality of connection electrodes of the first pixel circuit (for example, including the first connection electrode 301, the second connection electrode 302, the third connection electrode 303, and the fourth connection electrode 304), and the first voltage line 31. The third conductive layer of the second circuit unit may include at least: a plurality of connection electrodes of the inactive pixel circuit (for example, including the fifth connection electrode 305, the seventh connection electrode 307, the eighth connection electrode 308, the ninth connection electrode 309, and the tenth connection electrode 310), and the second voltage line 32.

[0263] In some examples, the ninth connecting electrode 309 can be electrically connected to the first region of the second active layer of the invalid pixel circuit; the tenth connecting electrode 310 can be electrically connected to the first plate of the storage capacitor of the invalid pixel circuit. The ninth connecting electrode 309 and the tenth connecting electrode 310 can be electrically connected to the second voltage line 32. For example, the ninth connecting electrode 309, the tenth connecting electrode 310 and the second voltage line 32 can be an integrated structure connected to each other. The ninth connecting electrode 309 can be located on the side of the scan line GL(m) in the opposite direction of the second direction Y, and the tenth connecting electrode 310 can be located on the side of the scan line GL(m) in the second direction Y. The orthographic projections of the ninth connecting electrode 309 and the tenth connecting electrode 310 on the substrate do not overlap with the orthographic projections of the scan line GL(m) on the substrate.

[0264] In some examples, as shown in Figures 32 and 34, the fourth conductive layer of the first circuit unit may include at least: multiple connection electrodes of the first pixel circuit (for example, including the eleventh connection electrode and the twelfth connection electrode), and a first shielding electrode 321 of the first pixel circuit. The fourth conductive layer of the second circuit unit may include at least: multiple connection electrodes of the inactive pixel circuit (for example, including the thirteenth connection electrode and the fourteenth connection electrode), and a third shielding electrode 323 and a fourth shielding electrode 324 of the inactive pixel circuit.

[0265] In some examples, within the second circuit unit, the third shielding electrode 323 is connected to the thirteenth connecting electrode 313 to achieve connection with the third voltage line 33. The third shielding electrode 323, the thirteenth connecting electrode 313, the second connecting block 33-2, and the third voltage line 33 can be an integrated structure connected to each other. The orthographic projection of the third shielding electrode 323 on the substrate can cover the orthographic projection of the ninth connecting electrode 309 on the substrate, and the orthographic projection of the third shielding electrode 323 on the substrate does not overlap with the orthographic projection of the scan line GL(m) on the substrate.

[0266] In some examples, within the second circuit unit, the fourth shielding electrode 324 can be electrically connected to the second voltage line 32 through a via. The orthographic projection of the fourth shielding electrode 324 on the substrate can cover the orthographic projection of the tenth connection electrode 310 on the substrate, and the orthographic projection of the fourth shielding electrode 324 on the substrate does not overlap with the orthographic projection of the scan line GL(m) on the substrate. The fourth shielding electrode 324 can shield

[0267] In this example, the ninth and tenth connecting electrodes electrically connected to the first node of the inactive pixel circuit are arranged on either side of the scan line to avoid overlapping with the scan line. The third and fourth shielding electrodes, which shield the first node of the inactive pixel circuit, are arranged on either side of the scan line to avoid overlapping with the scan line. This reduces the overlap area between the inactive pixel circuit and the scan line, thereby lowering the load on the scan line and helping to improve lateral display defects on the display substrate. In some examples, the load on the scan line of this example can be approximately 9.607 fF, which reduces the load on the scan line compared to conventional designs.

[0268] In other examples, based on the structure of the display substrate of this example, the invalid data line located in the fifth conductive layer may not overlap with the positive projection of the scanning line on the substrate. For example, the invalid data line may be electrically connected to the second voltage line (as shown in the embodiment of Figure 5) or the third voltage line (as shown in the embodiment of Figure 23).

[0269] The rest of the structure and preparation process of the display substrate of this example can be referred to the description of the aforementioned embodiment, so they will not be described again here.

[0270] Figure 35 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 35 , this embodiment provides a display device comprising: a display substrate 91; and a sensor 92 located on the light-emitting side (non-display side) of the display structure layer, away from the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 overlaps with the second display area A2.

[0271] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be any product or component with a display function, such as an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, etc., but the embodiments of the present disclosure are not limited thereto.

[0272] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: A substrate including a first display area; The driving circuit layer is located in the first display area, and includes: a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns; the plurality of circuit units at least include: a plurality of first circuit units and a plurality of second circuit units; the first circuit unit includes: a first pixel circuit and a scan line electrically connected to the first pixel circuit and extending along a first direction and a first data line extending along a second direction; at least one of the second circuit units includes: an invalid pixel circuit and the scan line electrically connected to the invalid pixel circuit and an invalid data line extending along the second direction; the first direction intersects with the second direction; a light emitting structure layer, located on a side of the driving circuit layer away from the substrate, comprising a plurality of first light emitting elements located in the first display area, at least one of the first pixel circuits being electrically connected to at least one of the first light emitting elements; The display substrate satisfies at least one of the following: an overlapping area of ​​the scan line with the first pixel circuit in the first circuit unit is larger than an overlapping area with the invalid pixel circuit in the second circuit unit; an overlapping area of ​​the scan line with the first data line in the first circuit unit is larger than an overlapping area with the invalid data line in the second circuit unit.

2. The display substrate according to claim 1, wherein: The orthographic projections of the scan line and the invalid data line in the second circuit unit on the substrate do not overlap.

3. The display substrate according to claim 2, wherein: In a unit column where the second circuit unit is located, multiple invalid data lines are arranged in sequence along the second direction, a first break is set between adjacent invalid data lines in the second direction, and the length of the scan line along the second direction is less than the length of the first break along the second direction.

4. The display substrate according to any one of claims 1 to 3, wherein: The invalid data line in the second circuit unit is electrically connected to a second voltage line extending along the second direction and transmitting a first voltage signal.

5. The display substrate according to claim 4, wherein: In a direction perpendicular to the display substrate, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged on the substrate; The scan line is located in the first conductive layer, the invalid data line and the first data line are located in the fifth conductive layer, and the second voltage line is located in the third conductive layer.

6. The display substrate according to any one of claims 1 to 3, wherein: The invalid data line in the second circuit unit is electrically connected to a third voltage line extending along the first direction and transmitting a second voltage signal.

7. The display substrate according to claim 6, wherein: The driving circuit layer also includes: a fourth voltage line extending along the second direction and transmitting the second voltage signal, the fourth voltage line is located on the side of the third voltage line away from the substrate and is electrically connected to the third voltage line; the invalid data line and the fourth voltage line are in the same layer structure.

8. The display substrate according to claim 7, wherein: In a direction perpendicular to the display substrate, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged on the substrate; The third voltage line is located in the fourth conductive layer, and the invalid data line and the fourth voltage line are located in the fifth conductive layer.

9. The display substrate according to claim 1, wherein: The first pixel circuit and the invalid pixel circuit each include at least: a driving transistor, a data writing transistor and a threshold compensation transistor; the gates of the data writing transistor and the threshold compensation transistor of the first pixel circuit and the invalid pixel circuit are electrically connected to the scanning line; A first electrode of the data writing transistor of the first pixel circuit is electrically connected to the first data line, and a second electrode of the data writing transistor of the first pixel circuit is electrically connected to a first electrode of the driving transistor of the first pixel circuit; a first electrode of the threshold compensation transistor of the first pixel circuit is electrically connected to a gate of the driving transistor of the first pixel circuit, and a second electrode of the threshold compensation transistor of the first pixel circuit is electrically connected to a second electrode of the driving transistor of the first pixel circuit; The first electrode of the data writing transistor of the invalid pixel circuit is electrically connected to the invalid data line, and the second electrode of the data writing transistor of the invalid pixel circuit is electrically connected to the first electrode of the driving transistor of the invalid pixel circuit; the first electrode of the threshold compensation transistor of the invalid pixel circuit is electrically connected to the gate of the driving transistor of the invalid pixel circuit, and the second electrode of the threshold compensation transistor of the invalid pixel circuit is electrically connected to the second electrode of the driving transistor of the invalid pixel circuit; The display substrate satisfies at least one of the following: the threshold compensation transistor of the first pixel circuit is a dual-gate structure, and the threshold compensation transistor of the invalid pixel circuit is a single-gate structure; the length of the gate of the data writing transistor of the first pixel circuit along the second direction is greater than the length of the gate of the data writing transistor of the invalid pixel circuit along the second direction.

10. The display substrate according to claim 9, wherein: The gates of the data writing transistors and the threshold compensation transistors of the first pixel circuit and the invalid pixel circuit are connected to the scanning line in an integrated structure.

11. The display substrate according to claim 1, wherein: The first pixel circuit and the invalid pixel circuit both include: a driving transistor, a first reset transistor, a threshold compensation transistor and a storage capacitor; The gate electrode of the driving transistor of the first pixel circuit, the second electrode of the first reset transistor, the first electrode of the threshold compensation transistor and the first electrode plate of the storage capacitor are electrically connected to the second connecting electrode; the orthographic projection of the second connecting electrode on the substrate overlaps with the orthographic projection of the scanning line on the substrate; The gate of the driving transistor of the invalid pixel circuit and the first plate of the storage capacitor are electrically connected to the ninth connecting electrode, the second electrode of the first reset transistor of the invalid pixel circuit and the first electrode of the threshold compensation transistor are electrically connected to the tenth connecting electrode, and the ninth connecting electrode and the tenth connecting electrode are located on both sides of the scanning line and do not overlap with the positive projection of the scanning line on the substrate.

12. The display substrate according to claim 11, wherein: The ninth connection electrode and the tenth connection electrode are both electrically connected to a second voltage line extending along the second direction and transmitting a first voltage signal.

13. The display substrate according to claim 11, wherein: The first pixel circuit further includes: a first shielding electrode, the first shielding electrode is located at a side of the second connecting electrode away from the substrate, and the orthographic projection of the first shielding electrode on the substrate covers the orthographic projection of the second connecting electrode on the substrate; The invalid pixel circuit also includes: a second shielding electrode, which is located on a side of the ninth connecting electrode and the tenth connecting electrode away from the substrate, and the orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the ninth connecting electrode and the tenth connecting electrode on the substrate.

14. The display substrate according to claim 11, wherein: The first pixel circuit further includes: a first shielding electrode, the first shielding electrode is located at a side of the second connecting electrode away from the substrate, and the orthographic projection of the first shielding electrode on the substrate covers the orthographic projection of the second connecting electrode on the substrate; The inactive pixel circuit further comprises: a third shielding electrode and a fourth shielding electrode, wherein the third shielding electrode and the fourth shielding electrode are located on a side of the ninth connecting electrode and the tenth connecting electrode away from the substrate; the orthographic projection of the third shielding electrode on the substrate covers the orthographic projection of the ninth connecting electrode on the substrate; The orthographic projection of the substrate covers the orthographic projection of the tenth connecting electrode on the substrate, and the orthographic projections of the third shielding electrode and the fourth shielding electrode on the substrate do not overlap with the orthographic projections of the scanning line on the substrate.

15. The display substrate according to claim 14, wherein: The third shielding electrode is electrically connected to a third voltage line extending along the first direction and transmitting a second voltage signal; the fourth shielding electrode is electrically connected to a second voltage line extending along the second direction and transmitting a first voltage signal, and the first voltage signal is greater than the second voltage signal.

16. The display substrate according to claim 1, wherein: The plurality of circuit units further include: a plurality of second pixel circuits; at least one of the second pixel circuits and the invalid pixel circuit are located in the same unit column; The substrate further includes: a second display area located at least on one side of the first display area; the light emitting structure layer further includes: a plurality of second light emitting elements located in the second display area; At least one of the second pixel circuits is electrically connected to at least one second light-emitting element via a conductive connection line.

17. A display device comprising: A display substrate as claimed in any one of claims 1 to 16, and a sensor located on a non-display surface side of the display substrate; The orthographic projection of the sensor on the display substrate at least partially overlaps with the second display area of ​​the display substrate.

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