Data encryption and decryption method, data encryption and decryption apparatus, device, and medium

Abstract

The present application relates to the technical field of data security, and discloses a data encryption and decryption method, a data encryption and decryption apparatus, a device, and a medium. The method comprises: on the basis of an encryption and decryption algorithm, a field-programmable gate array generating key information comprising an encryption key, a decryption key, and modulus; converting data to be processed into standardized data of a set bit width; on the basis of the effective bits matched with the encryption and decryption algorithm and the set bit width, calculating an optimization algorithm, and determining an exponent bit width and a modulus bit width; and on the basis of the exponent bit width, the modulus bit width, and the key and the modulus which are required by the standardized data, carrying out vector iterative addition and shift operations on the standardized data to obtain encrypted and decrypted data. A bit width is set, so that the compatibility of multiple types of encryption and decryption algorithms is realized. By relying on an exponent bit width and a modulus bit width, the operation of large bit width data is split into the operation of small bit width data by means of unit splitting and layer multiplexing, so that a field-programmable gate array can realize the operation of the large bit width data. Moreover, better system performance and security are achieved.

Description

Data encryption and decryption method, device, equipment and medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on June 14, 2023, with application number 202310701493.0, and application name “A method, device, equipment and medium for encryption and decryption of data”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of data security technology, and in particular to a method, apparatus, device and medium for encrypting and decrypting data. Background Art

[0004] With the rapid development of the internet and the rapid advancement of the digital economy, data is experiencing explosive growth. As a crucial component of cutting-edge technological development, data security is crucial. Using cryptographic algorithms to encrypt and decrypt data can enhance data security.

[0005] Commonly used cryptographic algorithms include the RSA algorithm. Proposed by Ron Rivest, Adi Shamir, and Leonard Adleman, the RSA algorithm is based on large prime numbers and modular exponentiation. Whether performing encryption or decryption, the RSA algorithm essentially performs modular exponentiation, and the encryption and decryption methods are identical. Commonly used encryption key e and decryption key d lengths include 1024 bits, 2048 bits, and 4096 bits.

[0006] Current computers are unable to directly perform modular exponentiation operations with such large bit widths. Field-Programmable Gate Arrays (FPGAs), as programmable logic devices, contain a rich set of logic gates and triggers, enabling the rapid and convenient construction of various hardware circuits. However, implementing operations such as addition, subtraction, multiplication, and modularization on large bit widths often requires complex wiring, resulting in extremely long compilation times or even compilation failures.

[0007] Summary of the Invention

[0008] The purpose of the embodiments of the present application is to provide a data encryption and decryption method, device, equipment and computer non-volatile readable storage medium, which can ensure that FPGA can perform operations on large bit-width data.

[0009] To solve the above technical problems, an embodiment of the present application provides a data encryption and decryption method, which is applied to a computer configured with a field programmable gate array, and includes:

[0010] Generate key information according to the encryption and decryption algorithm; wherein the key information includes encryption key, decryption key, and modulus;

[0011] Convert the acquired data to be processed into standardized data with a set bit width;

[0012] Determine the exponent bit width and modulus bit width based on the valid bits matched by the encryption and decryption algorithm and the set bit width calculation optimization algorithm;

[0013] Based on the exponent bit width, modulus bit width, and the key and modulus required for the standardized data, vector iterative addition and shift operations are performed on the standardized data to obtain encrypted and decrypted data.

[0014] In some embodiments, determining the exponent bit width and modulus bit width based on the valid bits matched by the encryption and decryption algorithms and the set bit width calculation optimization algorithm includes:

[0015] Setting the most significant bit of the first variable according to the valid bits matched by the encryption and decryption algorithm;

[0016] When the bit width signal is valid, performing multiple bit operations on the data to be measured according to the most significant bit of the first variable to obtain new data to be measured; wherein the data to be measured is an exponent or a modulus;

[0017] The new data to be tested is assigned to the second variable according to the set bit step until the second variable is a non-zero value, then the second variable is permuted according to the permutation rule, and the bit width of the data to be tested is determined based on the permuted second variable and the current first variable.

[0018] In some embodiments, performing multiple bit operations on the data to be tested according to the most significant bit of the first variable to obtain new data to be tested includes:

[0019] Shifting the first variable left in sequence to obtain the shift step length of the data to be measured; wherein the data to be measured is an exponent or a modulus;

[0020] Each time a shift step is obtained, the current data to be tested is right-shifted based on the shift step, and the result of the bitwise OR operation of the current data to be tested and the right-shifted data to be tested is used as the latest current data to be tested, until the most significant bit of the first variable is one, then the latest current data to be tested is output;

[0021] An addition operation is performed on the latest current data to be tested to obtain new data to be tested.

[0022] In some embodiments, assigning the new test data to the second variable according to the set bit step until the second variable is a non-zero value includes:

[0023] Cut off the lower 16 bits of data from the new data to be tested and assign them to the second variable;

[0024] Determine whether the second variable is zero;

[0025] When the second variable is zero, the remaining data after intercepting the lower 16 bits of data is used as new test data, and the step of intercepting the lower 16 bits of data from the new test data and assigning them to the second variable is returned;

[0026] When the second variable is non-zero, the second variable is permuted according to the permutation rule, and the difference between the first variable and the permuted second variable is used as the bit width of the data to be measured.

[0027] In some embodiments, permuting the second variable according to a permutation rule, and determining the bit width of the data to be measured based on the permuted second variable and the current first variable includes:

[0028] Querying a list of correspondences between variable values ​​and replacement values ​​to determine a second replacement value that matches the second variable;

[0029] The difference between the first variable and the second replacement value is used as the bit width of the data to be measured.

[0030] In some embodiments, based on the exponent bit width, the modulus bit width, and the key and modulus required for the normalized data, performing vector iterative addition and shift operations on the normalized data to obtain encrypted and decrypted data includes:

[0031] Determine whether the index is zero;

[0032] When the exponent is zero, the operation of encrypting and decrypting the normalized data using the key is converted into a modular division operation to obtain the encrypted and decrypted data;

[0033] In the case where the exponent is not zero, the operation of encrypting and decrypting the normalized data using the key is converted into a modular multiplication operation;

[0034] According to the exponent bit width and modulus bit width, the modular multiplication operation is split into multiple data addition and shift operations to obtain encrypted and decrypted data.

[0035] In some embodiments, based on the exponent bit width and the modulus bit width, splitting the modular multiplication operation into multiple data addition and shift operations to obtain encrypted and decrypted data includes:

[0036] The modulus data to be analyzed of the modulus bit width is intercepted from the current low bit of the modulus; the exponent data to be analyzed of the exponent bit width is intercepted from the current low bit of the exponent;

[0037] Select a matching operation rule based on the value of the highest bit of the index data to be analyzed;

[0038] Process the index data to be analyzed, the modulus data to be analyzed, and the standardized data according to the operation rules to obtain the operation results;

[0039] Each time an operation result is obtained, the exponent bit width is reduced by one; when the current exponent bit width after reduction by one is not zero, the steps of intercepting the modulus data to be analyzed with the modulus bit width from the current low bit of the modulus and intercepting the exponent data to be analyzed with the exponent bit width from the current low bit of the exponent are returned; when the current exponent bit width after reduction by one is zero, the current operation result is output.

[0040] In some embodiments, the operation rules include a first rule for performing a modular multiplication operation on the data based on a modulus, and a second rule for iterating based on a result of a previous modular multiplication operation;

[0041] Accordingly, based on the value of the highest bit of the index data to be analyzed, the matching operation rules are selected as follows:

[0042] When the highest bit of the index data to be analyzed is zero, the first rule is selected;

[0043] When the highest bit of the index data to be analyzed is not zero, the second rule is selected.

[0044] In some embodiments, processing the index data to be analyzed, the modulus data to be analyzed, and the normalized data according to the operation rules to obtain the operation results includes:

[0045] When the operation rule is the first rule, data addition and shift operations are performed on the normalized data according to the exponential data to be analyzed and the modulus data to be analyzed to obtain an operation result.

[0046] In some embodiments, performing a data addition operation on the normalized data according to the index data to be analyzed and the modulus data to be analyzed includes:

[0047] According to the valid bits matched by the encryption and decryption algorithm, the data addition operation on the normalized data according to the exponential data to be analyzed and the modulus data to be analyzed is split into multiple data addition sub-operations;

[0048] Perform iterative operations on multiple data addition operations.

[0049] In some embodiments, processing the index data to be analyzed, the modulus data to be analyzed, and the normalized data according to the operation rules to obtain the operation results includes:

[0050] When the operation rule is the second rule, data addition and shift operations are performed on the result of the previous modular multiplication operation according to the exponential data to be analyzed and the modulus data to be analyzed to obtain the operation result.

[0051] In some embodiments, performing a data addition operation on the result of the previous modular multiplication operation according to the exponential data to be analyzed and the modular data to be analyzed includes:

[0052] According to the valid bits matched by the encryption and decryption algorithm, the data addition operation on the result of the previous modular multiplication operation based on the exponential data to be analyzed and the modulus data to be analyzed is split into multiple data addition sub-operations;

[0053] Perform iterative operations on multiple data addition operations.

[0054] In some embodiments, after performing vector iterative addition and shift operations on the normalized data based on the exponent bit width, the modulus bit width, and the key and modulus required for the normalized data to obtain encrypted and decrypted data, the method further includes:

[0055] The encrypted and decrypted data are converted into data adapted to the bit width of the double rate synchronous dynamic random access memory, and the converted data are written into the double rate synchronous dynamic random access memory.

[0056] In some embodiments, after performing vector iterative addition and shift operations on the normalized data based on the exponent bit width, the modulus bit width, and the key and modulus required for the normalized data to obtain encrypted and decrypted data, the method further includes:

[0057] An interrupt signal is sent to the host computer so that the host computer can read data from the double rate synchronous dynamic random access memory after receiving the interrupt signal.

[0058] In some embodiments, generating key information according to an encryption / decryption algorithm includes:

[0059] Generate multiple random numbers using a stream cipher algorithm;

[0060] Select the first and second largest prime numbers from multiple random numbers;

[0061] Based on the first largest prime number and the second largest prime number, determine the modulus and the Euler function value of the modulus;

[0062] The coprime number of the Euler function value is used as the encryption key, and the decryption key is obtained by taking the modular inverse of the encryption key.

[0063] In some embodiments, selecting the first largest prime number and the second largest prime number from the plurality of random numbers includes:

[0064] Use the set prime array to screen multiple random numbers to obtain the prime numbers to be tested;

[0065] The prime numbers to be detected are detected according to a randomized algorithm, and the first and second largest prime numbers are screened out from the prime numbers to be detected based on the detection results.

[0066] In some embodiments, converting the acquired data to be processed into standardized data with a set bit width includes:

[0067] The acquired data to be processed is converted into 4096-bit standardized data.

[0068] In some embodiments, further comprising:

[0069] Based on the currently available logical resources and the type of encryption / decryption algorithm, determine the operation mode of executing the steps of executing the effective bits matched according to the encryption / decryption algorithm and the set bit width calculation optimization algorithm, and determine the exponent bit width and modulus bit width; wherein the operation mode includes parallel or cascade.

[0070] The embodiment of the present application also provides a data encryption and decryption device, which is applied to a computer, wherein the computer is configured with a field programmable gate array, and the device includes a generation unit, a conversion unit, a determination unit, and an operation unit;

[0071] A generating unit, configured to generate key information according to an encryption and decryption algorithm; wherein the key information includes an encryption key, a decryption key, and a modulus;

[0072] A conversion unit, configured to convert the acquired data to be processed into standardized data of a set bit width;

[0073] A determination unit, configured to determine the exponent bit width and modulus bit width based on the valid bits matched by the encryption and decryption algorithm and the set bit width calculation optimization algorithm;

[0074] The operation unit is used to perform vector iterative addition and shift operations on the standardized data based on the exponent bit width, the modulus bit width, and the key and modulus required for the standardized data to obtain encrypted and decrypted data.

[0075] In some embodiments, the determination unit includes a setting subunit, a bit operation subunit, an assignment subunit, and a substitution subunit;

[0076] A setting subunit, configured to set the most significant bit of the first variable according to the valid bits matched by the encryption and decryption algorithm;

[0077] A bit operation subunit is used to perform multiple bit operations on the data to be tested according to the most significant bit of the first variable to obtain new data to be tested when the bit width signal is valid; wherein the data to be tested is an exponent or a modulus;

[0078] an assignment subunit, configured to assign the new test data to the second variable in steps of set bits until the second variable reaches a non-zero value;

[0079] The substitution subunit is used to substitute the second variable according to the substitution rule, and determine the bit width of the data to be measured according to the second variable after substitution and the current first variable.

[0080] In some embodiments, the bit operation subunit is used to sequentially left-shift the first variable to obtain a shift step length of the data to be measured; wherein the data to be measured is an exponent or a modulus;

[0081] Each time a shift step is obtained, the current data to be tested is right-shifted based on the shift step, and the result of the bitwise OR operation of the current data to be tested and the right-shifted data to be tested is used as the latest current data to be tested, until the most significant bit of the first variable is one, then the latest current data to be tested is output;

[0082] An addition operation is performed on the latest current data to be tested to obtain new data to be tested.

[0083] In some embodiments, the assignment subunit is used to intercept the lower 16 bits of data from the new data to be tested and assign them to the second variable;

[0084] Determine whether the second variable is zero;

[0085] When the second variable is zero, the remaining data after intercepting the lower 16 bits of data is used as new test data, and the step of intercepting the lower 16 bits of data from the new test data and assigning them to the second variable is returned;

[0086] When the second variable is non-zero, the second variable is permuted according to the permutation rule, and the difference between the first variable and the permuted second variable is used as the bit width of the data to be measured.

[0087] In some embodiments, the substitution subunit is configured to query a list of correspondences between variable values ​​and substitution values ​​to determine a second substitution value that matches the second variable;

[0088] The difference between the first variable and the second replacement value is used as the bit width of the data to be measured.

[0089] In some embodiments, the operation unit includes a judgment subunit, a first conversion subunit, a second conversion subunit, and a splitting subunit;

[0090] A judgment subunit, used to judge whether the index is zero;

[0091] A first conversion subunit is configured to convert, when the exponent is zero, an operation of encrypting and decrypting the standardized data using the key into a modular division operation to obtain encrypted and decrypted data;

[0092] a second conversion subunit, configured to convert, when the exponent is not zero, an operation of encrypting and decrypting the standardized data using the key into a modular multiplication operation;

[0093] The splitting subunit is used to split the modular multiplication operation into multiple data addition and shift operations according to the exponent bit width and the modulus bit width to obtain encrypted and decrypted data.

[0094] In some embodiments, the splitting subunit is used to intercept the modulus data to be analyzed with the modulus bit width from the current low bit of the modulus; intercept the exponent data to be analyzed with the exponent bit width from the current low bit of the exponent;

[0095] Select a matching operation rule based on the value of the highest bit of the index data to be analyzed;

[0096] Process the index data to be analyzed, the modulus data to be analyzed, and the standardized data according to the operation rules to obtain the operation results;

[0097] Each time an operation result is obtained, the exponent bit width is reduced by one; when the current exponent bit width after reduction by one is not zero, the steps of intercepting the modulus data to be analyzed with the modulus bit width from the current low bit of the modulus and intercepting the exponent data to be analyzed with the exponent bit width from the current low bit of the exponent are returned; when the current exponent bit width after reduction by one is zero, the current operation result is output.

[0098] In some embodiments, the operation rules include a first rule for performing a modular multiplication operation on the data based on a modulus, and a second rule for iterating based on a result of a previous modular multiplication operation;

[0099] Accordingly, the splitting subunit is used to select the first rule when the highest bit of the index data to be analyzed is zero;

[0100] When the highest bit of the index data to be analyzed is not zero, the second rule is selected.

[0101] In some embodiments, the split subunits are used to

[0102] When the operation rule is the first rule, data addition and shift operations are performed on the normalized data according to the exponential data to be analyzed and the modulus data to be analyzed to obtain an operation result.

[0103] In some embodiments, the splitting sub-unit is used to split the data addition operation on the standardized data based on the exponential data to be analyzed and the modulus data to be analyzed into multiple data addition sub-operations according to the valid bits matched by the encryption and decryption algorithm; and perform iterative operations on the multiple data addition sub-operations.

[0104] In some embodiments, the splitting subunit is used to perform data addition and shift operations on the result of the previous modular multiplication operation according to the exponential data to be analyzed and the modulus data to be analyzed to obtain the operation result when the operation rule is the second rule.

[0105] In some embodiments, the splitting sub-unit is used to split the data addition operation on the result of the previous modular multiplication operation based on the exponential data to be analyzed and the modulus data to be analyzed into multiple data addition sub-operations according to the valid bits matched by the encryption and decryption algorithm; and perform iterative operations on the multiple data addition sub-operations.

[0106] In some embodiments, further comprising a storage unit;

[0107] The storage unit is used to convert the encrypted and decrypted data into data adapted to the bit width of the double rate synchronous dynamic random access memory, and write the converted data into the double rate synchronous dynamic random access memory.

[0108] In some embodiments, a sending unit is further included;

[0109] The sending unit is used to perform vector iterative addition and shift operations on the standardized data based on the exponent bit width, the modulus bit width, and the key and modulus required for the standardized data, and after obtaining the encrypted and decrypted data, send an interrupt signal to the host computer so that the host computer can read the data from the double-rate synchronous dynamic random access memory after receiving the interrupt signal.

[0110] In some embodiments, the generating unit includes a random subunit, a screening subunit, a determining subunit, and an acting subunit;

[0111] A random subunit, used for generating multiple random numbers using a stream cipher algorithm;

[0112] a screening subunit, configured to screen out a first largest prime number and a second largest prime number from a plurality of random numbers;

[0113] a determination subunit, configured to determine a modulus and a value of the Euler function of the modulus based on the first largest prime number and the second largest prime number;

[0114] As a subunit, it is used to use the coprime number of the Euler function value as the encryption key, and obtain the decryption key by performing modular inversion on the encryption key.

[0115] In some embodiments, the screening subunit is used to screen multiple random numbers using a set prime group to obtain prime numbers to be detected; detect the prime numbers to be detected according to the randomization algorithm, and screen out the first largest prime number and the second largest prime number from the prime numbers to be detected based on the detection results.

[0116] In some embodiments, the conversion unit is used to convert the acquired data to be processed into 4096-bit standardized data.

[0117] In some embodiments, a mode determination unit is further included;

[0118] A mode determination unit is used to determine the operation mode of executing the steps of determining the exponent bit width and modulus bit width according to the valid bits matched according to the encryption and decryption algorithm and the set bit width calculation optimization algorithm based on the currently available logical resources and the type of encryption and decryption algorithm; wherein the operation mode includes parallel or cascade.

[0119] An embodiment of the present application further provides an electronic device, including:

[0120] memory for storing computer programs;

[0121] A processor is used to execute a computer program to implement the steps of the above-mentioned data encryption and decryption method.

[0122] An embodiment of the present application further provides a computer non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned data encryption and decryption method are implemented.

[0123] It can be seen from the above technical solution that the field programmable gate array generates key information based on the encryption and decryption algorithm; wherein, the key information may include an encryption key, a decryption key, and a modulus; in order to be compatible with different types of encryption and decryption algorithms, the bit width can be set based on the key length of different types of encryption and decryption algorithms, and the acquired data to be processed is converted into standardized data with the set bit width. The encryption and decryption operations of data belong to the operations of large bit width data. In order to enable the field programmable gate array to smoothly implement the operations of large bit width data, the exponent bit width and the modulus bit width can be determined based on the effective bits matched by the encryption and decryption algorithm and the set bit width calculation optimization algorithm. Based on the exponent bit width, the modulus bit width and the key and modulus required for the standardized data, vector iterative addition and shift operations are performed on the standardized data to obtain encrypted and decrypted data. The beneficial effect of the present application is that by setting the bit width, compatibility with multiple types of encryption and decryption algorithms is achieved. By relying on the exponent and modulus bit widths, operations on large-bit-width data can be split into smaller ones through unit splitting and hierarchical reuse. Field-programmable gate arrays (FPGAs) can support small-bit-width operations without complex wiring. By splitting operations, FPGAs can perform operations on large-bit-width data. Furthermore, compared to software-based data encryption and decryption, FPGAs are hardware devices, offering improved system performance and security. BRIEF DESCRIPTION OF THE DRAWINGS

[0124] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0125] FIG1 is a flow chart of a method for encrypting and decrypting data provided by an embodiment of the present application;

[0126] FIG2 is a flow chart of a method for determining exponent bit width and modulus bit width provided in an embodiment of the present application;

[0127] FIG3 is a schematic diagram of a bit width calculation provided in an embodiment of the present application;

[0128] FIG4 is a flow chart of a method for encrypting and decrypting standardized data based on exponent bit width and modulus bit width provided in an embodiment of the present application;

[0129] FIG5 is a schematic diagram of a specific implementation of large bit width operation plus optimization provided by an embodiment of the present application;

[0130] FIG6 is a schematic diagram of an RSA encryption and decryption hardware implementation provided in an embodiment of the present application;

[0131] FIG7 is a schematic diagram of the structure of a data encryption and decryption device provided in an embodiment of the present application;

[0132] FIG8 is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0133] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0134] The terms "including" and "having," as well as any variations thereof, in the specification and claims of this application and the accompanying drawings, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0135] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0136] Next, a data encryption and decryption method provided by an embodiment of the present application is described in detail. FIG1 is a flow chart of a data encryption and decryption method provided by an embodiment of the present application, which is applied to a computer equipped with a field programmable gate array. The method includes:

[0137] S101: Generate key information according to the encryption and decryption algorithm.

[0138] The key information may include an encryption key, a decryption key, and a modulus.

[0139] For ease of description, in the embodiments of the present application, the symbol e may be used to represent an encryption key, d may be used to represent a decryption key, and N may be used to represent a modulus.

[0140] Taking m as plaintext data and c as ciphertext data as an example, the principle of encrypting plaintext data using encryption and decryption algorithms is c=m e (mod N), the principle of decrypting ciphertext data is m=c d (mod N). Therefore, when using encryption and decryption algorithms to perform encryption and decryption operations on data, it is necessary to first obtain the encryption key, decryption key, and modulus.

[0141] In an embodiment of the present application, a stream cipher algorithm can be used to generate multiple random numbers; a first largest prime number and a second largest prime number are screened out from the multiple random numbers; based on the first largest prime number and the second largest prime number, the modulus and the Euler function value of the modulus are determined; the coprime numbers of the Euler function values ​​are used as encryption keys, and the encryption key is modularly inverted to obtain a decryption key.

[0142] For the generation of random numbers, the international standard Grain algorithm of the stream cipher algorithm can be used, and its corresponding hardware structure mainly includes a linear feedback shift register, a nonlinear shift register and an output function.

[0143] According to the prime number theorem, the total number of prime numbers less than N is approximately N / lnN, and the probability that any random number is a prime number is 1 / lnN. If prime number detection is performed directly, the probability is very low.

[0144] Therefore, in an embodiment of the present application, a set prime array can be used to screen multiple random numbers to obtain prime numbers to be detected; the prime numbers to be detected are detected according to the randomization algorithm, and the first largest prime number and the second largest prime number are screened from the prime numbers to be detected based on the detection results.

[0145] The specific process of selecting the first and second largest prime numbers can include: first, using several small prime numbers to screen a large number of random numbers, and then sending them to the prime number detection module. The range of small prime numbers also determines the accuracy of the screening. The screening principle is as follows: p passes k small prime numbers m i (1≤i≤k) screening, k+1 prime numbers m are not passed k+1 Then add p to the product of the first k small prime numbers that have been screened, that is, because Can be m i Divisible by m, p cannot be divided by m i Divisible by m, so the addition cannot be divided by m iSimilarly, after addition, p cannot be divided by m either. k+1 For prime number detection, the Miller-Rabin method can be used. Briefly, for a given prime number n to be detected, a random number a (1 < a < n) is selected, and then n - 1 is expressed in the form of 2^s * d. Calculate a^d mod n. If the result is equal to 1 or n - 1, then n may be a prime number.

[0146] After selecting two large prime numbers p and q, N = p * q can be calculated according to the formula, and N and Calculate the Euler's totient function value of N. Selection of the public key exponent e: Make and It is recommended to use 65537 from the current international integer standard X.509. Finally, the decryption key d can be obtained by taking the modular inverse of the encryption key e.

[0147] S102: Convert the obtained data to be processed into standardized data with a set bit width.

[0148] Commonly used encryption and decryption algorithms include RSA1024, RSA2048, and RSA4096. In the embodiments of this application, to be compatible with different types of encryption and decryption algorithms, the set bit width can be 4096 bits. After obtaining the data to be processed, the data to be processed can be converted into standardized data with 4096 bits.

[0149] In practical applications, the AXI4_lite interface can be used to complete the configuration of various related control registers, that is, record the set bit width in the control register, so as to be compatible with the three types of encryption and decryption algorithms of RSA1024, RSA2048, and RSA4096. <好的,我将按照要求进行翻译。请提供需要翻译的内容。

[0150] [[ID=好的,请提供需要翻译的内容。<26]]S103: Calculate the optimization algorithm according to the effective bit width matched by the encryption and decryption algorithm and the set bit width, and determine the exponent bit width and the modulus bit width.

[0151] Commonly used key lengths are 1024bit, 2048bit, and 4096bit. Using the key for data encryption and decryption operations belongs to large-bit-width data operations. To implement large-bit-width data operations on FPGA requires complex wiring, which causes an extremely long compilation time. And there will be a phenomenon that compilation fails due to unsuccessful wiring.

[0152] Therefore, in the embodiment of the present application, in order to reduce the wiring difficulty and ensure that the FPGA can smoothly perform operations on large-bit-width data, an implementation method of splitting large-bit-width data operations into small-bit-width data operations is adopted. The wiring method corresponding to small-bit-width data operations is simple, and the FPGA can fully meet the wiring requirements of small-bit-width data operations, thereby achieving the purpose of ensuring that the FPGA can smoothly perform large-bit-width data operations.

[0153] Data encryption and decryption operations require the use of exponents and moduli. In order to split large-bit-width data operations into small-bit-width data operations, it is necessary to determine the exponent bit width and modulus bit width corresponding to the small-bit-width data operations.

[0154] The exponent bit width refers to the number of bits of the exponent that is used when performing data encryption and decryption operations, and the modulus bit width refers to the number of bits of the modulus that is used when performing data encryption and decryption operations.

[0155] In practical applications, the values ​​of the exponent bit width and modulus bit width are limited by the effective bits matched by the currently used encryption and decryption algorithm.

[0156] When the encryption and decryption algorithm used is RSA1024, due to 2 10 =1024, so the effective bit corresponding to RSA1024 is 10. When the encryption and decryption algorithm used is RSA2048, due to 2 11 =2048, so the effective bit corresponding to RSA2048 is 11. When the encryption and decryption algorithm used is RSA4096, due to 2 12 =4096, so the effective bit number corresponding to RSA4096 is 12.

[0157] In the embodiment of the present application, a bit width calculation optimization algorithm can be set based on the determination principle of the exponent bit width and the modulus bit width. The exponent bit width and the modulus bit width can be determined according to the effective bits matched by the encryption and decryption algorithm and the set bit width calculation optimization algorithm.

[0158] The principles for determining the exponent bit width and modulus bit width are similar. For example, the exponent bit width can be determined by performing bitwise operations on the exponent using the valid bits matched by the encryption and decryption algorithm. Similarly, the modulus bit width can be determined by performing bitwise operations on the modulus using the valid bits matched by the encryption and decryption algorithm. Therefore, the bit width calculation optimization algorithm can include specific methods for performing bitwise operations on the exponent and modulus.

[0159] In the embodiment of the present application, the exponent bit width and the modulus bit width may be determined in parallel, or may be determined in cascade.

[0160] In actual applications, based on the currently available logical resources and the type of encryption and decryption algorithm, the operation mode of executing the steps of executing the effective bits matched according to the encryption and decryption algorithm and the set bit width calculation optimization algorithm to determine the exponent bit width and modulus bit width can be determined; wherein, the operation mode includes parallel or cascade.

[0161] Based on the currently available logic resources of the FPGA and the type of RSA algorithm, multi-core parallelism can be instantiated and the operation mode can be determined at the same time to improve the overall computing efficiency.

[0162] S104: Based on the exponent bit width, the modulus bit width, and the key and modulus required for the normalized data, perform vector iterative addition and shift operations on the normalized data to obtain encrypted and decrypted data.

[0163] The operation of encrypting and decrypting standardized data using a key is essentially a modular exponentiation operation. In order to reduce the difficulty of the operation, in an embodiment of the present application, the modular exponentiation operation can be converted into a vector iterative addition and shift operation.

[0164] Since the length of the exponent and modulus is relatively long, the encryption and decryption operations on standardized data based on the exponent and modulus belong to operations on large bit-width data. In the embodiment of the present application, depending on the exponent bit width and the modulus bit width, the operations on large bit-width data can be split into operations on small bit-width data, so that the FPGA can smoothly implement the encryption and decryption operations on standardized data.

[0165] When the standardized data is ciphertext data, the key required is the decryption key, and the encrypted and decrypted data finally obtained is plaintext data; when the standardized data is plaintext data, the key required is the encryption key, and the encrypted and decrypted data finally obtained is ciphertext data.

[0166] It can be seen from the above technical solution that the field programmable gate array generates key information based on the encryption and decryption algorithm; wherein, the key information may include an encryption key, a decryption key, and a modulus; in order to be compatible with different types of encryption and decryption algorithms, the bit width can be set based on the key length of different types of encryption and decryption algorithms, and the acquired data to be processed is converted into standardized data with the set bit width. The encryption and decryption operations of data belong to the operations of large bit width data. In order to enable the field programmable gate array to smoothly implement the operations of large bit width data, the exponent bit width and the modulus bit width can be determined based on the effective bits matched by the encryption and decryption algorithm and the set bit width calculation optimization algorithm. Based on the exponent bit width, the modulus bit width and the key and modulus required for the standardized data, vector iterative addition and shift operations are performed on the standardized data to obtain encrypted and decrypted data. The beneficial effect of the present application is that by setting the bit width, compatibility with multiple types of encryption and decryption algorithms is achieved. By relying on the exponent and modulus bit widths, operations on large-bit-width data can be split into smaller ones through unit splitting and hierarchical reuse. Field-programmable gate arrays (FPGAs) can support small-bit-width operations without complex wiring. By splitting operations, FPGAs can perform operations on large-bit-width data. Furthermore, compared to software-based data encryption and decryption, FPGAs are hardware devices, offering improved system performance and security.

[0167] FIG2 is a flowchart of a method for determining the exponent bit width and the modulus bit width provided in an embodiment of the present application, the method comprising:

[0168] S201: Setting the most significant bit of the first variable according to the valid bits matched by the encryption and decryption algorithm.

[0169] When calculating the exponent bit width and modulus bit width, you can set two variables: the first variable and the second variable. For ease of description, you can use i to represent the first variable and T to represent the second variable. The initial value of the second variable is 0.

[0170] The most significant bit of the first variable can be set based on the number of valid bits matched by the encryption / decryption algorithm. Assuming that the number of valid bits matched by the encryption / decryption algorithm is 10, the most significant bit of the first variable i is the 10th bit. In binary notation, the 10th bit of the first variable i is 1, and the remaining bits are 0.

[0171] S202: When the bit width signal is valid, perform multiple bit operations on the data to be tested according to the most significant bit of the first variable to obtain new data to be tested.

[0172] The data to be measured may be an exponent or a modulus.

[0173] When the bit width signal is valid, it indicates that there is a need to determine the exponent bit width and the modulus bit width, and the process of determining the exponent bit width and the modulus bit width can be executed.

[0174] The principles for determining the exponent bit width and the modulus bit width are similar. In the embodiments of the present application, the exponent bit width is used as an example to explain. In order to detect the most significant bit of the exponent, the first variable can be left-shifted in sequence to obtain the shift step of the data to be tested. Each time the shift step is obtained, the current data to be tested is right-shifted based on the shift step, and the result of the bitwise OR operation of the current data to be tested and the right-shifted data to be tested is used as the latest current data to be tested, until the most significant bit of the first variable is one, then the latest current data to be tested is output; an addition operation is performed on the latest current data to be tested to obtain new data to be tested.

[0175] For example, if the first variable is shifted left, the corresponding shift step of the measured data is 2 i The initial value of i is 1. Each time it is shifted left, the value of i is increased by 1 until it reaches the most significant bit of the first variable. The left shift operation stops, and the latest current test data output at this time is the result of all the valid bits of the test data being set to 1. By performing the addition operation on the latest current test data, the valid bits of the test data can be cleared to zero, leaving only the bit above the most significant bit as 1.

[0176] S203: Assign the new test data to the second variable according to the set bit step until the second variable is a non-zero value, then permute the second variable according to the permutation rule, and determine the bit width of the test data based on the permuted second variable and the current first variable.

[0177] In an embodiment of the present application, the length of the second variable can be set to 16 bits. The lower 16 bits of data are intercepted from the new data to be tested and assigned to the second variable. It is determined whether the second variable is zero. If the second variable is zero, it indicates that the currently intercepted data does not contain the most significant bit of the new data to be tested. In this case, the remaining data after intercepting the lower 16 bits of data can be used as the new data to be tested, and the process returns to the step of intercepting the lower 16 bits of data from the new data to be tested and assigning them to the second variable.

[0178] When the second variable is non-zero, it indicates that the currently intercepted data contains the most significant bit of the new data to be tested. At this time, the second variable can be replaced according to the replacement rule, and the difference between the first variable and the replaced second variable is used as the bit width of the data to be tested.

[0179] The substitution rules may include substitution values ​​corresponding to different variables, and the substitution values ​​corresponding to each variable value may be recorded in a correspondence list.

[0180] In practical applications, a correspondence list between variable values ​​and replacement values ​​can be queried to determine the second replacement value that matches the second variable; and the difference between the first variable and the second replacement value is used as the bit width of the data to be measured.

[0181] Taking the second variable as 16 bits as an example, the value of the second variable is 2 x , the value of x ranges from 0 to 15, 2 0 The corresponding replacement values ​​are 16, 2 1 The corresponding replacement value is 15, that is, every time the value of x decreases by 1, the corresponding replacement value also decreases by 1. Assuming that the second variable is 4, the corresponding replacement value is 14. Assuming that the first variable is 32, the bit width of the data to be measured is 32-14=18 bits.

[0182] FIG3 is a schematic diagram of a bit width calculation provided by an embodiment of the present application. In the initial state, the first variable i takes the value of 1 and the second variable T takes the value of 0. Assuming that the effective bit matched by the encryption and decryption algorithm is 10, the most significant bit of the first variable is the 10th bit. Every time the first variable is shifted left by one bit, the value of i is increased by 1, and the data to be tested A is shifted by a step length of 2. i Shift right, and perform bitwise OR operation on the current test data and the right-shifted test data, that is, A|A>>2i. When i[max_b]==0, return to shift the first variable left by one, add 1 to the value of i, and shift the test data A by a step of 2. i Shift right and perform a bitwise OR operation on the current test data and the right-shifted test data. This process continues until the first variable is shifted left 9 times to reach its most significant bit, i.e., i[max_b]==1. Then, the newly obtained data A is incremented by 1, i.e., A>>A+1, and the first variable i becomes 0. A is assigned to the second variable T in 16-bit increments, i.e., T[j]=A[i+j]. Each time the value is assigned, i is incremented by 16 until the second variable becomes non-zero. Then, the latest second variable is converted, i.e., fun(T). The difference between the current first variable i and fun(T) is used as the final result, i.e., result=i-fun(T). The final result is the desired bit width. When the test data A is an exponent, the final result is the exponent bit width; when the test data A is a modulus, the final result is the modulus bit width.

[0183] In an embodiment of the present application, the exponent bit width and modulus bit width are determined based on the actual exponent and modulus and the valid bits matched by the encryption and decryption algorithm. Large bit-width data operations can be split into several small bit-width data operations, which greatly reduces the difficulty of FPGA wiring and is more conducive to FPGA supporting large bit-width data operations.

[0184] FIG4 is a flowchart of a method for encrypting and decrypting standardized data based on exponent bit width and modulus bit width provided in an embodiment of the present application. The method includes:

[0185] S401: Determine whether the index is zero.

[0186] If the index is zero, execute S402; if the index is not zero, execute S403.

[0187] S402: Converting the operation of encrypting and decrypting the standardized data using the key into a modular division operation to obtain encrypted and decrypted data.

[0188] The essence of using a key to encrypt and decrypt standardized data is modular exponentiation.

[0189] The method of converting modular exponentiation into modular division is a relatively common implementation method at present and will not be described in detail here.

[0190] S403: Convert the operation of encrypting and decrypting the standardized data using the key into a modular multiplication operation.

[0191] When the exponent is not zero, the modular exponentiation operation can be converted into a modular multiplication operation using the LR conversion rule.

[0192] S404: Split the modular multiplication operation into multiple data addition and shift operations according to the exponent bit width and the modulus bit width to obtain encrypted and decrypted data.

[0193] In an embodiment of the present application, the modulus data to be analyzed of the modulus bit width can be intercepted from the current low bit of the modulus; the exponent data to be analyzed of the exponent bit width can be intercepted from the current low bit of the exponent; and the matching operation rule is selected based on the value of the highest bit of the exponent data to be analyzed.

[0194] The highest bit can have two values, 0 and 1, so the set operation rules may include two rules, namely a first rule and a second rule. The first rule may be a rule for performing a modular multiplication operation on the data based on the modulus, and the second rule may be a rule for iterating the result of the previous modular multiplication operation.

[0195] When the highest bit of the index data to be analyzed is zero, the first rule is selected; when the highest bit of the index data to be analyzed is not zero, the second rule is selected.

[0196] The exponential data to be analyzed, the modulus data to be analyzed, and the standardized data are processed according to the operation rules to obtain the operation result; each time the operation result is obtained, the exponent bit width is reduced by one; when the exponent bit width after the current reduction by one is not zero, the modulus data to be analyzed with the modulus bit width intercepted from the current low bit of the modulus is returned; the exponential data to be analyzed with the exponent bit width intercepted from the current low bit of the exponent is returned; when the exponent bit width after the current reduction by one is zero, the current operation result is output.

[0197] When the operation rule is the first rule, data addition and shift operations may be performed on the standardized data according to the exponential data to be analyzed and the modulus data to be analyzed to obtain an operation result.

[0198] To reduce the difficulty of the operation, in an embodiment of the present application, the data addition operation can be split. In a specific implementation, the data addition operation performed on the normalized data based on the exponential data to be analyzed and the modulus data to be analyzed can be split into multiple data addition sub-operations based on the valid bits matched by the encryption and decryption algorithm; and the multiple data addition sub-operations can be iteratively calculated.

[0199] When the operation rule is the second rule, data addition and shift operations may be performed on the result of the previous modular multiplication operation according to the exponential data to be analyzed and the modulus data to be analyzed to obtain the operation result.

[0200] In order to reduce the difficulty of the operation, in the embodiment of the present application, the data addition operation can be split. In the specific implementation, the data addition operation performed on the result of the previous modular multiplication operation based on the exponential data to be analyzed and the modulus data to be analyzed can be split into multiple data addition sub-operations according to the valid bits matched by the encryption and decryption algorithm; and the multiple data addition sub-operations are iteratively operated. The modular multiplication operation mainly uses the Montgomery modular multiplication algorithm, and its core idea is to calculate a*b mod N. It is necessary to find an R that meets two conditions: 1. R = 2^k>N, k is the smallest integer that meets the conditions; 2. gcd(R, N) = 1, that is, R and N are relatively prime.

[0201] Based on the method flow in Figure 2, the modulus width n_len of the modulus N can be calculated in advance, and R = 2^n_len. First, calculate x = a*(2^n_len) mod N. Then calculate y = x*b*2^(-n_len) mod N, and obtain the final result of a*b mod N.

[0202] In both steps of modular multiplication, the large-bit-width modular multiplication is ultimately converted into a large-bit-width data addition and shift operation. In the embodiment of the present application, the large-bit-width data addition can be further split into several small-bit-width data additions. For ease of distinction, the split small-bit-width data additions can be referred to as data addition sub-operations.

[0203] The step size of the split can be controlled by an internal register, adapting to the strategies of different electronic design automation (EDA) software for large-bitwidth operations while also optimizing overall timing. A schematic diagram of the specific implementation of large-bitwidth operation optimization is shown in Figure 5. Assuming the number of valid bits matched by the encryption and decryption algorithm is M, the data addition operation can be split into multiple data addition sub-operations with a processing length of M. The core of the modular multiplication operation described above is the calculation of a*b mod N. The data represented at the top of Figure 5 is data a, and the data a after splitting is a1 to aN. The data represented at the bottom is data b, and the data b after splitting is b1 to bN. After splitting the large-bitwidth addition operation into multiple data addition sub-operations, the output of each data addition sub-operation is iteratively fed into the next data addition sub-operation. The result of the first data addition operation is called the first result, the result of the second data addition operation is called the second result, and so on. The result of the N-1th data addition operation is called the N-1th result. The calculation result obtained by the Nth data addition operation can be directly output as the result value.

[0204] In the present application embodiment, a kind of RSA encryption and decryption algorithm optimization design is realized using programmable logic devices, which has better system performance and security than software implementation. All functional modules can be designed, convenient system integration and transplantation using register transfer level circuit (Register Transfer Level, RTL). Data communication is completed using the stream-oriented bus protocol (AXI4-stream) of Advanced Microcontroller Bus Architecture (AMBA), the configuration of various related control registers is completed by utilizing the interface (AXI4_lite) for low-throughput storage mapping communication in Advanced eXtensible Interface (AXI), compatible with RSA1024, RSA2048, RSA4096 three encryption and decryption algorithms, while large bit width vector operations and large bit width length calculation related algorithms are optimized, large bit width operations are split into small bit width operations of variable step length, while using fewer clock cycles to complete the calculation of large bit width length, to adapt to the comprehensive compilation and layout and routing strategy of different EDA tools to the algorithm.

[0205] After the encrypted and decrypted data is obtained, the encrypted and decrypted data may be converted into data adapted to the bit width of the double data rate synchronous dynamic random access memory, and the converted data may be written into the double data rate synchronous dynamic random access memory (DDR).

[0206] When the encrypted and decrypted data are stored in the DDR, an interrupt signal can be sent to the host computer at the same time, so that the host computer can read the data from the double-rate synchronous dynamic random access memory after receiving the interrupt signal.

[0207] Figure 6 is a schematic diagram of an RSA encryption and decryption hardware implementation provided in an embodiment of the present application. Based on the functions to be implemented, a register control module, a data flow control module, an encryption and decryption module, and a key pair generation module can be divided in a field programmable gate array (FPGA).

[0208] The specific implementation process is as follows: the register control module first configures the relevant control registers (key length, encryption and decryption type, segmentation level, etc.) according to the RSA algorithm type. The key pair generation module generates the corresponding public key and private key. The public key can be the decryption key for decrypting data, and the private key can be the encryption key for encrypting data. In order to realize the interaction between FPGA and double-rate synchronous dynamic random access memory (DDR), a memory control module can be set in FPGA. The data flow control module can realize the interaction with the memory control module and the encryption and decryption module respectively. Based on this, the data flow control module can be divided into a format conversion submodule and a bit width conversion submodule. The format conversion submodule reads the plaintext data from DDR during encryption and reads the ciphertext data from DDR during decryption, and then converts it into AXI4-stream format. The bit width conversion submodule then performs a bit width conversion and converts it into a unified 4096-bit format and sends it to the encryption and decryption module. After the encryption or decryption module completes the encryption or decryption operation, it performs a bit width conversion to convert the data into data that adapts to the bit width of the DDR controller. The data is then converted into data in the axi4_full format and written into the DDR. At the same time, an interrupt is generated to the host computer, and the host computer can read the calculated data from the DDR.

[0209] In this embodiment, an optimized method for hardware implementation of the RSA encryption and decryption algorithm is designed using an FPGA as the hardware implementation unit, using AMBA AXI4-stream for data communication and the AXI4_lite interface for configuring various related control registers, thereby achieving compatibility with the RSA1024, RSA2048, and RSA4096 encryption and decryption algorithms.

[0210] FIG7 is a schematic diagram of the structure of a data encryption and decryption device provided in an embodiment of the present application, which is applied to a computer equipped with a field programmable gate array. The device includes a generation unit 71, a conversion unit 72, a determination unit 73, and an operation unit 74.

[0211] A generating unit 71 is configured to generate key information according to an encryption and decryption algorithm; wherein the key information includes an encryption key, a decryption key, and a modulus;

[0212] A conversion unit 72, configured to convert the acquired data to be processed into standardized data of a set bit width;

[0213] A determination unit 73 is configured to determine the exponent bit width and the modulus bit width based on the valid bits matched by the encryption and decryption algorithm and the set bit width calculation optimization algorithm;

[0214] The operation unit 74 is used to perform vector iterative addition and shift operations on the normalized data based on the exponent bit width, the modulus bit width, and the key and modulus required for the normalized data to obtain encrypted and decrypted data.

[0215] In some embodiments, the determination unit includes a setting subunit, a bit operation subunit, an assignment subunit, and a substitution subunit;

[0216] A setting subunit, configured to set the most significant bit of the first variable according to the valid bits matched by the encryption and decryption algorithm;

[0217] A bit operation subunit is used to perform multiple bit operations on the data to be tested according to the most significant bit of the first variable to obtain new data to be tested when the bit width signal is valid; wherein the data to be tested is an exponent or a modulus;

[0218] an assignment subunit, configured to assign the new test data to the second variable in steps of set bits until the second variable reaches a non-zero value;

[0219] The substitution subunit is used to substitute the second variable according to the substitution rule, and determine the bit width of the data to be measured according to the second variable after substitution and the current first variable.

[0220] In some embodiments, the bit operation subunit is used to sequentially left-shift the first variable to obtain a shift step length of the data to be measured; wherein the data to be measured is an exponent or a modulus;

[0221] Each time a shift step is obtained, the current data to be tested is right-shifted based on the shift step, and the result of the bitwise OR operation of the current data to be tested and the right-shifted data to be tested is used as the latest current data to be tested, until the most significant bit of the first variable is one, then the latest current data to be tested is output;

[0222] An addition operation is performed on the latest current data to be tested to obtain new data to be tested.

[0223] In some embodiments, the assignment subunit is used to intercept the lower 16 bits of data from the new data to be tested and assign them to the second variable;

[0224] Determine whether the second variable is zero;

[0225] When the second variable is zero, the remaining data after intercepting the lower 16 bits of data is used as new test data, and the step of intercepting the lower 16 bits of data from the new test data and assigning them to the second variable is returned;

[0226] When the second variable is non-zero, the second variable is permuted according to the permutation rule, and the difference between the first variable and the permuted second variable is used as the bit width of the data to be measured.

[0227] In some embodiments, the substitution subunit is configured to query a list of correspondences between variable values ​​and substitution values ​​to determine a second substitution value that matches the second variable;

[0228] The difference between the first variable and the second replacement value is used as the bit width of the data to be measured.

[0229] In some embodiments, the operation unit includes a judgment subunit, a first conversion subunit, a second conversion subunit, and a splitting subunit;

[0230] A judgment subunit, used to judge whether the index is zero;

[0231] A first conversion subunit is configured to convert, when the exponent is zero, an operation of encrypting and decrypting the standardized data using the key into a modular division operation to obtain encrypted and decrypted data;

[0232] a second conversion subunit, configured to convert, when the exponent is not zero, an operation of encrypting and decrypting the standardized data using the key into a modular multiplication operation;

[0233] The splitting subunit is used to split the modular multiplication operation into multiple data addition and shift operations according to the exponent bit width and the modulus bit width to obtain encrypted and decrypted data.

[0234] In some embodiments, the splitting subunit is used to intercept the modulus data to be analyzed with the modulus bit width from the current low bit of the modulus; intercept the exponent data to be analyzed with the exponent bit width from the current low bit of the exponent;

[0235] Select a matching operation rule based on the value of the highest bit of the index data to be analyzed;

[0236] Process the index data to be analyzed, the modulus data to be analyzed, and the standardized data according to the operation rules to obtain the operation results;

[0237] Each time an operation result is obtained, the exponent bit width is reduced by one; when the current exponent bit width after reduction by one is not zero, the steps of intercepting the modulus data to be analyzed with the modulus bit width from the current low bit of the modulus and intercepting the exponent data to be analyzed with the exponent bit width from the current low bit of the exponent are returned; when the current exponent bit width after reduction by one is zero, the current operation result is output.

[0238] In some embodiments, the operation rules include a first rule for performing a modular multiplication operation on the data based on a modulus, and a second rule for iterating based on a result of a previous modular multiplication operation;

[0239] Accordingly, the splitting subunit is used to select the first rule when the highest bit of the index data to be analyzed is zero;

[0240] When the highest bit of the index data to be analyzed is not zero, the second rule is selected.

[0241] In some embodiments, the splitting subunit is configured to perform data addition and shift operations on the normalized data according to the exponential data to be analyzed and the modulus data to be analyzed to obtain an operation result when the operation rule is the first rule.

[0242] In some embodiments, the splitting sub-unit is used to split the data addition operation on the standardized data based on the exponential data to be analyzed and the modulus data to be analyzed into multiple data addition sub-operations according to the valid bits matched by the encryption and decryption algorithm; and perform iterative operations on the multiple data addition sub-operations.

[0243] In some embodiments, the splitting subunit is used to perform data addition and shift operations on the result of the previous modular multiplication operation according to the exponential data to be analyzed and the modulus data to be analyzed to obtain the operation result when the operation rule is the second rule.

[0244] In some embodiments, the splitting sub-unit is used to split the data addition operation on the result of the previous modular multiplication operation based on the exponential data to be analyzed and the modulus data to be analyzed into multiple data addition sub-operations according to the valid bits matched by the encryption and decryption algorithm; and perform iterative operations on the multiple data addition sub-operations.

[0245] In some embodiments, further comprising a storage unit;

[0246] The storage unit is used to convert the encrypted and decrypted data into data adapted to the bit width of the double rate synchronous dynamic random access memory, and write the converted data into the double rate synchronous dynamic random access memory.

[0247] In some embodiments, a sending unit is further included;

[0248] The sending unit is used to perform vector iterative addition and shift operations on the standardized data based on the exponent bit width, the modulus bit width, and the key and modulus required for the standardized data, and after obtaining the encrypted and decrypted data, send an interrupt signal to the host computer so that the host computer can read the data from the double-rate synchronous dynamic random access memory after receiving the interrupt signal.

[0249] In some embodiments, the generating unit includes a random subunit, a screening subunit, a determining subunit, and an acting subunit;

[0250] A random subunit, used for generating multiple random numbers using a stream cipher algorithm;

[0251] a screening subunit, configured to screen out a first largest prime number and a second largest prime number from a plurality of random numbers;

[0252] a determination subunit, configured to determine a modulus and a value of the Euler function of the modulus based on the first largest prime number and the second largest prime number;

[0253] As a subunit, it is used to use the coprime number of the Euler function value as the encryption key, and obtain the decryption key by performing modular inversion on the encryption key.

[0254] In some embodiments, the screening subunit is used to screen multiple random numbers using a set prime group to obtain prime numbers to be detected; detect the prime numbers to be detected according to the randomization algorithm, and screen out the first largest prime number and the second largest prime number from the prime numbers to be detected based on the detection results.

[0255] In some embodiments, the conversion unit is used to convert the acquired data to be processed into 4096-bit standardized data.

[0256] In some embodiments, a mode determination unit is further included;

[0257] A mode determination unit is used to determine the operation mode of executing the steps of determining the exponent bit width and modulus bit width according to the valid bits matched according to the encryption and decryption algorithm and the set bit width calculation optimization algorithm based on the currently available logical resources and the type of encryption and decryption algorithm; wherein the operation mode includes parallel or cascade.

[0258] For the description of the features in the embodiment corresponding to FIG. 7 , reference can be made to the relevant description of the embodiments corresponding to FIG. 1 to FIG. 6 , and no further details will be given here.

[0259] It can be seen from the above technical solution that the field programmable gate array generates key information based on the encryption and decryption algorithm; wherein, the key information may include an encryption key, a decryption key, and a modulus; in order to be compatible with different types of encryption and decryption algorithms, the bit width can be set based on the key length of different types of encryption and decryption algorithms, and the acquired data to be processed is converted into standardized data with the set bit width. The encryption and decryption operations of data belong to the operations of large bit width data. In order to enable the field programmable gate array to smoothly implement the operations of large bit width data, the exponent bit width and the modulus bit width can be determined based on the effective bits matched by the encryption and decryption algorithm and the set bit width calculation optimization algorithm. Based on the exponent bit width, the modulus bit width and the key and modulus required for the standardized data, vector iterative addition and shift operations are performed on the standardized data to obtain encrypted and decrypted data. The beneficial effect of the present application is that by setting the bit width, compatibility with multiple types of encryption and decryption algorithms is achieved. By relying on the exponent and modulus bit widths, operations on large-bit-width data can be split into smaller ones through unit splitting and hierarchical reuse. Field-programmable gate arrays (FPGAs) can support small-bit-width operations without complex wiring. By splitting operations, FPGAs can perform operations on large-bit-width data. Furthermore, compared to software-based data encryption and decryption, FPGAs are hardware devices, offering improved system performance and security.

[0260] FIG8 is a structural diagram of an electronic device provided in an embodiment of the present application. As shown in FIG8 , the electronic device includes: a memory 80 for storing computer programs;

[0261] The processor 81 is configured to implement the steps of the data encryption and decryption method of the above embodiment when executing a computer program.

[0262] The electronic device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.

[0263] Among them, the processor 81 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 81 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 81 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 81 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 81 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0264] The memory 80 may include one or more computer non-volatile readable storage media, which may be non-transitory. The memory 80 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 80 is at least used to store the following computer program 801, wherein, after the computer program is loaded and executed by the processor 81, it can implement the relevant steps of the data encryption and decryption method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 80 may also include an operating system 802 and data 803, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 802 may include Windows, Unix, Linux, etc. The data 803 may include but is not limited to key information, set bit width, etc.

[0265] In some embodiments, the electronic device may further include a display screen 82 , an input / output interface 83 , a communication interface 84 , a power supply 85 , and a communication bus 86 .

[0266] Those skilled in the art will appreciate that the structure shown in FIG8 does not limit the electronic device and may include more or fewer components than shown in the figure.

[0267] It is understandable that if the data encryption and decryption method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the current technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium and executes all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk, etc. Various media that can store program code.

[0268] Based on this, an embodiment of the present application further provides a computer non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned data encryption and decryption method are implemented.

[0269] The above describes in detail the data encryption and decryption method, device, equipment, and computer non-volatile readable storage medium provided in the embodiments of the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to in detail. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For relevant parts, please refer to the method description.

[0270] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0271] The above is a detailed introduction to the data encryption and decryption method, device, equipment and computer non-volatile readable storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for encrypting and decrypting data, characterized in that: Applied to a computer, wherein the computer is provided with a field programmable gate array, the method comprising: Generate key information according to the encryption and decryption algorithm; wherein the key information includes an encryption key, a decryption key, and a modulus; Convert the acquired data to be processed into standardized data with a set bit width; Determine the exponent bit width and modulus bit width according to the effective bit positions matched by the encryption and decryption algorithm and the set bit width calculation optimization algorithm; Based on the exponent bit width, the modulus bit width, and the key and modulus required for the standardized data, vector iterative addition and shift operations are performed on the standardized data to obtain encrypted and decrypted data.

2. The data encryption and decryption method according to claim 1, characterized in that: Determining the exponent bit width and modulus bit width according to the effective bit positions matched by the encryption and decryption algorithm and the set bit width calculation optimization algorithm includes: Setting the most significant bit of the first variable according to the valid bits matched by the encryption and decryption algorithm; When the bit width signal is valid, performing multiple bit operations on the data to be tested according to the most significant bit of the first variable to obtain new data to be tested; wherein the data to be tested is an exponent or a modulus; The new data to be tested is assigned to the second variable according to the set bit step until the second variable is a non-zero value, and then the second variable is permuted according to the permutation rule, and the bit width of the data to be tested is determined based on the permuted second variable and the current first variable.

3. The data encryption and decryption method according to claim 2, characterized in that: The performing multiple bit operations on the data to be tested according to the most significant bit of the first variable to obtain new data to be tested includes: Sequentially left-shifting the first variable to obtain a shift step length of the data to be measured; wherein the data to be measured is an exponent or a modulus; Each time a shift step is obtained, the current data to be tested is right-shifted based on the shift step, and a bitwise OR operation result of the current data to be tested and the right-shifted data to be tested is used as the latest current data to be tested, until the most significant bit of the first variable is one, then the latest current data to be tested is output; An addition operation is performed on the latest current data to be tested to obtain new data to be tested.

4. The data encryption and decryption method according to claim 2, characterized in that: The step of assigning the new data to be tested to the second variable according to the set bit step until the second variable is a non-zero value includes: Extracting lower 16 bits of data from the new data to be tested and assigning them to the second variable; Determining whether the second variable is zero; When the second variable is zero, the remaining data after intercepting the lower 16 bits of data is used as new data to be tested, and the step of intercepting the lower 16 bits of data from the new data to be tested and assigning them to the second variable is returned; When the second variable is non-zero, the second variable is permuted according to a permutation rule, and a difference between the first variable and the permuted second variable is used as the bit width of the data to be measured.

5. The data encryption and decryption method according to claim 2, characterized in that: The step of replacing the second variable according to the replacement rule and determining the bit width of the data to be tested according to the replaced second variable and the current first variable includes: Querying a list of correspondences between variable values ​​and replacement values ​​to determine a second replacement value that matches the second variable; The difference between the first variable and the second replacement value is used as the bit width of the data to be tested.

6. The data encryption and decryption method according to claim 1, characterized in that: The performing vector iterative addition and shift operations on the standardized data based on the exponent bit width, the modulus bit width, and the key and modulus required for the standardized data to obtain the encrypted and decrypted data comprises: Determine whether the index is zero; When the exponent is zero, converting the encryption and decryption operation of the standardized data using the key into a modular division operation to obtain encrypted and decrypted data; In the case where the exponent is not zero, converting the operation of encrypting and decrypting the standardized data using the key into a modular multiplication operation; According to the exponent bit width and the modulus bit width, the modular multiplication operation is split into a plurality of data addition and shift operations to obtain encrypted and decrypted data.

7. The data encryption and decryption method according to claim 6, characterized in that: The step of splitting the modular multiplication operation into a plurality of data addition and shift operations according to the exponent bit width and the modulus bit width to obtain encrypted and decrypted data includes: intercepting the modulus data to be analyzed of the modulus bit width from the current low bit of the modulus; intercepting the exponent data to be analyzed of the exponent bit width from the current low bit of the exponent; Selecting a matching operation rule according to the value of the highest bit of the index data to be analyzed; Processing the index data to be analyzed, the modulus data to be analyzed, and the standardized data according to the operation rules to obtain an operation result; Each time a calculation result is obtained, the exponent bit width is reduced by one; when the current exponent bit width after reduction by one is not zero, the steps of intercepting the modulus data to be analyzed of the modulus bit width from the current low bit of the modulus and intercepting the exponent data to be analyzed of the exponent bit width from the current low bit of the exponent are returned; when the current exponent bit width after reduction by one is zero, the current calculation result is output.

8. The data encryption and decryption method according to claim 7, characterized in that: The operation rules include a first rule for performing modular multiplication operation on data based on a modulus, and a second rule for iterating the result of the previous modular multiplication operation; Correspondingly, the matching operation rule selected according to the value of the highest bit of the index data to be analyzed includes: When the highest bit of the index data to be analyzed is zero, selecting the first rule; When the highest bit of the index data to be analyzed is not zero, the second rule is selected.

9. The data encryption and decryption method according to claim 8, characterized in that: The processing of the index data to be analyzed, the modulus data to be analyzed, and the standardized data according to the operation rule to obtain the operation result includes: In the case where the operation rule is the first rule, data addition and shift operations are performed on the standardized data according to the exponential data to be analyzed and the modulus data to be analyzed to obtain an operation result.

10. The data encryption and decryption method according to claim 9, characterized in that: The performing a data addition operation on the standardized data according to the index data to be analyzed and the modulus data to be analyzed comprises: According to the valid bits matched by the encryption and decryption algorithm, the data addition operation performed on the standardized data according to the exponential data to be analyzed and the modulus data to be analyzed is divided into a plurality of data addition sub-operations; Iterate the multiple data addition operations.

11. The data encryption and decryption method according to claim 8, characterized in that: The processing of the index data to be analyzed, the modulus data to be analyzed, and the standardized data according to the operation rule to obtain the operation result includes: When the operation rule is the second rule, a data addition and shift operation is performed on the result of the previous modular multiplication operation according to the exponential data to be analyzed and the modulus data to be analyzed to obtain an operation result.

12. The data encryption and decryption method according to claim 11, characterized in that: The performing a data addition operation on the result of the previous modular multiplication operation according to the exponential data to be analyzed and the modular data to be analyzed comprises: According to the valid bits matched by the encryption and decryption algorithm, the data addition operation performed on the result of the previous modular multiplication operation according to the exponential data to be analyzed and the modulus data to be analyzed is divided into a plurality of data addition sub-operations; Iterate the multiple data addition operations.

13. The data encryption and decryption method according to claim 1, characterized in that: After performing vector iterative addition and shift operations on the standardized data based on the exponent bit width, the modulus bit width, and the key and modulus required for the standardized data to obtain encrypted and decrypted data, the method further includes: The encrypted and decrypted data is converted into data adapted to the bit width of the double rate synchronous dynamic random access memory, and the converted data is written into the double rate synchronous dynamic random access memory.

14. The data encryption and decryption method according to claim 13, characterized in that: After performing vector iterative addition and shift operations on the standardized data based on the exponent bit width, the modulus bit width, and the key and modulus required for the standardized data to obtain encrypted and decrypted data, the method further includes: An interrupt signal is sent to a host computer, so that the host computer reads data from the double rate synchronous dynamic random access memory after receiving the interrupt signal.

15. The data encryption and decryption method according to claim 1, characterized in that: The generating key information according to the encryption and decryption algorithm includes: Generate multiple random numbers using a stream cipher algorithm; Selecting a first largest prime number and a second largest prime number from the plurality of random numbers; Based on the first largest prime number and the second largest prime number, determining a modulus and a Euler function value of the modulus; The coprime number of the Euler function value is used as an encryption key, and the encryption key is modulo inverted to obtain a decryption key.

16. The data encryption and decryption method according to claim 15, characterized in that: The step of selecting the first largest prime number and the second largest prime number from the plurality of random numbers comprises: Using a set prime number array to screen a plurality of the random numbers to obtain a prime number to be detected; The prime numbers to be detected are detected according to a randomized algorithm, and a first largest prime number and a second largest prime number are screened out from the prime numbers to be detected according to the detection result.

17. The data encryption and decryption method according to claim 1, characterized in that: The step of converting the acquired data to be processed into standardized data with a set bit width includes: The acquired data to be processed is converted into 4096-bit standardized data.

18. The data encryption and decryption method according to any one of claims 1 to 17, characterized in that: Also includes: Based on the currently available logical resources and the type of the encryption / decryption algorithm, determine the operation mode of executing the steps of executing the effective bits matched according to the encryption / decryption algorithm and the set bit width calculation optimization algorithm, and determining the exponent bit width and modulus bit width; wherein the operation mode includes parallel or cascade.

19. A data encryption and decryption device, characterized in that: Applied to a computer, wherein the computer is provided with a field programmable gate array, the device comprises a generating unit, a converting unit, a determining unit and a computing unit; The generating unit is used to generate key information according to the encryption and decryption algorithm; wherein the key information includes encryption Key, decryption key, modulus; The conversion unit is used to convert the acquired data to be processed into standardized data with a set bit width; The determining unit is used to determine the exponent bit width and the modulus bit width according to the effective bits matched by the encryption and decryption algorithm and the set bit width calculation optimization algorithm; The operation unit is used to perform vector iterative addition and shift operations on the standardized data based on the exponent bit width, the modulus bit width, and the key and modulus required for the standardized data to obtain encrypted and decrypted data.

20. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the data encryption and decryption method as claimed in any one of claims 1 to 18.

21. A computer non-volatile readable storage medium, characterized in that: The computer non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data encryption and decryption method according to any one of claims 1 to 18 are implemented.

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