Display substrate and display device

Abstract

The present invention provides a display substrate and a display device. The display substrate comprises: a substrate base and a plurality of sub-pixels and a plurality of data lines which are both provided on the substrate base; each sub-pixel comprises a sub-pixel drive circuit and a light-emitting element which are coupled; a plurality of sub-pixel drive circuits comprised in the plurality of sub-pixels are divided into a plurality of drive circuit columns; each drive circuit column comprises a plurality of sub-pixel drive circuits arranged in a first direction; the plurality of drive circuit columns are divided into a plurality of column units; each unit comprises at least two adjacent drive circuit columns; the data lines coupled to the sub-pixel drive circuits comprised in each column unit are located on a first side and / or a second side of the column unit; the first side is opposite to the second side in a second direction; and the second direction intersects with the first direction.

Description

Display substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310699677.8 filed in China on June 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] With the continuous development of display technology, the application of display products is becoming more and more widespread, and people's demand for display quality is becoming increasingly higher. To achieve higher-quality displays, the sub-pixel driver circuits in sub-pixels must have high stability. However, when the data signals transmitted by the data lines in current display products change, they can significantly affect the stability of key nodes in the sub-pixel driver circuits, thereby affecting the stability of the sub-pixel driver circuits. Therefore, how to improve the operating stability of sub-pixel driver circuits has become a pressing technical problem.

[0005] Summary of the Invention

[0006] An object of the present disclosure is to provide a display substrate and a display device.

[0007] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0008] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate and a plurality of sub-pixels and a plurality of data lines each disposed on the base substrate, wherein the sub-pixels include a sub-pixel driving circuit and a light-emitting element coupled thereto;

[0009] The multiple sub-pixel driving circuits included in the multiple sub-pixels are divided into multiple columns of driving circuit columns, each column of driving circuit columns includes multiple sub-pixel driving circuits arranged along a first direction, and the multiple columns of driving circuit columns are divided into multiple column units, and the column units include at least two adjacent column of driving circuit columns; the data lines coupled to the sub-pixel driving circuits included in the column units are located on the first side and / or the second side of the column unit, the first side and the second side are opposite to each other along a second direction, and the second direction intersects with the first direction.

[0010] Optionally, the column unit includes at least one first drive circuit column and at least one second drive circuit column, and the first drive circuit column and the second drive circuit column are alternately arranged along the second direction;

[0011] The first driving circuit column includes a plurality of first sub-pixel driving circuits and a plurality of second sub-pixel driving circuits, the first sub-pixel driving circuits and the second sub-pixel driving circuits are alternately arranged along the first direction, the first sub-pixel driving circuits are coupled to first-color light-emitting elements, and the second sub-pixel driving circuits are coupled to second-color light-emitting elements; each first sub-pixel driving circuit in the first driving circuit column is coupled to the same data line, and each second sub-pixel driving circuit in the first driving circuit column is coupled to the same data line;

[0012] The sub-pixel driving circuit included in the second driving circuit column is coupled to the third color light emitting element; and each sub-pixel driving circuit in the second driving circuit column is coupled to the same data line.

[0013] Optionally, the data lines coupled to each first sub-pixel driving circuit in the first driving circuit column and the data lines coupled to each second sub-pixel driving circuit in the first driving circuit column are located on the first side of the column unit, and the data lines coupled to each sub-pixel driving circuit in the second driving circuit column are located on the second side of the column unit.

[0014] Optionally, the column unit includes two first drive circuit columns and two second drive circuit columns; each first sub-pixel drive circuit included in the two first drive circuit columns is coupled to the same first data line; each second sub-pixel drive circuit included in the two first drive circuit columns is coupled to the same second data line; each third sub-pixel drive circuit included in the first second drive circuit column is coupled to the same third data line; and each fourth sub-pixel drive circuit included in the second second drive circuit column is coupled to the same fourth data line.

[0015] The first data line, the second data line, the third data line and the fourth data line are sequentially arranged along the second direction.

[0016] Optionally, the column unit is divided into a plurality of sub-units sequentially arranged along the first direction, and the sub-units include two rows of driving circuits arranged along the first direction;

[0017] The first row of driving circuits includes a first sub-pixel driving circuit, a third sub-pixel driving circuit, a second sub-pixel driving circuit, and a fourth sub-pixel driving circuit arranged in sequence along the second direction; the second row of driving circuits includes a second sub-pixel driving circuit, a third sub-pixel driving circuit, a first sub-pixel driving circuit, and a fourth sub-pixel driving circuit arranged in sequence along the second direction;

[0018] The first data line and the second data line are located at a first side of the column unit, and the third data line and the fourth data line are located at a second side of the column unit.

[0019] Optionally, the first sub-pixel driving circuit in the first row of driving circuits includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the first data line is coupled to the first electrode of the data writing transistor via a first conductive connection portion;

[0020] The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the first data main portion included in the first data line on the base substrate and the orthographic projection of the second data main portion included in the second data line on the base substrate.

[0021] Optionally, the display substrate further includes a reference signal line and an initialization signal line;

[0022] The first conductive connection portion includes a first sub-portion and a second sub-portion coupled to each other, the first sub-portion extending along the second direction, the second sub-portion extending along the first direction, the first sub-portion coupled to the first data line, and the second sub-portion coupled to the first electrode of the data writing transistor;

[0023] At least a portion of an orthographic projection of the first sub-portion on the base substrate is located between an orthographic projection of the reference signal line on the base substrate and an orthographic projection of the initialization signal line on the base substrate.

[0024] Optionally, the first sub-pixel driving circuit in the second row of driving circuits includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the first data line is coupled to the first electrode of the data writing transistor via a second conductive connection portion;

[0025] The data writing transistor includes a data writing active layer, the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the second data main portion included in the second data line on the base substrate and the orthographic projection of the third data main portion included in the third data line on the base substrate.

[0026] Optionally, the second conductive connection portion includes a third sub-portion and a fourth sub-portion coupled to each other, at least a portion of the third sub-portion extends along the second direction, the fourth sub-portion at least partially surrounds the sensing opening area of ​​the display substrate, the third sub-portion is coupled to the first data line, and the fourth sub-portion is coupled to the first electrode of the data write transistor.

[0027] Optionally, the display substrate further includes a reference signal line and an initialization signal line; at least a portion of the orthographic projection of the third sub-portion on the base substrate is located between the orthographic projection of the reference signal line on the base substrate and the orthographic projection of the initialization signal line on the base substrate;

[0028] The orthographic projection of the fourth sub-portion on the substrate at least partially overlaps with the orthographic projection of the initialization signal line on the substrate; and / or the orthographic projection of the fourth sub-portion on the substrate at least partially overlaps with the orthographic projection of the reference signal line on the substrate.

[0029] Optionally, the second sub-pixel driving circuit in the first row of driving circuits includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the second data line is coupled to the first electrode of the data writing transistor via a third conductive connection portion;

[0030] The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the second data main portion included in the second data line on the base substrate and the orthographic projection of the third data main portion included in the third data line on the base substrate.

[0031] Optionally, the display substrate further includes a first scan line, and the second sub-pixel driving circuit in the first row of driving circuits further includes a compensation transistor, a first electrode of the compensation transistor is coupled to the first electrode of the driving transistor, a second electrode of the compensation transistor is coupled to the gate of the driving transistor, and the gate of the compensation transistor is coupled to the corresponding first scan line;

[0032] The third conductive connection portion includes a fifth sub-portion and a sixth sub-portion coupled to each other, the fifth sub-portion is coupled to the second data line, and the sixth sub-portion is coupled to the first electrode of the data writing transistor; the orthographic projection of the fifth sub-portion on the substrate at least partially overlaps with the orthographic projection of the first scanning line on the substrate.

[0033] Optionally, the second sub-pixel driving circuit in the second row of driving circuits includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the second data line is coupled to the first electrode of the data writing transistor via a fourth conductive connection portion;

[0034] The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the first data main portion included in the first data line on the base substrate and the orthographic projection of the second data main portion included in the second data line on the base substrate.

[0035] Optionally, the display substrate further includes a second scan line; the gate of the data writing transistor is coupled to the corresponding second scan line;

[0036] The fourth conductive connection portion includes a seventh sub-portion and an eighth sub-portion coupled to each other, the seventh sub-portion extending along the second direction, the eighth sub-portion extending along the first direction, the seventh sub-portion coupled to the second data line, and the eighth sub-portion coupled to the first electrode of the data writing transistor;

[0037] At least a portion of the orthographic projection of the seventh sub-portion on the base substrate is located between the orthographic projection of the second scan line on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate.

[0038] Optionally, the third sub-pixel driving circuit in the first row of driving circuits includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the third data line is coupled to the first electrode of the data writing transistor via a fifth conductive connection portion;

[0039] The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the second data main portion included in the second data line on the base substrate and the orthographic projection of the third data main portion included in the third data line on the base substrate.

[0040] Optionally, the fifth conductive connection portion includes a ninth sub-portion and a tenth sub-portion coupled to each other, at least a portion of the ninth sub-portion extends along the second direction, the tenth sub-portion at least partially surrounds the sensing opening area of ​​the display substrate, the ninth sub-portion is coupled to the third data line, and the tenth sub-portion is coupled to the first electrode of the data write transistor.

[0041] Optionally, the display substrate further includes a reference signal line and an initialization signal line; at least a portion of the orthographic projection of the ninth sub-portion on the base substrate is located between the orthographic projection of the reference signal line on the base substrate and the orthographic projection of the initialization signal line on the base substrate;

[0042] The orthographic projection of the tenth sub-portion on the substrate at least partially overlaps with the orthographic projection of the initialization signal line on the substrate; and / or, the orthographic projection of the tenth sub-portion on the substrate at least partially overlaps with the orthographic projection of the reference signal line on the substrate.

[0043] Optionally, the third sub-pixel driving circuit in the second row of driving circuits includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the third data line is coupled to the first electrode of the data writing transistor via a sixth conductive connection portion;

[0044] The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the second data main portion included in the second data line on the base substrate and the orthographic projection of the third data main portion included in the third data line on the base substrate.

[0045] Optionally, the display substrate further includes a second scan line; the gate of the data writing transistor is coupled to the corresponding second scan line;

[0046] The sixth conductive connection portion includes an eleventh sub-portion and a twelfth sub-portion coupled to each other, the eleventh sub-portion extending along the second direction, the twelfth sub-portion extending along the first direction, the eleventh sub-portion coupled to the third data line, and the twelfth sub-portion coupled to the first electrode of the data write transistor;

[0047] At least a portion of the orthographic projection of the eleventh sub-portion on the base substrate is located between the orthographic projection of the second scan line on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate.

[0048] Optionally, the fourth sub-pixel driving circuit in the first row of driving circuits includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the fourth data line is coupled to the first electrode of the data writing transistor via a seventh conductive connection portion;

[0049] The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the third data main portion included in the third data line on the base substrate and the orthographic projection of the fourth data main portion included in the fourth data line on the base substrate.

[0050] Optionally, the display substrate further includes a first scan line, and the fourth sub-pixel driving circuit in the first row of driving circuits further includes a compensation transistor, a first electrode of the compensation transistor is coupled to the first electrode of the driving transistor, a second electrode of the compensation transistor is coupled to the gate of the driving transistor, and the gate of the compensation transistor is coupled to the corresponding first scan line;

[0051] The seventh conductive connection portion includes a thirteenth sub-portion and a fourteenth sub-portion coupled to each other, the thirteenth sub-portion is coupled to the fourth data line, and the fourteenth sub-portion is coupled to the first electrode of the data writing transistor; the orthographic projection of the thirteenth sub-portion on the substrate at least partially overlaps with the orthographic projection of the first scanning line on the substrate.

[0052] Optionally, the fourth sub-pixel driving circuit in the second row of driving circuits includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the fourth data line is coupled to the first electrode of the data writing transistor via an eighth conductive connection portion;

[0053] The data writing transistor includes a data writing active layer, the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the third data main portion included in the third data line on the base substrate and the orthographic projection of the fourth data main portion included in the fourth data line on the base substrate.

[0054] Optionally, the display substrate further includes a reference signal line and an initialization signal line; the eighth conductive connection portion includes a fifteenth sub-portion and a sixteenth sub-portion coupled to each other, at least a portion of the fifteenth sub-portion extends along the second direction, and at least a portion of the sixteenth sub-portion extends along the first direction, the fifteenth sub-portion is coupled to the fourth data line, and the sixteenth sub-portion is coupled to the first electrode of the data write transistor;

[0055] At least a portion of the orthographic projection of the fifteenth sub-portion on the base substrate is located between the orthographic projection of the reference signal line on the base substrate and the orthographic projection of the initialization signal line on the base substrate.

[0056] Optionally, each sub-pixel driving circuit in the display substrate includes a driving transistor and a compensation transistor, the first electrode of the compensation transistor is coupled to the first electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor through a first switching pattern; at least a portion of the orthographic projection of the first switching pattern on the base substrate is located between the orthographic projection of the second data line on the base substrate and the orthographic projection of the third data line on the base substrate.

[0057] Optionally, the first transfer pattern includes a first end, a second end, and a connecting portion coupled to the first end and the second end respectively, the first end is coupled to the gate of the driving transistor, the second end is coupled to the second pole of the compensation transistor, and the connecting portion extends along the second direction.

[0058] Optionally, within the layout area of ​​the first row of driving circuits: the orthographic projection of the first switching pattern located in the layout area of ​​the second sub-pixel driving circuit on the substrate, and the orthographic projection of the first switching pattern located in the layout area of ​​the third sub-pixel driving circuit on the substrate, are both located between the orthographic projection of the second data line on the substrate and the orthographic projection of the third data line on the substrate; the orthographic projection of the first end portion located in the layout area of ​​the first sub-pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second data line on the substrate; the orthographic projection of the first end portion located in the layout area of ​​the fourth sub-pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the third data line on the substrate.

[0059] Optionally, within the layout area of ​​the second row of driving circuits: the orthographic projection of the first switching pattern located in the layout area of ​​the first sub-pixel driving circuit on the substrate, and the orthographic projection of the first switching pattern located in the layout area of ​​the third sub-pixel driving circuit on the substrate, are both located between the orthographic projection of the second data line on the substrate and the orthographic projection of the third data line on the substrate; the orthographic projection of the first end portion located in the layout area of ​​the second sub-pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second data line on the substrate; the orthographic projection of the first end portion located in the layout area of ​​the fourth sub-pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the third data line on the substrate.

[0060] Optionally, the display substrate further includes a power supply layer, and an orthographic projection of the power supply layer on the base substrate covers an orthographic projection of the first switching pattern on the base substrate.

[0061] Optionally, the power layer includes a plurality of first power lines and a plurality of second power lines, the first power lines and the second power lines are arranged crosswise, and the first power lines are coupled to the second power lines;

[0062] The orthographic projection of the first power line on the base substrate covers the orthographic projection of the first end portion on the base substrate, and / or the orthographic projection of the first power line on the base substrate at least partially overlaps with the orthographic projection of the connecting portion on the base substrate;

[0063] The orthographic projection of the second power line on the base substrate covers the orthographic projection of the second end portion on the base substrate, and / or the orthographic projection of the second power line on the base substrate at least partially overlaps with the orthographic projection of the connecting portion on the base substrate.

[0064] Optionally, the display substrate includes a plurality of first sensing opening areas and a plurality of second sensing opening areas; the first sensing opening areas are located between the second sub-pixel driving circuit layout area and the third sub-pixel driving circuit layout area in the corresponding first row driving circuit row; the second sensing opening areas are located between the first sub-pixel driving circuit layout area and the third sub-pixel driving circuit layout area in the corresponding second row driving circuit row.

[0065] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0067] FIG1 is a schematic structural diagram of a column unit and a data line provided by an embodiment of the present disclosure;

[0068] FIG2 is a schematic diagram showing the signal direction of a data signal transmitted via a data line according to an embodiment of the present disclosure;

[0069] FIG3 is a schematic diagram of the circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0070] FIG4 is a schematic diagram of the layout of column units provided in an embodiment of the present disclosure;

[0071] FIG5 is a schematic diagram of the layout of the polysilicon active layer in FIG4 ;

[0072] FIG6 is a schematic diagram of the layout of the polysilicon active layer and the first gate metal layer in FIG4 ;

[0073] FIG7 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG6 ;

[0074] FIG8 is a schematic diagram of the layout of the third gate metal layer in FIG4 ;

[0075] FIG9 is a schematic diagram of the layout of the oxide active layer in FIG4 ;

[0076] FIG10 is a schematic diagram of the layout of the second gate metal layer oxide active layer and the third gate metal layer in FIG4;

[0077] FIG11 is a schematic diagram of a layout in which an oxide active layer and a third gate metal layer are added to FIG7 ;

[0078] FIG12 is a schematic diagram of a via hole formed on an interlayer insulating layer;

[0079] FIG13 is a schematic diagram of a layout in which a first source / drain metal layer is added on the basis of FIG11 ;

[0080] FIG14 is a schematic diagram of the layout of the first source / drain metal layer added in FIG13;

[0081] FIG15 is a schematic diagram of a layout in which a first source / drain metal layer is added on the basis of FIG7 ;

[0082] FIG16 is a schematic diagram showing a layout in which a first source / drain metal layer is added on the basis of FIG10;

[0083] FIG17 is a schematic diagram of a layout in which a second source / drain metal layer is added on the basis of FIG13 ;

[0084] FIG18 is a schematic diagram of the layout of the second source / drain metal layer added in FIG17 ;

[0085] FIG19 is a schematic diagram of a via hole formed on the first flat layer in FIG17 ;

[0086] FIG20 is a schematic diagram of the layout of the first source-drain metal layer and the second source-drain metal layer in FIG4 ;

[0087] FIG21 is a schematic diagram of the layout of the third source / drain metal layer in FIG4 ;

[0088] FIG22 is a schematic diagram of a via formed on the second flat layer in FIG4 ;

[0089] FIG23 is a schematic diagram of the layout of the second source-drain metal layer and the third source-drain metal layer in FIG4 ;

[0090] FIG24 is a schematic diagram of the layout of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer in FIG4 ;

[0091] FIG25 is a schematic diagram of a via hole formed on the third flat layer in FIG4 ;

[0092] FIG26 is a schematic diagram showing the layout of the second source-drain metal layer, the third source-drain metal layer, and the anode layer in a column unit provided by an embodiment of the present disclosure;

[0093] FIG27 is a schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0094] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0095] Referring to Figures 1 and 2, an embodiment of the present disclosure provides a display substrate, including: a base substrate, and a plurality of sub-pixels and a plurality of data lines (e.g., a first data line DA1, a second data line DA2, a third data line DA3, and a fourth data line DA4) all disposed on the base substrate. The sub-pixels include coupled sub-pixel driving circuits (including a first sub-pixel driving circuit Q1, a second sub-pixel driving circuit Q2, a third sub-pixel driving circuit Q3, and a fourth sub-pixel driving circuit Q4) and light-emitting elements.

[0096] The multiple sub-pixel driving circuits included in the multiple sub-pixels are divided into multiple columns of driving circuit columns (including a first driving circuit column QL1 and a second driving circuit column QL2), each column of driving circuit column includes a plurality of the sub-pixel driving circuits arranged along a first direction, and the multiple columns of driving circuit columns are divided into multiple column units QL, and the column unit QL includes at least two adjacent column of driving circuit columns; the data lines coupled to the sub-pixel driving circuits included in the column unit QL are located on the first side and / or second side of the column unit QL, the first side and the second side are opposite to each other along a second direction, and the second direction intersects with the first direction.

[0097] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of driving circuits and a plurality of columns of driving circuits. The plurality of rows of driving circuits are arranged along a first direction, and each row of driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. The plurality of columns of driving circuits are arranged along a second direction, and each column of driving circuits includes a plurality of sub-pixel driving circuits arranged along the first direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a longitudinal direction, and the second direction includes a transverse direction.

[0098] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0099] Exemplarily, the plurality of driving circuit columns are divided into a plurality of column units QL arranged along the second direction. The column unit QL includes at least two adjacent driving circuit columns, and each driving circuit column belongs to only one column unit QL.

[0100] Exemplarily, the data lines coupled to the sub-pixel driving circuit included in the column unit QL are only located on the first side of the column unit QL; or, the data lines coupled to the sub-pixel driving circuit included in the column unit QL are only located on the second side of the column unit QL; or, among the data lines coupled to the sub-pixel driving circuit included in the column unit QL, a portion of the data lines are located on the first side, and another portion of the data lines are located on the second side.

[0101] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present disclosure, the data line coupled to the sub-pixel driving circuit included in the column unit QL is arranged to be located on the first side and / or the second side of the column unit QL, so that the data line is far away from each sub-pixel driving circuit in the column unit QL. In this way, when the data signal transmitted by the data line changes, the impact on the stability of the key nodes in the sub-pixel driving circuit is small, thereby ensuring the stability of the sub-pixel driving circuit.

[0102] As shown in FIG1 and FIG2 , in some embodiments, the column unit QL includes at least one first driving circuit column QL1 and at least one second driving circuit column QL2 , and the first driving circuit column QL1 and the second driving circuit column QL2 are alternately arranged along the second direction;

[0103] The first driving circuit column QL1 includes a plurality of first sub-pixel driving circuits Q1 and a plurality of second sub-pixel driving circuits Q2. The first sub-pixel driving circuits Q1 and the second sub-pixel driving circuits Q2 are alternately arranged along the first direction. The first sub-pixel driving circuits Q1 are coupled to first-color light-emitting elements, and the second sub-pixel driving circuits Q2 are coupled to second-color light-emitting elements. Each of the first sub-pixel driving circuits Q1 in the first driving circuit column QL1 is coupled to the same data line, and each of the second sub-pixel driving circuits Q2 in the first driving circuit column QL1 is coupled to the same data line.

[0104] The sub-pixel driving circuit included in the second driving circuit column QL2 is coupled to the third color light emitting element; each sub-pixel driving circuit in the second driving circuit column QL2 is coupled to the same data line.

[0105] Exemplarily, the first color light emitting element includes a red light emitting element, the second color light emitting element includes a blue light emitting element, and the third color light emitting element includes a green light emitting element, but is not limited thereto.

[0106] Exemplarily, in adjacent first drive circuit columns QL1, the odd-numbered sub-pixel drive circuit in one column of the first drive circuit column QL1 is the first sub-pixel drive circuit Q1, and the even-numbered sub-pixel drive circuit is the second sub-pixel drive circuit Q2; and the even-numbered sub-pixel drive circuit in another column of the first drive circuit column QL1 is the first sub-pixel drive circuit Q1, and the odd-numbered sub-pixel drive circuit is the second sub-pixel drive circuit Q2.

[0107] Exemplarily, the same data line coupled to each first sub-pixel driver circuit Q1 in the first driver circuit column QL1, the same data line coupled to each second sub-pixel driver circuit Q2 in the first driver circuit column QL1, and the same data line coupled to each sub-pixel driver circuit in the second driver circuit column QL2 are located on the first side and / or second side of the column unit QL to which they belong. More specifically, for example, the same data line coupled to each first sub-pixel driver circuit Q1 in the first driver circuit column QL1 and the same data line coupled to each second sub-pixel driver circuit Q2 in the first driver circuit column QL1 are located on the first side of the column unit QL to which they belong; and the same data line coupled to each sub-pixel driver circuit in the second driver circuit column QL2 is located on the second side of the column unit QL to which they belong.

[0108] In the display substrate provided by the above-mentioned embodiment, it is possible to achieve that the light-emitting elements coupled to the sub-pixel driving circuits to which the data lines are coupled emit the same color of light. Therefore, when the shift register unit scans the sub-pixels row by row, that is, when the data line provides data signals to the sub-pixels coupled thereto in sequence, the voltage variation range of the data signal transmitted by the data line is very small or unchanged. In this way, the driving chip does not need to repeatedly jump and charge the data signal, and can ensure that the data line provides the sub-pixels coupled thereto with data signals within the corresponding data range, thereby effectively reducing the power consumption of the driving chip and reducing the overall power consumption of the display product.

[0109] In more detail, when displaying a red monochrome picture and a blue monochrome picture, the data signals transmitted by the first data line DA1 and the second data line DA2 will not jump, which effectively reduces the power consumption of the driving chip.

[0110] As shown in Figures 1 and 2, in some embodiments, the data lines coupled to each first sub-pixel driving circuit Q1 in the first driving circuit column QL1 and the data lines coupled to each second sub-pixel driving circuit Q2 in the first driving circuit column QL1 are both located on the first side of the column unit QL, and the data lines coupled to each sub-pixel driving circuit in the second driving circuit column QL2 are located on the second side of the column unit QL.

[0111] The above-mentioned setting method makes the distance between the data line and each sub-pixel driving circuit in the column unit QL farther, so that when the data signal transmitted by the data line changes, the impact on the stability of the key nodes in the sub-pixel driving circuit is relatively small, thereby ensuring the stability of the sub-pixel driving circuit.

[0112] The above-mentioned setting method enables the data lines corresponding to the coupled column units QL to be distributed on both sides of the column units QL. This method can not only ensure the connection reliability between the data lines and the sub-pixel driving circuits, but also effectively reduce the layout difficulty of the data lines and the column units QL.

[0113] As shown in FIG1 and FIG2 , in some embodiments, the column unit QL includes two first drive circuit columns QL1 and two second drive circuit columns QL2; each first sub-pixel drive circuit Q1 included in the two first drive circuit columns QL1 is coupled to the same first data line DA1; each second sub-pixel drive circuit Q2 included in the two first drive circuit columns QL1 is coupled to the same second data line DA2; each third sub-pixel drive circuit Q3 included in the first second drive circuit column QL2 is coupled to the same third data line DA3; each fourth sub-pixel drive circuit Q4 included in the second second drive circuit column QL2 is coupled to the same fourth data line DA4;

[0114] The first data line DA1 , the second data line DA2 , the third data line DA3 , and the fourth data line DA4 are sequentially arranged along the second direction.

[0115] Exemplarily, the first data line DA1 and the second data line DA2 are located at a first side of the column unit QL, and the third data line DA3 and the fourth data line DA4 are located at a second side of the column unit QL.

[0116] Exemplarily, each data line is coupled to a corresponding sub-pixel driving circuit via a corresponding conductive connection portion 513. At least a portion of the data line extends along the first direction. At least a portion of the conductive connection portion 513 extends along the second direction.

[0117] Exemplarily, the data line is provided in the same layer and material as the third source / drain metal layer in the display substrate, and the conductive connection portion 513 is provided in the same layer and material as the second source / drain metal layer in the display substrate.

[0118] The above-mentioned setting method effectively reduces the number of data lines and effectively reduces the difficulty of layout of data lines and column units QL. Moreover, in the display substrate provided by the above-mentioned embodiment, it can be achieved that the light-emitting elements coupled to the sub-pixel driving circuits corresponding to the data lines have the same luminous color. Therefore, when the shift register unit scans the sub-pixels row by row, that is, when the data line provides data signals to the sub-pixels coupled thereto in turn, the voltage variation range of the data signal transmitted by the data line is very small or unchanged. In this way, the driver chip does not need to repeatedly jump and charge the data signal, and can ensure that the data line provides the sub-pixels coupled thereto with data signals in the corresponding data range, thereby effectively reducing the power consumption of the driver chip and reducing the overall power consumption of the display product. The above-mentioned setting method enables the display substrate to be compatible with ADP (English: Advanced Diamond Pixel) technology.

[0119] The first data line DA1, the second data line DA2, the third data line DA3 and the fourth data line DA4 are arranged on the first side and / or the second side of the column unit QL, so that the data lines are far away from each sub-pixel driving circuit in the column unit QL, thereby reducing the coupling capacitance between the data lines and the key nodes in the sub-pixel driving circuit. In this way, when the data signal transmitted by the data line changes, the impact on the stability of the key nodes in the sub-pixel driving circuit is small, thereby ensuring the stability of the sub-pixel driving circuit.

[0120] As shown in FIG1 and FIG2 , in some embodiments, the column unit QL is divided into a plurality of sub-units QLZ arranged in sequence along the first direction, and the sub-unit QLZ includes two rows of driving circuits arranged along the first direction;

[0121] The first row driving circuit row QH1 includes a first sub-pixel driving circuit Q1, a third sub-pixel driving circuit Q3, a second sub-pixel driving circuit Q2, and a fourth sub-pixel driving circuit Q4 arranged in sequence along the second direction; the second row driving circuit row QH2 includes a second sub-pixel driving circuit Q2, a third sub-pixel driving circuit Q3, a first sub-pixel driving circuit Q1, and a fourth sub-pixel driving circuit Q4 arranged in sequence along the second direction;

[0122] The first data line DA1 and the second data line DA2 are located at a first side of the column unit QL, and the third data line DA3 and the fourth data line DA4 are located at a second side of the column unit QL.

[0123] Exemplarily, the sub-unit QLZ serves as the smallest repeating unit in the display substrate, and the display substrate includes a plurality of sub-units QLZ distributed in an array.

[0124] Exemplarily, the first data line DA1 is coupled to the first sub-pixel driving circuit Q1 in the first row driver circuit row QH1, and to the first sub-pixel driving circuit Q1 in the second row driver circuit row QH2. The second data line DA2 is coupled to the second sub-pixel driving circuit Q2 in the first row driver circuit row QH1, and to the second sub-pixel driving circuit Q2 in the second row driver circuit row QH2. The third data line DA3 is coupled to the third sub-pixel driving circuit Q3 in the first row driver circuit row QH1, and to the third sub-pixel driving circuit Q3 in the second row driver circuit row QH2. The fourth data line DA4 is coupled to the fourth sub-pixel driving circuit Q4 in the first row driver circuit row QH1, and to the fourth sub-pixel driving circuit Q4 in the second row driver circuit row QH2.

[0125] The above arrangement effectively reduces the number of data lines and the difficulty of laying out the data lines and column units QL. Furthermore, the above arrangement can effectively reduce the power consumption of the driver chip and the overall power consumption of the display product. Furthermore, by laying out each data line in the above manner, the data line is relatively far away from each sub-pixel driver circuit in the column unit QL. This means that changes in the data signals transmitted by the data lines have minimal impact on the stability of key nodes in the sub-pixel driver circuit, thereby ensuring the stability of the sub-pixel driver circuit.

[0126] As shown in FIG3 to FIG26 , in some embodiments, the first sub-pixel driving circuit Q1 in the first row driving circuit QH1 includes: a driving transistor (i.e., a third transistor T3) and a data writing transistor (i.e., a fourth transistor T4), wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the first data line DA1 is coupled to the first electrode of the data writing transistor via a first conductive connection portion 51;

[0127] As shown in Figures 4, 5, 6, 13, 17, 21, 23 and 24, the data writing transistor includes a data writing active layer (i.e., the fourth active layer 14), and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the first data main portion DA11 included in the first data line DA1 on the base substrate and the orthographic projection of the second data main portion DA21 included in the second data line DA2 on the base substrate.

[0128] Illustratively, the first data line DA1 includes a first data main portion DA11 and a first data extension portion DA12. The first data main portion DA11 includes at least a portion extending along the first direction, and the first data extension portion DA12 protrudes from the first data main portion DA11 along the second direction. The second data line DA2 includes a second data main portion DA21 and a second data extension portion DA22. The second data main portion DA21 includes at least a portion extending along the first direction, and the second data extension portion DA22 protrudes from the first data main portion DA11 along the second direction.

[0129] Exemplarily, the first data main portion DA11 and the first sub-pixel driving circuit Q1 layout area are arranged along the second direction. At least a portion of the second data main portion DA21 is located in the first sub-pixel driving circuit Q1 layout area.

[0130] Exemplarily, the display substrate further includes a reference signal line Vref and an initialization signal line Vinit1; the first conductive connection portion 31 includes a first sub-portion 311 and a second sub-portion 312 coupled to each other, the first sub-portion 311 extending along the second direction, the second sub-portion 312 extending along the first direction, the first sub-portion 311 coupled to the first data line DA1, and the second sub-portion 312 coupled to the first electrode of the data write transistor;

[0131] At least a portion of the orthographic projection of the first sub-portion 311 on the base substrate is located between the orthographic projection of the reference signal line Vref on the base substrate and the orthographic projection of the initialization signal line Vinit1 on the base substrate.

[0132] Exemplarily, the first sub-portion 311 and the second sub-portion 312 are formed into an integral structure.

[0133] Exemplarily, the orthographic projection of the first sub-portion 311 on the substrate overlaps with the orthographic projection of the initialization signal line Vinit1 on the substrate.

[0134] The above-mentioned setting couples the first data line DA1 with the first electrode of the data writing transistor through the first conductive connection part 31, so that the first data main part DA11 can be set at a position far away from the key node of the sub-pixel driving circuit, while reducing the influence of the data line on the key node, and also reducing the layout difficulty of the first data line DA1.

[0135] The above-mentioned setting sets the orthographic projection of the data writing active layer on the base substrate, which is located between the orthographic projection of the first data main part DA11 on the base substrate and the orthographic projection of the second data main part DA21 on the base substrate, so that the first data line DA1 and the second data line DA2 can both be located on the first side of the column unit QL and can be as close to the edge of the column unit QL as possible. This not only reduces the influence of the data line on the key nodes in the current column unit QL, but also helps to reduce the influence of the data line on the key nodes in the adjacent column unit QL.

[0136] As shown in FIG4, FIG5, FIG6, FIG13, FIG17, FIG21, FIG23 and FIG24, in some embodiments, the first sub-pixel driving circuit Q1 in the second row driving circuit row QH2 includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the first data line DA1 is coupled to the first electrode of the data writing transistor via a second conductive connection portion 32;

[0137] The data writing transistor includes a data writing active layer, the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the second data main portion DA21 included in the second data line DA2 on the base substrate and the orthographic projection of the third data main portion DA31 included in the third data line DA3 on the base substrate.

[0138] Exemplarily, the third data line DA3 includes a third data main portion DA31 and a third data extension portion DA32, wherein the third data main portion DA31 includes at least a portion extending along the first direction, and the third data extension portion DA32 protrudes from the first data main portion DA11 along the second direction.

[0139] Exemplarily, the second conductive connection portion 32 includes a third sub-portion 321 and a fourth sub-portion 322 coupled to each other, at least a portion of the third sub-portion 321 extends along the second direction, and the fourth sub-portion 322 at least partially surrounds the sensing opening area of ​​the display substrate, the third sub-portion 321 is coupled to the first data line DA1, and the fourth sub-portion 322 is coupled to the first electrode of the data write transistor.

[0140] Illustratively, the third sub-portion 321 and the fourth sub-portion 322 are formed into an integral structure.

[0141] Illustratively, the fourth sub-portion 322 bypasses the sensing opening region and is coupled to the first electrode of the data writing transistor.

[0142] Exemplarily, the display substrate further includes a reference signal line Vref and an initialization signal line Vinit1; at least a portion of the orthographic projection of the third sub-portion 321 on the base substrate is located between the orthographic projection of the reference signal line Vref on the base substrate and the orthographic projection of the initialization signal line Vinit1 on the base substrate.

[0143] Exemplarily, the orthographic projection of the third sub-portion 321 on the substrate overlaps with the orthographic projection of the initialization signal line Vinit1 on the substrate.

[0144] Exemplarily, the orthographic projection of the fourth sub-portion 322 on the substrate substrate at least partially overlaps with the orthographic projection of the initialization signal line Vinit1 on the substrate substrate; and / or, the orthographic projection of the fourth sub-portion 322 on the substrate substrate at least partially overlaps with the orthographic projection of the reference signal line Vref on the substrate substrate.

[0145] The above-mentioned setting couples the first data line DA1 with the first electrode of the data writing transistor through the second conductive connection part 32, so that the first data main part DA11 can be set at a position far away from the key node of the sub-pixel driving circuit, while reducing the influence of the data line on the key node, and also reducing the layout difficulty of the first data line DA1.

[0146] The above-mentioned setting sets the orthographic projection of the data writing active layer on the base substrate, which is located between the orthographic projection of the second data main part DA21 on the base substrate and the orthographic projection of the third data main part DA31 on the base substrate, so that the second data line DA2 can be located on the first side of the column unit QL, and the third data line DA3 can be located on the second side of the column unit QL, and can be as close to the edge of the column unit QL as possible. This not only reduces the influence of the data line on the key nodes in the current column unit QL, but also helps to reduce the influence of the data line on the key nodes in the adjacent column unit QL.

[0147] As shown in FIG4, FIG5, FIG6, FIG13, FIG17, FIG21, FIG23 and FIG24, in some embodiments, the second sub-pixel driving circuit Q2 in the first row driving circuit QH1 includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the second data line DA2 is coupled to the first electrode of the data writing transistor via a third conductive connection portion 33;

[0148] The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the second data main portion DA21 included in the second data line DA2 on the base substrate and the orthographic projection of the third data main portion DA31 included in the third data line DA3 on the base substrate.

[0149] Exemplarily, the display substrate also includes a first scan line GA1, and the second sub-pixel driving circuit Q2 in the first row driving circuit row QH1 also includes a compensation transistor, the first electrode of the compensation transistor is coupled to the first electrode of the driving transistor, the second electrode of the compensation transistor is coupled to the gate of the driving transistor, and the gate of the compensation transistor is coupled to the corresponding first scan line GA1; the third conductive connection portion 33 includes a fifth sub-portion 331 and a sixth sub-portion 332 coupled to each other, the fifth sub-portion 331 is coupled to the second data line DA2, and the sixth sub-portion 332 is coupled to the first electrode of the data writing transistor; the orthographic projection of the fifth sub-portion 331 on the base substrate at least partially overlaps with the orthographic projection of the first scan line GA1 on the base substrate.

[0150] Illustratively, the fifth sub-portion 331 and the sixth sub-portion 332 form an integral structure.

[0151] Exemplarily, the first scanning line GA1 includes a first scanning layer GA11 and a second scanning layer GA12. The first scanning layer is provided in the same layer and material as the second gate metal layer in the display substrate, and the second scanning layer is provided in the same layer and material as the third gate metal layer in the display substrate.

[0152] Exemplarily, the orthographic projection of the fifth sub-portion 331 on the base substrate at least partially overlaps with the orthographic projection of the first scanning layer on the base substrate; and / or, the orthographic projection of the sixth sub-portion 332 on the base substrate at least partially overlaps with the orthographic projection of the second scanning layer on the base substrate.

[0153] Exemplarily, the display substrate also includes a second scan line GA2; the gate of the data writing transistor is coupled to the corresponding second scan line GA2; at least part of the orthographic projection of the fifth sub-portion 331 on the base substrate is located between the orthographic projection of the second scan line GA2 on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate.

[0154] The above-mentioned setting of coupling the second data line DA2 to the first electrode of the data writing transistor through the third conductive connection part 33 allows the second data main part DA21 to be set at a position far away from the key node of the sub-pixel driving circuit, while reducing the influence of the data line on the key node, and also reducing the layout difficulty of the second data line DA2.

[0155] The above-mentioned setting sets the orthographic projection of the data writing active layer on the base substrate, which is located between the orthographic projection of the second data main part DA21 on the base substrate and the orthographic projection of the third data main part DA31 on the base substrate, so that the second data line DA2 can be located on the first side of the column unit QL, and the third data line DA3 can be located on the second side of the column unit QL, and can be as close to the edge of the column unit QL as possible. This not only reduces the influence of the data line on the key nodes in the current column unit QL, but also helps to reduce the influence of the data line on the key nodes in the adjacent column unit QL.

[0156] As shown in FIG4, FIG5, FIG6, FIG13, FIG17, FIG21, FIG23 and FIG24, in some embodiments, the second sub-pixel driving circuit Q2 in the second row driving circuit row QH2 includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the second data line DA2 is coupled to the first electrode of the data writing transistor via a fourth conductive connection portion 34;

[0157] The data writing transistor includes a data writing active layer, and the data writing active layer's orthographic projection on the base substrate is located between the orthographic projection of the first data main portion DA11 included in the first data line DA1 on the base substrate and the orthographic projection of the second data main portion DA21 included in the second data line DA2 on the base substrate.

[0158] Exemplarily, the display substrate also includes a second scan line GA2; the gate of the data write transistor is coupled to the corresponding second scan line GA2; the fourth conductive connection portion 34 includes a seventh sub-portion 341 and an eighth sub-portion 342 coupled to each other, the seventh sub-portion 341 extends along the second direction, the eighth sub-portion 342 extends along the first direction, the seventh sub-portion 341 is coupled to the second data line DA2, and the eighth portion is coupled to the first electrode of the data write transistor; at least part of the orthographic projection of the seventh sub-portion 341 on the base substrate is located between the orthographic projection of the second scan line GA2 on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate.

[0159] Illustratively, the seventh sub-portion 341 and the eighth sub-portion 342 form an integral structure.

[0160] Exemplarily, exemplary, the orthographic projection of the seventh sub-portion 341 on the substrate substrate at least partially overlaps with the orthographic projection of the first scanning layer on the substrate substrate; and / or, the orthographic projection of the seventh sub-portion 341 on the substrate substrate at least partially overlaps with the orthographic projection of the second scanning layer on the substrate substrate.

[0161] The above-mentioned setting of coupling the second data line DA2 to the first electrode of the data writing transistor through the fourth conductive connection part 34 allows the second data main part DA21 to be set at a position far away from the key node of the sub-pixel driving circuit, while reducing the influence of the data line on the key node, and also reducing the layout difficulty of the second data line DA2.

[0162] The above-mentioned setting sets the orthographic projection of the data writing active layer on the base substrate, which is located between the orthographic projection of the first data main part DA11 on the base substrate and the orthographic projection of the second data main part DA21 on the base substrate, so that the first data line DA1 and the second data line DA2 can both be located on the first side of the column unit QL and can be as close to the edge of the column unit QL as possible. This not only reduces the influence of the data line on the key nodes in the current column unit QL, but also helps to reduce the influence of the data line on the key nodes in the adjacent column unit QL.

[0163] As shown in FIG4, FIG5, FIG6, FIG13, FIG17, FIG21, FIG23 and FIG24, in some embodiments, the third sub-pixel driving circuit Q3 in the first row driving circuit QH1 includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the third data line DA3 is coupled to the first electrode of the data writing transistor via a fifth conductive connection portion 35;

[0164] The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the second data main portion DA21 included in the second data line DA2 on the base substrate and the orthographic projection of the third data main portion DA31 included in the third data line DA3 on the base substrate.

[0165] Exemplarily, the fifth conductive connection portion 35 includes a ninth sub-portion 351 and a tenth sub-portion 352 coupled to each other, at least a portion of the ninth sub-portion 351 extends along the second direction, the tenth sub-portion 352 at least partially surrounds the sensing opening area of ​​the display substrate, the ninth sub-portion 351 is coupled to the third data line DA3, and the tenth sub-portion 352 is coupled to the first electrode of the data write transistor.

[0166] Illustratively, the ninth sub-portion 351 and the tenth sub-portion 352 are formed into an integral structure.

[0167] Illustratively, the tenth sub-portion 352 bypasses the sensing opening region and is coupled to the first electrode of the data writing transistor.

[0168] Illustratively, the orthographic projection of the ninth sub-portion 351 on the substrate partially overlaps with the orthographic projection of the initialization signal line Vinit1 on the substrate. The orthographic projection of the ninth sub-portion 351 on the substrate does not overlap with the orthographic projection of the reference signal line Vref on the substrate.

[0169] Exemplarily, the display substrate further includes a reference signal line Vref and an initialization signal line Vinit1; at least a portion of the orthographic projection of the ninth sub-portion 351 on the base substrate is located between the orthographic projection of the reference signal line Vref on the base substrate and the orthographic projection of the initialization signal line Vinit1 on the base substrate; the orthographic projection of the tenth sub-portion 352 on the base substrate at least partially overlaps with the orthographic projection of the initialization signal line Vinit1 on the base substrate; and / or the orthographic projection of the tenth sub-portion 352 on the base substrate at least partially overlaps with the orthographic projection of the reference signal line Vref on the base substrate.

[0170] The above-mentioned setting couples the third data line DA3 with the first electrode of the data writing transistor through the fifth conductive connection part 35, so that the third data main part DA31 can be set at a position far away from the key node of the sub-pixel driving circuit, while reducing the influence of the data line on the key node, and also reducing the layout difficulty of the third data line DA3.

[0171] The above-mentioned setting sets the orthographic projection of the data writing active layer on the base substrate, which is located between the orthographic projection of the second data main part DA21 on the base substrate and the orthographic projection of the third data main part DA31 on the base substrate, so that the second data line DA2 can be located on the first side of the column unit QL, and the third data line DA3 can be located on the second side of the column unit QL, and can be as close to the edge of the column unit QL as possible. This not only reduces the influence of the data line on the key nodes in the current column unit QL, but also helps to reduce the influence of the data line on the key nodes in the adjacent column unit QL.

[0172] As shown in FIG4, FIG5, FIG6, FIG13, FIG17, FIG21, FIG23 and FIG24, in some embodiments, the third sub-pixel driving circuit Q3 in the second row driving circuit row QH2 includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the third data line DA3 is coupled to the first electrode of the data writing transistor via a sixth conductive connection portion 36;

[0173] The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the second data main portion DA21 included in the second data line DA2 on the base substrate and the orthographic projection of the third data main portion DA31 included in the third data line DA3 on the base substrate.

[0174] Exemplarily, the display substrate also includes a second scan line GA2; the gate of the data write transistor is coupled to the corresponding second scan line GA2; the sixth conductive connection portion 36 includes an eleventh sub-portion 361 and a twelfth sub-portion 362 coupled to each other, the eleventh sub-portion 361 extends along the second direction, the twelfth sub-portion 362 extends along the first direction, the eleventh sub-portion 361 is coupled to the third data line DA3, and the twelfth sub-portion 362 is coupled to the first electrode of the data write transistor.

[0175] Illustratively, the eleventh sub-portion 361 and the twelfth sub-portion 362 are formed into an integral structure.

[0176] Illustratively, at least a portion of the orthographic projection of the eleventh sub-portion 361 on the base substrate is located between the orthographic projection of the second scan line GA2 on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate.

[0177] Illustratively, the orthographic projection of the eleventh sub-portion 361 on the base substrate at least partially overlaps with the orthographic projection of the first scanning line GA1 on the base substrate.

[0178] Illustratively, the orthographic projection of the eleventh sub-portion 361 on the base substrate at least partially overlaps with the orthographic projection of the first scanning layer on the base substrate. And / or, the orthographic projection of the eleventh sub-portion 361 on the base substrate at least partially overlaps with the orthographic projection of the second scanning layer on the base substrate.

[0179] The above-mentioned setting couples the third data line DA3 with the first electrode of the data writing transistor through the sixth conductive connection part 36, so that the third data main part DA31 can be set at a position far away from the key node of the sub-pixel driving circuit, while reducing the influence of the data line on the key node, and also reducing the layout difficulty of the third data line DA3.

[0180] The above-mentioned setting sets the orthographic projection of the data writing active layer on the base substrate, which is located between the orthographic projection of the second data main part DA21 on the base substrate and the orthographic projection of the third data main part DA31 on the base substrate, so that the second data line DA2 can be located on the first side of the column unit QL, and the third data line DA3 can be located on the second side of the column unit QL, and can be as close to the edge of the column unit QL as possible. This not only reduces the influence of the data line on the key nodes in the current column unit QL, but also helps to reduce the influence of the data line on the key nodes in the adjacent column unit QL.

[0181] As shown in FIG4, FIG5, FIG6, FIG13, FIG17, FIG21, FIG23 and FIG24, in some embodiments, the fourth sub-pixel driving circuit Q4 in the first row driving circuit row QH1 includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the fourth data line DA4 is coupled to the first electrode of the data writing transistor via a seventh conductive connection portion 37;

[0182] The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the third data main portion DA31 included in the third data line DA3 on the base substrate and the orthographic projection of the fourth data main portion DA41 included in the fourth data line DA4 on the base substrate.

[0183] Exemplarily, the fourth data line DA4 includes a fourth data main portion DA41 and a fourth data extension portion DA42. The fourth data main portion DA41 includes at least a portion extending along the first direction, and the fourth data extension portion DA42 protrudes from the fourth data main portion DA41 along the second direction.

[0184] Exemplarily, the display substrate further includes a first scan line GA1, and the fourth sub-pixel driving circuit Q4 in the first row driving circuit row QH1 further includes a compensation transistor, a first electrode of the compensation transistor is coupled to the first electrode of the driving transistor, a second electrode of the compensation transistor is coupled to the gate of the driving transistor, and the gate of the compensation transistor is coupled to the corresponding first scan line GA1;

[0185] The seventh conductive connection portion 37 includes a thirteenth sub-portion 371 and a fourteenth sub-portion 372 coupled to each other, the thirteenth sub-portion 371 is coupled to the fourth data line DA4, and the fourteenth sub-portion 372 is coupled to the first electrode of the data writing transistor; the orthographic projection of the thirteenth sub-portion 371 on the substrate at least partially overlaps with the orthographic projection of the first scanning line GA1 on the substrate.

[0186] Illustratively, the thirteenth sub-portion 371 and the fourteenth sub-portion 372 are formed into an integral structure.

[0187] Illustratively, the orthographic projection of the thirteenth sub-portion 371 on the base substrate at least partially overlaps with the orthographic projection of the first scanning layer on the base substrate. And / or, the orthographic projection of the thirteenth sub-portion 371 on the base substrate at least partially overlaps with the orthographic projection of the second scanning layer on the base substrate.

[0188] Illustratively, the orthographic projection of the thirteenth sub-portion 371 on the base substrate is located between the orthographic projection of the second scan line GA2 on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate.

[0189] The above-mentioned setting couples the fourth data line DA4 with the first electrode of the data writing transistor through the seventh conductive connection part 37, so that the fourth data main part DA41 can be set at a position far away from the key node of the sub-pixel driving circuit, while reducing the influence of the data line on the key node, and also reducing the layout difficulty of the fourth data line DA4.

[0190] The above-mentioned setting sets the orthographic projection of the data writing active layer on the base substrate, which is located between the orthographic projection of the third data main part DA31 included in the third data line DA3 on the base substrate, and the orthographic projection of the fourth data main part DA41 included in the fourth data line DA4 on the base substrate, so that the third data line DA3 and the fourth data line DA4 can both be located on the second side of the column unit QL and as close to the edge of the column unit QL as possible. This not only reduces the influence of the data line on the key nodes in the current column unit QL, but also helps to reduce the influence of the data line on the key nodes in the adjacent column unit QL.

[0191] As shown in FIG4, FIG5, FIG6, FIG13, FIG17, FIG21, FIG23 and FIG24, in some embodiments, the fourth sub-pixel driving circuit Q4 in the second row driving circuit row QH2 includes: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the fourth data line DA4 is coupled to the first electrode of the data writing transistor via an eighth conductive connection portion 38;

[0192] The data writing transistor includes a data writing active layer, the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the third data main portion DA31 included in the third data line DA3 on the base substrate and the orthographic projection of the fourth data main portion DA41 included in the fourth data line DA4 on the base substrate.

[0193] Exemplarily, the display substrate further includes a reference signal line Vref and an initialization signal line Vinit1; the eighth conductive connection portion 38 includes a fifteenth sub-portion 381 and a sixteenth sub-portion 382 coupled to each other, at least a portion of the fifteenth sub-portion 381 extending along the second direction, and at least a portion of the sixteenth sub-portion 382 extending along the first direction, the fifteenth sub-portion 381 coupled to the fourth data line DA4, and the sixteenth sub-portion 382 coupled to the first electrode of the data write transistor;

[0194] At least a portion of the orthographic projection of the fifteenth sub-portion 381 on the base substrate is located between the orthographic projection of the reference signal line Vref on the base substrate and the orthographic projection of the initialization signal line Vinit1 on the base substrate.

[0195] Illustratively, the fifteenth sub-portion 381 and the sixteenth sub-portion 382 form an integral structure.

[0196] Illustratively, an orthographic projection of the fifteenth sub-portion 381 on the substrate at least partially overlaps with an orthographic projection of the initialization signal line Vinit1 on the substrate.

[0197] The above-mentioned setting couples the fourth data line DA4 with the first electrode of the data writing transistor through the eighth conductive connection part 38, so that the fourth data main part DA41 can be set at a position far away from the key node of the sub-pixel driving circuit, while reducing the influence of the data line on the key node, and also reducing the layout difficulty of the fourth data line DA4.

[0198] The above-mentioned setting sets the orthographic projection of the data writing active layer on the base substrate, which is located between the orthographic projection of the third data main part DA31 included in the third data line DA3 on the base substrate, and the orthographic projection of the fourth data main part DA41 included in the fourth data line DA4 on the base substrate, so that the third data line DA3 and the fourth data line DA4 can both be located on the second side of the column unit QL and as close to the edge of the column unit QL as possible. This not only reduces the influence of the data line on the key nodes in the current column unit QL, but also helps to reduce the influence of the data line on the key nodes in the adjacent column unit QL.

[0199] As shown in FIG18 , in some embodiments, the first sub-portion 311 , the fifth sub-portion 331 , the seventh sub-portion 341 , the eleventh sub-portion 361 , the thirteenth sub-portion 371 and the fifteenth sub-portion 381 all extend as far as possible toward the middle region of the column unit QL to better improve the uniformity of the display substrate.

[0200] As shown in Figures 4, 6, 13, 14, 17, 21, 23 and 24, in some embodiments, each sub-pixel driving circuit in the display substrate includes a driving transistor and a compensation transistor (i.e., a second transistor T2), the first electrode of the compensation transistor is coupled to the first electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor through a first switching graphic 51; at least a portion of the orthographic projection of the first switching graphic 51 on the base substrate is located between the orthographic projection of the second data line DA2 on the base substrate and the orthographic projection of the third data line DA3 on the base substrate.

[0201] Exemplarily, the location of the first switching pattern 51 and the structure coupled to the first switching pattern 51 form the first node N1 of the sub-pixel driving circuit.

[0202] Exemplarily, the first transfer pattern 51 is provided in the same layer and with the same material as the first source / drain metal layer in the display substrate.

[0203] The above-mentioned setting of at least a portion of the orthographic projection of the first switching pattern 51 on the base substrate is located between the orthographic projection of the second data line DA2 on the base substrate and the orthographic projection of the third data line DA3 on the base substrate, which can realize the centering of the first switching pattern 51, so that the first switching pattern 51 is far away from the first data line DA1, the second data line DA2, the third data line DA3 and the fourth data line DA4, thereby minimizing the influence of the data signal jump transmitted on the data line on the first node N1, thereby effectively improving the crosstalk phenomenon.

[0204] As shown in Figures 4, 6, 13, 14, 17, 21, 23 and 24, in some embodiments, the first transfer graphic 51 includes a first end 511, a second end 512, and a connecting portion 513 coupled to the first end 511 and the second end 512, respectively, the first end 511 is coupled to the gate of the driving transistor, the second end 512 is coupled to the second pole of the compensation transistor, and the connecting portion 513 extends along the second direction.

[0205] Illustratively, the first end portion 511 , the second end portion 512 and the connecting portion 513 form an integral structure.

[0206] Illustratively, the first end 511 and the second end 512 are at least partially staggered along the first direction.

[0207] The above-mentioned setting of the connecting portion 513 extending along the second direction can achieve the goal of placing at least a portion of the first switching pattern 51 as close as possible to the middle area of ​​the column unit QL, so that the first switching pattern 51 and the first data line DA1, the second data line DA2, the third data line DA3 and the fourth data line DA4 are all at a long distance, thereby minimizing the impact of the data signal jump transmitted on the data line on the first node N1, thereby effectively improving the crosstalk phenomenon.

[0208] As shown in Figures 4, 6, 13, 14, 17, 21, 23 and 24, in some embodiments, within the layout area of ​​the first row driving circuit row QH1: the orthographic projection of the first switching pattern 51 located in the layout area of ​​the second sub-pixel driving circuit Q2 on the substrate, and the orthographic projection of the first switching pattern 51 located in the layout area of ​​the third sub-pixel driving circuit Q3 on the substrate, are both located between the orthographic projection of the second data line DA2 on the substrate and the orthographic projection of the third data line DA3 on the substrate.

[0209] As shown in Figures 4, 6, 13, 14, 17, 21, 23 and 24, in some embodiments, within the layout area of ​​the first row driver circuit row QH1: the orthographic projection of the first end portion 511 located in the layout area of ​​the first sub-pixel driver circuit Q1 on the substrate at least partially overlaps with the orthographic projection of the second data line DA2 on the substrate; the orthographic projection of the first end portion 511 located in the layout area of ​​the fourth sub-pixel driver circuit Q4 on the substrate at least partially overlaps with the orthographic projection of the third data line DA3 on the substrate.

[0210] As shown in Figures 4, 6, 13, 14, 17, 21, 23 and 24, in some embodiments, within the layout area of ​​the second row driving circuit row QH2: the orthographic projection of the first switching pattern 51 located in the layout area of ​​the first sub-pixel driving circuit Q1 on the substrate, and the orthographic projection of the first switching pattern 51 located in the layout area of ​​the third sub-pixel driving circuit Q3 on the substrate, are both located between the orthographic projection of the second data line DA2 on the substrate and the orthographic projection of the third data line DA3 on the substrate.

[0211] As shown in Figures 4, 6, 13, 14, 17, 21, 23 and 24, in some embodiments, the orthographic projection of the first end portion 511 located in the layout area of ​​the second sub-pixel driving circuit Q2 on the base substrate at least partially overlaps with the orthographic projection of the second data line DA2 on the base substrate; the orthographic projection of the first end portion 511 located in the layout area of ​​the fourth sub-pixel driving circuit Q4 on the base substrate at least partially overlaps with the orthographic projection of the third data line DA3 on the base substrate.

[0212] The above-mentioned setting method can achieve the goal of placing at least a portion of the first transfer pattern 51 as close as possible to the middle area of ​​the column unit QL, so that at least a portion of the first transfer pattern 51 can have a relatively long distance from the first data line DA1, the second data line DA2, the third data line DA3 and the fourth data line DA4, thereby minimizing the impact of the data signal jump transmitted on the data line on the first node N1, thereby effectively improving the crosstalk phenomenon.

[0213] Furthermore, the above configuration can minimize the overlapping area between the data line and the node inside the column unit QL, and is also beneficial to reducing the loading of the scanning signal in the display substrate.

[0214] As shown in FIG. 3 and FIG. 17 to FIG. 26 , in some embodiments, the display substrate further includes a power layer VDD, and the orthographic projection of the power layer VDD on the base substrate covers the orthographic projection of the first transfer pattern 51 on the base substrate.

[0215] Exemplarily, the orthographic projection of the power layer VDD on the base substrate completely covers the orthographic projection of the first transfer pattern 51 on the base substrate.

[0216] Exemplarily, an orthographic projection of the power layer VDD on the base substrate at least partially overlaps with an orthographic projection of the first transfer pattern 51 on the base substrate.

[0217] The above configuration enables the power layer VDD to shield and protect the first node, thereby preventing the first node from being disturbed.

[0218] As shown in Figures 3 and 17 to 26, in some embodiments, the power layer VDD includes multiple first power lines VDD1 and multiple second power lines VDD2, the first power lines VDD1 and the second power lines VDD2 are cross-arranged, and the first power lines VDD1 are coupled to the second power lines VDD2.

[0219] Exemplarily, the orthographic projection of the first power line VDD1 on the base substrate covers the orthographic projection of the first end portion 511 on the base substrate.

[0220] Exemplarily, an orthographic projection of the first power line VDD1 on the base substrate at least partially overlaps with an orthographic projection of the connecting portion 513 on the base substrate.

[0221] Exemplarily, an orthographic projection of the first power line VDD1 on the base substrate at least partially overlaps with an orthographic projection of the second end portion 512 on the base substrate.

[0222] Exemplarily, the orthographic projection of the second power line VDD2 on the base substrate covers the orthographic projection of the second end portion 512 on the base substrate.

[0223] Exemplarily, an orthographic projection of the second power line VDD2 on the base substrate at least partially overlaps with an orthographic projection of the connecting portion 513 on the base substrate.

[0224] Exemplarily, the orthographic projection of the second power line VDD2 on the base substrate does not overlap with the orthographic projection of the first end portion 511 on the base substrate.

[0225] Exemplarily, the plurality of first power lines VDD1 are arranged along the first direction, and the first power lines VDD1 include at least a portion extending along the second direction. The plurality of second power lines VDD2 are arranged along the second direction, and the second power lines VDD2 include at least a portion extending along the first direction.

[0226] Exemplarily, the first power line VDD1 is provided in the same layer and material as the second source / drain metal layer in the display substrate, and the second power line VDD2 is provided in the same layer and material as the third source / drain metal layer in the display substrate.

[0227] Exemplarily, the first power line VDD1 is coupled to the plurality of second power lines VDD2 respectively, and the second power line VDD2 is coupled to the plurality of first power lines VDD1 respectively.

[0228] The power layer VDD is configured to include the first power line VDD1 and the second power line VDD2 , so that the first power line VDD1 and the second power line VDD2 form a grid structure, effectively reducing the loading of the power layer VDD.

[0229] The above configuration enables the first power line VDD1 and the second power line VDD2 to shield and protect the first node, thereby preventing the first node from being disturbed.

[0230] As shown in Figures 13 to 15, in some embodiments, the display substrate further includes a plurality of compensation initial lines (i.e., the eighth transfer pattern 58), which are respectively coupled to a plurality of initialization signal lines Vinit1, so that the plurality of compensation initial lines and the plurality of initialization signal lines Vinit1 form a grid structure, thereby reducing the loading of the initialization signal line Vinit1.

[0231] As shown in Figures 1, 4 and 17, in some embodiments, the display substrate includes multiple first sensing opening areas 41 and multiple second sensing opening areas 42; the first sensing opening areas 41 are located between the layout area of ​​the second sub-pixel driving circuit Q2 and the layout area of ​​the third sub-pixel driving circuit Q3 in the corresponding first row driving circuit row QH1; the second sensing opening area 42 is located between the layout area of ​​the first sub-pixel driving circuit Q1 and the layout area of ​​the third sub-pixel driving circuit Q3 in the corresponding second row driving circuit row QH2.

[0232] Exemplarily, the first sensing opening regions 41 correspond to the first row driving circuit rows QH1 in a one-to-one manner, and the second sensing opening regions 42 correspond to the second row driving circuit rows QH2 in a one-to-one manner.

[0233] Exemplarily, the sub-pixel driving circuit in the display substrate can implement an LTPO structure, but is not limited thereto.

[0234] Exemplarily, the display substrate is compatible with a COE (English: Color On Encapsulation) structure, but is not limited thereto.

[0235] The display substrate is provided with an under-screen sensor, and the display substrate is provided with a plurality of first sensor opening areas 41 and a plurality of second sensor opening areas 42, which can meet the transmittance requirement of the under-screen sensor.

[0236] The above configuration method is conducive to increasing the area of ​​each sensing opening region, thereby effectively improving the transmittance of the display substrate.

[0237] The technical solution provided by the embodiment of the present disclosure can be implemented in a compatible manner with a SIP routing solution, and can achieve a narrow frame and layout of a negative power signal line VSS within the display area.

[0238] In more detail, the technical solution provided by the embodiments of the present disclosure can be compatible with a variety of circuit structures, for example: a 7T1C (i.e., 7 transistors and 1 capacitor) circuit structure that includes only low-temperature polysilicon transistors, an 8T1C (i.e., 8 transistors and 1 capacitor) circuit structure that includes both low-temperature polysilicon transistors and oxide transistors, and a 7T1C circuit structure that includes both low-temperature polysilicon transistors and oxide transistors, but is not limited to these.

[0239] The following describes a detailed circuit structure and layout structure by taking a 7T1C circuit structure in which a sub-pixel driving circuit includes both low-temperature polysilicon transistors and oxide transistors as an example.

[0240] As shown in FIG3 , the sub-pixel driving circuit includes a first transistor T1 to a seventh transistor T7 and a storage capacitor.

[0241] A gate of the first transistor T1 is coupled to a corresponding reset signal line RST, a first electrode of the first transistor T1 is coupled to an initialization signal line Vinit1, and a second electrode of the first transistor T1 is coupled to an anode of a corresponding light emitting element.

[0242] A gate of the second transistor T2 is coupled to the corresponding first scan line GA1 , a first electrode of the second transistor T2 is coupled to a first electrode of the third transistor T3 , and a second electrode of the second transistor T2 is coupled to a gate T3 - g of the third transistor T3 .

[0243] A gate of the fourth transistor T4 is coupled to the corresponding second scan line GA2 , a first electrode of the fourth transistor T4 is coupled to the corresponding data DA, and a second electrode of the fourth transistor T4 is coupled to the second electrode of the third transistor T3 .

[0244] A gate of the fifth transistor T5 is coupled to the corresponding light emitting control signal line EM, a first electrode of the fifth transistor T5 is coupled to the power layer VDD, and a second electrode of the fifth transistor T5 is coupled to the lower first electrode of the third transistor T3.

[0245] A gate of the sixth transistor T6 is coupled to the corresponding light emitting control signal line EM, a first electrode of the sixth transistor T6 is coupled to the second electrode of the third transistor T3 , and a second electrode of the sixth transistor T6 is coupled to the anode of the corresponding light emitting element.

[0246] A gate of the seventh transistor T7 is coupled to the corresponding reset signal line RST, a first electrode of the seventh transistor T7 is coupled to the corresponding reference signal line, and a second electrode of the seventh transistor T7 is coupled to the first electrode of the third transistor T3.

[0247] The first plate Cst1 of the storage capacitor Cst is coupled to the gate of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power supply layer VDD. Exemplarily, the gate of the third transistor T3 can be reused as the first plate Cst1 of the storage capacitor Cst.

[0248] It should be noted that, in two adjacent sub-pixel driving circuits arranged along the first direction, the first transistor T1 in the upper sub-pixel driving circuit and the seventh transistor T1 in the lower sub-pixel driving circuit may share the same reset signal line RST.

[0249] As shown in Figure 5, the first active layer 11 included in the first transistor T1, the third active layer 13 included in the third transistor T3, the fourth active layer 14 included in the fourth transistor T4, the fifth active layer 15 included in the fifth transistor T5, the sixth active layer included in the sixth transistor T6, and the seventh active layer 17 included in the seventh transistor T7 are illustrated.

[0250] 9 , the second active layer 12 of the second transistor T2 is shown. The second transistor T2 includes an oxide transistor.

[0251] As shown in FIG14 , a first switching pattern 51 , a second switching pattern 52 , a third switching pattern 53 , a fourth switching pattern 54 , a fifth switching pattern 55 , a sixth switching pattern 56 , a seventh switching pattern 57 , an eighth switching pattern 58 and a ninth switching pattern are illustrated.

[0252] As shown in FIG11 to FIG16, the first end 511 of the first switching pattern 51 is coupled to the gate T3-g of the third transistor T3 through the seventh via Via7, and the second end 512 of the first switching pattern 51 is coupled to the second electrode of the second transistor T2 through the sixth via Via6.

[0253] The second transfer pattern 52 is coupled to the first electrode of the seventh transistor T7 through the first via Via1 , and the second transfer pattern 52 is coupled to the reference signal line Vref through the thirteenth via Via13 .

[0254] The third transfer pattern 53 is coupled to the initialization signal line Vinit1 through the eleventh via hole Via11 , and the third transfer pattern 53 is coupled to the first electrode of the first transistor T1 through the twelfth via hole Via12 .

[0255] The fourth transfer pattern 54 is coupled to the second electrode of the seventh transistor T7 through the second via Via2 , coupled to the first electrode of the third transistor T3 through the fourth via Via4 , and coupled to the first electrode of the second transistor T2 through the fifth via Via5 .

[0256] The fifth transfer pattern 55 is coupled to the first electrode of the fourth transistor T4 through the third via Via3 .

[0257] The sixth transfer pattern 56 is coupled to the second electrode Cst2 of the storage capacitor Cst through the eighth via Via8 , and the sixth transfer pattern 56 is coupled to the first electrode of the fifth transistor T5 through the tenth via Via10 .

[0258] The seventh transfer pattern 57 is coupled to the second electrode of the sixth transistor T6 through a ninth via hole Via9 .

[0259] The eighth transfer pattern 58 and the third transfer pattern 53 form an integrated structure. The eighth transfer pattern 58 is coupled to the initialization signal line Vinit1 to form a grid structure for transmitting the initialization signal.

[0260] The ninth transfer pattern 59 and the second transfer pattern 52 form an integrated structure. The ninth transfer pattern 59 is coupled to the reference signal line Vref to form a grid structure for transmitting the reference signal.

[0261] As shown in FIG. 18 , a tenth switching pattern 60 and an eleventh switching pattern 61 are illustrated.

[0262] As shown in Figures 17 to 20, the tenth transfer pattern 60 is coupled to the sixth transfer pattern 56 through the eighteenth via hole Via18. The eleventh transfer pattern 61 is coupled to the seventh transfer pattern 57 through the nineteenth via hole Via19.

[0263] As shown in Fig. 21, the twelfth transfer pattern 70 is shown. As shown in Figs. 20 to 23, the twelfth transfer pattern 70 is coupled to the eleventh transfer pattern 61 through the twenty-sixth via Via26.

[0264] As shown in FIG19 , the fourteenth via hole Via14 , the fifteenth via hole Via15 , the sixteenth via hole Via16 , the seventeenth via hole Via17 , the eighteenth via hole Via18 , the nineteenth via hole Via19 , the twentieth via hole Via20 , the twenty-first via hole Via21 , the twenty-second via hole Via22 , and the twenty-third via hole Via23 are illustrated.

[0265] As shown in FIG. 17 to FIG. 21 , in the first sub-pixel driving circuit Q1 of the first driving circuit row QH1 , the fifth transfer pattern 55 is coupled to the second sub-portion 312 through the fourteenth via hole Via14 .

[0266] In the third sub-pixel driving circuit Q3 of the first driving circuit row QH1 , the fifth transfer pattern 55 is coupled to the tenth sub-portion 352 through the fifteenth via hole Via15 .

[0267] In the second sub-pixel driving circuit Q2 of the first driving circuit row QH1 , the fifth transfer pattern 55 is coupled to the sixth sub-portion 332 through the sixteenth via hole Via16 .

[0268] In the fourth sub-pixel driving circuit Q4 of the first driving circuit row QH1 , the fifth transfer pattern 55 is coupled to the fourteenth sub-portion 372 through the seventeenth via hole Via17 .

[0269] In the second sub-pixel driving circuit Q2 of the second driving circuit row QH2, the fifth transfer pattern 55 is coupled to the eighth sub-portion 342 through the twentieth via hole Via20.

[0270] In the third sub-pixel driving circuit Q3 of the second driving circuit row QH2 , the fifth transfer pattern 55 is coupled to the twelfth sub-portion 362 through the twenty-first via hole Via21 .

[0271] In the first sub-pixel driving circuit Q1 of the second driving circuit row QH2 , the fifth transfer pattern 55 is coupled to the fourth sub-portion 322 through the twenty-second via hole Via22 .

[0272] In the fourth sub-pixel driving circuit Q4 of the second driving circuit row QH2, the fifth transfer pattern 55 is coupled to the sixteenth sub-portion 382 through the twenty-third via hole Via23.

[0273] As shown in Figure 22, the twenty-fourth via Via24, the twenty-fifth via Via25, the twenty-sixth via Via26, the twenty-seventh via Via27, the twenty-eighth via Via28, the twenty-ninth via Via29, the thirtieth via Via30, the thirty-first via Via31, the thirty-second via Via32, the thirty-third via Via33 and the thirty-fifth via Via35 are illustrated.

[0274] As shown in FIG. 20 to FIG. 23 , the first conductive connection portion 31 is coupled to the first data line DA1 through the twenty-fourth via hole Via24 .

[0275] The third conductive connection portion 33 is coupled to the second data line DA2 through the twenty-fifth via hole Via25 .

[0276] The twelfth transfer pattern 70 is coupled to the eleventh transfer pattern 61 through the twenty-sixth via hole Via26 .

[0277] The second conductive connection portion 32 is coupled to the first data line DA1 through the twenty-seventh via hole Via27 .

[0278] The fourth conductive connection portion 34 is coupled to the second data line DA2 through the twenty-eighth via hole Via28 .

[0279] The fifth conductive connection portion 35 is coupled to the third data line DA3 through the twenty-ninth via hole Via29 .

[0280] The seventh conductive connection portion 37 is coupled to the fourth data line DA4 through the thirtieth via hole Via30 .

[0281] The eighth conductive connection portion 38 is coupled to the fourth data line DA4 through the thirty-first via hole Via31 .

[0282] The sixth conductive connection portion 36 is coupled to the third data line DA3 through the thirty-second via hole Via32 .

[0283] The first power line VDD1 is coupled to the second power line VDD2 through the thirty-third via Via33 .

[0284] The tenth transfer pattern 60 is coupled to the second power line VDD2 through the thirty-fifth via hole Via35 .

[0285] As shown in Fig. 25, a thirty-fourth via hole Via34 is shown. As shown in Figs. 23 to 26, the twelfth transfer pattern 70 is coupled to the anode ANO through the thirty-fourth via hole Via34.

[0286] As shown in FIG27 , the display substrate exemplarily includes a buffer layer BF, a polysilicon active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, a third gate insulating layer GI3, an oxide active layer ACT, a fourth gate insulating layer GI4, a third gate metal layer gate3, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarizing layer PLN1, a second source / drain metal layer SD2, a second planarizing layer PLN2, a third source / drain metal layer SD3, a third planarizing layer PLN3, an anode layer ANO, a pixel defining layer PDL, a light emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked in a direction away from the base substrate 90. A passivation layer PVX may also be provided on the display substrate as needed.

[0287] It should be noted that the sub-pixel driving circuits in two adjacent columns of driving circuits are arranged symmetrically.

[0288] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0289] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0290] In the display substrate provided by the above embodiment, the data lines coupled to the sub-pixel driving circuits included in the column units are arranged to be located on the first side and / or the second side of the column units, so that the data lines are far away from each sub-pixel driving circuit in the column units. In this way, when the data signal transmitted by the data lines changes, the impact on the stability of the key nodes in the sub-pixel driving circuit is small, thereby ensuring the stability of the sub-pixel driving circuit.

[0291] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0292] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0293] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0294] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0295] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0296] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0297] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0298] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0299] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate and a plurality of sub-pixels and a plurality of data lines all disposed on the base substrate, wherein the sub-pixels include a sub-pixel driving circuit and a light-emitting element coupled to each other; The multiple sub-pixel driving circuits included in the multiple sub-pixels are divided into multiple columns of driving circuit columns, each column of driving circuit columns includes multiple sub-pixel driving circuits arranged along a first direction, and the multiple columns of driving circuit columns are divided into multiple column units, and the column unit includes at least two adjacent columns of driving circuit columns; the data lines coupled to the sub-pixel driving circuits included in the column units are located on the first side and / or the second side of the column unit, the first side and the second side are opposite to each other along a second direction, and the second direction intersects with the first direction.

2. The display substrate according to claim 1, wherein: The column unit comprises at least one first driving circuit column and at least one second driving circuit column, and the first driving circuit column and the second driving circuit column are alternately arranged along the second direction; The first driving circuit column includes a plurality of first sub-pixel driving circuits and a plurality of second sub-pixel driving circuits, the first sub-pixel driving circuits and the second sub-pixel driving circuits are alternately arranged along the first direction, the first sub-pixel driving circuits are coupled to the first color light emitting element, and the second sub-pixel driving circuits are coupled to the second color light emitting element; each first sub-pixel driving circuit in the first driving circuit column is coupled to the same data line, and each second sub-pixel driving circuit in the first driving circuit column is coupled to the same data line; The sub-pixel driving circuit included in the second driving circuit column is coupled to the third color light emitting element; and each sub-pixel driving circuit in the second driving circuit column is coupled to the same data line.

3. The display substrate according to claim 2, wherein: The data lines coupled to each first sub-pixel driving circuit in the first driving circuit column and the data lines coupled to each second sub-pixel driving circuit in the first driving circuit column are both located on the first side of the column unit, and the data lines coupled to each sub-pixel driving circuit in the second driving circuit column are located on the second side of the column unit.

4. The display substrate according to claim 3, wherein: The column unit includes two first drive circuit columns and two second drive circuit columns; each first sub-pixel drive circuit included in the two first drive circuit columns is coupled to the same first data line; each second sub-pixel drive circuit included in the two first drive circuit columns is coupled to the same second data line; each third sub-pixel drive circuit included in the first second drive circuit column is coupled to the same third data line; each fourth sub-pixel drive circuit included in the second second drive circuit column is coupled to the same fourth data line; The first data line, the second data line, the third data line and the fourth data line are arranged in sequence along the second direction.

5. The display substrate according to claim 4, wherein: The column unit is divided into a plurality of sub-units arranged in sequence along the first direction, and the sub-units include two rows of driving circuits arranged along the first direction; The first row of driving circuits includes a first sub-pixel driving circuit, a third sub-pixel driving circuit, a second sub-pixel driving circuit and a fourth sub-pixel driving circuit arranged in sequence along the second direction; the second row of driving circuits includes a second sub-pixel driving circuit, a third sub-pixel driving circuit, a first sub-pixel driving circuit and a fourth sub-pixel driving circuit arranged in sequence along the second direction; The first data line and the second data line are located at a first side of the column unit, and the third data line and the fourth data line are located at a second side of the column unit.

6. The display substrate according to claim 5, wherein: The first sub-pixel driving circuit in the first row of driving circuits comprises: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the first data line is coupled to the first electrode of the data writing transistor via a first conductive connection portion; The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the first data main body included in the first data line on the base substrate and the orthographic projection of the second data main body included in the second data line on the base substrate.

7. The display substrate according to claim 6, wherein: The display substrate further includes a reference signal line and an initialization signal line; The first conductive connection portion includes a first sub-portion and a second sub-portion coupled to each other, the first sub-portion extends along the second direction, the second sub-portion extends along the first direction, the first sub-portion is coupled to the first data line, and the second sub-portion is coupled to the first electrode of the data writing transistor; At least part of the orthographic projection of the first sub-portion on the substrate is located at the reference The signal line is between the orthographic projection of the base substrate and the orthographic projection of the initialization signal line on the base substrate.

8. The display substrate according to claim 5, wherein: The first sub-pixel driving circuit in the second row of driving circuits comprises: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the first data line is coupled to the first electrode of the data writing transistor via a second conductive connection portion; The data writing transistor includes a data writing active layer, the data writing active layer having an orthographic projection on the substrate, which is located between the orthographic projection of the second data main body included in the second data line on the substrate and the orthographic projection of the third data main body included in the third data line on the substrate.

9. The display substrate according to claim 8, wherein: The second conductive connection portion includes a third sub-portion and a fourth sub-portion coupled to each other, at least a portion of the third sub-portion extends along the second direction, the fourth sub-portion at least partially surrounds the sensing opening area of ​​the display substrate, the third sub-portion is coupled to the first data line, and the fourth sub-portion is coupled to the first electrode of the data write transistor.

10. The display substrate according to claim 9, wherein: The display substrate further includes a reference signal line and an initialization signal line; at least a portion of the orthographic projection of the third sub-portion on the base substrate is located between the orthographic projection of the reference signal line on the base substrate and the orthographic projection of the initialization signal line on the base substrate; The orthographic projection of the fourth sub-portion on the substrate at least partially overlaps with the orthographic projection of the initialization signal line on the substrate; And / or, an orthographic projection of the fourth sub-portion on the substrate at least partially overlaps with an orthographic projection of the reference signal line on the substrate.

11. The display substrate according to claim 5, wherein: The second sub-pixel driving circuit in the first row of driving circuits comprises: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the second data line is coupled to the first electrode of the data writing transistor via a third conductive connection portion; The data writing transistor includes a data writing active layer, and the data writing active layer has an orthographic projection on the substrate, which is located between the orthographic projection of the second data main body included in the second data line on the substrate and the orthographic projection of the third data main body included in the third data line on the substrate.

12. The display substrate according to claim 11, wherein: The display substrate further includes a first scan line, the second sub-pixel driving circuit in the first row driving circuit further includes a compensation transistor, a first electrode of the compensation transistor is coupled to a first electrode of the driving transistor, a second electrode of the compensation transistor is coupled to a gate of the driving transistor, and the gate of the compensation transistor is coupled to the corresponding first scan line; The third conductive connection portion includes a fifth sub-portion and a sixth sub-portion coupled to each other, the fifth sub-portion is coupled to the second data line, and the sixth sub-portion is coupled to the first electrode of the data writing transistor; the orthographic projection of the fifth sub-portion on the substrate at least partially overlaps with the orthographic projection of the first scanning line on the substrate.

13. The display substrate according to claim 5, wherein: The second sub-pixel driving circuit in the second row of driving circuits comprises: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the second data line is coupled to the first electrode of the data writing transistor via a fourth conductive connection portion; The data writing transistor includes a data writing active layer, and the orthographic projection of the data writing active layer on the base substrate is located between the orthographic projection of the first data main body included in the first data line on the base substrate and the orthographic projection of the second data main body included in the second data line on the base substrate.

14. The display substrate according to claim 13, wherein: The display substrate further includes a second scan line; the gate of the data writing transistor is coupled to the corresponding second scan line; The fourth conductive connection portion includes a seventh sub-portion and an eighth sub-portion coupled to each other, the seventh sub-portion extends along the second direction, the eighth sub-portion extends along the first direction, the seventh sub-portion is coupled to the second data line, and the eighth sub-portion is coupled to the first electrode of the data writing transistor; At least a portion of the orthographic projection of the seventh sub-portion on the substrate is located between the orthographic projection of the second scan line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate.

15. The display substrate according to claim 5, wherein: The third sub-pixel driving circuit in the first row of driving circuits comprises: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the third data line is coupled to the first electrode of the data writing transistor via a fifth conductive connection portion; The data writing transistor includes a data writing active layer, and the data writing active layer has an orthographic projection on the substrate, which is located between the orthographic projection of the second data main body included in the second data line on the substrate and the orthographic projection of the third data main body included in the third data line on the substrate.

16. The display substrate according to claim 15, wherein: The fifth conductive connection portion includes a ninth sub-portion and a tenth sub-portion coupled to each other, at least a portion of the ninth sub-portion extends along the second direction, the tenth sub-portion at least partially surrounds the sensing opening area of ​​the display substrate, the ninth sub-portion is coupled to the third data line, and the tenth sub-portion is coupled to the first electrode of the data write transistor.

17. The display substrate according to claim 16, wherein: The display substrate further includes a reference signal line and an initialization signal line; at least a portion of the orthographic projection of the ninth sub-portion on the base substrate is located between the orthographic projection of the reference signal line on the base substrate and the orthographic projection of the initialization signal line on the base substrate; The orthographic projection of the tenth sub-portion on the substrate at least partially overlaps with the orthographic projection of the initialization signal line on the substrate; And / or, an orthographic projection of the tenth sub-portion on the substrate at least partially overlaps with an orthographic projection of the reference signal line on the substrate.

18. The display substrate according to claim 5, wherein: The third sub-pixel driving circuit in the second row of driving circuits comprises: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the third data line is coupled to the first electrode of the data writing transistor via a sixth conductive connection portion; The data writing transistor includes a data writing active layer, and the data writing active layer has an orthographic projection on the substrate, which is located between the orthographic projection of the second data main body included in the second data line on the substrate and the orthographic projection of the third data main body included in the third data line on the substrate.

19. The display substrate according to claim 18, wherein: The display substrate further includes a second scan line; the gate of the data writing transistor is coupled to the corresponding second scan line; The sixth conductive connection portion includes an eleventh sub-portion and a twelfth sub-portion coupled to each other, the eleventh sub-portion extends along the second direction, and the twelfth sub-portion extends along the first direction, The eleventh sub-portion is coupled to the third data line, and the twelfth sub-portion is coupled to the first electrode of the data writing transistor; At least a portion of the orthographic projection of the eleventh sub-portion on the substrate is located between the orthographic projection of the second scan line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate.

20. The display substrate according to claim 5, wherein: The fourth sub-pixel driving circuit in the first row of driving circuits comprises: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the fourth data line is coupled to the first electrode of the data writing transistor via a seventh conductive connection portion; The data writing transistor includes a data writing active layer, and the data writing active layer has an orthographic projection on the substrate, which is located between the orthographic projection of the third data main body included in the third data line on the substrate and the orthographic projection of the fourth data main body included in the fourth data line on the substrate.

21. The display substrate according to claim 20, wherein: The display substrate further includes a first scan line, the fourth sub-pixel driving circuit in the first row of driving circuits further includes a compensation transistor, a first electrode of the compensation transistor is coupled to a first electrode of the driving transistor, a second electrode of the compensation transistor is coupled to a gate of the driving transistor, and the gate of the compensation transistor is coupled to the corresponding first scan line; The seventh conductive connection portion includes a thirteenth sub-portion and a fourteenth sub-portion coupled to each other, the thirteenth sub-portion is coupled to the fourth data line, and the fourteenth sub-portion is coupled to the first electrode of the data write transistor; the orthographic projection of the thirteenth sub-portion on the substrate at least partially overlaps with the orthographic projection of the first scan line on the substrate.

22. The display substrate according to claim 5, wherein: The fourth sub-pixel driving circuit in the second row of driving circuits comprises: a driving transistor and a data writing transistor, wherein the second electrode of the data writing transistor is coupled to the second electrode of the driving transistor; the fourth data line is coupled to the first electrode of the data writing transistor through an eighth conductive connection portion; The data writing transistor includes a data writing active layer, the positive projection of the data writing active layer on the substrate is located between the positive projection of the third data main body of the third data line on the substrate and the positive projection of the fourth data main body of the fourth data line on the substrate. Between the orthographic projections on .

23. The display substrate according to claim 22, wherein: The display substrate further includes a reference signal line and an initialization signal line; the eighth conductive connection portion includes a fifteenth sub-portion and a sixteenth sub-portion coupled to each other, at least a portion of the fifteenth sub-portion extends along the second direction, at least a portion of the sixteenth sub-portion extends along the first direction, the fifteenth sub-portion is coupled to the fourth data line, and the sixteenth sub-portion is coupled to the first electrode of the data writing transistor; At least a portion of the orthographic projection of the fifteenth sub-portion on the base substrate is located between the orthographic projection of the reference signal line on the base substrate and the orthographic projection of the initialization signal line on the base substrate.

24. The display substrate according to claim 5, wherein: Each sub-pixel driving circuit in the display substrate includes a driving transistor and a compensation transistor, wherein a first electrode of the compensation transistor is coupled to a first electrode of the driving transistor, and a second electrode of the compensation transistor is coupled to a gate electrode of the driving transistor via a first switching pattern; at least a portion of an orthographic projection of the first switching pattern on the base substrate is located between an orthographic projection of the second data line on the base substrate and an orthographic projection of the third data line on the base substrate.

25. The display substrate according to claim 24, wherein: The first switching pattern includes a first end, a second end, and a connecting portion respectively coupled to the first end and the second end, the first end is coupled to the gate of the driving transistor, the second end is coupled to the second electrode of the compensation transistor, and the connecting portion extends along the second direction.

26. The display substrate according to claim 24, wherein: In the layout area of ​​the first row driving circuit row: the orthographic projection of the first switching pattern in the layout area of ​​the second sub-pixel driving circuit on the substrate, and the orthographic projection of the first switching pattern in the layout area of ​​the third sub-pixel driving circuit on the substrate, are both located between the orthographic projection of the second data line on the substrate and the orthographic projection of the third data line on the substrate; An orthographic projection of a first end portion located in a layout area of ​​the first sub-pixel driving circuit on the base substrate at least partially overlaps with an orthographic projection of the second data line on the base substrate; An orthographic projection of the first end portion located in the layout area of ​​the fourth sub-pixel driving circuit on the base substrate at least partially overlaps with an orthographic projection of the third data line on the base substrate.

27. The display substrate according to claim 24, wherein: In the layout area of ​​the second row of driving circuits: the orthographic projection of the first switching pattern in the layout area of ​​the first sub-pixel driving circuit on the substrate, and the orthographic projection of the first switching pattern in the layout area of ​​the third sub-pixel driving circuit on the substrate, are both located between the orthographic projection of the second data line on the substrate and the orthographic projection of the third data line on the substrate; An orthographic projection of the first end portion located in the layout area of ​​the second sub-pixel driving circuit on the base substrate at least partially overlaps with an orthographic projection of the second data line on the base substrate; An orthographic projection of the first end portion located in the layout area of ​​the fourth sub-pixel driving circuit on the base substrate at least partially overlaps with an orthographic projection of the third data line on the base substrate.

28. The display substrate according to claim 25, wherein: The display substrate further comprises a power supply layer, and the orthographic projection of the power supply layer on the base substrate covers the orthographic projection of the first switching pattern on the base substrate.

29. The display substrate according to claim 28, wherein: The power layer includes a plurality of first power lines and a plurality of second power lines, the first power lines and the second power lines are arranged crosswise, and the first power lines are coupled to the second power lines; The orthographic projection of the first power line on the base substrate covers the orthographic projection of the first end on the base substrate, and / or the orthographic projection of the first power line on the base substrate at least partially overlaps with the orthographic projection of the connecting portion on the base substrate; The orthographic projection of the second power line on the base substrate covers the orthographic projection of the second end on the base substrate, and / or the orthographic projection of the second power line on the base substrate at least partially overlaps with the orthographic projection of the connecting portion on the base substrate.

30. The display substrate according to claim 5, wherein: The display substrate includes a plurality of first sensing opening areas and a plurality of second sensing opening areas; the first sensing opening areas are located between a layout area of ​​a second sub-pixel driving circuit and a layout area of ​​a third sub-pixel driving circuit in a corresponding first row of driving circuits; the second sensing opening areas are located between a layout area of ​​a first sub-pixel driving circuit and a layout area of ​​a third sub-pixel driving circuit in a corresponding second row of driving circuits.

31. A display device comprising the display substrate according to any one of claims 1 to 30.

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