Pixel unit and manufacturing method therefor, micro display screen, and pixel-level discrete device

Abstract

Provided are a pixel unit and a manufacturing method therefor, a micro display screen comprising the pixel unit, and a pixel-level discrete device. The pixel unit comprises a driving backplane (10) and a display unit (20) disposed on the driving backplane (10); the display unit (20) comprises a first device layer (30), a second device layer (40) and a third device layer (50) which are sequentially and vertically stacked, the first device layer (30) comprises at least one first sub-pixel (31), the second device layer (40) comprises at least one second sub-pixel (41), the third device layer (50) comprises at least one third sub-pixel (51), and the projection of any first sub-pixel (31), any second sub-pixel (41) or any third sub-pixel (51) on the driving backplane (10) is located in the projection of any sub-pixel above the sub-pixel on the driving backplane (10); the first device layer (30) emits red light in a working state, the second device layer (40) emits green light in a working state, and the third device layer (50) emits blue light in a working state. The pixel unit is arranged by means of vertical and coaxial stacking, so that the pixel density is effectively increased, and different color matching requirements can be met by adjusting the sizes of the sub-pixels in different device layers.

Description

Pixel unit and manufacturing method thereof, micro display screen, and pixel-level discrete device

[0001] This application claims priority to Chinese patent application No. 202310742884.7 filed on June 21, 2023, entitled “Pixel unit and manufacturing method thereof, micro display screen, pixel-level discrete device,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of semiconductor device technology, and in particular to a pixel unit and a manufacturing method thereof, a micro display screen, and a pixel-level discrete device. Background Art

[0003] Micro-LED display technology is widely considered to be the next generation of display technology, with great prospects in both wearable devices and direct display. However, achieving color display is still a very challenging problem. Currently, Micro-LED is mainly divided into vertical non-coaxial stacking and vertical coaxial stacking.

[0004] In vertically non-coaxially stacked Micro-LEDs, the anode electrical connection must be made from the sidewalls, typically requiring metal bonding materials for bonding between device layers. Therefore, the compound at the bottom of the upper pixel layer does not participate in photoelectric conversion at all, sacrificing a large amount of space. Furthermore, the sidewall electrical connection is limited by the material's encapsulation capabilities, making the process challenging to implement. Most importantly, the pixel density of vertically non-coaxially stacked Micro-LEDs is low.

[0005] In comparison, vertical coaxial stacking of Micro-LEDs can achieve higher pixel density. In existing vertical coaxial stacking of Micro-LEDs, the sub-pixels of different device layers gradually shrink from bottom to top, making it difficult to adjust pixel size and color matching as needed. The reason for this gradual shrinkage is that the existing pixel stacking process first stacks all compound semiconductor layers, then performs etching and other processes from top to bottom to expose and electrically connect the structure. This results in a structure where the top sub-pixels are the smallest and the bottom sub-pixels are the largest.

[0006] Therefore, it is urgent to find a pixel unit that can effectively overcome the above defects.

[0007] Summary of the Invention

[0008] The purpose of this application is to provide a pixel unit and a manufacturing method thereof, a micro display screen, and a pixel-level discrete device. The pixel unit can flexibly adjust the sub-pixel size on the basis of improving the pixel density, thereby realizing diversified color matching requirements.

[0009] To achieve the above application objectives, the present application provides, in a first aspect, a pixel unit, comprising:

[0010] Driver backplane;

[0011] A display unit, the display unit being provided on the driving backplane, the display unit comprising a first device layer, a second device layer, and a third device layer stacked vertically in sequence in a direction away from the driving backplane, the first device layer comprising at least one first sub-pixel, the second device layer comprising at least one second sub-pixel, and the third device layer comprising at least one third sub-pixel, wherein a projection of any first sub-pixel, any second sub-pixel, or any third sub-pixel on the driving backplane is located within a projection of any sub-pixel above the first sub-pixel on the driving backplane;

[0012] The first device layer emits red light in an operating state, the second device layer emits green light in an operating state, and the third device layer emits blue light in an operating state.

[0013] In a preferred embodiment, the center point of any one of the first sub-pixel, the second sub-pixel and the third sub-pixel is located on the same vertical line of the driving backplane.

[0014] In a preferred embodiment, the first device layer further includes a first filling layer encapsulating any of the first sub-pixels, wherein the transmittance of the first filling layer to visible light in the 600nm to 650nm band is not less than 90%, and the reflectivity of the first filling layer to visible light in the 500nm to 550nm band is not less than 90%;

[0015] The second device layer further includes a second filling layer encapsulating any second sub-pixel, wherein the transmittance of the second filling layer to visible light in the wavelength bands of 600nm to 650nm and 500nm to 550nm is not less than 90%, and the reflectivity of the second filling layer to visible light in the wavelength band of 400nm to 460nm is not less than 90%;

[0016] The third device layer further includes a third filling layer wrapping any of the third sub-pixels, and the transmittance of the third filling layer to visible light in the 600nm to 650nm band, the 500nm to 550nm band, and the 400nm to 460nm band is not less than 90%.

[0017] In a preferred embodiment, the second device layer further includes a second passivation layer and a second ohmic layer;

[0018] The second passivation layer is disposed on a surface of any second sub-pixel;

[0019] The second ohmic layer is covered on the surface of the second passivation layer, and the second ohmic layer passes through the second passivation layer and is connected to any of the second sub-pixels.

[0020] In a preferred embodiment, the driving backplane includes at least three anodes, the first device layer further includes at least three anode filling layers, and any of the anode filling layers is respectively connected to any corresponding anode;

[0021] At least one point of any one of the at least three anode filling layers is located on the same straight line of the driving back plate.

[0022] In a preferred embodiment, the second device layer further comprises at least two first connecting layers, and any one of the first connecting layers is located above any one of the anode filling layers;

[0023] The first device layer further includes at least one anode electrical connection structure. One end of any anode electrical connection structure in the first device layer is connected to the anode filling layer, and the other end is connected to the corresponding first connecting layer.

[0024] In a preferred embodiment, any of the first sub-pixels is connected to the corresponding anode filling layer; or,

[0025] The first device layer further includes at least one first conductive layer, wherein a side of any first conductive layer away from the driving backplane is connected to any first sub-pixel, and a side close to the driving backplane is connected to the corresponding anode filling layer.

[0026] In a preferred embodiment, when any of the first sub-pixel, the second sub-pixel and the third sub-pixel is a hemisphere, a hemi-ellipsoid or a cylinder with a hemispherical light-emitting surface, and the volume of any sub-pixel is equal, the projection of any of the sub-pixels on the driving backplane does not overlap with the projection of any of the anode electrical connection structures on the driving backplane.

[0027] In a preferred embodiment, the second device layer further includes at least one second conductive layer, and the projection of the second conductive layer on the driving backplane is larger than the projection of the second sub-pixel on the driving backplane;

[0028] One side of any second conductive layer is connected to any second sub-pixel, and the other side is connected to the corresponding first connecting layer.

[0029] In a preferred embodiment, when any of the first sub-pixel, the second sub-pixel and the third sub-pixel is a rectangular parallelepiped, any of the anode electrical connection structures in the first device layer is embedded in the corresponding first sub-pixel, and the projection of any of the anode electrical connection structures in the first device layer on the driving backplane is located within the projection of any of the third sub-pixels on the driving backplane.

[0030] In a preferred embodiment, any one of the first device layer, the second device layer and the third device layer further includes a color conversion layer disposed above any sub-pixel, and the color conversion layer absorbs the excitation light source emitted by the corresponding sub-pixel and converts it into a target light source.

[0031] In a preferred embodiment, the display unit further includes at least one reinforcement structure provided in a circumferential direction of any device layer.

[0032] In a second aspect, a method for manufacturing a pixel unit is provided, the method comprising:

[0033] Prepare the drive backplane;

[0034] Manufacturing a display unit, bonding a first target compound semiconductor to the driving backplane and constructing at least one first sub-pixel to form a first device layer; bonding a second target compound semiconductor to the first device layer and constructing at least one second sub-pixel to form a second device layer; bonding a third target compound semiconductor to the second device layer and constructing at least one third sub-pixel to form a third device layer; wherein a projection of any of the first sub-pixels, any of the second sub-pixels, or any of the third sub-pixels on the driving backplane is located within a projection of any sub-pixel above them on the driving backplane;

[0035] The first device layer emits red light in an operating state, the second device layer emits green light in an operating state, and the third device layer emits blue light in an operating state.

[0036] In a third aspect, a micro display screen is provided, wherein the micro display screen comprises:

[0037] A micro display screen backplane, comprising a drive circuit, an input interface, and an output interface;

[0038] A display area, the display area being provided on the back panel of the micro display screen, and the display area comprising at least two display units included in the pixel unit according to any one of the first aspects, wherein the at least two display units are arranged in an array;

[0039] A peripheral common cathode is electrically connected to each of the display units.

[0040] In a fourth aspect, a pixel-level discrete device is provided, wherein the pixel-level discrete device comprises:

[0041] A discrete device backplane, the discrete device backplane comprising at least two anode pads and at least one cathode pad;

[0042] The device body is arranged on the discrete device backplane, and the device body includes at least two display units included in the pixel unit as described in any one of the first aspects, and at least two of the display units are arranged in an array.

[0043] Compared with the prior art, this application has the following beneficial effects:

[0044] The present application provides a pixel unit and a manufacturing method thereof, a micro display screen, and a pixel-level discrete device. The pixel unit includes a driving backplane and a display unit. The display unit is provided on the driving backplane, and the display unit includes a first device layer, a second device layer, and a third device layer vertically stacked in sequence in a direction away from the driving backplane. The first device layer includes at least one first sub-pixel, the second device layer includes at least one second sub-pixel, and the third device layer includes at least one third sub-pixel. The projection of any first sub-pixel, any second sub-pixel, or any third sub-pixel on the driving backplane is located within the projection of any sub-pixel above it on the driving backplane. The first device layer emits red light in an operating state, the second device layer emits green light in an operating state, and the third device layer emits blue light in an operating state. In the present application, the pixel unit adopts a vertical coaxial stacking method to effectively improve the pixel density. On this basis, it is possible to achieve different color matching requirements by adjusting the size of the sub-pixels in different device layers.

[0045] Furthermore, the present application realizes multi-color display while improving the brightness of the light source by arranging the filling layer included in the device layer to allow the light of the lower device layer to pass through and reflect the light source of the upper device layer;

[0046] Furthermore, when any of the first, second, and third sub-pixels is a hemisphere, a hemi-ellipsoid, or a cylinder with a hemispherical light-emitting surface, and the volumes of any of the sub-pixels are equal, the projection of any third sub-pixel on the driver backplane does not overlap with the projection of any anode electrical connection structure on the driver backplane. This application improves sub-pixel brightness by more than 30% by optimizing the sub-pixel structure to increase light extraction efficiency.

[0047] Furthermore, when any of the first, second, and third sub-pixels is a rectangular parallelepiped, any anode electrical connection structure is embedded in the corresponding first sub-pixel, and the projection of any anode electrical connection structure on the driver backplane is located within the projection of any third sub-pixel on the driver backplane. The anode electrical connection structure of the pixel unit of the present application is arranged below the sub-pixel. Compared with the existing method of arranging the anode electrical connection structure laterally, this can effectively avoid the space loss caused by the electrical connection, thereby increasing the effective light-emitting area and improving the structural reliability of the pixel unit. More importantly, the sub-pixel with a rectangular parallelepiped structure can be infinitely extended in the circumferential direction to increase the proportion of the light-emitting area of ​​each sub-pixel, thereby improving the pixel density.

[0048] It should be noted that this application only needs to achieve at least one of the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 is a top view of a pixel unit in Example 1;

[0050] FIG2 is a cross-sectional view of the AB section in FIG1 under a pixel unit structure;

[0051] FIG3 is a cross-sectional view of the AB section in FIG1 under another pixel unit structure;

[0052] FIG4 is a block diagram of an exemplary driving circuit;

[0053] FIG5 is an exemplary circuit structure diagram corresponding to a device layer;

[0054] FIG6 is a top view of the driving back plate after the anode filling layer is formed;

[0055] FIG7 is a cross-sectional view of the driving backplane after being covered with a bonding layer during non-aligned bonding;

[0056] FIG8 is a cross-sectional view of the first target compound semiconductor after being covered with a bonding layer during non-aligned bonding;

[0057] 9 is a cross-sectional view of the driving backplane and the first target compound semiconductor after non-aligned bonding;

[0058] FIG10 is a schematic diagram of the structure of the first sub-pixel after non-aligned bonding;

[0059] FIG11 is a cross-sectional view of the driving backplane after being covered with a bonding layer during alignment bonding;

[0060] 12 is a cross-sectional view of the first target compound semiconductor after being covered with a bonding layer during alignment bonding;

[0061] 13 is a cross-sectional view of the drive backplane and the first target compound semiconductor after alignment and bonding;

[0062] FIG14 is a schematic diagram of the structure of the first sub-pixel after alignment and bonding;

[0063] FIG15 is a schematic diagram of the structure of the first sub-pixel after roughening treatment;

[0064] FIG16 is a schematic diagram of the structure after the first passivation layer and the first ohmic layer are covered;

[0065] FIG17 is a schematic diagram of the structure after constructing the anode electrical connection structure;

[0066] FIG18 is a schematic diagram of the structure after filling the first filling layer;

[0067] FIG19 is a schematic diagram of the structure after the second sub-pixel is constructed;

[0068] FIG20 is another schematic diagram of the structure after the second sub-pixel is constructed;

[0069] FIG21 is a schematic diagram of the structure after constructing the second device layer;

[0070] FIG22 is a cross-sectional view of the AB section of the pixel unit structure in Example 2;

[0071] FIG23 is a schematic structural diagram of a micro display screen in Example 3;

[0072] Figure 24 is a schematic structural diagram of the pixel-level discrete device in Example 4.

[0073] Figure 1: 100-pixel unit, 10-driving backplane, 11-first anode, 12-second anode, 13-third anode, 111-anode filling layer, 20-display unit, 30-first device layer, 31-first sub-pixel, 32-first dielectric layer, 33-first passivation layer, 34-first ohmic layer, 35-first filling layer, 36-first conductive layer, 40-second device layer, 41-second sub-pixel, 42-second dielectric layer, 43-second passivation layer, 44-second ohmic layer, 45-second filling layer, 46-first connecting layer, 47-second conductive layer, 50-third device layer, 51-third sub-pixel, 52-third dielectric layer, 53-third Passivation layer, 54-third ohmic layer, 55-third filling layer, 56-second connecting layer, 57-third conductive layer, 60-anode electrical connection structure, 70-enhancement structure, 81-optical lens, 82-color conversion layer, 91-first target compound semiconductor, 200-micro display screen, 300-micro display screen backplane, 400-display area, 500-peripheral common cathode, 600-external IO interface, 700-pixel-level discrete device, 710-discrete device backplane, 720-device body, 730-anode pad. DETAILED DESCRIPTION

[0074] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0075] In the description of this application, it should be understood that the terms "upper", "lower", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "multiple" means two or more.

[0076] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0077] Example 1

[0078] As shown in Figures 1 to 3, this embodiment provides a pixel unit 100. The pixel unit 100 is used in semiconductor devices, including but not limited to micro-LEDs, micro-lasers, and other optoelectronic devices. The pixel unit 100 includes a driver backplane 10 and a display unit 20 disposed on the driver backplane 10.

[0079] Note: Figure 1 is a top view of the pixel unit 100, and Figures 2 and 3 are cross-sectional views of the pixel unit 100 under different structures, such as the AB section in Figure 1. The subsequent structural figures are also top views under the current structure or cross-sectional views of the corresponding AB section.

[0080] The driving backplane 10 in this embodiment can be an active backplane that is a combination of one or more thin film transistors (TFT), LTPS low temperature polysilicon, CMOS integrated circuits, high mobility transistors (HEMT), etc. Specifically, the driving backplane 10 is provided with a driving circuit, and the driving circuit 10 is provided with at least one anode. Exemplarily, the circuit structure diagram of the driving circuit is shown in FIG4 . It should be noted that the circuit diagram shown in this embodiment is only a simple schematic diagram. The driving circuit may include an active, passive or semi-passive control circuit, as shown in FIG5 , which is an exemplary circuit diagram of any device layer. All anodes included in the driving circuit may be arranged linearly or in an array, and any anode may be located in the middle or at the edge of the driving backplane 10. This embodiment does not impose any restrictions on this.

[0081] In some embodiments, the driving backplane 10 includes at least one top metal, which covers at least one anode; or, the driving backplane 10 includes an in-situ reflector provided on its upper surface, which covers or exposes at least one anode. The in-situ reflector can be a metal, such as aluminum, gold, silver, etc.; it can also be a Bragg reflector layer, which is composed of two or more thin films with different refractive indices stacked together, such as a stack of silicon oxide and titanium oxide, a stack of silicon oxide and aluminum oxide, a stack of silicon oxide and silicon nitride, etc.; it can also be an ODR total reflector stacked with a metal and a dielectric, such as at least one combination of silver and silicon oxide, aluminum and aluminum oxide, or gold and silicon oxide.

[0082] As an example, in this embodiment, the driving circuit in the driving backplane 10 includes at least three anodes, and all the anodes are arranged side by side. As shown in Figures 6 and 7, the at least three anodes include a first anode 11, a second anode 12 and a third anode 13.

[0083] The pixel unit 100 provided in this embodiment is a vertically stacked pixel (VSP). Compared with a pixel unit in which different sub-pixels are arranged in the same horizontal direction, VSP can effectively increase pixel density.

[0084] 2 , the display unit 20 includes a first device layer 30, a second device layer 40, and a third device layer 50, which are stacked vertically in sequence in a direction away from the driving backplane 10. The first device layer 30 includes at least one first sub-pixel 31, the second device layer 40 includes at least one second sub-pixel 41, and the third device layer 50 includes at least one third sub-pixel 51. The projection of any first sub-pixel 31, any second sub-pixel 41, or any third sub-pixel 51 on the driving backplane 10 is located within the projection of any sub-pixel above it on the driving backplane 10.

[0085] In some embodiments, the display device 20 further includes a top via corresponding to each anode, wherein the top via is filled with metal to form an anode filling layer. The distribution and shape of the anode filling layer are determined by a heavy-duty layer (RDL) process.

[0086] As described above, the pixel unit 100 in this embodiment can achieve RGB full-color display. The first device layer 30 emits red light in the working state, the second device layer 40 emits green light in the working state, and the third device layer 50 emits blue light in the working state. When any device layer is illuminated alone, a color display can be achieved, and when all three device layers are illuminated simultaneously, a white light display can be achieved. Therefore, the first sub-pixel 31 is made of an InGaN ternary material system or a quaternary AlGaInP red light compound on a GaAs substrate. The corresponding substrate material can be GaAs, Si, Sapphire, or Ga2O3. The second sub-pixel 41 is made of a green light InGaN ternary material system, and the third sub-pixel 51 is made of a blue light InGaN ternary material system. The corresponding substrate can be GaN, Si, SiC, Sapphire, etc.

[0087] In this embodiment, any sub-pixel among the first sub-pixel 31, the second sub-pixel 41 and the third sub-pixel 51 is a hemisphere, a hemi-ellipsoid or a cylinder with a hemispherical light-emitting surface. The hemispherical or quasi-hemispherical sub-pixel can increase the light extraction efficiency, and it has been verified that it can increase the pixel brightness by more than 30%.

[0088] As shown in FIG15 , the surface of the first sub-pixel 31 , the second sub-pixel 41 or the third sub-pixel 51 is roughened to further enhance the light extraction efficiency.

[0089] In one structure, the center point of any one of the first sub-pixel 31, the second sub-pixel 41, and the third sub-pixel 51 is located on the same vertical line of the driving backplane 10. In this structure, the volume of any sub-pixel is equal to or greater than the volume of any sub-pixel located below it, as shown in Figures 2, 19, and 21. In another structure, the center point of at least one of the first sub-pixel 31, the second sub-pixel 41, and the third sub-pixel 51 is located outside the same vertical line of the driving backplane 10, as shown in Figure 20. In this structure, the volume of any sub-pixel is greater than the volume of any sub-pixel located below it. Both of the above structures are coaxial vertical stacking structures of related sub-pixels in different device layers considered in this embodiment.

[0090] Continuing with Figures 2 and 6 , corresponding to the at least three anodes provided on the driver backplane 10, the first device layer 30 is provided with at least three top through-holes corresponding to the first anode 11. Each of the top through-holes is filled with a metal conductive material to form an anode filling layer 111. Each anode filling layer 111 corresponds to an anode, facilitating subsequent electrical connections between the device layer and the anode. In a preferred embodiment, at least one point of any of the at least three anode filling layers 111 is located on the same straight line of the driver backplane 10. For example, the center points of the three anode filling layers 111 are located on the same diagonal line of the driver backplane 10, with the diagonal line located within the AB cross-section. As shown in Figure 6 , the anode filling layers 111 corresponding to the first anode 11 and the third anode 13 are located at two opposite corners of the driver backplane 10, respectively, while the anode filling layer 111 corresponding to the second anode 12 is located at the center of the driver backplane 12. Of course, in order to subsequently stack more redundant device layers to improve the reliability and brightness of the pixel unit 100, the number of anode filling layers 111 can be four or even more. For example, two anode filling layers 111 are provided for the first anode 11 and the third anode 13. For ease of description, the present embodiment shows the structure along the AB section and provides the following detailed description. Further technical solutions based on this are also within the scope of implementation of this embodiment.

[0091] Therefore, in one structure, any first sub-pixel 31 is connected to the corresponding anode filling layer 111 to achieve anode electrical connection, and the corresponding bonding process is alignment bonding.

[0092] As mentioned above, the first device layer 30 also includes a first dielectric layer 32, a first passivation layer 33, a first ohmic layer 34 and a first filling layer 35. The first dielectric layer 32 is entirely covered on the driving backplane 10, and any of the above-mentioned anode filling layers 111 are embedded in the first dielectric layer 32. Any first sub-pixel 31 is provided on the surface of the first dielectric layer 32 away from the driving backplane 10, and any first sub-pixel 31 is connected to the top of the anode filling layer 111 corresponding to the first anode 11. The first passivation layer 33 is also a full-surface structure, covering any first sub-pixel 31 and the surface of the first dielectric layer 32 away from the driving backplane 10. Of course, the first passivation layer 33 is provided with openings corresponding to any first sub-pixel 31 and any anode filling layer 111 respectively. The first ohmic layer 34 is also a full-surface structure, and the first passivation layer 33 is provided with openings corresponding to any anode filling layer 111. The first ohmic layer 34 is connected to any first sub-pixel 31 through the opening of the first passivation layer 33 , so as to realize cathode connection of any first sub-pixel 31 .

[0093] Therefore, the first dielectric layer 32, the first passivation layer 33, and the first ohmic layer 34 in the first device layer 30 are all full-surface structures with at least one opening. The first dielectric layer 32 is made of a transparent or opaque dielectric material, which can be silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, etc., or can be an organic silicon type material, such as organic silicon modified polyimide (PI), polymethyl methacrylate (PMMA), photoresist (SU8), etc. The first passivation layer 33 is made of a transparent dielectric material, such as silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, etc. The anode filling layer 111 is made of a conductive material, such as a metal or a laminate such as Al, Cu, Au, W, Ti, etc., or can be a metal oxide material such as ITO, ZnO, etc. The first ohmic layer 34 is made of a transparent conductive material, such as a transparent conductive metal oxide such as ITO or ZnO, or a thin alloy or laminate of a metal such as Al, Au, Ge, Ni, or Cr. It can also be a mixture of a metal oxide and a metal, such as ITO and Al, ITO and Au, or ITO and Ag. The first filling layer 35 is made of a transparent dielectric material, such as silicon oxide, silicon nitride, aluminum oxide, or aluminum nitride.

[0094] The first filling layer 35 wraps any first sub-pixel 31 and is used for filling and smoothing the first device layer 30. The first filling layer 35 is made of a transparent dielectric material, and preferably, the transparent dielectric material used in the first filling layer 35 has a light screening function, allowing the first sub-pixel 31 light source (red light) to pass through, and has a reflection function for the second sub-pixel 41 light source (green light) and the third sub-pixel 51 light source (blue light). Specifically, the transmittance of the first filling layer 35 to visible light in the 600nm to 650nm band (red light band) is not less than 90%, and the reflectivity of the first filling layer 35 to visible light in the 500nm to 550nm band (green light band) is not less than 90%. This effectively improves the light transmittance of the vertically coaxially stacked pixel unit 100 and avoids light loss.

[0095] The above is a structure when alignment bonding is adopted between the first device layer 30 and the driving backplane 10 .

[0096] When the first device layer 30 and the driving backplane 10 are non-alignedly bonded, the difference from the above-mentioned aligned bonding is that the first device layer 30 also includes at least one first conductive layer 36, any first conductive layer 36 is arranged between any first sub-pixel 31 and the first dielectric layer 32, and the first conductive layer 36 is connected to the corresponding anode filling layer 111 to realize the anode electrical connection of the first sub-pixel 31.

[0097] As described above, the second device layer 40 further includes a second dielectric layer 42, a second passivation layer 43, a second ohmic layer 44, a second filling layer 45, and at least two first connecting layers 46. The second passivation layer 43 is disposed on the surface of any second sub-pixel 41, and the second ohmic layer 44 is disposed on the surface of the second passivation layer 43. The second ohmic layer 44 is connected to any second sub-pixel 41 through the second passivation layer 43. The materials used for each layer of the second device layer 40 are substantially the same as those used for the first device layer 30. The second ohmic layer 44 is a full-surface film structure made of a transparent conductive material, while the second passivation layer 43 is a full-surface film structure made of a transparent dielectric material. Both the second ohmic layer 44 and the second passivation layer 43 have multiple openings for electrical connection between the device layer and the upper device layer. The second ohmic layer 44 is bonded and connected to the corresponding second sub-pixel 41 through the openings in the second passivation layer 43 to establish the cathode electrical connection of the second device layer 40.

[0098] Preferably, the transparent dielectric material used in the second filling layer 45 has a light-filtering function, with a transmittance of not less than 90% for visible light in the 600nm to 650nm band and the 500nm to 550nm band. Furthermore, the second filling layer 45 has a reflectivity of not less than 90% for visible light in the 400nm to 460nm band. In other words, the second filling layer 45 allows the light source (red light) of the first sub-pixel 31 and the light source (green light) of the second sub-pixel 41 to pass through, while reflecting the light source (blue light) of the third sub-pixel 51.

[0099] Any first connecting layer 46 is embedded within the second dielectric layer 42 and positioned above any anode fill layer 111. At least one first connecting layer 46 serves to electrically connect the anode of the second sub-pixel 41. The first device layer 30 also includes at least one anode electrical connection structure 60. One end of any anode electrical connection structure 60 in the first device layer 30 is connected to the anode fill layer 111, and the other end is connected to the corresponding first connecting layer 46. Therefore, the second device layer 40 achieves anode electrical connection via the sequentially connected first connecting layer 46, anode electrical connection structure 60, and anode fill layer 111.

[0100] Preferably, the second device layer 40 under this structure further includes a second conductive layer 47, one side of the second conductive layer 47 is connected to the second sub-pixel 41, and the other side is connected to the corresponding first connecting layer 46. It can be understood that this structure is implemented using a non-aligned bonding process.

[0101] On this basis, in one structure, as shown in FIG2 , when the volume of the sub-pixels in each device layer is equal, the center point of each sub-pixel lies on the same straight line. To prevent the anode electrical connection structure 60 of the upper device layer from damaging or blocking the sub-pixels in the lower layer, the projection of the second conductive layer 47 on the driving backplane 10 is larger than the projection of the second sub-pixel 41 on the driving backplane 10. That is, the second conductive layer 47 extends laterally to connect with the corresponding first connecting layer 46. As a result, the second sub-pixel 41 is connected to the second anode 12 through the second conductive layer 47, the first connecting layer 46, the anode electrical connection structure 60, and the anode filling layer 111, thereby achieving anode electrical connection.

[0102] In another structure, as shown in FIG20 , when the volume of the second sub-pixel 41 is larger than the volume of the corresponding first sub-pixel 31, the projection of the second sub-pixel 41 on the driver backplane 10 is larger than the projection of the first sub-pixel 31 on the driver backplane 10. Therefore, an anode electrical connection structure 60 is constructed vertically in the portion of the structure where the second sub-pixel 41 horizontally extends beyond the first sub-pixel 31 to achieve anode electrical connection. That is, when the volume of the second sub-pixel 41 is larger than the volume of the corresponding first sub-pixel 31, the projection of the anode electrical connection structure 60 corresponding to the second sub-pixel 41 on the driver backplane 10 is located within the projection of the second sub-pixel 41 on the driver backplane 10, and the anode electrical connection structure 60 is spaced apart from the first sub-pixel 31.

[0103] With this structure, the size and horizontal relative position of the first and second sub-pixels 31 and 41 can be adjusted based on both optical and physical requirements. The anode electrical connection structure 60 of each corresponding sub-pixel is then combined to achieve electrical connection of the anodes of each device layer. Therefore, within the pixel unit 100 with this structure, each device layer can customize the position and size of any sub-pixel, provided the aforementioned conditions are met, to meet diverse color matching requirements, providing greater flexibility.

[0104] Similarly, the third device layer 50 also includes a third dielectric layer 52, a third passivation layer 53, a third ohmic layer 54, a third filling layer 55, a second busbar layer 56, and a third conductive layer 57. The third passivation layer 53 covers the surface of any third sub-pixel 51, and the third ohmic layer 54 covers the surface of the third passivation layer 53. The third ohmic layer 54 penetrates the third passivation layer 53 and connects to any third sub-pixel 51. Similar to the second device layer 40, the third passivation layer 53 and the third ohmic layer 54 are solid structures with corresponding openings. Furthermore, the third dielectric layer 52, the third conductive layer 57, the third sub-pixels 51, the third passivation layer 53, and the third ohmic layer 54 are stacked in sequence, away from the driver backplane 10. Furthermore, the volume of any third sub-pixel 51 can be larger or the same as that of the sub-pixel below it. Of course, the corresponding third conductive layer 57 and the corresponding anode electrical connection structure 60 are arranged in the same manner as the structure of the second device layer 40. For details, please refer to the above description.

[0105] Preferably, the transparent dielectric material used in the third filling layer 55 has a light-filtering function, with a transmittance of not less than 90% for visible light in the 600nm to 650nm, 500nm to 550nm, and 400nm to 460nm bands. In other words, the third filling layer 55 allows the light source (red light) of the first sub-pixel 31, the light source (green light) of the second sub-pixel 41, and the light source (blue light) of the third sub-pixel 51 to pass through.

[0106] As previously mentioned, as shown in Figures 2 and 17 , each device layer also includes a reinforcement structure 70. This reinforcement structure 70 is disposed around the circumference of each device layer and is made of a metal filler material to enhance optical performance and structural stability. Specifically, one end of the reinforcement structure 70 is connected to the ohmic layer of the device layer in question, and the other end is connected to the passivation layer of the previous device layer.

[0107] As shown in FIG2 , an optical lens 81 is further provided above the display unit 20. The optical lens 81 is a hemispherical structure made of an inorganic transparent dielectric material or an organic transparent dielectric material. The provision of the optical lens 81 in this embodiment can further enhance the luminance and optimize the luminous angle of the pixel unit 100.

[0108] As described above, as shown in FIG3 , any of the first device layer 30, the second device layer 40, and the third device layer 50 further includes a color conversion layer 82 disposed above any sub-pixel, the color conversion layer 82 absorbing the excitation light source emitted by the corresponding sub-pixel and converting it to a target light source. Exemplarily, the first device layer 30 further includes a color conversion layer 82 disposed above any sub-pixel, the color conversion layer 82 absorbing the excitation light source emitted by the first sub-pixel 31 and converting it to red light. In this structure, the first sub-pixel 31 is made of a blue light InGaN compound or a green light InGaN compound to form an excitation light source, and the color conversion layer 82 is made of a red light quantum dot material or a red phosphor material. Specifically, the red light quantum dot material can be a mixture of one or more of a perovskite red light quantum dot material, a CsPdI3 material, an InP material, a CdSe material, or a CdS material.

[0109] Corresponding to the pixel unit 100, this embodiment further provides a method for manufacturing the pixel unit 100, the manufacturing method comprising:

[0110] S10 , preparing to drive the backplane 10 .

[0111] This embodiment preferably utilizes a CMOS integrated circuit backplane, which is provided with a top metal and includes a common cathode disposed on its periphery. The driver backplane 10 has multiple anodes. To achieve full-color display, this embodiment includes at least three anodes: a first anode 11, a second anode 12, and a third anode 13, corresponding to the three sub-pixels of R (red), G (green), and B (blue), respectively. This embodiment does not restrict the distribution of the individual anodes, and each anode can have a multi-channel redundant structure.

[0112] In particular, in order to meet the optoelectronic requirements of subsequent device layers, the electrical channels of the CMOS integrated circuit backplane are reconstructed through redistribution layer technology (RDL), that is, the dielectric layer, top through-hole and anode filling layer are arranged on the driving backplane 10 using semiconductor technology.

[0113] The specific steps are as follows:

[0114] S101, coating the entire surface of the driving backplane 10 with a dielectric layer, where the dielectric layer may be made of dielectric materials such as silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or an organic silicon material such as PI, PMMA, or SU8;

[0115] S102, forming a plurality of top through holes on the dielectric layer using a patterning process;

[0116] S103 , filling each top through hole with a conductive material to form a corresponding anode filling layer. The conductive material includes a metal or a laminate such as Al, Cu, Au, W, Ti, or a metal oxide material such as ITO or ZnO.

[0117] In this embodiment, as shown in FIG. 6 , two anode filling layers corresponding to the first anode 11 , one anode filling layer corresponding to the second anode 12 , and two anode filling layers corresponding to the third anode 13 are formed.

[0118] S20, manufacturing the display unit 20. The steps include:

[0119] S210 , as shown in FIG. 7 to FIG. 18 , bonding the first target compound semiconductor 91 to the driving backplane 10 and constructing at least one first sub-pixel 31 to form a first device layer 30 ;

[0120] S220 , as shown in FIG. 19 to FIG. 21 , bonding the second target compound semiconductor to the first device layer 30 and constructing at least one second sub-pixel 41 to form a second device layer 40 ;

[0121] S230 , bonding the third target compound semiconductor to the second device layer 40 and constructing at least one third sub-pixel 51 to form a third device layer 50 , as shown in FIG. 2 or FIG. 3 .

[0122] Among them, the projection of any first sub-pixel 31, any second sub-pixel 41 or any third sub-pixel 51 on the driving backplane 10 is located within the projection of any sub-pixel above it on the driving backplane 10; the first device layer 30 emits red light in the working state, the second device layer 40 emits green light in the working state, and the third device layer 50 emits blue light in the working state.

[0123] Specifically, step S210 includes:

[0124] S211 : Prepare a first target compound semiconductor 91 .

[0125] The compound semiconductor in this embodiment is typically a wafer or a region of suitable size cut from a wafer. The wafer has semiconductor properties such as a defined bandgap and band structure. The wafer may include crystalline inorganic compounds (such as III-V and II-VI compound semiconductors), organic compounds (such as organic semiconductors), or oxide semiconductors, and any combination thereof can be used in the subsequent VSP stacking of compounds. The wafer includes a compound epitaxial layer and a substrate. In this embodiment, the compound epitaxial material used for the red sub-pixel is InGaN ternary material system epitaxy or quaternary AlGaInP red light compound epitaxy, and the substrate material may be GaAs, Si, Sapphire, Ga2O3, etc. The compound semiconductor material used for the blue / green sub-pixel is green light InGaN or blue light InGaN ternary material system, and the substrate material may be GaN, Si, SiC, Sapphire, etc. Specifically, the compound epitaxial layer includes, in the direction close to the substrate, a P contact, an active quantum hydrazine layer (MQW), an N contact, and an etch stop layer.

[0126] In this embodiment, the first target compound semiconductor 91 is made of InGaN ternary material system epitaxy or quaternary AlGaInP red light compound epitaxy, and the specific structure is shown in Table 1 or Table 2 below:

[0127] Table 1

[0128] Table 2

[0129] S212, bonding the first target compound semiconductor 91 to the driving backplane 10. The bonding method in this step can be aligned bonding or non-aligned bonding.

[0130] When non-aligned bonding is used, as shown in FIG7 to FIG10 , the following steps are included:

[0131] S212a1, preparing an ohmic contact layer on the P contact surface of the first target compound semiconductor 91;

[0132] S212a2, coating the entire surface of the first target compound semiconductor 91 with a bonding layer;

[0133] S212a3, plating a bonding layer on the entire surface of the driving backplane 10 obtained in S103;

[0134] S212a4, bonding the first target compound semiconductor 91 obtained in S212b2 to the two bonding surfaces of the driving back plate 10 obtained in S212a3;

[0135] In step S212 a 4 , the anode filling layer constructed on the surface of the driving back plate 10 is the anode filling layer 111 of the first device layer 30 .

[0136] S212a4: Use wet etching to remove the substrate of the first target compound semiconductor 91, exposing the N-contact surface.

[0137] As described above, when non-aligned bonding is used, the ohmic contact layer and the bonding layer of the P contact surface of the first target compound semiconductor 91 in step S212b4 are combined into a first conductive layer 36, which is provided between the driving backplane 10 and the active quantum hydrazine layer.

[0138] When alignment bonding is used, as shown in Figures 11 to 14, the following steps are included:

[0139] S212b1. Prepare an ohmic contact layer on the P contact surface of the first target compound semiconductor 91. The contact material can be a transparent conductive material such as ITO, ZnO, etc., or a stack or alloy of metal materials such as Ni, Au, Ag, Be, Zn, etc.

[0140] For example, a GaAs-based red light AlGaInP compound is used to coat an AuBe alloy film by evaporation, sputtering, etc. The AuBe alloy film has a thickness of 60 nm and is annealed at 410°C in an N2 environment to form an ohmic contact. The thickness and formation conditions of the ohmic contact layer on the surface of the compound can be adjusted according to needs.

[0141] S212b2, coating the entire surface of the first target compound semiconductor 91 with a dielectric layer, forming a plurality of through holes in the dielectric layer using a patterning process, and filling each through hole with a conductive material to form a corresponding anode filling layer. The distribution of the anode filling layer in this step corresponds to the distribution of the top through holes in step S103;

[0142] S212b3: Patterning a bonding layer is performed on the first target compound semiconductor 91, and patterning a bonding layer is performed on the driving backplane 10 obtained in step S103. Specifically, the bonding layer is deposited by sputtering or evaporating 1 nm of Cr and / or 50 nm of Au. Of course, the same bonding material is used in one bonding.

[0143] S212b4, bonding the first target compound semiconductor 91 in S212b3 to the surface of the driving backplane 10 coated with a bonding layer.

[0144] In step S212b4, the anode filling layer and the bonding layer included in the first target compound semiconductor 91 are stacked with the anode filling layer constructed on the surface of the driving backplane 10 to form the anode filling layer 111 of the first device layer 30.

[0145] It should be noted that chemical mechanical polishing (CMP) is used for planarization before bonding, so that the flatness of the bonding surface is less than 5 nm, or even less than 0.5 nm.

[0146] S212b5. Use wet etching to remove the substrate of the first target compound semiconductor 91 to expose the N contact surface.

[0147] S213: Construct at least one first sub-pixel 31. As shown in FIG16 , S213 includes the following sub-steps:

[0148] S2131: Pattern the active quantum well layer according to a preset sub-pixel pattern and perform etching to form at least one first sub-pixel 31. In this embodiment, the first sub-pixel 31 is a hemisphere, a hemi-ellipsoid, or a column with a hemispherical light-emitting surface.

[0149] Preferably, the formed first sub-pixel 31 is subjected to a surface roughening treatment to improve its surface roughness.

[0150] When non-aligned bonding is used in step S212 , the first conductive layer 36 having a shape and an electrical connection structure corresponding to the first sub-pixel 31 is simultaneously etched in this step.

[0151] S2132 , a transparent dielectric material is deposited on the entire surface of the first sub-pixel 31 to form a first passivation layer 33 .

[0152] Specifically, the first passivation layer 33 is prepared by ALD, CVD, PVD or the like, and the transparent dielectric material includes but is not limited to single layers or stacked layers of aluminum oxide, silicon oxide, silicon nitride, aluminum nitride or the like.

[0153] S2133: Patterned etching is used to create an opening in the first passivation layer 33 corresponding to the top of the first sub-pixel 31, thereby exposing the top of the first sub-pixel 31. A corresponding opening is also created in the anode fill layer 111, which is provided for redundant electrical connection. Etching methods include, but are not limited to, wet etching or dry etching.

[0154] S2134 , performing full-surface coating on the surface of the first passivation layer 33 to form a first ohmic layer 34 .

[0155] Specifically, the first ohmic layer 34 is prepared by electron beam, ion beam, sputtering, etc., and corresponding openings are opened in the anode filling layer 111 preset for redundant electrical connection by etching, corresponding to the openings opened in the first passivation layer 33.

[0156] The first ohmic layer 34 is a combination of one or more of transparent metal oxides, metal thin layers, alloy thin layers, and metal stacks, such as ITO, ZnO, Al, Au, Ge, Ni, Cr, Ag, etc. For example, ITO and Al, ITO and Au, ITO and Ag, etc.

[0157] S214, as shown in Figures 17 and 18, construct an anode electrical connection structure 60 for subsequent device layers and perform device layer filling to form a first device layer 30. This step includes the following two implementations.

[0158] In one method, at least two anode electrical connection structures 60 are first constructed, and then filled with a transparent dielectric material to form a first filling layer 35 . The filling layer is planarized to expose the upper ends of the anode electrical connection structures 60 .

[0159] In another method, a transparent dielectric material is first used to fill and planarize the device layer, and then a through hole for constructing the corresponding anode electrical connection structure 60 is formed by a patterned etching method, and finally a metal is filled in the through hole to form the anode electrical connection structure 60.

[0160] As described above, while constructing the anode electrical connection structure 60 , a metal filling method is used to construct the reinforcement structure 70 surrounding the first device layer 30 .

[0161] As mentioned above, the first filling layer 35 is made of an organic material with light-filtering properties, or a Bragg reflector layer composed of a silicon oxide and titanium oxide laminate. Organic materials include silicone-modified polyimide (PI), polymethyl methacrylate (PMMA), and photoresist (SU8). As previously mentioned, the first filling layer 35 has a transmittance of at least 90% for visible light in the 600nm to 650nm band (red band), and a reflectance of at least 90% for visible light in the 500nm to 550nm band (green band).

[0162] After the first device layer 30 is constructed, step S220 is performed. As shown in Figures 19 to 21, step S220 includes:

[0163] S221 , plating a bonding layer on the surface of the second target compound semiconductor, plating a bonding layer on the surface of the first device layer 30 , and bonding the second target compound semiconductor and the first device layer 30 relative to each other.

[0164] S222: Construct at least one second sub-pixel 41, a corresponding second dielectric layer 42, and a second ohmic layer 44. The projection of the first sub-pixel 31 on the driver backplane 10 is located within the projection of the corresponding second sub-pixel 41 on the driver backplane 10. That is, the second sub-pixel 41 and the first sub-pixel 31 are coaxially and vertically stacked, and the volume of the second sub-pixel 41 is not less than that of the first sub-pixel 31. Based on this, the volume of the first sub-pixel 31 can be adjusted flexibly to meet different color matching requirements, as shown in Figures 19 and 20.

[0165] S223 , constructing an anode electrical connection structure 60 for a subsequent device layer of the present device level and performing device layer filling to form a second device layer 40 .

[0166] In the above steps, the second target compound semiconductor is made of a green light InGaN ternary material system, and an exemplary structure is shown in Table 3 or Table 4 below:

[0167] Table 3

[0168] Furthermore, the second sub-pixel 42 is a hemisphere, a hemi-ellipsoid or a column with a hemispherical light-emitting surface, and a lateral anode electrical connection structure 60 needs to be constructed. Therefore, non-aligned bonding is used during bonding in step S221 to construct a second conductive layer 47 with a certain extension length.

[0169] As described above, step S230 is performed in the same manner, with the only difference being that the third target compound semiconductor 99 is made of its blue light InGaN ternary material system.

[0170] In the process of manufacturing the RGB pixel unit including three device layers, the display unit 20 is manufactured after completing the above S230. Of course, constructing more device layers on this basis to achieve a redundant structure is also within the scope of this embodiment.

[0171] Furthermore, after the display unit 20 is manufactured, the manufacturing method further includes constructing an optical lens 81 on a side of the display unit 20 away from the driving backplane 10 .

[0172] In summary, the pixel units in this embodiment adopt a vertical coaxial stacking method to effectively improve the pixel density, and on this basis, it is possible to meet different color matching requirements by adjusting the volume size of the sub-pixels in different device layers; and, this embodiment realizes multi-color display while improving the brightness of the light source by setting the filling layer included in the device layer to allow light to pass through the lower device layer and reflect the light source of the upper device layer; and, this embodiment increases the light extraction efficiency by constructing sub-pixels with a hemispherical structure, and the brightness of the sub-pixels is improved by more than 30%.

[0173] Example 2

[0174] As shown in FIG22 , this embodiment provides a pixel unit 100 in another structure. The pixel unit 100 includes a driving backplane 10 and a display unit 20 disposed on the driving backplane 10. The display unit 20 includes a first device layer 30, a second device layer 40, and a third device layer 50, which are stacked vertically in a direction away from the driving backplane 10. The first device layer 30 includes at least one first sub-pixel 31, the second device layer 40 includes at least one second sub-pixel 41, and the third device layer 50 includes at least one third sub-pixel 51. The projection of any first sub-pixel 31, any second sub-pixel 41, or any third sub-pixel 51 on the driving backplane 10 is located within the projection of any sub-pixel above it on the driving backplane 10. The first device layer 30 emits red light in an operating state, the second device layer 40 emits green light in an operating state, and the third device layer 50 emits blue light in an operating state.

[0175] Compared to Example 1, the pixel unit 100 in this embodiment differs in that: any first sub-pixel 31, any second sub-pixel 41, and any third sub-pixel 51 is a rectangular parallelepiped; any anode electrical connection structure 60 in the first device layer 30 is embedded in the corresponding first sub-pixel 31; and the projection of any anode electrical connection structure 60 in the first device layer 30 on the driver backplane 10 is located within the projection of any third sub-pixel 51 on the driver backplane 10. In other words, the anode electrical connection structure 60 corresponding to the upper device layer passes through the lower device layer and is connected to the corresponding anode in the driver backplane 10.

[0176] 22 , any sub-pixel extends circumferentially to the edge of the device layer so that the first sub-pixel 31 , the second sub-pixel 41 and the third sub-pixel 51 have equal areas in the horizontal direction, thereby increasing the proportion of the light-emitting area of ​​each sub-pixel to improve the pixel density.

[0177] Similarly, this embodiment also provides a method for manufacturing a pixel unit, which is similar to the manufacturing method in Example 1. Since this embodiment does not require a lateral construction of the anode electrical connection structure 60, the bonding between the device layers adopts alignment bonding, and there is no need to form any conductive layer.

[0178] Therefore, the structure and manufacturing method of the pixel unit 100 in this embodiment are similar to those in Example 1, and will not be described in detail in this embodiment. The specific structure can refer to the description in Example 1.

[0179] Example 3

[0180] This embodiment provides a micro display screen 200, as shown in FIG23 , and the micro display screen 200 includes:

[0181] The micro display backplane 300 includes at least two driving circuits, an input interface, and an output interface;

[0182] A display area 400 is provided on the micro display back panel 300 and includes at least two display units 20 such as the pixel units 100 in Example 1 or Example 2, wherein the at least two display units 20 are arranged in an array;

[0183] The peripheral common cathode 500 is electrically connected to any ohmic layer of each display unit 20 , so that the entire micro display screen 200 has a common cathode. It should be noted that the peripheral common cathode 500 is a metal frame structure surrounding the display area 400 .

[0184] The external IO interface 600 is located at any position of the micro display screen back panel 300 .

[0185] Furthermore, this embodiment does not impose any restriction on the arrangement direction of each pixel unit 100 adjacently arranged in an array in the micro display screen 200 .

[0186] For the specific structure and corresponding technical effects of the micro display screen in this embodiment, please refer to the relevant description of Example 1, and no further detailed description will be given in this embodiment.

[0187] Example 4

[0188] As shown in FIG. 24 , this embodiment provides a pixel-level discrete device 700 , which includes:

[0189] A discrete device backplane 710 , the discrete device backplane 710 includes at least three anode pads 730 and at least one cathode pad (not shown);

[0190] The device body 720 is disposed on the discrete device backplane 710 , and the device body 720 includes at least two display units 20 such as those included in the pixel unit 100 in Example 1 or Example 2, and the at least two display units 20 are arranged in an array.

[0191] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present application, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the scope of protection of the present application and will not be described in detail here.

[0192] It should be noted that the above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A pixel unit, characterized in that: The pixel unit comprises: Driver backplane; A display unit, the display unit is arranged on the driving backplane, the display unit comprises a first device layer, a second device layer and a third device layer which are stacked vertically in sequence in a direction away from the driving backplane, the first device layer comprises at least one first sub-pixel, the second device layer comprises at least one second sub-pixel, the third device layer comprises at least one third sub-pixel, and a projection of any of the first sub-pixel, any of the second sub-pixel or any of the third sub-pixel on the driving backplane is located within a projection of any of the sub-pixels above them on the driving backplane; The first device layer emits red light in an operating state, the second device layer emits green light in an operating state, and the third device layer emits blue light in an operating state.

2. The pixel unit according to claim 1, characterized in that: The center point of any one of the first sub-pixel, the second sub-pixel and the third sub-pixel is located on the same vertical line of the driving backplane.

3. The pixel unit according to claim 1, characterized in that: The first device layer further comprises a first filling layer encapsulating any of the first sub-pixels, wherein the transmittance of the first filling layer to visible light in the wavelength band of 600nm to 650nm is not less than 90%, and the reflectivity of the first filling layer to visible light in the wavelength band of 500nm to 550nm is not less than 90%; The second device layer further comprises a second filling layer encapsulating any of the second sub-pixels, wherein the transmittance of the second filling layer to visible light in the wavelength bands of 600nm to 650nm and 500nm to 550nm is not less than 90%, and the reflectivity of the second filling layer to visible light in the wavelength band of 400nm to 460nm is not less than 90%; The third device layer also includes a third filling layer that wraps any of the third sub-pixels, and the transmittance of the third filling layer to visible light in the 600nm to 650nm band, the 500nm to 550nm band, and the 400nm to 460nm band is not less than 90%.

4. The pixel unit according to claim 1, characterized in that: The second device layer further includes a second passivation layer and a second ohmic layer; The second passivation layer is disposed on a surface of any second sub-pixel; The second ohmic layer is covered on a surface of the second passivation layer, and the second ohmic layer passes through the second passivation layer and is connected to any of the second sub-pixels.

5. The pixel unit according to claim 1, characterized in that: The driving backplane includes at least three anodes, the first device layer also includes at least three anode filling layers, and any of the anode filling layers is respectively connected to any corresponding anode; At least one point of any one of the at least three anode filling layers is located on the same straight line of the driving back plate.

6. The pixel unit according to claim 5, characterized in that: The second device layer further comprises at least two first connecting layers, any of the first connecting layers being located above any of the anode filling layers; The first device layer also includes at least one anode electrical connection structure. One end of any anode electrical connection structure in the first device layer is connected to the anode filling layer, and the other end is connected to the corresponding first interconnection layer.

7. The pixel unit according to claim 5, characterized in that: Any of the first sub-pixels is connected to the corresponding anode filling layer; or, The first device layer further includes at least one first conductive layer, one side of any first conductive layer is connected to any first sub-pixel, and the other side is connected to the corresponding anode filling layer.

8. The pixel unit according to claim 6, characterized in that: When any of the first sub-pixel, the second sub-pixel and the third sub-pixel is a hemisphere, a hemi-ellipsoid or a cylinder with a hemispherical light-emitting surface, and the volume of any sub-pixel is equal, the projection of any of the sub-pixels on the driving backplane does not overlap with the projection of any of the anode electrical connection structures on the driving backplane.

9. The pixel unit according to claim 8, characterized in that: The second device layer further comprises at least one second conductive layer, wherein a projection of the second conductive layer on the driving backplane is larger than a projection of the second sub-pixel on the driving backplane; One side of any second conductive layer is connected to any second sub-pixel, and the other side is connected to the corresponding first connecting layer.

10. The pixel unit according to claim 6, characterized in that: When any of the first sub-pixel, the second sub-pixel and the third sub-pixel is a rectangular parallelepiped, any of the anode electrical connection structures in the first device layer is embedded in the corresponding first sub-pixel, and the projection of any of the anode electrical connection structures in the first device layer on the driving backplane is located within the projection of any of the third sub-pixels on the driving backplane.

11. The pixel unit according to claim 1, characterized in that: Any device layer among the first device layer, the second device layer and the third device layer further includes a color conversion layer disposed above any sub-pixel, and the color conversion layer absorbs the excitation light source emitted by the corresponding sub-pixel and converts it into a target light source.

12. The pixel unit according to claim 1, characterized in that: The display unit further includes at least one reinforcing structure disposed in a circumferential direction of any device layer.

13. A method for manufacturing a pixel unit, characterized in that: The production method comprises: Prepare the drive backplane; Manufacturing a display unit, bonding a first target compound semiconductor to the driving backplane and constructing at least one first sub-pixel to form a first device layer; bonding a second target compound semiconductor to the first device layer and constructing at least one second sub-pixel to form a second device layer; bonding a third target compound semiconductor to the second device layer and constructing at least one third sub-pixel to form a third device layer; the projection of any of the first sub-pixel, any of the second sub-pixel or any of the third sub-pixel on the driving backplane is located within the projection of any of the sub-pixels above it on the driving backplane; The first device layer emits red light in an operating state, the second device layer emits green light in an operating state, and the third device layer emits blue light in an operating state.

14. A micro display screen, characterized in that: The micro display screen comprises: A micro display screen backplane, the micro display screen backplane comprising a driving circuit, an input interface and an output interface; A display area, the display area is arranged on the back panel of the micro display screen, and the display area includes at least two display units included in the pixel unit according to any one of claims 1 to 12, and at least two of the display units are arranged in an array; A peripheral common cathode is electrically connected to each of the display units.

15. A pixel-level discrete device, characterized in that: The pixel-level discrete device comprises: A discrete device backplane, the discrete device backplane comprising at least two anode pads and at least one cathode pad; A device body, wherein the device body is disposed on the discrete device backplane, and the device body comprises at least two display units included in the pixel unit according to any one of claims 1 to 12, and at least two of the display units are arranged in an array.

Images