Scramble circuit, communication system, and scramble method

The scrambling circuit addresses the challenge of rising data speeds by implementing parallel processing techniques, dividing data into sets and using multiple temporary and pattern generation circuits with EXOR operations, resulting in reduced processing time and improved efficiency.

WO2024262312A1PCT designated stage expired Publication Date: 2024-12-26NTT INNOVATIVE DEVICES CORP
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Patent Information

Application Number
PCT/JP2024/020538
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-06-19
Filing Date
2024-06-05
Publication Date
2024-12-26

AI Technical Summary

Technical Problem

Conventional scrambling circuits struggle to keep pace with increasing data speeds due to serial processing limitations, leading to inefficiencies in data scrambling and descrambling.

Method used

A scrambling circuit design that employs parallel processing by dividing data into sets and utilizing multiple temporary scrambling circuits and pattern generation circuits, along with EXOR circuits to perform exclusive OR operations, reducing the number of serial processing stages and enhancing processing speed.

Benefits of technology

This approach significantly reduces scrambling processing time, enabling the system to handle faster data speeds by parallelizing the scrambling of data sets, thus maintaining efficiency with increased data rates.

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Abstract

[PROBLEM] To reduce a scrambling time. [SOLUTION] These k temporary scramble circuits TS1-TSk use, as one data set, L (L is a natural number) x k (k is a natural number) pieces of data that are every k sets of every L pieces obtained by delimiting a series of data, and scramble k sequences of the one data set with each other in parallel. k pattern generation circuits PG1-PGk generate output data only from initial values without inputting the series of data. k EXOR circuits EX1-EXk obtain exclusive OR values for each piece of data in the same order with respect to the outputs of the k temporary scramble circuits TS1-TSk and the outputs of the k pattern generation circuits PG1-PGk, and output sequentially scrambled data for Lxk pieces of data. As an initial value of the i-th (i is a natural number of 2 to k) pattern generation circuit PGi among the k pattern generation circuits PG1-PGk, a portion of an output of an (i-1)-th EXOR circuit PGi-1 is set.
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Citation Information

Patent Citations

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    JP2001237826A