GOA driving circuit, display panel and display apparatus

Abstract

A GOA driving circuit (100), a display panel (1) and a display apparatus. The GOA driving circuit (100) comprises multiple cascaded GOA units (110), each GOA unit (110) comprising a trigger circuit (10), an inverter circuit (20), a pull-up circuit (30) and a pull-down circuit (40). The inverter circuit (20) comprises a first thin film transistor (T1) and a second thin film transistor (T2). When a first clock signal (CKL) is at a high level, the trigger circuit (10) and the first thin film transistor (T1) are turned on. When the trigger circuit (10) outputs a high level, voltages at two ends of the second thin film transistor (T2) are both at a high level, and a through current of the second thin film transistor (T2) is small. When the first clock signal (CKL) is at a low level, the first thin film transistor (T1) is turned off, and a through current cannot be formed at the second thin film transistor (T2).

Description

GOA driving circuit, display panel and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 14, 2023, with application number 202310863346.3 and invention name “GOA driving circuit, display panel and display device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the technical field of display panels, and in particular relates to a GOA driving circuit, a display panel, and a display device. Background Art

[0003] GOA (Gate Driver on Array) technology integrates the TFT (Thin Film Transistor) in the GOA drive circuit onto the array substrate, thereby eliminating the gate driver integrated circuit part originally set outside the array substrate, reducing product costs in terms of both material costs and process steps.

[0004] The GOA driving circuit usually includes multiple cascaded GOA units. The commonly used GOA unit is shown in Figure 1, which usually includes an inverting module, a reset module, a trigger module and an output module. The inverting module is used to realize the inverting conversion of the pull-up control signal PU to the pull-down control signal PD. However, in the inverting module, when PU is set high, T6 is turned on to pull the PD node low. At this time, T5 is in the on state, which will cause a through current between Vgh and Vgl, resulting in abnormal GOA unit, and then causing abnormal display of the display panel. Technical issues

[0005] The purpose of the present application is to provide a GOA driving circuit, which aims to solve the problem of abnormal display of the display panel caused by the through current problem in the inverting module of the traditional GOA unit. Technical Solutions

[0006] In order to solve the above technical problems, the technical solutions adopted in the embodiments of the present application are:

[0007] A first aspect of an embodiment of the present application provides a GOA driving circuit, comprising a plurality of cascaded GOA units, each of which comprises:

[0008] a trigger circuit, wherein the input end of the trigger circuit is used to input a start signal or an output signal of a previous-level GOA unit, and the control end of the trigger circuit is used to input a first clock signal. The trigger circuit is triggered to turn on and output the start signal or the output signal by a high-level signal of the first clock signal, and is triggered to turn off by a low-level signal of the first clock signal;

[0009] a pull-up circuit, wherein the input end of the pull-up circuit is used to input the second clock signal, the output end of the pull-up circuit constitutes the signal output end of the GOA unit, the control end of the pull-up circuit is connected to the output end of the trigger circuit, and the pull-up circuit is triggered by the start signal or the output signal to conduct and output the second clock signal;

[0010] An inverter circuit includes a first thin film transistor and a second thin film transistor, wherein a first terminal of the first thin film transistor is connected to a positive power supply terminal, a control terminal of the first thin film transistor and a second terminal of the second thin film transistor are used to input the first clock signal, the second terminal of the first thin film transistor and the first terminal of the second thin film transistor constitute an output terminal of the inverter circuit, the control terminal of the second thin film transistor is connected to the output terminal of the trigger circuit, and the first thin film transistor and the second thin film transistor are triggered to turn on by a high-level signal and to turn off by a low-level signal;

[0011] A pull-down circuit, wherein the input end of the pull-down circuit is used to input a first row shutdown signal, the output end of the pull-down circuit is commonly connected to the output end of the pull-up circuit, the control end of the pull-down circuit is connected to the output end of the inverter circuit, and the pull-down circuit is triggered to turn on by a high-level signal.

[0012] Optionally, the multiple levels of GOA units are respectively connected to corresponding row scan lines of the array substrate, and the multiple rows of scan lines are connected to multiple rows of pixel units on the array substrate. The multiple levels of GOA units output row open signals and row close signals to the multiple rows of pixel units row by row.

[0013] Optionally, the first thin film transistor and the second thin film transistor are N-channel thin film transistors.

[0014] Optionally, the trigger circuit includes a third thin film transistor and a fourth thin film transistor;

[0015] The first end of the third thin film transistor constitutes the input end of the trigger circuit, the second end of the third thin film transistor is connected to the first end of the fourth thin film transistor, the second end of the fourth thin film transistor constitutes the output end of the trigger circuit, and the control end of the third thin film transistor and the control end of the fourth thin film transistor are connected together to constitute the control end of the trigger circuit.

[0016] Optionally, the GOA driving circuit further includes:

[0017] A reset circuit, connected to the output end of the trigger circuit, and triggered by a reset control signal to reset each circuit of the GOA unit;

[0018] The reset circuit includes a fifth thin film transistor and a sixth thin film transistor;

[0019] The first end of the fifth thin film transistor is used to input the second row shutdown signal, the second end of the fifth thin film transistor and the first end of the sixth thin film transistor are connected in common, the second end of the sixth thin film transistor constitutes the output end of the reset circuit, and the control end of the fifth thin film transistor and the control end of the sixth thin film transistor are connected in common and input the reset control signal.

[0020] Optionally, the first row shutdown signal and the second row shutdown signal are low level signals.

[0021] Optionally, the GOA driving circuit further includes:

[0022] a stage transmission circuit, wherein the input end of the stage transmission circuit is used to input a third clock signal that is in antiphase with the first clock signal, the output end of the stage transmission circuit is connected to the input end of the trigger circuit of the GOA unit of the next stage, and the stage transmission circuit is triggered by the start signal or the output signal to conduct and output the third clock signal;

[0023] A bootstrap capacitor is connected in parallel between the output terminal and the control terminal of the stage transmission circuit.

[0024] Optionally, the stage transfer circuit includes a seventh thin film transistor, an eighth thin film transistor and a ninth thin film transistor;

[0025] The first end of the seventh thin film transistor and the first end of the ninth thin film transistor are connected together to form the input end of the stage transmission circuit, the second end of the seventh thin film transistor, the first end of the eighth thin film transistor, the control end of the ninth thin film transistor and the first end of the bootstrap capacitor are connected together to form the output end of the stage transmission circuit, the control end of the seventh thin film transistor, the second end of the bootstrap capacitor and the output end of the trigger circuit are connected, the control end of the eighth thin film transistor is connected to the output end of the inverter circuit, and the second end of the eighth thin film transistor is used to input the first row shutdown signal.

[0026] Optionally, the pull-up circuit includes a tenth thin film transistor, and the first end, the second end and the control end of the tenth thin film transistor constitute the input end, the output end and the control end of the pull-up circuit respectively;

[0027] The pull-down circuit includes an eleventh thin film transistor, and the first end, the second end and the control end of the eleventh thin film transistor respectively constitute the input end, the output end and the control end of the pull-down circuit.

[0028] Optionally, the pull-down circuit further includes a twelfth thin film transistor, a thirteenth thin film transistor and a coupling capacitor;

[0029] The first end of the coupling capacitor is used to input the third clock signal, the second end of the coupling capacitor, the control end of the twelfth thin film transistor and the first end of the thirteenth thin film transistor are connected in common, the first end and the second end of the twelfth thin film transistor are connected in parallel to the first end and the second end of the eleventh thin film transistor, the control end of the thirteenth thin film transistor is connected to the output end of the stage transfer circuit, and the second end of the thirteenth thin film transistor is used to input the second row shutdown signal.

[0030] Optionally, the stage transfer circuit further includes a fourteenth thin film transistor and a fifteenth thin film transistor;

[0031] The control end of the fourteenth thin film transistor is connected to the second end of the coupling capacitor, the first end and the second end of the fourteenth thin film transistor are connected in parallel to the first end and the second end of the eighth thin film transistor, the first end of the fifteenth thin film transistor is connected to the output end of the inverter circuit, the second end of the fifteenth thin film transistor is used to input the second row shutdown signal, and the control end of the fifteenth thin film transistor is used to input the third clock signal.

[0032] Optionally, during the time when the stage transfer circuit and the pull-down circuit continuously output low-level signals, the eighth thin film transistor and the fourteenth thin film transistor are cross-connected and the eleventh thin film transistor and the twelfth thin film transistor are cross-connected and turned off.

[0033] A second aspect of the embodiments of the present application provides a display panel, including an array substrate and the GOA driving circuit as described above, wherein the GOA driving circuit is disposed on one side or both sides of the array substrate.

[0034] A third aspect of the embodiments of the present application provides a display device, comprising a backlight module, a driver circuit board, and the display panel as described above, wherein the backlight module and the display panel are arranged opposite to each other, and the driver circuit board is electrically connected to the display panel.

[0035] Optionally, the backlight module is used to provide backlight, the driver circuit board is connected to the display panel through the chip-on-chip film, and inputs an external control signal to the driver chip in the chip-on-chip film, and the driver chip converts the external control signal into a data signal and a control signal required for driving the GOA driver circuit. Beneficial effects

[0036] A first aspect of an embodiment of the present application provides a GOA driving circuit, comprising a plurality of cascaded GOA units, each GOA unit comprising a trigger circuit, an inverter circuit, a pull-up circuit, and a pull-down circuit, the inverter circuit comprising a first thin film transistor and a second thin film transistor, when the first clock signal is at a high level, the trigger circuit and the first thin film transistor are turned on, when the trigger circuit outputs a high level, the voltages at both ends of the second thin film transistor are both at a high level, the through current of the second thin film transistor is small, and when the first clock signal is at a low level, the first thin film transistor is turned off, and the second thin film transistor is also unable to form a through current, thereby improving the working reliability of the GOA unit and thereby improving the display reliability of the display panel.

[0037] It can be understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] FIG1 is a circuit diagram of a conventional GOA unit;

[0040] FIG2 is a schematic structural diagram of a GOA driving circuit provided in Example 1 of the present application;

[0041] FIG3 is a schematic diagram of the first structure of the GOA unit provided in Example 1 of the present application;

[0042] FIG4 is a schematic diagram of a second structure of a GOA unit provided in Example 1 of the present application;

[0043] FIG5 is a circuit diagram of a GOA unit provided in Example 2 of the present application;

[0044] FIG6 is a schematic structural diagram of a GOA unit provided in Example 3 of the present application;

[0045] FIG7 is a circuit diagram of a GOA unit provided in Example 3 of the present application;

[0046] FIG8 is a schematic diagram of the signal timing of the GOA unit provided in Example 3 of the present application;

[0047] FIG9 is a waveform diagram of a GPD node provided in Example 4 of the present application;

[0048] FIG10 is a schematic diagram showing changes in current and voltage of a thin film transistor provided in Example 4 of the present application;

[0049] FIG11 is a circuit diagram of a GOA unit provided in Example 4 of the present application;

[0050] FIG12 is a schematic diagram of the signal timing of the GOA unit provided in Example 4 of the present application;

[0051] FIG13 is a schematic diagram of a first structure of a thin film transistor provided in Example 4 of the present application;

[0052] FIG14 is a schematic diagram of a second structure of a thin film transistor provided in Example 4 of the present application;

[0053] FIG15 is a schematic diagram of a third structure of a thin film transistor provided in Example 4 of the present application;

[0054] FIG16 is a schematic structural diagram of a display panel provided in Example 5 of the present application;

[0055] FIG17 is a schematic structural diagram of a display device provided in Example 6 of the present application.

[0056] Among them, the reference numerals in the figures are:

[0057] 1. Display panel; 2. Driver circuit board; 3. Backlight module; 100. GOA driver circuit; 200. Array substrate; 110. GOA unit; 10. Trigger circuit; 20. Inverter circuit; 30. Pull-up circuit; 40. Pull-down circuit; 50. Reset circuit; 60. Stage transfer circuit; 11. Substrate; 12. Buffer layer; 13. Active layer; 14. Gate insulation layer; 15. Top gate layer; 16. Interlayer insulation layer; 171. Source; 172. Drain; 18. Bottom gate layer;

[0058] T1, first thin film transistor; T2, second thin film transistor; T3, third thin film transistor; T4, fourth thin film transistor; T5, fifth thin film transistor; T6, sixth thin film transistor; T7, seventh thin film transistor; T8, eighth thin film transistor; T9, ninth thin film transistor; T10, tenth thin film transistor; T11, eleventh thin film transistor; T12, twelfth thin film transistor; T13, thirteenth thin film transistor; T14, fourteenth thin film transistor; T15, fifteenth thin film transistor; C1, bootstrap capacitor; C2, coupling capacitor;

[0059] STV, start signal; Cn1, first-level transmission signal; Cn2, second-level transmission signal; Cn3, third-level transmission signal; Gn1, first scan signal; Gn2, second scan signal; Gn3, third scan signal; Cn-1, level transmission signal of previous-level GOA unit; CKL, first clock signal; CKBL, third clock signal; CK, second clock signal; CKB, fourth clock signal; ECK1, fifth clock signal; ECK2, sixth clock signal; VDD, positive power supply signal; RST, reset control signal; Cn, level transmission signal of current-level GOA unit; Gn, scan signal of current-level GOA unit; VGL1, first-row shutdown signal; VGL2, second-row shutdown signal; GPU, output signal of trigger circuit; GPD, output signal of inverter circuit; GPDB, coupling signal. Modes for Carrying Out the Invention

[0060] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0061] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0062] Example 1

[0063] In a first aspect of an embodiment of the present application, a GOA driving circuit 100 is proposed, comprising a plurality of cascaded GOA units 110. The multi-stage GOA units 110 are respectively connected to corresponding row scan lines of an array substrate 200. The multiple row scan lines are connected to multiple rows of pixel units on the array substrate 200. The multi-stage GOA units 110 output row-on signals and row-off signals to the multiple rows of pixel units row by row, thereby realizing row scanning drive, and combined with the data signal input by the source driving circuit and the backlight source, drive the pixel units to display corresponding image information.

[0064] Among them, each level of GOA unit 110 is used to receive and correspond to the start signal STV, clock signal, row close signal, level transmission signal output by the previous level GOA unit 110, etc. to trigger the output of the level transmission signal Cn required by the next level GOA unit 110, for example, outputting the first level transmission signal Cn1, the second level transmission signal Cn2, and the third level transmission signal Cn3 in sequence, and at the same time, triggering the output of the scanning signal required by the pixel unit of this level, for example, the first scanning signal Gn1 output to the first row of pixel units, the second scanning signal Gn2 to the second row of pixel units, and the third scanning signal Gn3 to the third row of pixel units.

[0065] The clock signal may include a first clock signal CKL, a second clock signal CK, a third clock signal CKBL, and a fourth clock signal CKB, wherein the scan signal Gn and the level transfer signal Cn may be the same signal or different signals, and the specific type is not limited. Adjacent level transfer signal waveforms are the same and differ by a preset phase, and adjacent scan signal waveforms are the same and differ by a preset phase. The duration of the preset phase corresponds to the unit duration of a clock signal. For example, as shown in Figure 8, the first level transfer signal Cn1 and the second level transfer signal Cn2 differ by the unit duration of a clock signal, and the first scan signal Gn1 and the second scan signal Gn2 differ by the unit duration of a clock signal.

[0066] As shown in Figure 2, the GOA driving circuit 100 may further include an EOA circuit, which includes a plurality of EOA units, wherein the GOA unit 110 is driven by the fifth clock signal ECK1, the sixth clock signal ECK2 and the scanning signal corresponding to the GOA unit 110, and outputs a high level in the data input stage and a low level in other stages. The EOA unit outputs a low level in the data input stage and a high level in other stages, that is, in the data input stage, the EOA unit is in a cut-off state and does not output a signal. The EOA unit can be composed of an nT1C structure, such as a 4T1C, 8T1C and other structures.

[0067] In order to solve the problem of shoot-through current in the inverter circuit, in this embodiment, each GOA unit 110 includes a trigger circuit 10 , a pull-up circuit 30 , a pull-down circuit 40 and an inverter circuit 20 .

[0068] The input terminal of the trigger circuit 10 is used to input the start signal STV or the output signal of the previous-stage GOA unit 110. The control terminal of the trigger circuit 10 is used to input the first clock signal CKL. The trigger circuit 10 is triggered to turn on and output the start signal STV or the output signal by a high-level signal of the first clock signal CKL, and is triggered to turn off by a low-level signal of the first clock signal CKL.

[0069] The input end of the pull-up circuit 30 is used to input the second clock signal CK, and the output end of the pull-up circuit 30 constitutes the signal output end of the GOA unit 110. The control end of the pull-up circuit 30 is connected to the output end of the trigger circuit 10. The pull-up circuit 30 is triggered by the start signal STV or the output signal to turn on and output the second clock signal CK;

[0070] The inverter circuit 20 includes a first thin-film transistor T1 and a second thin-film transistor T2. A first terminal of the first thin-film transistor T1 is connected to a positive power supply terminal. A control terminal of the first thin-film transistor T1 and a second terminal of the second thin-film transistor T2 are used to input a first clock signal CKL. The second terminal of the first thin-film transistor T1 and the first terminal of the second thin-film transistor T2 constitute an output terminal of the inverter circuit 20. The control terminal of the second thin-film transistor T2 is connected to an output terminal of the trigger circuit 10. The first thin-film transistor T1 and the second thin-film transistor T2 are triggered to turn on by a high-level signal and to turn off by a low-level signal.

[0071] The input end of the pull-down circuit 40 is used to input the first row shutdown signal VGL1, the output end of the pull-down circuit 40 is connected to the output end of the pull-up circuit 30, and the control end of the pull-down circuit 40 is connected to the output end of the inverter circuit 20. The pull-down circuit 40 is triggered to turn on by a high-level signal.

[0072] In this embodiment, the output end of the trigger circuit 10 is set to the GPU node, the output signal of the trigger circuit 10 is GPU, the output end of the inverter circuit 20 is the GPD node, the output signal of the inverter circuit 20 is GPD, the high and low levels of the GPU node are used to control the on and off of the pull-up circuit 30, and the high and low levels of the GPD node are used to control the on and off of the pull-down circuit 40. The inverter circuit 20 is used to receive the signal of the GPU node and output the signal of the GPD node according to the corresponding level states of the first clock signal CKL, the positive power signal VDD of the positive power end, and the signal of the GPU node.

[0073] The first thin film transistor T1 and the second thin film transistor T2 are N-channel thin film transistors, and are triggered to be turned on when receiving a high level, and triggered to be turned off when receiving a low level.

[0074] Among them, when the start signal STV or the output signal of the previous level GOA unit 110 is written into the trigger waveform, the output signal of the previous level GOA unit 110 may be the level transfer signal Cn-1 or the scanning signal Gn-1 output to the pixel unit. At this time, the first clock signal CKL is a high-level signal, the trigger circuit 10 and the first thin-film transistor T1 are turned on, the start signal STV or the output signal of the previous level GOA unit 110 is output through the trigger circuit 10, the GPU node signal is high, the high-level signal is output to the pull-up circuit 30, the pull-up circuit 30 is triggered to turn on, and the second clock signal CK is output. The second clock signal CK is output as the output signal of the current level GOA unit 110 to the next level GOA unit 110 and the pixel unit of the corresponding row of the current level. At this time, the voltages at both ends of the second thin-film transistor T2 are both high, and the through current of the second thin-film transistor T2 is small.

[0075] Then, the first clock signal CKL switches to a low level, the trigger circuit 10 and the first thin film transistor T1 are turned off, and the pull-up circuit 30 is turned off. At this time, since the first thin film transistor T1 is turned off, the second thin film transistor T2 cannot form a through current, thereby improving the working reliability of the GOA unit 110, and further improving the display reliability of the display panel 1.

[0076] When the first clock signal CKL switches to a high level again, since the start signal STV or the output signal of the previous level GOA unit 110 is written as a low level signal, at this time, the pull-up circuit 30 is turned off, the first thin film transistor T1 is turned on, the second thin film transistor T2 is turned off, the GPD node signal is switched to the high level of the positive power supply signal VDD, the pull-down circuit 40 is turned on, and the GOA unit 110 continuously outputs the first row shutdown signal VGL1, wherein the first row shutdown signal VGL1 is a low level signal.

[0077] By adjusting the structure of the inverter circuit 20 , the through current of the inverter circuit is improved, thereby improving the operating reliability of the GOA unit 110 and the display reliability of the display panel 1 .

[0078] Furthermore, in order to restore the GOA unit 110 to its initial state before switching between different frame images, optionally, as shown in Figure 4, optionally, the GOA driving circuit 100 also includes a reset circuit 50, and the reset circuit 50 is connected to the output end of the trigger circuit 10, and is triggered by the reset control signal RST to reset each circuit of the GOA unit 110. Before the frame image is switched, the reset control signal RST resets the GOA units 110 of all levels, and the reset circuit 50 outputs a low-level signal to the pull-up circuit 30 and the inverter circuit 20. The pull-up circuit 30, the pull-down circuit 40 and the inverter circuit 20 are reset and switched to the off state, and after the reset is completed, the start signal STV or the output signal of the previous level GOA unit 110 is received.

[0079] The trigger circuit 10 , the pull-up circuit 30 , the pull-down circuit 40 and the reset circuit 50 may adopt corresponding thin film transistor structures, and the specific structures are not limited.

[0080] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the above-mentioned GOA driving circuit 100 includes a plurality of cascaded GOA units 110, each GOA unit 110 includes a trigger circuit 10, an inverter circuit 20, a pull-up circuit 30 and a pull-down circuit 40, the inverter circuit 20 includes a first thin film transistor T1 and a second thin film transistor T2, when the first clock signal CKL is at a high level, the trigger circuit 10 and the first thin film transistor T1 are turned on, when the trigger circuit 10 outputs a high level, the voltages at both ends of the second thin film transistor T2 are both at a high level, the through current of the second thin film transistor T2 is small, and when the first clock signal CKL is at a low level, the first thin film transistor T1 is turned off, and the second thin film transistor T2 also cannot form a through current, thereby improving the working reliability of the GOA unit 110, and thereby improving the display reliability of the display panel 1.

[0081] Example 2

[0082] As shown in Figure 1, when the reset circuit 50 and the trigger circuit 10 adopt a single thin-film transistor structure, the thin-film transistors of the GPU node may become leakage paths. That is, when the GPU node is at a high level and the other end of the trigger circuit 10 and the reset circuit 50 is at a low level, a voltage difference occurs, resulting in leakage, causing the GPU node voltage to drop, affecting the on-off output of the pull-up circuit 30.

[0083] To solve this problem, as shown in FIG5 , optionally, the trigger circuit 10 includes a third thin film transistor T3 and a fourth thin film transistor T4 ;

[0084] A first end of the third thin film transistor T3 constitutes an input end of the trigger circuit 10, a second end of the third thin film transistor T3 is connected to a first end of the fourth thin film transistor T4, a second end of the fourth thin film transistor T4 constitutes an output end of the trigger circuit 10, and a control end of the third thin film transistor T3 and a control end of the fourth thin film transistor T4 are connected together to constitute a control end of the trigger circuit 10.

[0085] The reset circuit 50 includes a fifth thin film transistor T5 and a sixth thin film transistor T6;

[0086] A first end of the fifth thin film transistor T5 is used to input the second row shutdown signal VGL2, a second end of the fifth thin film transistor T5 and a first end of the sixth thin film transistor T6 are connected in common, a second end of the sixth thin film transistor T6 constitutes an output end of the reset circuit 50, and a control end of the fifth thin film transistor T5 and a control end of the sixth thin film transistor T6 are connected in common and input a reset control signal RST.

[0087] The pull-up circuit 30 includes a tenth thin film transistor T10, wherein the first terminal, the second terminal and the control terminal of the tenth thin film transistor T10 respectively constitute the input terminal, the output terminal and the control terminal of the pull-up circuit 30;

[0088] The pull-down circuit 40 includes an eleventh thin film transistor T11 . The first terminal, the second terminal and the control terminal of the eleventh thin film transistor T11 respectively constitute the input terminal, the output terminal and the control terminal of the pull-down circuit 40 .

[0089] In this embodiment, the trigger circuit 10 and the reset circuit 50 are both composed of two thin film transistors connected in series. Before the frame image is switched, the reset control signal RST is switched to a high level, the fifth thin film transistor T5 and the sixth thin film transistor T6 of the reset circuit 50 are turned on, and the second row shutdown signal VGL2 is output to the GPU node. The second row shutdown signal VGL2 is a low level signal, and the low level signal is output to the pull-up circuit 30 and the inverter circuit 20. The pull-up circuit 30, the pull-down circuit 40 and the inverter circuit 20 are reset and switched to the off state. After the reset is completed, the start signal STV or the output signal of the previous level GOA unit 110 is received.

[0090] Then, when the start signal STV or the output signal of the previous level GOA unit 110 is written into the trigger waveform, the output signal of the previous level GOA unit 110 may be the stage transfer signal Cn-1 or the scanning signal Gn-1 output to the pixel unit. At this time, the first clock signal CKL is a high-level signal, the third thin-film transistor T3 and the fourth thin-film transistor T4 of the trigger circuit 10 and the first thin-film transistor T1 of the inverter circuit 20 are turned on, the start signal STV or the output signal of the previous level GOA unit 110 is output through the trigger circuit 10, the GPU node is high, and the high-level signal is output to the tenth thin-film transistor T10 of the pull-up circuit 30. The tenth thin-film transistor T10 is triggered to turn on and outputs the second clock signal CK. The second clock signal CK is output as the output signal of the current level GOA unit 110 to the next level GOA unit 110 and the pixel unit of the corresponding row of the current level. At this time, the voltages at both ends of the second thin-film transistor T2 are both high, and the through current of the second thin-film transistor T2 is small.

[0091] Then, the first clock signal CKL switches to a low level, the trigger circuit 10 and the first thin film transistor T1 are turned off, and the tenth thin film transistor T10 is turned off. At this time, since the first thin film transistor T1 is turned off, the second thin film transistor T2 cannot form a through current, thereby improving the working reliability of the GOA unit 110, and thereby improving the display reliability of the display panel 1.

[0092] When the first clock signal CKL switches to a high level again, since the start signal STV or the output signal of the previous level GOA unit 110 is written to a low level signal, at this time, the tenth thin film transistor T10 is turned off, the first thin film transistor T1 is turned on, the second thin film transistor T2 is turned off, the GPD node signal is switched to a high level of the positive power supply signal VDD, the eleventh thin film transistor T11 of the pull-down circuit 40 is turned on, and the GOA unit 110 continues to output the first row shutdown signal VGL1.

[0093] Among them, the leakage path of the GPU node adopts a dual thin film transistor series structure, that is, the trigger circuit 10 and the reset circuit 50 both adopt a dual thin film transistor structure, which reduces the leakage of the GPU node and further ensures the working reliability of the GOA unit 110 and the display reliability of the display panel 1.

[0094] Example 3

[0095] As shown in Figure 1, when the output signal of the pull-up circuit 30 is used as the trigger signal of the next-stage GOA unit 110, when an abnormality occurs in the pixel unit of the array substrate 200, there is a possibility that the normal operation of the GOA unit 110 is affected, resulting in abnormal operation of the subsequent-stage GOA unit 110 and failure of the cascade drive.

[0096] To solve this problem, as shown in FIG6 , optionally, the GOA driving circuit 100 further includes:

[0097] The stage transmission circuit 60 has an input terminal for inputting a third clock signal CKBL that is in phase opposite to the first clock signal CKL. The output terminal of the stage transmission circuit 60 is connected to the input terminal of the trigger circuit 10 of the next-stage GOA unit 110. The stage transmission circuit 60 is triggered to turn on and output the third clock signal CKBL by the start signal STV or the output signal.

[0098] The bootstrap capacitor C1 is connected in parallel between the output terminal and the control terminal of the stage transmission circuit 60 .

[0099] In this embodiment, before the frame image is switched, the reset control signal RST is switched to a high level, the fifth thin film transistor T5 and the sixth thin film transistor T6 of the reset circuit 50 are turned on, and the second row shutdown signal VGL2 is output to the GPU node, and the low level signal is output to the pull-up circuit 30 and the inverter circuit 20. The pull-up circuit 30, the pull-down circuit 40 and the inverter circuit 20 are reset and switched to the off state, and after the reset is completed, the start signal STV or the output signal of the previous level GOA unit 110 is received.

[0100] Then, when the start signal STV or the output signal of the previous level GOA unit 110 is written into the trigger waveform, the output signal of the previous level GOA unit 110 may be the level transfer signal Cn-1 of the previous level. At this time, the first clock signal CKL is a high-level signal, the third thin-film transistor T3 and the fourth thin-film transistor T4 of the trigger circuit 10 and the first thin-film transistor T1 of the inverter circuit 20 are turned on, the start signal STV or the output signal of the previous level GOA unit 110 is output through the trigger circuit 10, the GPU node signal is high, and the high-level signal is output to the tenth thin-film transistor T10 of the pull-up circuit 30 and the level transfer circuit 60. The tenth thin-film transistor T10 and the level transfer circuit 60 are triggered to turn on, and the tenth thin-film transistor T10 outputs the second clock signal CK. The second clock signal CK is output as the output signal of the current level GOA unit 110 to the pixel unit of the corresponding row of the current level. At this time, the voltages at both ends of the second thin-film transistor T2 are both high, and the through current of the second thin-film transistor T2 is small.

[0101] Then, the first clock signal CKL switches to a low level, the trigger circuit 10 and the first thin film transistor T1 are turned off. Due to the presence of the bootstrap capacitor C1, the high level of the GPU node is stored in the bootstrap capacitor C1, and the GPU node maintains a high level. When the third clock signal CKBL switches to a high level, the potential of the GPU node is pulled up again through the coupling of the level transmission circuit 60. At this time, the level transmission circuit 60 and the pull-up circuit 30 are fully opened, and the level transmission circuit 60 outputs the level transmission signal Cn of this level to the trigger circuit 10 of the next level GOA unit 110, and the pull-up circuit 30 outputs the output signal Gn of the GOA unit 110 of this level to the pixel unit of the corresponding row. Similarly, since the first thin film transistor T1 is turned off, the second thin film transistor T2 cannot form a through current, which improves the working reliability of the GOA unit 110, and thereby improves the display reliability of the display panel 1.

[0102] When the first clock signal CKL switches to a high level again, since the start signal STV or the stage transfer signal Cn-1 of the previous level GOA unit 110 is written with a low level signal, at this time, the tenth thin film transistor T10 is turned off, the first thin film transistor T1 is turned on, the second thin film transistor T2 is turned off, the GPD node signal is switched to the high level of the positive power supply signal VDD, the eleventh thin film transistor T11 of the pull-down circuit 40 is turned on, and the GOA unit 110 continues to output the first row shutdown signal VGL1.

[0103] By using the stage transmission circuit 60 and the pull-up circuit 30 to separate the signals output by the GOA unit 110 to the next stage GOA unit 110 and the signals output to the pixel unit, the influence of the pixel unit on the signal output of the GOA unit 110 is reduced, and the working reliability of the GOA unit 110 is improved.

[0104] The level transmission circuit 60 may adopt a corresponding thin film transistor structure, as shown in FIG7 . Optionally, the level transmission circuit 60 includes a seventh thin film transistor T7 , an eighth thin film transistor T8 , and a ninth thin film transistor T9 .

[0105] The first end of the seventh thin film transistor T7 and the first end of the ninth thin film transistor T9 are connected together to form the input end of the stage transmission circuit 60. The second end of the seventh thin film transistor T7, the first end of the eighth thin film transistor T8, the control end of the ninth thin film transistor T9 and the first end of the bootstrap capacitor C1 are connected together to form the output end of the stage transmission circuit 60. The control end of the seventh thin film transistor T7, the second end of the bootstrap capacitor C1 are connected to the output end of the trigger circuit 10, the control end of the eighth thin film transistor T8 is connected to the output end of the inverter circuit 20, and the second end of the eighth thin film transistor T8 is used to input the first row shutdown signal VGL1.

[0106] In this embodiment, as shown in Figure 8, when the start signal STV or the stage transfer signal Cn-1 of the previous stage GOA unit 110 is written into the trigger waveform, at this time, the first clock signal CKL is a high-level signal, the third thin film transistor T3 and the fourth thin film transistor T4 of the trigger circuit 10 and the first thin film transistor T1 of the inverter circuit 20 are turned on, the start signal STV or the stage transfer signal Cn-1 of the previous stage GOA unit 110 is output through the trigger circuit 10, the GPU node signal is high, and the high-level signal is output to the tenth thin film transistor T10 of the pull-up circuit 30 and the seventh thin film transistor T7 and the ninth thin film transistor T9 of the stage transfer circuit 60. The tenth thin film transistor T10, the seventh thin film transistor T7 and the ninth thin film transistor T9 are triggered to be turned on, and the tenth thin film transistor T10 outputs the second clock signal CK, which is output as the output signal Gn of the current stage GOA unit 110 to the pixel unit of the corresponding row of the current stage. At this time, the voltages at both ends of the second thin film transistor T2 are both high, and the through current of the second thin film transistor T2 is small.

[0107] Then, the first clock signal CKL switches to a low level, the trigger circuit 10 and the first thin film transistor T1 are turned off, and due to the existence of the bootstrap capacitor C1, the high level of the GPU node is stored in the bootstrap capacitor C1, and the GPU node maintains a high level. When the third clock signal CKBL switches to a high level, the potential of the GPU node is pulled up again through the coupling of the seventh thin film transistor T7. At this time, the seventh thin film transistor T7 and the tenth thin film transistor T10 are fully turned on, and the stage transmission circuit 60 outputs the stage transmission signal Cn of this stage to the trigger circuit 10 of the next stage GOA unit 110, and the pull-up circuit 30 outputs the output signal Gn of the GOA unit 110 of this stage to the pixel unit of the corresponding row. Since the ninth thin-film transistor T9 inputs a high-level signal, the high-level signal is output to the connection node of the third thin-film transistor T3 and the fourth thin-film transistor T4 through the ninth thin-film transistor T9, and the high-level signal is output to the connection node of the fifth thin-film transistor T5 and the sixth thin-film transistor T6 through the ninth thin-film transistor T9. Therefore, when the GPU node is at a high level, the connection node of the third thin-film transistor T3 and the fourth thin-film transistor T4 is at a high level, and the connection node of the fifth thin-film transistor T5 and the sixth thin-film transistor T6 is at a high level, thereby reducing the source-drain potential difference between the fourth thin-film transistor T4 and the fifth thin-film transistor T5, further reducing leakage, and stabilizing the high-level state of the GPU node.

[0108] Likewise, since the first thin film transistor T1 is turned off, the second thin film transistor T2 cannot generate a through current, thereby improving the operating reliability of the GOA unit 110 and further improving the display reliability of the display panel 1 .

[0109] When the first clock signal CKL switches to a high level again, since the start signal STV or the stage transmission signal Cn-1 of the previous level GOA unit 110 is written with a low level signal, at this time, the tenth thin film transistor T10 is turned off, the first thin film transistor T1 is turned on, the second thin film transistor T2 is turned off, the GPD node signal is switched to the high level of the positive power supply signal VDD, the eleventh thin film transistor T11 of the pull-down circuit 40 and the eighth thin film transistor T8 of the stage transmission circuit 60 are turned on, the pull-down circuit 40 continuously outputs the first row shutdown signal VGL1 to the pixel unit of this row, and the stage transmission circuit 60 continuously outputs the first row shutdown signal VGL1 to the trigger circuit 10 of the next level GOA unit 110.

[0110] Example 4

[0111] As shown in FIG9 , during operation, the time during which the GPD node is at a low potential is only 1 / the number of pixel rows in the display time of one frame of picture. Therefore, the gates of the thin film transistors of the pull-down circuit 40 and / or the stage transfer circuit 60 are operated under high voltage for a long time. As shown in FIG7 , the eighth thin film transistor T8 and the eleventh thin film transistor T11 are easily changed in characteristics under long-term high-voltage drive. As shown in FIG10 , the threshold turn-on voltage Vth drifts, and the GOA unit 110 has poor stability.

[0112] In order to solve the problem that the thin film transistors of the pull-down circuit 40 and / or the stage transfer circuit 60 are in a high voltage state for a long time, causing the characteristics to change, optionally, as shown in FIG11 , the pull-down circuit 40 further includes a twelfth thin film transistor T12, a thirteenth thin film transistor T13 and a coupling capacitor C2;

[0113] A first end of the coupling capacitor C2 is used to input the third clock signal CKBL. A second end of the coupling capacitor C2, the control end of the twelfth thin film transistor T12, and the first end of the thirteenth thin film transistor T13 are connected in common. The first and second ends of the twelfth thin film transistor T12 are connected in parallel to the first and second ends of the eleventh thin film transistor T11. The control end of the thirteenth thin film transistor T13 is connected to the output end of the stage transfer circuit 60. The second end of the thirteenth thin film transistor T13 is used to input the second row shut-off signal VGL2.

[0114] The stage transfer circuit 60 further includes a fourteenth thin film transistor T14 and a fifteenth thin film transistor T15;

[0115] The control end of the fourteenth thin film transistor T14 is connected to the second end of the coupling capacitor C2, the first end and the second end of the fourteenth thin film transistor T14 are connected in parallel to the first end and the second end of the eighth thin film transistor T8, the first end of the fifteenth thin film transistor T15 is connected to the output end of the inverter circuit 20, the second end of the fifteenth thin film transistor T15 is used to input the second row shut-off signal VGL2, and the control end of the fifteenth thin film transistor T15 is used to input the third clock signal CKBL.

[0116] 11 and 12 , GPDB is set as a coupling signal, which is a control signal output to the fourteenth thin film transistor T14 and the twelfth thin film transistor T12. In the first time period, RST controls the second row shutdown signal VGL2 input to reset the GOA units 110 of all levels.

[0117] In the second time period, the start signal STV or the level transfer signal Cn-1 output by the previous level GOA unit 110 is written into the trigger waveform. At this time, the first clock signal CKL is at a high level, the third thin film transistor T3 and the fourth thin film transistor T4 are turned on, and the start signal STV or the level transfer signal Cn-1 output by the previous level GOA unit 110 is written into the GPU node. At this time, the GPU controls the second thin film transistor T2 to write the first clock signal CKL into the GPD node, and sets the GPD node to a high level. Since the third clock signal CKBL is set to a low level, the GPDB is set to a low level through the coupling capacitor C2, the twelfth thin film transistor T12 and the fourteenth thin film transistor T14 are turned off, and since the third clock signal CKBL is a low level signal at this time, the fifteenth thin film transistor T15 is turned off, the eighth thin film transistor T8 is turned on, and outputs a low level signal.

[0118] In the third time period, the first clock signal CKL switches to a low level, and the high level of the GPU node is stored in the bootstrap capacitor C1 and maintained until the third clock signal CKBL switches to a high potential. The potential of the GPU node is pulled high again through coupling through the seventh thin-film transistor T7. At this time, the seventh thin-film transistor T7 and the tenth thin-film transistor T10 are fully turned on, and the GOA unit 110 outputs Cn and Gn, which are the high potentials of the third clock signal CKBL and the second clock signal CK, respectively.

[0119] At this time, the third clock signal CKBL controls the fifteenth thin film transistor T15 to be turned on, the GPD node writes the second row shutdown signal VGL2, and the GPDB controls the thirteenth thin film transistor T13 to be turned on due to Cn, and writes the first row shutdown signal VGL1 to ensure that the pull-down circuit 40 has no output.

[0120] In the fourth time period, when the first clock signal CKL is switched to a high level again, the start signal STV or the level transfer signal Cn-1 output by the previous level GOA unit 110 writes a low potential to the GPU, the seventh thin film transistor T7 and the tenth thin film transistor T10 are turned off, the second thin film transistor T2 is turned off, the first thin film transistor T1 is turned on, the positive power supply signal VDD is written to the GPD node, and the eighth thin film transistor T8 and the eleventh thin film transistor T11 are controlled to be turned on, and Cn and Gn output the first row shutdown signal VGL1.

[0121] At this time, the third clock signal CKBL is at a low level, and the GPDB voltage is set to a low level through coupling by the coupling capacitor C2 , and the fourteenth thin film transistor T14 and the twelfth thin film transistor T12 are turned off.

[0122] In the fifth time period, when the first clock signal CKL switches to a low level, the third clock signal CKBL controls the fifteenth thin film transistor T15 to turn on, the low potential of the second row shutdown signal VGL2 is written to the GPD node, the eighth thin film transistor T8 and the eleventh thin film transistor T11 are turned off, and the third clock signal CKBL sets the GPDB voltage to a high level through the coupling capacitor C2, the fourteenth thin film transistor T14 and the twelfth thin film transistor T12 are turned on, and Cn and Gn output the first row shutdown signal VGL1.

[0123] Before the next frame initialization reset, the fourth time period and the fifth time period will be repeated cyclically.

[0124] That is, during the time when the stage transfer circuit 60 and the pull-down circuit 40 continuously output low-level signals, the eighth thin-film transistor T8 and the fourteenth thin-film transistor T14 are cross-connected and disconnected, and the eleventh thin-film transistor T11 and the twelfth thin-film transistor T12 are cross-connected and disconnected, and the voltages at their control terminals are switched to changing pulse signals rather than continuous high-level signals, thereby improving the characteristic drift problem of the thin-film transistors under long-term bias and improving the stability of the GOA unit 110 during long-term operation.

[0125] As shown in Figures 13 to 15, the thin film transistor includes a stacked substrate 11, a bottom gate layer 18, a buffer layer 12, an active layer 13, a gate insulating layer 14, a top gate layer 15, an interlayer insulating layer 16, a source 171 and a drain 172. As shown in Figure 13, when the top gate layer 15 is connected to a high level and the bottom gate layer 18 is connected to a low level, the top channel of the channel region of the active layer 13 is turned on, and as shown in Figure 14, when the bottom gate layer 18 is connected to a high level and the top gate layer 15 is connected to a low level, the bottom channel of the channel region of the active layer 13 is turned on, and as shown in Figure 15, when the bottom gate layer 18 and the top gate layer 15 are connected to a low level, no channel is closed.

[0126] By switching the top gate on and bottom gate on states, the thin film transistor is prevented from being in the top gate on state for a long time, and the carriers are captured by the interface defects of the active layer 13 or the gate insulating layer 14 and the internal defects of the gate insulating layer 14, causing the device drift.

[0127] At the same time, when the bottom gate is turned on, the negative voltage of the top gate will stimulate the carriers captured in the defects, thereby resetting the threshold voltage.

[0128] Example 5

[0129] The present application also provides a display panel 1, as shown in FIG16 , which includes an array substrate 200 and a GOA driving circuit 100. The specific structure of the GOA driving circuit 100 is similar to the above-described embodiments. Since the present display panel 1 employs all the technical solutions of all the above-described embodiments, it at least has all the beneficial effects brought about by the technical solutions of the above-described embodiments, which will not be described in detail here. The GOA driving circuit 100 is disposed on one or both sides of the array substrate 200.

[0130] In this embodiment, the array substrate 200 includes a display area and a non-display area. The non-display area is provided with a binding pin area and a GOA driving circuit 100. The GOA driving circuit 100 is arranged on one side or both sides of the non-display area of ​​the array substrate 200, and is used for row-by-row scanning of the display area, and cooperates with the data signal to realize row-by-row scanning driving of the display area.

[0131] Example 6

[0132] This application also proposes a display device, as shown in FIG17 , which includes a backlight module 3, a driver circuit board 2, and a display panel 1. The specific structure of the display panel 1 is similar to the above-mentioned embodiments. Since this display device adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above-mentioned embodiments, which will not be described in detail here. Among them, the backlight module 3 and the display panel 1 are arranged relative to each other, and the driver circuit board 2 is electrically connected to the display panel 1.

[0133] In this embodiment, the backlight module 3 is used to provide backlight, the driving circuit board 2 is connected to the display panel 1 through the chip-on-chip film, and inputs an external control signal to the driving chip in the chip-on-chip film. The driving chip converts the external control signal into a data signal and a control signal required for driving the GOA driving circuit 100. The GOA driving circuit 100 converts and outputs a shift pulse signal composed of multiple sub-row scan signals, and cooperates with the data signal to realize row-by-row scanning drive of the display area.

[0134] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A GOA driving circuit, wherein: It includes multiple cascaded GOA units, each of which includes: A trigger circuit, wherein the input end of the trigger circuit is used to input a start signal or an output signal of a previous-level GOA unit, the control end of the trigger circuit is used to input a first clock signal, the trigger circuit is triggered to turn on and output the start signal or the output signal by a high-level signal of the first clock signal, and is triggered to turn off by a low-level signal of the first clock signal; A pull-up circuit, wherein the input end of the pull-up circuit is used to input a second clock signal, the output end of the pull-up circuit constitutes the signal output end of the GOA unit, the control end of the pull-up circuit is connected to the output end of the trigger circuit, and the pull-up circuit is triggered by the start signal or the output signal to conduct and output the second clock signal; An inverter circuit, comprising a first thin film transistor and a second thin film transistor, wherein a first end of the first thin film transistor is connected to a positive power supply end, a control end of the first thin film transistor and a second end of the second thin film transistor are used to input the first clock signal, the second end of the first thin film transistor and the first end of the second thin film transistor constitute an output end of the inverter circuit, the control end of the second thin film transistor is connected to an output end of the trigger circuit, and the first thin film transistor and the second thin film transistor are turned on by a high level signal and turned off by a low level signal; A pull-down circuit, wherein the input end of the pull-down circuit is used to input a first row closing signal, the output end of the pull-down circuit is connected in common with the output end of the pull-up circuit, the control end of the pull-down circuit is connected to the output end of the inverter circuit, and the pull-down circuit is triggered to conduct when turned on by a high-level signal.

2. The GOA driving circuit according to claim 1, wherein: The multiple levels of GOA units are respectively connected to corresponding rows of scan lines of the array substrate, and the multiple rows of scan lines are connected to multiple rows of pixel units on the array substrate. The multiple levels of GOA units output row-on signals and row-off signals to the multiple rows of pixel units row by row.

3. The GOA driving circuit according to claim 1, wherein: The first thin film transistor and the second thin film transistor are N-channel thin film transistors.

4. The GOA driving circuit according to claim 1, wherein: The trigger circuit includes a third thin film transistor and a fourth thin film transistor; The first end of the third thin film transistor constitutes the input end of the trigger circuit, the second end of the third thin film transistor is connected to the first end of the fourth thin film transistor, the second end of the fourth thin film transistor constitutes the output end of the trigger circuit, and the control end of the third thin film transistor and the control end of the fourth thin film transistor are connected together to constitute the control end of the trigger circuit.

5. The GOA driving circuit according to claim 4, wherein: The GOA driving circuit also includes: A reset circuit, connected to the output end of the trigger circuit, and triggered by a reset control signal to reset each circuit of the GOA unit; The reset circuit includes a fifth thin film transistor and a sixth thin film transistor; The first end of the fifth thin film transistor is used to input a second row shutdown signal, the second end of the fifth thin film transistor and the first end of the sixth thin film transistor are connected in common, the second end of the sixth thin film transistor constitutes the output end of the reset circuit, and the control end of the fifth thin film transistor and the control end of the sixth thin film transistor are connected in common and input a reset control signal.

6. The GOA driving circuit as claimed in claim 5, wherein: The first row shut-down signal and the second row shut-down signal are low level signals.

7. The GOA driving circuit according to claim 5, wherein: The GOA driving circuit also includes: A level transmission circuit, wherein the input end of the level transmission circuit is used to input a third clock signal that is inverted with the first clock signal, the output end of the level transmission circuit is connected to the input end of the trigger circuit of the GOA unit of the next level, the control end of the level transmission circuit is connected to the output end of the trigger circuit, and the level transmission circuit is triggered by the high level signal output by the trigger circuit to conduct and output the third clock signal; A bootstrap capacitor is connected in parallel between the output terminal and the control terminal of the stage transmission circuit.

8. The GOA driving circuit according to claim 7, wherein: The stage transfer circuit includes a seventh thin film transistor, an eighth thin film transistor and a ninth thin film transistor; The first end of the seventh thin film transistor and the first end of the ninth thin film transistor are connected together to form the input end of the stage transmission circuit, the second end of the seventh thin film transistor, the first end of the eighth thin film transistor, the control end of the ninth thin film transistor and the first end of the bootstrap capacitor are connected together to form the output end of the stage transmission circuit, the control end of the seventh thin film transistor, the second end of the bootstrap capacitor and the output end of the trigger circuit are connected, the control end of the eighth thin film transistor is connected to the output end of the inverter circuit, the second end of the eighth thin film transistor is used to input the first row shutdown signal, the second end of the ninth thin film transistor, the second end of the third thin film transistor and the first end of the fourth thin film transistor are connected.

9. The GOA driving circuit according to claim 8, wherein: The pull-up circuit comprises a tenth thin film transistor, wherein the first end, the second end and the control end of the tenth thin film transistor respectively constitute the input end, the output end and the control end of the pull-up circuit; The pull-down circuit comprises an eleventh thin film transistor, and the first end, the second end and the control end of the eleventh thin film transistor respectively constitute the input end, the output end and the control end of the pull-down circuit.

10. The GOA driving circuit according to claim 9, wherein: The pull-down circuit further includes a twelfth thin film transistor, a thirteenth thin film transistor and a coupling capacitor; The first end of the coupling capacitor is used to input the third clock signal, the second end of the coupling capacitor, the control end of the twelfth thin film transistor and the first end of the thirteenth thin film transistor are connected in common, the first end and the second end of the twelfth thin film transistor are respectively connected in parallel to the first end and the second end of the eleventh thin film transistor, the control end of the thirteenth thin film transistor is connected to the output end of the stage transfer circuit, and the second end of the thirteenth thin film transistor is used to input the second row closing signal.

11. The GOA driving circuit according to claim 10, wherein: The stage transmission circuit further includes a fourteenth thin film transistor and a fifteenth thin film transistor; The control end of the fourteenth thin film transistor is connected to the second end of the coupling capacitor, the first end and the second end of the fourteenth thin film transistor are respectively connected in parallel to the first end and the second end of the eighth thin film transistor, the first end of the fifteenth thin film transistor is connected to the output end of the inverter circuit, the second end of the fifteenth thin film transistor is used to input the second row shutdown signal, and the control end of the fifteenth thin film transistor is used to input the third clock signal.

12. The GOA driving circuit according to claim 11, wherein: During the time when the stage transfer circuit and the pull-down circuit continue to output low-level signals, the eighth thin film transistor and the fourteenth thin film transistor are cross-connected and the eleventh thin film transistor and the twelfth thin film transistor are cross-connected and cut off.

13. A display panel, wherein: It comprises an array substrate and the GOA driving circuit as claimed in claim 1, wherein the GOA driving circuit is arranged on one side or both sides of the array substrate.

14. A display device, wherein: It comprises a backlight module, a driving circuit board and the display panel as claimed in claim 13, wherein the backlight module and the display panel are arranged opposite to each other, and the driving circuit board is electrically connected to the display panel.

15. The display device according to claim 14, wherein: The backlight module is used to provide backlight, the driving circuit board is connected to the display panel through the chip-on-chip film, and inputs an external control signal to the driving chip in the chip-on-chip film. The driving chip converts the external control signal into a data signal and a control signal required for driving the GOA driving circuit.

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