Array substrate and manufacturing method therefor, and display device

Abstract

Provided is an array substrate, comprising: a base substrate; a first passivation layer provided on the base substrate; a first conductive layer provided on the side of the first passivation layer distant from the base substrate; and a second passivation layer provided on the side of the first conductive layer distant from the base substrate. The first conductive layer has a stack structure, and comprises a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer; the first sub-conductive layer is located on the side of the first passivation layer distant from the base substrate, the second sub-conductive layer is located on the side of the first sub-conductive layer distant from the base substrate, and the third sub-conductive layer is located on the side of the second sub-conductive layer distant from the base substrate; the first sub-conductive layer and the third sub-conductive layer are made of the same material, and the second sub-conductive layer and the third sub-conductive layer are made of different materials; the thickness of the third sub-conductive layer is less than that of the first sub-conductive layer, and the thickness of the second sub-conductive layer is greater than that of each of the first sub-conductive layer and the third conductive layer.

Description

Array substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display device, and a method for manufacturing the array substrate. Background Art

[0002] Light emitting diode (LED) technology has been developed for nearly three decades, and its application range continues to expand. For example, it can be used in the display field as a backlight source for display devices or in LED display screens. With the development of technology, sub-millimeter light emitting diodes (Mini LED) and micro light emitting diodes (Micro LED) have gradually become a research hotspot in the field of display technology. For example, Mini LED or Micro LED can be used in the light-emitting modules of liquid crystal display devices as the light-emitting elements of the light-emitting modules.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, an array substrate is provided, comprising: a base substrate; a first passivation layer disposed on the base substrate; a first conductive layer disposed on a side of the first passivation layer away from the base substrate; and a second passivation layer disposed on a side of the first conductive layer away from the base substrate, wherein the array substrate comprises a plurality of array units, the plurality of array units being distributed in an array on the base substrate, at least one of the array units comprising a light-emitting diode, the light-emitting diode comprising a first electrode and a second electrode; the array substrate comprises a plurality of pad pairs, the plurality of pad pairs being located in the first conductive layer, at least one of the pad pairs comprising a first pad and a second pad, the first pad being used to be electrically connected to the first electrode, and the second pad being electrically connected to the first electrode. Used to be electrically connected to the second electrode; the first conductive layer has a stacked structure, the stacked structure of the first conductive layer includes a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer is located on the side of the first passivation layer away from the substrate, the second sub-conductive layer is located on the side of the first sub-conductive layer away from the substrate, and the third sub-conductive layer is located on the side of the second sub-conductive layer away from the substrate; the first sub-conductive layer and the third sub-conductive layer are made of the same material, and the second sub-conductive layer and the third sub-conductive layer are made of different materials; and the thickness of the third sub-conductive layer is less than the thickness of the first sub-conductive layer, and the thickness of the second sub-conductive layer is greater than the thickness of each of the first sub-conductive layer and the third conductive layer.

[0006] For example, in some exemplary embodiments, the array substrate may be an array substrate of a display panel, and accordingly, the array unit may be a pixel unit of the display panel; or, the array substrate may be a substrate of a backlight module, and accordingly, the array unit may be a light-emitting unit of the backlight module.

[0007] According to some exemplary embodiments, the thickness of the third sub-conductive layer is less than or equal to half the thickness of the first sub-conductive layer.

[0008] According to some exemplary embodiments, the thickness of the third sub-conductive layer is greater than 0 angstrom and less than or equal to 150 angstroms.

[0009] According to some exemplary embodiments, the thickness of the second sub-conductive layer is greater than or equal to 1.8 micrometers.

[0010] According to some exemplary embodiments, a ratio of a thickness of the second passivation layer to a thickness of the third sub-conductive layer is greater than 26.

[0011] According to some exemplary embodiments, a thickness of the second passivation layer is greater than a thickness of the first passivation layer.

[0012] According to some exemplary embodiments, the thickness of the second passivation layer is greater than or equal to 4000 angstroms and less than or equal to 6000 angstroms.

[0013] According to some exemplary embodiments, the orthographic projection of the third sub-conductive layer on the base substrate falls within the orthographic projection of the second sub-conductive layer on the base substrate; and / or the orthographic projection of the second sub-conductive layer on the base substrate falls within the orthographic projection of the first sub-conductive layer on the base substrate.

[0014] According to some exemplary embodiments, the array substrate further includes a second conductive layer, which is located on a side of the first passivation layer close to the base substrate; and a thickness of the second conductive layer is smaller than a thickness of the first conductive layer.

[0015] According to some exemplary embodiments, the array substrate further includes a plurality of terminals, the plurality of terminals being located in the first conductive layer, the plurality of terminals being used to be electrically connected to the pins of the driving chip; and the array substrate further includes a plurality of conductive connection parts, the plurality of conductive connection parts being located in the first conductive layer, at least one of the conductive connection parts electrically connecting at least one of the terminals with at least one of the first pads.

[0016] According to some exemplary embodiments, the array substrate further includes a plurality of traces, which are located in the second conductive layer; the array substrate further includes: a via located in the first passivation layer; and a conductive portion located in the first conductive layer; and one end of the conductive portion is electrically connected to at least one of the second pads, and at least one of the traces is electrically connected to the conductive portion through the via.

[0017] According to some exemplary embodiments, the multiple terminals include a first terminal, which is used to be electrically connected to the ground signal pin of the driver chip; the multiple routings include a first routing, which is used to transmit the ground signal; and the vias include multiple first vias, the conductive part includes a first conductive part, the first routing is electrically connected to the first conductive part through the multiple first vias, the other end of the first conductive part is electrically connected to the first terminal, and the orthographic projections of the multiple first vias on the substrate are arranged side by side along a first direction within the orthographic projection of the first conductive part on the substrate.

[0018] According to some exemplary embodiments, the array substrate also includes a grounding line, which is located in the first conductive layer, the grounding line extends along a first direction, the first routing line extends along a second direction, and the first direction and the second direction intersect; the via includes a plurality of second vias, the first routing line is electrically connected to the grounding line through the plurality of second vias, and the orthographic projections of the plurality of second vias on the base substrate are arranged side by side along the first direction within the orthographic projection of the grounding line on the base substrate.

[0019] According to some exemplary embodiments, the array unit may be a pixel unit, at least one of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel includes a first light-emitting diode, the second sub-pixel includes a second light-emitting diode, and the third sub-pixel includes a third light-emitting diode; the multiple terminals also include a second terminal, a third terminal and a fourth terminal, the multiple pad pairs include a first pad pair, a second pad pair and a third pad pair, the first pad and the second pad of the first pad pair are used to be electrically connected to the first electrode and the second electrode of the first light-emitting diode, respectively, the first pad and the second pad of the second pad pair are used to be electrically connected to the first electrode and the second electrode of the second light-emitting diode, respectively, and the first pad and the second pad of the third pad pair are used to be electrically connected to the first electrode and the second electrode of the third light-emitting diode, respectively; and the conductive connecting portion includes a first conductive connecting portion, a second conductive connecting portion and a third conductive connecting portion, the second terminal is electrically connected to the first pad of the first pad pair through the first conductive connecting portion, the third terminal is electrically connected to the first pad of the second pad pair through the second conductive connecting portion, and the fourth terminal is electrically connected to the first pad of the third pad pair through the third conductive connecting portion.

[0020] According to some exemplary embodiments, the multiple routings further include a second routing and a third routing, the second routing being used to transmit a first voltage signal to the first light-emitting diode, and the third routing being used to transmit a second voltage signal to the second light-emitting diode and the third light-emitting diode; the vias include a third via and a plurality of fourth vias, the conductive portion includes a second conductive portion and a third conductive portion, the second routing is electrically connected to one end of the second conductive portion through the third via, the other end of the second conductive portion is electrically connected to the second pad of the first pad pair, the third routing is electrically connected to the third conductive portion through the plurality of fourth vias, the third conductive portion is electrically connected to the second pad of the second pad pair and the second pad of the third pad pair, and the orthographic projections of the plurality of fourth vias on the substrate are arranged side by side along the second direction within the orthographic projection of the third conductive portion on the substrate.

[0021] According to some exemplary embodiments, the array unit may be a pixel unit, at least one of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel includes a first light-emitting diode, the second sub-pixel includes a second light-emitting diode, and the third sub-pixel includes a third light-emitting diode; the multiple pad pairs include a first pad pair, a second pad pair and a third pad pair, the first pad and the second pad of the first pad pair are used to be electrically connected to the first electrode and the second electrode of the first light-emitting diode, respectively, the first pad and the second pad of the second pad pair are used to be electrically connected to the first electrode and the second electrode of the second light-emitting diode, respectively, and the first pad and the second pad of the third pad pair are used to be electrically connected to the first electrode and the second electrode of the third light-emitting diode, respectively; and the array substrate includes a first voltage signal line and a second voltage signal line located in the first conductive layer, the first pad of the first pad pair is electrically connected to the first voltage signal line, the first pad of the second pad pair and the first pad of the third pad pair are both electrically connected to the second voltage signal line, and the first pad pair, the second pad pair and the third pad pair are located between the first voltage signal line and the second voltage signal line in the first direction.

[0022] According to some exemplary embodiments, materials of the first sub-conductive layer and the third sub-conductive layer include MoNb, and material of the second sub-conductive layer includes Cu.

[0023] In another aspect, an array substrate is provided, comprising: a base substrate; a first passivation layer disposed on the base substrate; a first conductive layer disposed on a side of the first passivation layer away from the base substrate; and a second passivation layer disposed on a side of the first conductive layer away from the base substrate, wherein the array substrate comprises a plurality of array units, the plurality of array units being distributed in an array on the base substrate, at least one of the array units comprising a light-emitting diode, the light-emitting diode comprising a first electrode and a second electrode; the array substrate comprises a plurality of pad pairs, the plurality of pad pairs being located in the first conductive layer, at least one of the pad pairs comprising a first pad and a second pad, the first pad being configured to be electrically connected to the first electrode, and the second pad being configured to be electrically connected to the second electrode; the first conductive layer having a stacked structure, the stacked structure of the first conductive layer comprising a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer, the first sub-conductive layer being located on a side of the first passivation layer away from the base substrate, the second sub-conductive layer being located on a side of the first sub-conductive layer away from the base substrate, and the third sub-conductive layer being located on a side of the second sub-conductive layer away from the base substrate; and a ratio of a thickness of the second passivation layer to a thickness of the third sub-conductive layer being greater than 26.

[0024] In yet another aspect, a display device is provided, wherein the display device includes the array substrate as described above.

[0025] In another aspect, a method for preparing an array substrate is provided, the method comprising: providing a base substrate; forming a first passivation layer on the base substrate; forming a first conductive material layer on a side of the first passivation layer away from the base substrate; performing a patterning process on the first conductive material layer to form a plurality of pad pairs, wherein at least one of the pad pairs includes a first pad and a second pad, the first pad being used to electrically connect to a first electrode of a light-emitting diode, and the second pad being used to electrically connect to a second electrode of the light-emitting diode; and forming a second passivation layer on a side of the plurality of pad pairs away from the base substrate, wherein the second passivation layer formed on a side of the first passivation layer away from the base substrate The first conductive material layer includes: a first sub-conductive material layer formed on the side of the first passivation layer away from the base substrate; a second sub-conductive material layer formed on the side of the first sub-conductive layer away from the base substrate; and a third sub-conductive material layer formed on the side of the second sub-conductive layer away from the base substrate, wherein the first sub-conductive material layer and the third sub-conductive material layer are made of the same material, and the second sub-conductive material layer and the third sub-conductive material layer are made of different materials; and the thickness of the third sub-conductive material layer is less than the thickness of the first sub-conductive material layer, and the thickness of the second sub-conductive material layer is greater than the thickness of each of the first sub-conductive material layer and the third conductive material layer.

[0026] According to some exemplary embodiments, the patterning process performed on the first conductive material layer includes: coating a photoresist layer on the first conductive material layer; performing a pre-bake process on the photoresist layer; exposing the photoresist layer; and performing a post-bake process on the photoresist layer, wherein, in the post-bake process, the post-bake temperature is greater than 130° C. and the post-bake time is greater than 8 minutes.

[0027] According to some exemplary embodiments, forming the second passivation layer on a side of the plurality of pad pairs away from the base substrate includes: forming the second passivation layer on a side of the plurality of pad pairs away from the base substrate by a chemical vapor deposition process. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0029] FIG1 is a schematic diagram of a partial structure of a display panel according to some exemplary embodiments of the present disclosure;

[0030] FIG2 is a partial schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, showing an electrical connection relationship between a pad and a pixel unit;

[0031] 3 is a partial schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, showing the projection relationship between the first sub-conductive layer, the second sub-conductive layer, and the third sub-conductive layer in a space perpendicular to the substrate;

[0032] 4 is a partial schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, showing the positional relationship between the second conductive layer and the first passivation layer;

[0033] FIG5 is a schematic plan view of a display panel according to some embodiments of the present disclosure, showing an electrical connection structure of a driving chip, terminals, conductive connection portions, and pads;

[0034] FIG6 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection between the first conductive layer and the second conductive layer, and the electrical connection between the traces, the conductive portion, the terminal, and the driver chip. FIG6 also shows the electrical connection between the ground line and the first trace.

[0035] FIG7 is a schematic plan view of a display panel according to some embodiments of the present disclosure, showing the electrical connection relationship among pixels, terminals, pads, and conductive connection parts;

[0036] FIG8 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship among traces, conductive portions, pads, and light-emitting diodes;

[0037] FIG9 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship between the first voltage signal line and the second voltage signal line, the pad, and the light-emitting diode;

[0038] FIG10 is a schematic structural diagram of a display panel according to some other embodiments of the present disclosure, showing a thickness ratio of the second passivation layer to the third sub-conductive layer;

[0039] FIG11 is a schematic structural diagram of some other embodiments of the present disclosure, in which a backlight module is shown as a backlight source in a liquid crystal panel;

[0040] FIG12A shows a schematic structural diagram of a backlight module according to another embodiment of the present disclosure, and FIG12B shows a planar schematic diagram of a backlight module, wherein FIG12B shows an electrical connection relationship between a light-emitting unit and a pair of pads in a backlight module;

[0041] FIG13 shows a schematic structural diagram of a backlight module according to some other embodiments of the present disclosure, wherein the thickness relationship between the second conductive layer and the first conductive layer is shown;

[0042] 14A and 14B are respectively a display device according to an exemplary embodiment of the present disclosure;

[0043] FIG. 15 is a diagram illustrating a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure; and

[0044] FIG. 16 is a flowchart of a patterning process performed on a first conductive material layer according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0046] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0047] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent," or "on..." versus "directly on...", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0048] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0049] In this article, inorganic light-emitting diodes refer to light-emitting elements made of inorganic materials, where LED represents an inorganic light-emitting element that is different from OLED. Specifically, inorganic light-emitting elements can include sub-millimeter light-emitting diodes (Mini Light Emitting Diode, abbreviated as Mini LED in English) and micro light-emitting diodes (Micro LED in English). Among them, micro light-emitting diodes (i.e. Micro LEDs) refer to ultra-small light-emitting diodes with a grain size of less than 100 microns, and sub-millimeter light-emitting diodes (i.e. Mini LEDs) refer to small light-emitting diodes with a grain size between Micro LEDs and traditional LEDs. For example, the grain size of Mini LEDs can be between 50 and 400 microns.

[0050] In current LCD displays, brightness is controlled by deflecting the liquid crystals, which takes time, typically in the microsecond range. Rapidly moving images can easily cause image smearing. Smearing occurs whenever the speed of an object exceeds the display device's maximum response speed. Smearing is inherent in LCD systems and can be mitigated, but not eliminated, by overdriving. Newer display systems, such as Mini LED or Micro LED, overcome this phenomenon by directly utilizing light-emitting diodes to generate light. In these new Mini LED and Micro LED displays, the conductive medium in the circuit must possess excellent electrical conductivity and high ductility. In actual manufacturing processes, this often leads to poor protection of the conductive medium, which can corrode and ultimately cause display anomalies. Therefore, in display panel manufacturing, efforts are underway to improve the protection of the conductive medium to prevent corrosion and enhance the reliability of the display panel.

[0051] An embodiment of the present disclosure provides an array substrate, which includes: a base substrate; a first passivation layer arranged on the base substrate; a first conductive layer arranged on a side of the first passivation layer away from the base substrate; and a second passivation layer arranged on a side of the first conductive layer away from the base substrate, wherein the array substrate includes a plurality of array units, the plurality of array units are distributed in an array on the base substrate, at least one of the array units includes a light-emitting diode, and the light-emitting diode includes a first electrode and a second electrode; the array substrate includes a plurality of pad pairs, the plurality of pad pairs are located in the first conductive layer, at least one of the pad pairs includes a first pad and a second pad, the first pad is used to be electrically connected to the first electrode, and the second pad Used to electrically connect with the second electrode; the first conductive layer has a stacked structure, the stacked structure of the first conductive layer includes a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer is located on the side of the first passivation layer away from the substrate, the second sub-conductive layer is located on the side of the first sub-conductive layer away from the substrate, and the third sub-conductive layer is located on the side of the second sub-conductive layer away from the substrate; the first sub-conductive layer and the third sub-conductive layer are made of the same material, the second sub-conductive layer and the third sub-conductive layer are made of different materials; and the thickness of the third sub-conductive layer is less than the thickness of the first sub-conductive layer, and the thickness of the second sub-conductive layer is greater than the thickness of each of the first sub-conductive layer and the third conductive layer. In the embodiment of the present disclosure, the etching rate of the second sub-conductive layer and the third sub-conductive layer can be adjusted by optimizing the thickness relationship between the second sub-conductive layer and the third sub-conductive layer, avoiding the indentation phenomenon or the top protrusion phenomenon during etching, thereby improving the product yield.

[0052] It should be noted that in the embodiments of the present disclosure, the array substrate may be an array substrate of a display panel, and accordingly, the array unit may be a pixel unit of the display panel; alternatively, the array substrate may be a substrate of a backlight module, and accordingly, the array unit may be a light-emitting unit of the backlight module. In the following description, the array substrate according to the embodiments of the present disclosure is described in detail using the display panel and the backlight module as examples. It should be understood that such separate descriptions are only for the purpose of convenience of description. In the absence of conflict, the structures of the display panel and the backlight module can be combined and referenced with each other.

[0053] FIG. 1 is a schematic diagram of a partial structure of a display panel according to some exemplary embodiments of the present disclosure.

[0054] 1 , the display panel 100 may include a plurality of film layers disposed on a base substrate 1. For example, the plurality of film layers include: a first passivation layer 2 disposed on the base substrate 1, a first conductive layer 3 disposed on a side of the first passivation layer 2 away from the base substrate, and a second passivation layer 4 disposed on a side of the first conductive layer 3 away from the base substrate.

[0055] For example, the material of the base substrate 1 may include but is not limited to glass, quartz, plastic, silicon, polyimide, etc.

[0056] Referring to Figure 1 , in the disclosed embodiment, the first conductive layer 3 has a stacked structure, comprising a first sub-conductive layer 31 located on the side of the first passivation layer 2 away from the substrate, a second sub-conductive layer 32 located on the side of the first sub-conductive layer 31 away from the substrate, and a third sub-conductive layer located on the side of the second sub-conductive layer 32 away from the substrate. Conductive components for connecting to light-emitting diodes or driver chips can be located within the first conductive layer 3. For example, the second sub-conductive layer 32 of the first conductive layer 3 can be made of a highly conductive material such as Cu.

[0057] In the display manufacturing process, when the copper electrode is at a high temperature, Cu ions will diffuse across the gate insulating layer into the semiconductor, causing the performance of the thin film transistor to deteriorate, so it is usually necessary to add a diffusion prevention layer on the surface of the copper electrode. For example, in the embodiment of the present disclosure, the first sub-conductive layer 31 and the third sub-conductive layer 33 of the first conductive layer 3 are diffusion prevention layers, wherein the material of the first sub-conductive layer 31 and the third sub-conductive layer 33 can be the same. The material of the first sub-conductive layer 31 can be a metal layer, a metal nitride layer, a metal alloy, etc., such as metal titanium (Ti), molybdenum (Mo), niobium molybdenum alloy (MoNb), etc. The material of the second sub-conductive layer 32 is different from that of the first sub-conductive layer 31. The first sub-conductive layer 31 is located between the first passivation layer 2 and the second sub-conductive layer 32. When the thickness of the first sub-conductive layer 31 is relatively thick, for example, the thickness D1 of the first sub-conductive layer 31 is 300 angstroms, the first sub-conductive layer 31 can better prevent the second sub-conductive layer 32 from diffusing into the gate insulating layer.

[0058] The inventors have discovered that while adding a diffusion-preventing layer can prevent the diffusion of copper electrodes into the gate insulating layer, due to the inconsistent etching rates of the diffusion-preventing layer and the copper electrode, different etching shapes of the diffusion-preventing layer and the copper electrode may occur in the subsequent patterning process, resulting in poor protection of the copper electrode by the diffusion-preventing layer, thereby causing product defects. For example, when the first conductive layer 3 adopts a laminated structure, due to the inconsistent etching rates of the third sub-conductive layer 33 and the second sub-conductive layer 32, when the etching rate of the third sub-conductive layer 33 is higher than the etching rate of the second sub-conductive layer 32, the etched area will be indented, resulting in the final shape of the third sub-conductive layer 33 and the second sub-conductive layer 32 being uneven, and the remaining area of ​​the third sub-conductive layer being smaller than the area of ​​the second sub-conductive layer 32. The resulting poor appearance will cause the product to be judged as defective. When the etching rate of the third sub-conductive layer 33 is lower than that of the second sub-conductive layer 32, a protrusion may occur in the etched area, and the remaining area of ​​the third sub-conductive layer may be larger than that of the second sub-conductive layer 32, ultimately resulting in a poor appearance. By optimizing the thickness relationship between the second and third sub-conductive layers 32, 33, the etching rates of the second and third sub-conductive layers 32, 33 can be adjusted to avoid indentation or protrusion during etching.

[0059] In the embodiment of the present disclosure, referring to Figure 1, the thickness D3 of the third sub-conductive layer 33 is less than the thickness D1 of the first sub-conductive layer 31, and the thickness D2 of the second sub-conductive layer 32 is greater than the thickness of each of the first sub-conductive layer 31 and the third sub-conductive layer 33.

[0060] For example, in some other embodiments of the present disclosure, the thickness D3 of the third sub-conductive layer 33 is less than or equal to half of the thickness D1 of the first sub-conductive layer.

[0061] Illustratively, in some other embodiments of the present disclosure, the thickness D3 of the third sub-conductive layer is greater than 0 angstrom and less than or equal to 150 angstroms.

[0062] By controlling the thickness D3 of the third sub-conductive layer 33 to be relatively thin, etching of the third sub-conductive layer 33 is facilitated, and the tip protrusion phenomenon is less likely to occur. Furthermore, by controlling the photoresist on the surface of the third sub-conductive layer 33, the third sub-conductive layer 33 can be protected, reducing the etching speed of the third sub-conductive layer 33 and thus reducing the indentation phenomenon. This improves the consistency of the etched morphologies of the second sub-conductive layer 32 and the third sub-conductive layer 33, thereby increasing the product yield.

[0063] FIG. 2 is a partial schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, showing an electrical connection relationship between a pad and a pixel unit.

[0064] 2 , the display panel may include a plurality of pixel units 5, which are distributed in an array on a substrate 1. At least one of the pixel units includes a light-emitting diode 51, and the light-emitting diode 51 includes a first electrode 511 and a second electrode 512. The display panel also includes a plurality of pad pairs 6, which are located in the first conductive layer 3. At least one of the pad pairs 6 includes a first pad 61 and a second pad 62. The first pad 61 is configured to be electrically connected to the first electrode 511, and the second pad 62 is configured to be electrically connected to the second electrode 512.

[0065] In new display panels, as pixel density increases, the space for signal routing becomes smaller and smaller, so the line width of the conductive traces becomes narrower and narrower. In order to maintain sufficient conductivity of the signal traces to meet a sufficiently fast response speed, the thickness of the conductive traces needs to be relatively thick, thereby reducing the resistance of the conductive traces and ensuring that the display panel has a fast response speed.

[0066] Illustratively, in some embodiments of the present disclosure, the thickness D2 of the second sub-conductive layer is greater than or equal to 1.8 microns.

[0067] In the display panel, for example, the first conductive layer used for wire routing also needs a passivation layer for protection. Referring to Figure 1, the first conductive layer 3 is covered with a second passivation layer 4 on the side away from the base substrate. The second passivation layer 4 can reduce the corrosion of the first conductive layer by other processes, such as etching process, nickel-gold process, etc. in the subsequent process. In order to improve the protection effect of the second passivation layer 4 on the first conductive layer 3, the second passivation layer 4 needs to have sufficient wrapping properties for the first conductive layer 3 to form a good fitting coverage. For example, the second passivation layer 4 can be prepared by a chemical vapor deposition method. When the first conductive layer 3 has a large thickness, in order to achieve good coverage and wrapping of the first conductive layer 3, the second passivation layer 4 also needs to increase its thickness accordingly to match the thickness of the first conductive layer.

[0068] For example, in some embodiments of the present disclosure, a ratio of the thickness D4 of the second passivation layer 4 to the thickness D3 of the third sub-conductive layer 33 is greater than 26.

[0069] For example, in some embodiments of the present disclosure, the thickness D4 of the second passivation layer 4 is greater than the thickness D5 of the first passivation layer 2 .

[0070] For example, in some embodiments of the present disclosure, the thickness D4 of the second passivation layer 4 is greater than or equal to 4000 angstroms and less than or equal to 6000 angstroms.

[0071] The second passivation layer 4 and the first passivation layer 2 can be formed by physical vapor deposition, chemical vapor deposition, spraying, sputtering, and other processes. The materials of the second passivation layer 4 and the first passivation layer 2 can be the same or different. The first passivation layer 2 can be formed in one step using a single process, or in several steps using a single process, or in steps using different processes. Similarly, the second passivation layer 4 can be formed in one step using a single process, or in several steps using a single process, or in steps using different processes.

[0072] 3 is a partial schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, showing an orthographic projection relationship of a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer on a base substrate.

[0073] 1 and 3 , the display panel includes a first conductive layer 3 having a stacked structure and including a first sub-conductive layer 31, a second sub-conductive layer 32, and a third sub-conductive layer 33. The second sub-conductive layer 32 is located on a side of the first sub-conductive layer 31 away from a base substrate 1, wherein the orthographic projection of the second sub-conductive layer 32 on the base substrate 1 falls within the orthographic projection of the first sub-conductive layer 31 on the base substrate 1; and / or the third sub-conductive layer 33 is located on a side of the second sub-conductive layer 32 away from the base substrate 1, wherein the orthographic projection of the third sub-conductive layer 33 on the base substrate 1 falls within the orthographic projection of the second sub-conductive layer 32 on the base substrate 1.

[0074] Continuing with reference to Figures 1 and 3, the first sub-conductive layer 31 is located between the first passivation layer 2 and the second sub-conductive layer 32. Since the first sub-conductive layer 31 is made of a metal or alloy with relatively high thermal stability, such as titanium (Ti), molybdenum (Mo), or niobium-molybdenum alloy (MoNb), and the second sub-conductive layer 32 is generally made of a high-conductivity material such as copper or aluminum due to its high conductivity requirements, the thermal stability of such high-conductivity metals is generally poor. Therefore, during the display panel manufacturing process, the first sub-conductive layer 31 located between the second sub-conductive layer 32 and the first passivation layer 2 can prevent the second sub-conductive layer 32 from diffusing into the first passivation layer 2 and the semiconductor region below the first passivation layer 2, thereby reducing the probability of transistor performance degradation. In order to achieve a better anti-diffusion effect, the orthographic projection of the second sub-conductive layer 32 on the base substrate 1 is generally designed to fall within the orthographic projection of the first sub-conductive layer 31 on the base substrate 1. This design can block the direct diffusion channel of the metal in the second sub-conductive layer 32 into the first passivation layer 2, reduce the probability of the metal in the second sub-conductive layer 32 diffusing into the semiconductor region, and better improve the stability of the display panel.

[0075] Continuing to refer to Figures 1 and 3, the third sub-conductive layer 33 is located on the side of the second sub-conductive layer 32 away from the base substrate 1. Usually, the third sub-conductive layer 33 uses a metal or alloy with high thermal stability similar to the first sub-conductive layer 31, which can prevent the second sub-conductive layer 32 from diffusing into other film layers, and can also play a certain protective role for the second sub-conductive layer 32 in processes such as etching. The orthographic projection of the third sub-conductive layer 33 on the base substrate 1 falls within the orthographic projection of the second sub-conductive layer 32 on the base substrate 1. When it is necessary to achieve direct electrical connection between the second sub-conductive layer 32 and other traces in a local area to meet high-performance conductivity, the local area of ​​the third sub-conductive layer 33 can be opened to expose the second sub-conductive layer in the local area to achieve direct electrical connection with other traces.

[0076] FIG. 4 is a partial schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, in which a second conductive layer is shown.

[0077] With reference to FIG4 , the display panel may further include a second conductive layer 7. The second conductive layer 7 may be a single-layer structure or a stacked-layer structure similar to the first conductive layer 3. The second sub-conductive layer 7 is located between the base substrate 1 and the first passivation layer 2. By designing a double-layer conductive layer, such as the first conductive layer 3 and the second conductive layer 7 shown in FIG4 , the longitudinal space perpendicular to the base substrate can be fully utilized, and the wiring layout can be more flexibly designed to achieve electrical connections between the conductive layer and the transistor gate, source, drain, and external driver chip pins. This further reduces the wiring width in the conductive layer, improves the pixel density of the display panel, and further achieves high resolution of the display panel.

[0078] FIG5 is a schematic plan view of a display panel according to some embodiments of the present disclosure, showing an electrical connection structure of a driving chip, terminals, conductive connection parts, and pads.

[0079] The display panel can be controlled by connecting an IC (integrated circuit) driver chip. Referring to FIG5 , the display panel further includes a plurality of terminals 8, which are located in the first conductive layer 3 and are used to electrically connect to the pins 9 of the driver chip. The display panel further includes a plurality of conductive connection portions 10, which are located in the first conductive layer 3, and at least one conductive connection portion 10 connects at least one terminal 8 and the first pad 61 of at least one pad pair. Through the electrical connection between at least one pad pair, at least one conductive connection portion 10, at least one terminal 8, and the pins of at least one driver chip, and then through the electrical connection between at least one pad pair and a pixel unit, such as a light-emitting diode, the driver chip can control the pixel unit to achieve different display effects.

[0080] Figure 6 shows a planar schematic diagram of the display panel of some other embodiments of the present disclosure, which shows the electrical connection relationship between the first conductive layer and the second conductive layer and the electrical connection relationship between the wiring, the conductive part, the terminal and the driving chip. Figure 6 also shows the electrical connection relationship between the ground line and the first wiring.

[0081] 6 , the display panel further includes a plurality of traces 72 located in the second conductive layer 7. The display panel further includes a via 13 located in the first passivation layer 2 and a conductive portion 11 located in the first conductive layer 3. One end of the conductive portion 11 is electrically connected to the second pad 62 of at least one pad pair, and at least one trace 72 is electrically connected to the conductive portion 11 through the via 13.

[0082] Continuing with reference to FIG6 , the display panel further includes a plurality of terminals, including a first terminal 81, the first terminal 81 being configured to electrically connect to a ground signal pin 91 of the driver chip; the display panel further includes a plurality of traces 72, the plurality of traces 72 including a first trace 721, the first trace 721 being configured to transmit a ground signal; the display panel further includes a plurality of vias 13, the plurality of vias 13 including a plurality of first vias 131; and the display panel further includes a conductive portion 11, the conductive portion 11 including a first conductive portion 111. The first trace 721 is electrically connected to the first conductive portion 111 via the plurality of first vias 131, the other end of the first conductive portion 111 being electrically connected to the first terminal 81, and the orthographic projections of the plurality of first vias 131 on the base substrate 1 are arranged side by side along a first direction within the orthographic projection of the first conductive portion 111 on the base substrate 1.

[0083] Continuing with reference to Figure 6, the display panel also includes a grounding wire 14, which is located in the first conductive layer 3 and extends along the first direction; the display panel also includes a first routing line 721, which extends along the second direction, and the first direction and the second direction intersect; the display panel also includes a plurality of vias 13, and the plurality of vias 13 include a plurality of second vias 132, and the first routing line 721 is electrically connected to the grounding wire 14 through the plurality of second vias 132, and the orthographic projections of the plurality of second vias 132 on the base substrate 1 are arranged side by side along the first direction within the orthographic projection of the grounding wire 14 on the base substrate 1.

[0084] FIG7 shows a schematic plan view of a display panel according to some embodiments of the present disclosure, illustrating the electrical connection relationship among pixels, terminals, pads, and conductive connection portions.

[0085] 7 , the display panel includes a plurality of pixel units 5, a plurality of terminals 8, and a plurality of pad pairs 6. Among the plurality of pixel units 5, at least one pixel unit includes a first sub-pixel 52, a second sub-pixel 53, and a third sub-pixel. The first sub-pixel 52 includes a first light-emitting diode 521, the second sub-pixel 53 includes a second light-emitting diode 531, and the third sub-pixel includes a third light-emitting diode. The plurality of terminals 8 further include a second terminal 82, a third terminal 83, and a fourth terminal 84. The plurality of pad pairs 6 include a first pad pair 601, a second pad pair 602, and a third pad pair 603. The first pad and the second pad of the first pad pair 601 are respectively electrically connected to the first electrode and the second electrode of the first light-emitting diode 521, the first pad and the second pad of the second pad pair 602 are respectively electrically connected to the first electrode and the second electrode of the second light-emitting diode, and the first pad and the second pad of the third pad pair 603 are respectively electrically connected to the first electrode and the second electrode of the third light-emitting diode. The display panel also includes a conductive connecting part 10, which includes a first conductive connecting part 101, a second conductive connecting part 102 and a third conductive connecting part 103. The second terminal 82 is electrically connected to the first pad of the first pad pair 601 through the first conductive connecting part 101, the third terminal 83 is electrically connected to the first pad of the second pad pair 602 through the second conductive connecting part 102, and the fourth terminal 84 is electrically connected to the first pad of the third pad pair 603 through the third conductive connecting part 103.

[0086] FIG8 is a plan view schematic diagram of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship among traces, conductive parts, pads, and light-emitting diodes.

[0087] 8 , a display panel includes a plurality of lines, wherein the plurality of lines include a second line 722 and a third line 723 , wherein the second line 722 is used to transmit a first voltage signal to the first light-emitting diode 521 , and the third line 723 is used to transmit a second voltage signal to the second light-emitting diode 531 and the third light-emitting diode 541 . The display panel also includes multiple vias and conductive parts, the multiple vias include a third via 133 and multiple fourth vias 134, the conductive parts include a second conductive part 112 and a third conductive part 113, the second trace 722 is electrically connected to one end of the second conductive part 112 through the third via 133, and the other end of the second conductive part 112 is electrically connected to the second pad of the first pad pair 601, the third trace 723 is electrically connected to the third conductive part 113 through the multiple fourth vias 134, the third conductive part 113 is electrically connected to the second pad of the second pad pair 602 and the second pad of the third pad pair 603, and the orthographic projections of the multiple fourth vias 134 on the base substrate 1 are arranged side by side along the second direction within the orthographic projection of the third conductive part 113 on the base substrate 1.

[0088] The display panel can not only control the display effect through the IC driver chip, but also control the display effect through the low-temperature polysilicon technology LTPS (Low Temperature Poly-silicon) driver circuit to achieve control of different screens.

[0089] FIG9 is a schematic plan view of a display panel according to some other embodiments of the present disclosure, showing the electrical connection relationship between the first voltage signal line, the second voltage signal line, the pad, and the light-emitting diode.

[0090] With reference to Figures 7 and 9, an exemplary embodiment of a display panel controlled by an LTPS driving circuit is given. Referring to Figure 7, the display panel has multiple pixel units and multiple pad pairs, at least one of which includes a first sub-pixel 52, a second sub-pixel 53, and a third sub-pixel 54, the first sub-pixel includes a first light-emitting diode 521, the second sub-pixel includes a second light-emitting diode 531, and the third sub-pixel includes a third light-emitting diode 541; the multiple pad pairs include a first pad pair 601, a second pad pair 602, and a third pad pair 603, the first pad and the second pad of the first pad pair 601 being used to electrically connect to the first electrode and the second electrode of the first light-emitting diode 521, respectively, the first pad and the second pad of the second pad pair 602 being used to electrically connect to the first electrode and the second electrode of the second light-emitting diode, respectively, and the first pad and the second pad of the third pad pair 603 being used to electrically connect to the first electrode and the second electrode of the third light-emitting diode, respectively. Referring to Figure 9, the display panel includes a first voltage signal line V1 and a second voltage signal line V2 located in the first conductive layer 3, the first pad of the first pad pair 601 is electrically connected to the first voltage signal line, the first pad of the second pad pair 602 and the first pad of the third pad pair 603 are both electrically connected to the second voltage signal line, and the first pad pair 601, the second pad pair 602 and the third pad pair are located between the first voltage signal line V1 and the second voltage signal line V2 in the first direction.

[0091] Exemplarily, the display panel includes a first conductive layer 3. Referring to Figure 1, the first conductive layer 3 includes a first sub-conductive layer 31, a second sub-conductive layer 32 and a third sub-conductive layer 33. The material of the first sub-conductive layer 31 and the third sub-conductive layer 33 includes molybdenum-niobium alloy (MoNb), and the material of the second sub-conductive layer 32 includes copper (Cu).

[0092] FIG10 is a schematic structural diagram of a display panel according to some other embodiments of the present disclosure, wherein the thickness ratio of the second passivation layer to the third sub-conductive layer is shown.

[0093] 10 , the present disclosure provides a display panel, comprising: a base substrate 1, a first passivation layer 2 arranged on the base substrate, a first conductive layer 3 arranged on a side of the first passivation layer 2 away from the base substrate 1, and a second passivation layer 4 arranged on a side of the first conductive layer 3 away from the base substrate 1. 2 , the display panel includes a plurality of pixel units 5, which are distributed in an array on the substrate 1, and at least one of the pixel units 5 includes a light-emitting diode 51, which includes a first electrode 511 and a second electrode 512; the display panel includes a plurality of pad pairs 6, which are located in the first conductive layer 3, and at least one of the pad pairs 6 includes a first pad 61 and a second pad 62, the first pad 61 is used to be electrically connected to the first electrode 511, and the second pad 62 is used to be electrically connected to the second electrode 512; with reference to FIG10 , the first conductive layer 3 has a stacked structure, and the stacked structure of the first conductive layer includes a first sub-conductive layer 31, a second sub-conductive layer 32 and a third sub-conductive layer 33, the first sub-conductive layer 31 is located on the side of the first passivation layer 2 away from the substrate 1, the second sub-conductive layer 32 is located on the side of the first sub-conductive layer 31 away from the substrate 1, and the third sub-conductive layer 33 is located on the side of the second sub-conductive layer 32 away from the substrate 1. The thickness of the second passivation layer 4 is D4, the thickness of the third sub-conductive layer 33 is D3, and the ratio of the thickness D4 of the second passivation layer 4 to the thickness D3 of the third sub-conductive layer 33 is greater than 26.

[0094] LED light sources can not only be used as display pixels to make display panels, but can also be used as backlight light sources in display panels, and then combined with light guide plates, diffuser plates, prism plates and liquid crystal modules to make display devices.

[0095] FIG11 shows a schematic structural diagram of some other embodiments of the present disclosure, in which a backlight module is shown as a backlight source in a display device.

[0096] 11 , the present disclosure further provides a backlight module for use as a backlight source in a display device. The display device includes a backlight module 30 , a light guide plate 31 , a diffuser plate 32 , a prism plate 33 , and a liquid crystal module 34 .

[0097] FIG12A shows a schematic structural diagram of a backlight module according to some other embodiments of the present disclosure, and FIG12B shows a planar schematic diagram of the backlight module, wherein FIG12B shows an electrical connection relationship between a light-emitting unit and a pair of pads in a backlight module.

[0098] 12A , the backlight module 30 includes multiple film layers disposed on a base substrate 1. For example, the multiple film layers include: a first passivation layer 2 disposed on the base substrate 1; a first conductive layer 3 disposed on a side of the first passivation layer 2 away from the base substrate; and a second passivation layer 4 disposed on a side of the first conductive layer 3 away from the base substrate. The base substrate 1 may be made of, but is not limited to, glass, quartz, plastic, silicon, polyimide, and the like.

[0099] Continuing with reference to FIG12A , in the embodiment of the present disclosure, the first conductive layer 3 is a stacked structure, which includes a first sub-conductive layer 31 located on the side of the first passivation layer 2 away from the substrate, a second sub-conductive layer 32 located on the side of the first sub-conductive layer 31 away from the substrate, and a third sub-conductive layer located on the side of the second sub-conductive layer 32 away from the substrate. The conductive component used to connect to the light-emitting diode or the driver chip can be located in the first conductive layer 3. For example, the second sub-conductive layer 32 of the first conductive layer 3 can be a material with high conductivity such as Cu. The first sub-conductive layer 31 and the third sub-conductive layer 33 are made of the same material, the second sub-conductive layer 32 and the third sub-conductive layer 33 are made of different materials, the thickness D3 of the third sub-conductive layer 33 is less than the thickness D1 of the first sub-conductive layer 31, and the thickness D2 of the second sub-conductive layer 32 is greater than the thickness of each of the first sub-conductive layer 31 and the third sub-conductive layer 33.

[0100] With reference to FIG12B , in the embodiment of the present disclosure, the backlight module 30 further includes a plurality of light-emitting units 20, which are distributed in an array on the base substrate 1. At least one of the pixel units includes a light-emitting diode 51, and the light-emitting diode 51 includes a first electrode 511 and a second electrode 512. The backlight module further includes a plurality of pad pairs 6, which are located in the first conductive layer 3. At least one of the pad pairs 6 includes a first pad 61 and a second pad 62. The first pad 61 is used to electrically connect to the first electrode 511, and the second pad 62 is used to electrically connect to the second electrode 512.

[0101] FIG13 is a schematic structural diagram of a backlight module according to some other embodiments of the present disclosure, which shows the thickness relationship between the second conductive layer and the first conductive layer.

[0102] 13 , the present disclosure provides another backlight module. The backlight module includes a first conductive layer 3 and a second conductive layer 7. The second conductive layer 7 is located on a side of the first passivation layer 2 close to the base substrate 1. The thickness D6 of the second conductive layer is less than the thickness D7 of the first conductive layer.

[0103] 14A and 14B are each a display device according to an exemplary embodiment of the present disclosure.

[0104] 14A , an embodiment of the present disclosure exemplarily provides a display device 200 , wherein the display device 200 includes any of the aforementioned display panels 100 .

[0105] 14B , an embodiment of the present disclosure exemplarily provides another display device 200 , wherein the display device 200 includes any of the aforementioned backlight modules 30 .

[0106] FIG15 is a diagram illustrating a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure. As shown in FIG15 , the method may include steps S01 to S07.

[0107] It should be noted that some steps of the above manufacturing method can be performed individually or in combination, and can be performed in parallel or sequentially, and are not limited to the specific operation sequence shown in the figures.

[0108] In step S01, a base substrate 1 is provided;

[0109] In step S02, a first passivation layer 2 is formed on the base substrate 1;

[0110] In step S03, a first sub-conductive material layer 31 of a first conductive layer is formed on a side of the first passivation layer 2 away from the base substrate 1;

[0111] In step S04, a second sub-conductive material layer 32 of the first conductive layer is formed on a side of the first sub-conductive material layer 31 away from the base substrate 1;

[0112] In step S05, a third sub-conductive material layer 33 of the first conductive layer is formed on the side of the second sub-conductive material layer 32 away from the base substrate 1;

[0113] The first sub-conductive material layer 31 , the second sub-conductive material layer 32 and the third sub-conductive material layer 33 are collectively referred to as the first conductive material layer 3 .

[0114] The first sub-conductive material layer and the third sub-conductive material layer are made of the same material, and the second sub-conductive material layer and the third sub-conductive material layer are made of different materials; the thickness of the third sub-conductive material layer is less than the thickness of the first sub-conductive material layer, and the thickness of the second sub-conductive material layer is greater than the thickness of each of the first sub-conductive material layer and the third conductive material layer.

[0115] In step S06, a patterning process is performed on the first conductive material layer 3 to form a plurality of pad pairs 6, wherein at least one of the pad pairs includes a first pad and a second pad, the first pad is used to be electrically connected to the first electrode of the light-emitting diode, and the second pad is used to be electrically connected to the second electrode of the light-emitting diode.

[0116] In step S07 , a second passivation layer 4 is formed on a side of the plurality of pad pairs 6 away from the base substrate 1 .

[0117] FIG16 is a flow chart of a process for patterning a first conductive material layer according to an exemplary embodiment of the present disclosure. As shown in FIG16 , the method may include steps S061 - S064 .

[0118] In step S061, a photoresist layer is coated on the first conductive material layer;

[0119] In step S062, a pre-baking process is performed on the photoresist layer;

[0120] In step S063, exposing the photoresist layer;

[0121] In step S064, a post-baking process is performed on the photoresist layer.

[0122] Wherein, in the post-baking process, the post-baking temperature is greater than 130° C., and the post-baking time is greater than 8 minutes.

[0123] By optimizing the post-baking temperature and post-baking time in the patterning process of the first conductive material layer, the etching speeds of the first sub-conductive material layer and the second sub-conductive material layer in the first conductive material layer can be made close in the etching process, ensuring that the patterns of the first sub-conductive material layer and the second sub-conductive material layer remain consistent after etching, without indentation or top protrusion, thereby improving the stability and yield of the product.

[0124] In step S07 , forming the second passivation layer 4 on the side of the plurality of pad pairs 6 away from the base substrate includes forming the second passivation layer 4 on the side of the plurality of pad pairs 6 away from the base substrate 1 by a chemical vapor deposition process.

[0125] Through the chemical vapor deposition process, the bonding force between the second passivation layer 4 and the first conductive material layer 3 can be increased, and the wrapping performance of the second passivation layer 4 on the first conductive material layer 3 can be improved, so that the second passivation layer 4 has a better protective effect on the first conductive material layer, thereby improving the reliability of the display panel.

[0126] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or couplings are intended to fall within the scope of this disclosure.

[0127] Although the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made to the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by the equivalents of the appended claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises: substrate substrate; A first passivation layer disposed on the substrate; A first conductive layer disposed on a side of the first passivation layer away from the substrate; and A second passivation layer is disposed on a side of the first conductive layer away from the substrate. Wherein, the array substrate comprises a plurality of array units, the plurality of array units are distributed in an array on the base substrate, at least one of the array units comprises a light emitting diode, and the light emitting diode comprises a first electrode and a second electrode; The display panel includes a plurality of pad pairs, the plurality of pad pairs are located in the first conductive layer, at least one of the pad pairs includes a first pad and a second pad, the first pad is used to be electrically connected to the first electrode, and the second pad is used to be electrically connected to the second electrode; The first conductive layer has a stacked structure, the stacked structure of the first conductive layer includes a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer is located on a side of the first passivation layer away from the base substrate, the second sub-conductive layer is located on a side of the first sub-conductive layer away from the base substrate, and the third sub-conductive layer is located on a side of the second sub-conductive layer away from the base substrate; The first sub-conductive layer and the third sub-conductive layer are made of the same material, and the second sub-conductive layer and the third sub-conductive layer are made of different materials; and The thickness of the third sub-conductive layer is smaller than that of the first sub-conductive layer, and the thickness of the second sub-conductive layer is larger than that of each of the first sub-conductive layer and the third conductive layer.

2. The array substrate according to claim 1, wherein: The thickness of the third sub-conductive layer is less than or equal to half of the thickness of the first sub-conductive layer.

3. The array substrate according to claim 1 or 2, wherein: The thickness of the third sub-conductive layer is greater than 0 angstrom and less than or equal to 150 angstroms.

4. The array substrate according to claim 1 or 2, wherein: The thickness of the second sub-conductive layer is greater than or equal to 1.8 micrometers.

5. The array substrate according to claim 1 or 2, wherein: A ratio of a thickness of the second passivation layer to a thickness of the third sub-conductive layer is greater than 26.

6. The array substrate according to claim 5, wherein: The thickness of the second passivation layer is greater than the thickness of the first passivation layer.

7. The array substrate according to claim 5, wherein: The thickness of the second passivation layer is greater than or equal to 4000 angstroms and less than or equal to 6000 angstroms.

8. The array substrate according to claim 1 or 2, wherein: The orthographic projection of the third sub-conductive layer on the base substrate falls within the orthographic projection of the second sub-conductive layer on the base substrate; and / or the orthographic projection of the second sub-conductive layer on the base substrate falls within the orthographic projection of the first sub-conductive layer on the base substrate.

9. The array substrate according to claim 1 or 2, wherein: The array substrate further includes a second conductive layer, and the second conductive layer is located on a side of the first passivation layer close to the base substrate; and The thickness of the second conductive layer is smaller than the thickness of the first conductive layer.

10. The array substrate according to claim 1 or 2, wherein: The array substrate further comprises a plurality of terminals, the plurality of terminals are located in the first conductive layer, and the plurality of terminals are used to be electrically connected to the pins of the driving chip; and The array substrate further includes a plurality of conductive connection portions, wherein the plurality of conductive connection portions are located in the first conductive layer, and at least one of the conductive connection portions electrically connects at least one of the terminals with at least one of the first pads.

11. The array substrate according to claim 10, wherein: The array substrate further comprises a plurality of wirings, and the plurality of wirings are located in the second conductive layer; The array substrate further includes: a via hole located in the first passivation layer; and a conductive portion located in the first conductive layer; and One end of the conductive portion is electrically connected to at least one of the second pads, and at least one of the traces is electrically connected to the conductive portion through the via hole.

12. The array substrate according to claim 11, wherein: The plurality of terminals include a first terminal, the first terminal being used to be electrically connected to a ground signal pin of the driving chip; The plurality of routing lines include a first routing line, the first routing line being used to transmit a ground signal; and The via includes a plurality of first vias, the conductive portion includes a first conductive portion, the first trace is electrically connected to the first conductive portion through the plurality of first vias, the other end of the first conductive portion is electrically connected to the first terminal, and the orthographic projections of the plurality of first vias on the base substrate are arranged side by side along a first direction within the orthographic projection of the first conductive portion on the base substrate.

13. The array substrate according to claim 12, wherein: The array substrate further includes a grounding line, the grounding line is located in the first conductive layer, the grounding line extends along a first direction, the first routing line extends along a second direction, and the first direction and the second direction intersect; The vias include a plurality of second vias, the first trace is electrically connected to the ground line through the plurality of second vias, and the orthographic projections of the plurality of second vias on the base substrate are arranged side by side along a first direction within the orthographic projection of the ground line on the base substrate.

14. The array substrate according to any one of claims 11 to 13, wherein: The array unit is a pixel unit, at least one of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel includes a first light-emitting diode, the second sub-pixel includes a second light-emitting diode, and the third sub-pixel includes a third light-emitting diode; The plurality of terminals further include a second terminal, a third terminal and a fourth terminal, the plurality of pad pairs include a first pad pair, a second pad pair and a third pad pair, the first pad and the second pad of the first pad pair being used to be electrically connected to the first electrode and the second electrode of the first light-emitting diode, respectively, the first pad and the second pad of the second pad pair being used to be electrically connected to the first electrode and the second electrode of the second light-emitting diode, respectively, and the first pad and the second pad of the third pad pair being used to be electrically connected to the first electrode and the second electrode of the third light-emitting diode, respectively; and The conductive connection portion includes a first conductive connection portion, a second conductive connection portion and a third conductive connection portion, the second terminal is electrically connected to the first pad of the first pad pair through the first conductive connection portion, and the third terminal is electrically connected to the first pad pair through the third conductive connection portion. The fourth terminal is electrically connected to the first pad of the second pad pair through the second conductive connecting portion, and the fourth terminal is electrically connected to the first pad of the third pad pair through the third conductive connecting portion.

15. The array substrate according to claim 14, wherein: The plurality of wirings further include a second wiring and a third wiring, the second wiring is used to transmit a first voltage signal to the first light emitting diode, and the third wiring is used to transmit a second voltage signal to the second light emitting diode and the third light emitting diode; The via includes a third via and a plurality of fourth vias, the conductive portion includes a second conductive portion and a third conductive portion, the second routing is electrically connected to one end of the second conductive portion through the third via, the other end of the second conductive portion is electrically connected to the second pad of the first pad pair, the third routing is electrically connected to the third conductive portion through the plurality of fourth vias, the third conductive portion is electrically connected to both the second pad of the second pad pair and the third pad of the third pad pair, and the orthographic projections of the plurality of fourth vias on the substrate are arranged side by side along the second direction within the orthographic projection of the third conductive portion on the substrate.

16. The array substrate according to claim 1 or 2, wherein: The array unit is a pixel unit, at least one of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel includes a first light-emitting diode, the second sub-pixel includes a second light-emitting diode, and the third sub-pixel includes a third light-emitting diode; The plurality of pad pairs include a first pad pair, a second pad pair, and a third pad pair, wherein the first pad and the second pad of the first pad pair are respectively electrically connected to the first electrode and the second electrode of the first light-emitting diode, the first pad and the second pad of the second pad pair are respectively electrically connected to the first electrode and the second electrode of the second light-emitting diode, and the first pad and the second pad of the third pad pair are respectively electrically connected to the first electrode and the second electrode of the third light-emitting diode; and The array substrate includes a first voltage signal line and a second voltage signal line located in the first conductive layer, the first pad of the first pad pair is electrically connected to the first voltage signal line, the first pad of the second pad pair and the first pad of the third pad pair are both electrically connected to the second voltage signal line, and the first pad pair, the second pad pair and the third pad pair are located between the first voltage signal line and the second voltage signal line in a first direction.

17. The array substrate according to claim 1 or 2, wherein: The materials of the first sub-conductive layer and the third sub-conductive layer include MoNb, and the material of the second sub-conductive layer includes Cu.

18. An array substrate, characterized in that: The array substrate comprises: substrate substrate; A first passivation layer disposed on the substrate; A first conductive layer disposed on a side of the first passivation layer away from the substrate; and A second passivation layer is disposed on a side of the first conductive layer away from the substrate. Wherein, the array substrate comprises a plurality of array units, the plurality of array units are distributed in an array on the base substrate, at least one of the array units comprises a light emitting diode, and the light emitting diode comprises a first electrode and a second electrode; The array substrate comprises a plurality of pad pairs, the plurality of pad pairs are located in the first conductive layer, at least one of the pad pairs comprises a first pad and a second pad, the first pad is used to be electrically connected to the first electrode, and the second pad is used to be electrically connected to the second electrode; The first conductive layer has a stacked structure, the stacked structure of the first conductive layer includes a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer is located on a side of the first passivation layer away from the base substrate, the second sub-conductive layer is located on a side of the first sub-conductive layer away from the base substrate, and the third sub-conductive layer is located on a side of the second sub-conductive layer away from the base substrate; and A ratio of a thickness of the second passivation layer to a thickness of the third sub-conductive layer is greater than 26.

19. A display device, wherein: The display device comprises the array substrate according to any one of claims 1 to 18.

20. A method for preparing an array substrate, characterized in that: The preparation method comprises: providing a substrate base plate; forming a first passivation layer on the base substrate; forming a first conductive material layer on a side of the first passivation layer away from the substrate; Performing a patterning process on the first conductive material layer to form a plurality of pad pairs, wherein at least one of the pad pairs includes a first pad and a second pad, the first pad being used to be electrically connected to a first electrode of a light-emitting diode, and the second pad being used to be electrically connected to a second electrode of the light-emitting diode; and forming a second passivation layer on a side of the plurality of pad pairs away from the substrate; Wherein, forming a first conductive material layer on a side of the first passivation layer away from the substrate includes: forming a first sub-conductive material layer on a side of the first passivation layer away from the substrate; forming a second sub-conductive material layer on a side of the first sub-conductive layer away from the base substrate; and A third sub-conductive material layer is formed on a side of the second sub-conductive layer away from the base substrate, The first sub-conductive material layer and the third sub-conductive material layer are made of the same material, and the second sub-conductive material layer and the third sub-conductive material layer are made of different materials; and The thickness of the third sub-conductive material layer is smaller than that of the first sub-conductive material layer, and the thickness of the second sub-conductive material layer is larger than that of each of the first sub-conductive material layer and the third conductive material layer.

21. The method of claim 20, wherein: The patterning process of the first conductive material layer comprises: coating a photoresist layer on the first conductive material layer; performing a pre-baking process on the photoresist layer; exposing the photoresist layer; performing a post-baking process on the photoresist layer, Wherein, in the post-baking process, the post-baking temperature is greater than 130° C., and the post-baking time is greater than 8 minutes.

22. The method of claim 20 or 21, wherein: The forming of the second passivation layer on the side of the plurality of pad pairs away from the base substrate comprises: forming the second passivation layer on the side of the plurality of pad pairs away from the base substrate by a chemical vapor deposition process.

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