Chip, chip manufacturing method, computing device, and signal transmission method

Abstract

A chip, a chip manufacturing method, a computing device, and a signal transmission method. A packaging substrate of the chip comprises a basic pattern unit having six signal pins, wherein a first pin, a second pin, a third pin and a fourth pin are sequentially arranged at intervals in a first direction, and a fifth pin and a sixth pin are arranged at an interval in a second direction; the fifth pin and the sixth pin are respectively located on two sides of a connecting line of the second pin and the third pin; and the first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins. According to the solution, the data signal pins are respectively arranged at four outwards-extending ends of the cross-shaped pattern unit, the data signal pins are far away from each other, and each data signal pin does not have an adjacent data signal pin capable of forming a crosstalk source, effectively reducing electromagnetic crosstalk between pins; additionally, the density of the arrangement of the pins can be improved, reducing the packaging area.

Description

Chip, chip manufacturing method, computing device and signal transmission method

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on July 21, 2023, with application number 202310905856.2 and invention name “A chip, chip manufacturing method, computing device and signal transmission method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of electronic device packaging, and in particular to a chip, a chip manufacturing method, a computing device, and a signal transmission method. Background Art

[0003] With the continuous advancement of storage technology, double data rate synchronous dynamic random access memory (DDR SDRAM) systems have been widely used in computing products, such as, but not limited to, servers. However, the performance improvements of DDR systems, along with the evolution of DDR generations, have placed higher demands on chip packaging technology.

[0004] In DDR systems, the increasing number of channels and input / output (I / O) pins has led to larger chip packages. Larger packages typically increase both size and mass, generating more heat during soldering between the chip and the printed circuit board (PCB). The chip package and the PCB often have different thermal expansion coefficients, leading to large soldering temperature gradients, causing thermal stress and fatigue, and increasing solder joint risk. Furthermore, large package deformation is difficult to control, leading to the risk of solder defects and poor connections, which directly impacts product cost and yield.

[0005] On the other hand, the increasing speed of DDR interfaces has a greater impact on crosstalk between adjacent signals. To reduce electromagnetic crosstalk between pins, a typical approach is to place ground solder balls around the pins on the chip package substrate. This can reduce the impact of electromagnetic crosstalk, but the placement of ground solder balls increases chip size.

[0006] Therefore, the pin arrangement of the chip packaging substrate needs to take into account two trending design requirements: high-density arrangement and low crosstalk to meet the performance requirements of the product.

[0007] Summary of the Invention

[0008] The embodiments of the present application provide a chip, a chip manufacturing method, a computing device, and a signal transmission method, which can improve the arrangement density and effectively reduce electromagnetic crosstalk.

[0009] According to a first aspect of an embodiment of the present application, a chip is provided, wherein a core particle of the chip is arranged on a packaging substrate thereof, and the packaging substrate is a carrier for the core particle packaging. A plurality of pin arrangement graphic units are provided in the pin area of ​​the packaging substrate, and at least two of the plurality of pin arrangement graphic units are basic graphic units including six signal pins. Among them, the first pin, the second pin, the third pin, and the fourth pin of the six signal pins of the basic graphic unit are arranged in sequence in a first direction, and the fifth pin and the sixth pin of the six signal pins are arranged in a second direction in a spaced manner, the first direction is different from the second direction, and the fifth pin and the sixth pin are respectively located on both sides of the line connecting the second pin and the third pin. In addition, the first pin, the fourth pin, the fifth pin, and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins.

[0010] With this arrangement, the pins of the basic graphics unit are arranged in a cross-shaped pattern, with the four data signal pins placed at the four protruding ends of the cross-shaped graphics unit and the control signal pins placed in the center of the cross-shaped graphics unit. This allows the data signal pins to be separated from each other, and each data signal pin has no adjacent data signal pins that could form a crosstalk source, effectively avoiding the impact of electromagnetic crosstalk between adjacent data signal pins. Based on this pinmap solution, on the one hand, it effectively reduces electromagnetic crosstalk between pins, supporting higher DDR operating rates; on the other hand, it increases pin layout density, saves packaging area, and provides technical support for further improving product yield and reducing processing costs.

[0011] For example, each pin in the package substrate pin region can be a solder ball structure, electrically connected to a corresponding pad on the circuit board through soldering. Each pin in the package substrate pin region can also be a metal contact point structure, with a corresponding metal spring provided on the circuit board. The metal contact points and the metal springs can be provided in a one-to-one correspondence. The assembled metal contact points press against the metal springs, and the deformed metal springs maintain a reliable electrical connection with the corresponding metal contact points.

[0012] In actual applications, the multiple pin arrangement graphic units in the pin area of ​​the package substrate can be configured into different pin arrangements according to actual functional requirements; for example, a part of the pin arrangement graphic units are configured as basic graphic units in the cross-shaped pattern to be used to build channels of the DDR memory system; another part of the pin arrangement graphic units are configured to include graphic units with other arrangements to achieve electrical connection with corresponding external circuits; that is, the pin arrangement of the pin area of ​​the package substrate can be obtained by combining and arranging several types of graphic units.

[0013] Based on the first aspect, the present application also provides a first implementation of the first aspect, wherein the fifth and sixth pins are arranged on a perpendicular line to the line connecting the second and third pins, where the first direction is perpendicular to the second direction. Furthermore, the fifth and sixth pins can be arranged on a perpendicular midline to the line connecting the second and third pins, achieving good overall structural symmetry and a more compact overall layout in the pin area.

[0014] In practical applications, the connection line between the fifth pin and the sixth pin may also intersect the connection line between the second pin and the third pin at other angles, which can also keep the data signal pins away from each other and reduce electromagnetic crosstalk.

[0015] Based on the first aspect, or the first embodiment of the first aspect, the present application also provides a second embodiment of the first aspect: the basic graphic unit adopts a centrally symmetrical structure or an axially symmetrical structure. This allows full utilization of the pin area to achieve high-density layout, effectively reducing electromagnetic crosstalk between pins while more reasonably controlling the package size.

[0016] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, the embodiment of the present application also provides a third embodiment of the first aspect: the pins in the pin area of ​​the packaging substrate are arranged in an array, wherein the pins between rows and columns are staggered, that is, each row of pins and each column of pins are staggered with each other, and as many pins as possible can be arranged in a limited layout space, which can achieve a tight alternating arrangement of cross-shaped graphic units and further improve the pin arrangement density.

[0017] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, the present application also provides a fourth embodiment of the first aspect: the pins in the pin region of the package substrate are arranged in a triangular grid, with the line connecting a pin and two adjacent pins forming an equilateral triangle. This further enables a tight alternating arrangement of the cross-shaped pattern units, thereby increasing the pin arrangement density.

[0018] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, the embodiments of the present application further provide a fifth embodiment of the first aspect: the basic graphics unit further includes ground pins, where the ground pins are arranged around the six signal pins. Thus, based on the arrangement of the ground pins, a low-impedance ground path can be provided, forming a uniform ground potential, thereby directing electromagnetic field energy to the ground plane, thereby reducing electromagnetic crosstalk between signal pins, helping to maintain signal integrity, and reducing noise.

[0019] Exemplarily, the ground pin may be a solder ball structure, or may be a metal contact point structure.

[0020] Based on the fifth implementation of the first aspect, the embodiment of the present application also provides a sixth implementation of the first aspect: the basic graphic unit has fourteen ground pins, which are arranged on the periphery of the six signal pins, and the fourteen ground pins are arranged in sequence; as a whole, the fourteen ground pins are arranged in sequence to form a fourteen-sided polygon; the data signal pins adjacent to two adjacent ground pins and the line connecting these two adjacent ground pins form an equilateral triangle. This arrangement makes full use of the pin area space where the pin rows and columns are staggered, and constructs the Pinmap unit according to the rules of alternating arrangement, and the distance between any two adjacent pins is consistent. While providing the return ground function, it can increase the pin arrangement density and have a higher signal-to-ground ratio.

[0021] Based on the fifth implementation of the first aspect or the sixth implementation of the first aspect, the present application also provides a seventh implementation of the first aspect: two basic graphic units are arranged adjacent to each other, one of which is a first basic graphic unit and the other is a second basic graphic unit, and the adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin. In other words, the ground pins on the adjacent sides of the two basic graphic units are shared. In this way, in addition to effectively reducing electromagnetic crosstalk, the pin layout density is more compact and reasonable.

[0022] In practical applications, the staggered arrangement of pin rows and columns in the package substrate pin area can be combined to form different pin layout units through translation or rotational translation. For example, a cross-shaped pin layout unit can transmit a half-byte of data, while a pin layout unit formed by combining two pin layout units can transmit a byte of data.

[0023] Illustratively, one of the two pin arrangement graphic units of the pin arrangement combination unit may be a graphic unit formed by translation relative to the other; or one may be a graphic unit formed by rotation and translation relative to the other.

[0024] Based on the seventh implementation of the first aspect, the embodiment of the present application also provides an eighth implementation of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in the first direction. The first basic graphic unit and the second basic graphic have a common ground pin, and the first pin, second pin, third pin and fourth pin of the first basic graphic unit are arranged in the same direction as the first pin, second pin, third pin and fourth pin of the second basic graphic unit; the common ground pin is located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0025] Based on the seventh implementation of the first aspect, the embodiment of the present application also provides a ninth implementation of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in the second direction, and the fifth pin and the sixth pin of the first basic graphic unit are arranged in the same direction as the fifth pin and the sixth pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the sixth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0026] Based on the seventh implementation manner of the first aspect, the embodiment of the present application also provides a tenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first pin, second pin, third pin and fourth pin of the first basic graphic unit are arranged in the same direction as the sixth pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0027] Based on the seventh implementation manner of the first aspect, the embodiment of the present application also provides an eleventh implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the fifth pin and the sixth pin of the first basic graphic unit are arranged in the same direction as the first pin of the second basic graphic unit; the fourth pin of the first basic graphic unit is arranged in the same direction as the fifth pin and the sixth pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence, wherein two common ground pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit, and the other two common ground pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0028] Based on the seventh implementation manner of the first aspect, the embodiment of the present application also provides a twelfth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit are arranged in the same direction; the sixth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit are arranged in the same direction; the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence, wherein two common ground pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit, and the other two common ground pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0029] Based on the seventh implementation manner of the first aspect, the embodiment of the present application also provides a thirteenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, the first pin and the fifth pin of the first basic graphic unit are arranged in the same direction as the fifth pin and the sixth pin of the second basic graphic unit; the sixth pin and the fourth pin of the first basic graphic unit are arranged in the same direction as the first pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic have four common grounding pins; the four common grounding pins are arranged in sequence, two of which are adjacent to the fifth pin of the first basic graphic unit, and the other two common grounding pins are adjacent to the fourth pin of the first basic graphic unit.

[0030] Based on the fifth implementation of the first aspect, the embodiment of the present application further provides a fourteenth implementation of the first aspect: the basic graphics unit has fourteen ground pins, which are sequentially spaced and arranged around the six signal pins; furthermore, in the first direction, the first ground pin is located beside the first pin, and the eighth ground pin is located beside the fourth pin; at the same time, the second ground pin, the third ground pin, the fourth ground pin, the fifth ground pin, the sixth ground pin, and the seventh ground pin are sequentially arranged between the first ground pin and the eighth ground pin; and the ninth ground pin, the tenth ground pin, the eleventh ground pin, the twelfth ground pin, the thirteenth ground pin, and the fourteenth ground pin are sequentially arranged between the eighth ground pin and the first ground pin. The overall layout is more compact and reasonable.

[0031] Based on the fourteenth implementation manner of the first aspect, the embodiment of the present application also provides the fifteenth implementation manner of the first aspect: two basic graphic units are arranged adjacent to each other, one of the two basic graphic units is a first basic graphic unit, and the other of the two basic graphic units is a second basic graphic unit, and the adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin.

[0032] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides the sixteenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, wherein the eighth ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are a common ground pin.

[0033] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides the seventeenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, wherein the twelfth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are shared ground pins; wherein the eleventh ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are shared ground pins.

[0034] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides the eighteenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, wherein the seventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are shared ground pins; wherein the eighth ground pin of the first basic graphic unit and the fourteenth ground pin of the second basic graphic unit are shared ground pins.

[0035] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides a nineteenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, wherein the twelfth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are a common ground pin; wherein the eleventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are a common ground pin; wherein the tenth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are a common ground pin; wherein the ninth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are a common ground pin.

[0036] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides a twentieth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, wherein the eleventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are shared ground pins; wherein the tenth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are shared ground pins; wherein the ninth ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are shared ground pins; wherein the eighth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are shared ground pins.

[0037] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides the twenty-first implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics; wherein, the fifth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are shared ground pins; wherein, the sixth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are shared ground pins; wherein, the seventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are shared ground pins; wherein, the eighth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are shared ground pins.

[0038] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, or the ninth embodiment of the first aspect, or the tenth embodiment of the first aspect, or the eleventh embodiment of the first aspect, or the twelfth embodiment of the first aspect, or the thirteenth embodiment of the first aspect, or the fourteenth embodiment of the first aspect, or the fifteenth embodiment of the first aspect, or the sixteenth embodiment of the first aspect, or the seventeenth embodiment of the first aspect, or the eighteenth embodiment of the first aspect, or the nineteenth embodiment of the first aspect Method, or the twentieth embodiment of the first aspect, or the twenty-first embodiment of the first aspect, the embodiment of the present application also provides a twenty-second embodiment of the first aspect: for a basic graphic unit including six signal pins, its first pin, fourth pin, fifth pin and sixth pin are single-ended signal pins for transmitting DQ data signals; its second pin and third pin are differential signal pins for transmitting DQS signals, so that when the two control signal pins transmit the DQS differential clock signal, the polarity of the differential signal pair is opposite during transmission, that is, the amplitudes of the signals transmitted on the two pins of the differential signal pair are opposite, thereby, the interference to the two single-ended signal pins adjacent to it above and below in the second direction can be completely offset, and the crosstalk to the two single-ended signal pins on the left and right of the first direction can be partially offset, thereby reducing the total crosstalk amount suffered by the single-ended signal.

[0039] In practical applications, such as in X8 scenarios, differential signal pins can be configured to multiplex DM signal channels to transmit DM signals, providing shielding and selective writing of each data bit. When control signal pins are used to transmit DM signals, the actual electromagnetic crosstalk generated is low and will not affect data transmission on the data signal pins.

[0040] Based on the first aspect, the present application also provides a twenty-third implementation of the first aspect: the chip may be a central processing unit, wherein the central processing unit is configured with multiple memory channels. Specifically, the memory channels include multiple byte units, each of which corresponds to two of at least some basic graphics units, and the data signal pins in the basic graphics units are used to transmit data signals for the corresponding byte units. As a result, by effectively reducing electromagnetic crosstalk between the pins, higher data transmission speeds and higher access efficiency can be achieved.

[0041] A second aspect of an embodiment of the present application provides an electronic device, including a housing and a circuit board arranged in the housing, on which a chip is arranged; the chip adopts the chip described above, and the signal pins of the chip are electrically connected to the circuit board.

[0042] In practical applications, the electronic device may be a computing device such as a server, a supercomputer, or an Ethernet switch, or a terminal device such as a mobile phone, a learning machine, or a laptop computer.

[0043] A third aspect of an embodiment of the present application provides a chip manufacturing method, wherein a chip is disposed on a packaging substrate and the chip and the packaging substrate are assembled together to form the chip. Specifically, a plurality of pin arrangement pattern units are disposed in a pin region of the packaging substrate, and at least two of the plurality of pin arrangement pattern units are basic pattern units including six signal pins. A first pin, a second pin, a third pin, and a fourth pin of the six signal pins of the basic pattern unit are sequentially spaced apart in a first direction, and a fifth pin and a sixth pin of the six signal pins are spaced apart in a second direction, the first direction being different from the second direction, and the fifth pin and the sixth pin are respectively located on either side of a line connecting the second pin and the third pin. The first pin, the fourth pin, the fifth pin, and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins. The method comprises the following steps: transmitting a data signal through the first pin, the fourth pin, the fifth pin, and the sixth pin, and transmitting a control signal through the second pin and the third pin. Based on the cross-shaped arrangement of basic graphic units, the chip ensures correct signal transmission through excellent anti-crosstalk performance, thus providing technical support for high-performance and reliable system applications.

[0044] Based on the third aspect, the embodiment of the present application also provides a first implementation method of the third aspect: the fifth pin and the sixth pin are arranged on a perpendicular line of the line connecting the second pin and the third pin, where the first direction is perpendicular to the second direction.

[0045] Based on the first implementation of the third aspect, the embodiment of the present application also provides a second implementation of the third aspect: the fifth pin and the sixth pin are arranged on the perpendicular bisector of the line connecting the second pin and the third pin, and the basic graphic unit adopts a centrally symmetrical structure and can also adopt an axially symmetrical structure.

[0046] Based on the third aspect, or the first embodiment of the third aspect, or the second embodiment of the third aspect, the present application further provides a third embodiment of the third aspect: the pins in the pin region of the package substrate are arranged in a triangular grid. Specifically, the line connecting a pin and two adjacent pins forms an equilateral triangle. This further enables a closely alternating arrangement of the cross-shaped pattern units, thereby increasing the pin arrangement density.

[0047] Based on the third implementation of the third aspect, the present application also provides a fourth implementation of the third aspect: two basic graphic units are arranged adjacent to each other, one of the two basic graphic units is a first basic graphic unit, and the other of the two basic graphic units is a second basic graphic unit, and the adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin. In other words, the ground pins on the adjacent sides of the two basic graphic units are shared. In this way, in addition to effectively reducing electromagnetic crosstalk, the pin layout density is more compact and reasonable.

[0048] Based on the fourth implementation of the third aspect, the embodiment of the present application also provides a fifth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are translated graphics of each other, and the translation can be a translation in the first direction. The first basic graphic unit and the second basic graphic have a common ground pin, and the common ground pin is located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0049] Based on the fourth implementation of the third aspect, the embodiment of the present application also provides a sixth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in the second direction. The first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the sixth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0050] Based on the fourth implementation of the third aspect, the embodiment of the present application also provides a seventh implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0051] Based on the fourth implementation of the third aspect, the embodiment of the present application also provides an eighth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence at intervals, wherein two common ground pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit, and the other two common ground pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0052] Based on the fourth implementation of the third aspect, the embodiment of the present application also provides a ninth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence at intervals, wherein two common ground pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit, and the other two common ground pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0053] Based on the fourth implementation of the third aspect, the embodiment of the present application also provides a tenth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, and the first basic graphic unit and the second basic graphics have four common ground pins; the four common ground pins are arranged in sequence at intervals, two of which are adjacent to the fifth pin of the first basic graphic unit, and the other two common ground pins are adjacent to the fourth pin of the first basic graphic unit.

[0054] A fourth aspect of an embodiment of the present application provides a signal transmission method, which is applied to a chip. Specifically, the chip includes a packaging substrate, wherein a plurality of pin arrangement pattern units are provided in a pin region of the packaging substrate, and at least two of the plurality of pin arrangement pattern units are basic pattern units including six signal pins. A first pin, a second pin, a third pin, and a fourth pin of the six signal pins of the basic pattern unit are sequentially spaced apart in a first direction, and a fifth pin and a sixth pin of the six signal pins are spaced apart in a second direction, the first direction being different from the second direction, and the fifth pin and the sixth pin are respectively located on opposite sides of a line connecting the second pin and the third pin. The first pin, the fourth pin, the fifth pin, and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins. The method comprises the following steps: transmitting a data signal via the first pin, the fourth pin, the fifth pin, and the sixth pin, and transmitting a control signal via the second pin and the third pin. Based on the cross-shaped arrangement of basic graphic units, the chip ensures correct signal transmission through excellent anti-crosstalk performance, thus providing technical support for high-performance and reliable system applications.

[0055] Based on the fourth aspect, the embodiment of the present application also provides a first implementation method of the fourth aspect: the fifth pin and the sixth pin are arranged on a perpendicular line of the line connecting the second pin and the third pin, where the first direction is perpendicular to the second direction.

[0056] Based on the first implementation of the fourth aspect, the embodiment of the present application also provides a second implementation of the fourth aspect: the fifth pin and the sixth pin are arranged on the perpendicular bisector of the line connecting the second pin and the third pin, and the basic graphic unit adopts a centrally symmetrical structure and can also adopt an axially symmetrical structure.

[0057] Based on the fourth aspect, or the first embodiment of the fourth aspect, or the second embodiment of the fourth aspect, the present application also provides a third embodiment of the fourth aspect: the pins in the pin region of the package substrate are arranged in a triangular grid. Specifically, the line connecting a pin and two adjacent pins forms an equilateral triangle. This further enables a closely alternating arrangement of the cross-shaped pattern units, thereby increasing the pin arrangement density.

[0058] Based on the third implementation of the fourth aspect, the present application also provides a fourth implementation of the fourth aspect: two basic graphic units are arranged adjacent to each other, one of the two basic graphic units is a first basic graphic unit, and the other of the two basic graphic units is a second basic graphic unit, and the adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin. In other words, the ground pins on the adjacent sides of the two basic graphic units are shared. In this way, in addition to effectively reducing electromagnetic crosstalk, the pin layout density is more compact and reasonable.

[0059] Based on the fourth implementation of the fourth aspect, the embodiment of the present application also provides a fifth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are translated graphics of each other, and the translation can be a translation in the first direction. The first basic graphic unit and the second basic graphic have a common ground pin, and the common ground pin is located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0060] Based on the fourth implementation of the fourth aspect, the embodiment of the present application also provides a sixth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in the second direction. The first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the sixth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0061] Based on the fourth implementation of the fourth aspect, the embodiment of the present application also provides a seventh implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0062] Based on the fourth implementation of the fourth aspect, the embodiment of the present application also provides an eighth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence at intervals, wherein two common ground pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit, and the other two common ground pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0063] Based on the fourth implementation of the fourth aspect, the embodiment of the present application also provides a ninth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence at intervals, wherein two common ground pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit, and the other two common ground pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0064] Based on the fourth implementation of the fourth aspect, the embodiment of the present application also provides a tenth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, and the first basic graphic unit and the second basic graphics have four common ground pins; the four common ground pins are arranged in sequence at intervals, two of which are adjacent to the fifth pin of the first basic graphic unit, and the other two common ground pins are adjacent to the fourth pin of the first basic graphic unit.

[0065] A fifth aspect of an embodiment of the present application provides a method for a CPU to read and send data, the CPU comprising a packaging substrate, a pin area of ​​the packaging substrate comprising a data signal pin and a data strobe signal pin, and the data signal pin and the data strobe signal pin are arranged according to a pin arrangement graphic unit, the pin arrangement graphic unit comprising six signal pins, a first pin, a fourth pin, a fifth pin and a sixth pin of the six signal pins being data signal pins, and a second pin and a third pin of the six signal pins being data strobe signal pins; wherein the first pin, the second pin, the third pin and the fourth pin are arranged in a first direction according to The fifth pin and the sixth pin are arranged at intervals in the second direction, the fifth pin and the sixth pin are arranged on a vertical line connecting the second pin and the third pin, and are respectively located on both sides of the second pin and the third pin; the method for the CPU to read and send data includes the following steps: responding to a write instruction or a read instruction of a DDR signal; sending data to the DDR memory through the data signal pin according to the write instruction, and outputting a data selection signal through the data selection signal pin; or receiving data from the DDR memory through the data signal pin according to the read instruction, and reading the data selection signal through the data selection signal pin.

[0066] A sixth aspect of an embodiment of the present application provides a method for a CPU to read data, the CPU comprising a packaging substrate, a pin area of ​​the packaging substrate comprising a data signal pin and a data strobe signal pin, and the data signal pin and the data strobe signal pin are arranged according to a pin arrangement graphic unit, the pin arrangement graphic unit comprising six signal pins, the first pin, the fourth pin, the fifth pin and the sixth pin of the six signal pins being data signal pins, the second pin and the third pin of the six signal pins being data strobe signal pins; wherein the first pin, the second pin, the third pin and the fourth pin are arranged in sequence in a first direction, and the fifth pin and the sixth pin are arranged in sequence in a second direction. The fifth and sixth pins are arranged at intervals, and are configured on a vertical line connecting the second pin and the third pin, and are respectively located on both sides of the second pin and the third pin; the method for reading data from the CPU includes the following steps: responding to a write instruction of a DDR signal. In a specific implementation, when the CPU or other device needs to read data in the memory, the memory controller sends a read command to the memory module and specifies the address to be read; sending data to the DDR memory through the data signal pin according to the write instruction, and outputting a data select signal through the data select signal pin, that is, providing a data clock signal to the DDR memory, so that the DDR memory can correctly receive and parse the data sent by the CPU.

[0067] A seventh aspect of an embodiment of the present application provides a method for a CPU to send data, the CPU including a packaging substrate, a pin area of ​​the packaging substrate including a data signal pin and a data strobe signal pin, and the data signal pin and the data strobe signal pin are arranged according to a pin arrangement graphic unit, the pin arrangement graphic unit including six signal pins, a first pin, a fourth pin, a fifth pin, and a sixth pin of the six signal pins are data signal pins, and a second pin and a third pin of the six signal pins are data strobe signal pins; wherein the first pin, the second pin, the third pin, and the fourth pin are arranged in sequence in a first direction, and the fifth pin and the sixth pin are arranged in sequence in a second direction. , the fifth pin and the sixth pin are configured on a vertical line connecting the second pin and the third pin, and are respectively located on both sides of the second pin and the third pin; the method for the CPU to read and send data includes the following steps: responding to a read instruction of a DDR signal. In a specific implementation, when the CPU or other device needs to write data to the memory, the memory controller sends a write command to the memory module and provides the data to be written and the target address; receiving data from the DDR memory through the data signal pin according to the read instruction, and reading the data select signal through the data select signal pin, that is, providing a data clock signal to the CPU so that the CPU can correctly sample and parse the data transmitted from the DDR memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] FIG1 is a schematic diagram of a partial structure of an electronic device provided in an embodiment of the present application;

[0069] FIG2 is a schematic diagram of a pin arrangement of a packaging substrate provided in an embodiment of the present application;

[0070] FIG3 is a schematic diagram of the arrangement structure of the pin area of ​​the package substrate provided in an embodiment of the present application;

[0071] FIG4 is a schematic diagram of the construction relationship of basic graphic units provided in an embodiment of the present application;

[0072] FIG5 is a schematic diagram of a combination method of basic graphic units provided in an embodiment of the present application;

[0073] 6 to 10 are schematic diagrams of combinations of five other basic graphic units provided in embodiments of the present application;

[0074] FIG11 is a schematic diagram of the hardware architecture of a CPU DDR interface provided in an embodiment of the present application;

[0075] FIG12 is a schematic diagram showing the relationship between the CPU DDR interface and the basic graphics unit provided in an embodiment of the present application;

[0076] FIG13 is a schematic diagram of two other combinations of multiple basic graphic units provided in an embodiment of the present application;

[0077] FIG14 is a flow chart of a method for a CPU to read and send data provided by an embodiment of the present application;

[0078] FIG15 is a schematic diagram of pin configuration in a CPU application scenario provided by an embodiment of the present application;

[0079] FIG16 is a schematic diagram of pin configuration in another CPU application scenario provided by an embodiment of the present application;

[0080] FIG17 is a schematic diagram of pin configuration in another CPU application scenario provided by an embodiment of the present application;

[0081] FIG18 is a schematic diagram of the architecture of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0082] The embodiment of the present application provides a chip packaging substrate pin arrangement solution, which can effectively reduce crosstalk between pins on the basis of reasonably controlling the package size by increasing the pin arrangement density.

[0083] Please refer to Figure 1, which is a partial structural diagram of an electronic device provided in an embodiment of the present application. The electronic device 100 includes a circuit board 10 and a chip 20 disposed on the circuit board 10. In a specific implementation, the electronic device can be a communication terminal device, a server, a supercomputer, a router, a switch, or other device.

[0084] The chip 20 may include a package substrate 1 and a core 2. The package substrate 1 is a carrier for encapsulating the core 2 and is encapsulated by a housing 3. Here, the core (Chip) refers to the die formed by processing and cutting the wafer. The package substrate (Package substrate) is the carrier for encapsulating the semiconductor chip, and the external pins of the semiconductor package are formed on the package substrate. The current development direction of the package substrate is to achieve multi-pin, reduce the size of the packaged product, realize high-density design of the package pins, and improve the electrical performance of the physical interface.

[0085] During semiconductor die packaging, the die 2 can be placed on a packaging substrate 1, with the upper surface of the packaging substrate 1 serving as the die placement area. Specifically, during the manufacturing process of the chip 20, the die can be packaged through a packaging process to form a semiconductor package (i.e., a chip product) that provides protection, thermal management, mechanical support, and electrical connections.

[0086] Specifically, when manufacturing a semiconductor package, a chip is typically placed on a packaging substrate. The chip's pins are then electrically connected to the substrate's solder balls or pads through methods such as gold wire bonding, flip-chip bonding, or tape automated bonding. The chip and packaging substrate are then packaged together to form a semiconductor package, typically a different chip product. The chip's external pins can then be electrically connected to the PCB, thereby connecting the chip to external circuits. The chip can also be electrically connected to other devices via PCB traces.

[0087] As shown in Figure 1, the pins on the chip 2 are connected to the solder balls or pads of the package substrate 1 through flip-chip technology. In other specific implementations, the pins on the chip 2 can also be connected to the solder balls or pads of the package substrate 1 through gold wire bonding technology, which is not limited in this embodiment of the application.

[0088] A packaging filler 4 can also be provided between the packaging substrate 1 and the shell 3. On the one hand, the packaging filler 4 can be used to wrap the core particle 2 to reduce the adverse effects of external dust, impurities, etc. on the performance of the core particle 2. On the other hand, the packaging substrate 1, the shell 3 and the core particle 2 and other components can be coupled into one to improve the structural strength of the chip 20.

[0089] The external pins of the chip 20 are located on the package substrate 1, the lower surface of which serves as the pin area. Accordingly, a pin interface for connecting to the chip 20 can be provided on the circuit board 10. The signal pins 11 on the package substrate 1 can be solder balls, as shown in the figure. These pins are electrically connected to corresponding pads on the circuit board 10 through soldering. The conductors on the circuit board 10 connect the chip 2 to other devices, thereby connecting the chip 2 to external circuits.

[0090] It is understood that signal pins are used to establish signal transmission and data exchange between chips. Signal pins include data signal pins and control signal pins, which can be applied to different parallel bus transmission modes to transmit large amounts of data and control signals. Specifically, data signal pins are used to transmit DQ (Data Input / Output) signals to transmit data bit or byte information. Specifically, control signal pins can transmit corresponding control signals according to different application scenarios. For example, but not limited to, based on the DDR bus protocol, control signal pins can be used to transmit DQS (Data Strobe) signals to indicate the data sampling time; control signal pins can also be used to transmit DM (Input Data Mask) signals to indicate the validity of each data signal bit (DQ), enabling masking and selective writing of each data bit; or, based on the ONFI (Open NAND Flash Interface) bus protocol for flash (flash memory), these control signal pins are used to transmit signals that control data transmission to enable data transmission and communication between the flash controller and the flash chip.

[0091] In a specific implementation, the signal pins on the chip 20 can also be metal contact points located on the package substrate 1, and metal springs are correspondingly provided on the circuit board 10. The metal contact points on the chip 20 side are provided in a one-to-one correspondence with the metal springs on the circuit board 10 side (not shown in the figure); after the chip 20 is fixed to the mounting position on the circuit board 10, the metal contact points press against the metal springs, and the deformed metal springs maintain reliable contact with the corresponding metal contact points to achieve electrical connection of the corresponding pins. It is understandable that the specific connection structure between the external pins of the chip 20 and the circuit board 10 can be configured according to the actual application scenario and is not limited in the embodiments of this application.

[0092] Typically, an important indicator for measuring the performance of chip packaging technology is the ratio of chip area (bare die area) to package area. When the area of ​​the core 2 is constant, the smaller the ratio, the larger the package area, that is, the larger the size of the chip 20, which will lead to a decrease in the manufacturing yield of the chip 20 and increase the production cost. The closer the ratio is to 1, the smaller the package area, thus increasing the manufacturing yield of the chip 20 and reducing the production cost accordingly. For the packaging substrate 1, the pin arrangement density of the packaging substrate 1 is an important factor affecting the packaging area. However, an increase in the pin arrangement density of the packaging substrate 1 will lead to electromagnetic crosstalk between the pins, affecting the performance of the chip product.

[0093] In addition, in order to reduce electromagnetic crosstalk between pins, ground pins are set around the pins of the chip package substrate, and ground connections are provided through the ground pins. Specifically, in the pinmap of the chip, based on the arrangement of the ground pins, a low-impedance ground path can be provided to form a uniform ground potential, which can guide the energy of the electromagnetic field to the ground plane, thereby reducing electromagnetic crosstalk (also known as mutual interference) between signal pins, helping to maintain signal integrity and reduce noise. However, the setting of the ground pin will increase the chip size, so it is necessary to further increase the pin arrangement density to reduce the package area.

[0094] Based on this, an embodiment of the present application provides a Pinmap pin layout solution. Please refer to Figure 2, which is a schematic diagram of a pin layout on a package substrate provided in an embodiment of the present application. For ease of description, two layout directions of the pin area of ​​package substrate 1 are defined herein: the first direction X represents the left-right arrangement direction of the pins shown in the figure, and the second direction Y represents the up-down arrangement direction of the pins shown in the figure. It should be understood that the use of the above-mentioned directional terms does not constitute a substantial limitation on the technical solution described in this application.

[0095] The pin area on the package substrate 1 is provided with a plurality of pinmap patterns. As shown in FIG2 , the pinmap pattern is a basic pattern unit P including six signal pins 11. Among the six signal pins 11, a first pin 111, a second pin 112, a third pin 113, and a fourth pin 114 are sequentially spaced apart in a first direction X. A fifth pin 115 and a sixth pin 116 are spaced apart in a second direction Y. The fifth pin 115 and the sixth pin 116 are disposed on a perpendicular midline L2 of a line L1 connecting the second pin 112 and the third pin 113, and are located on either side of the line L1 connecting the second pin 112 and the third pin 113, respectively. Among them, the first pin 111, the fourth pin 114, the fifth pin 115 and the sixth pin 116 are data signal pins a (pins shown as solid filled in the figure), and the second pin 111 and the third pin 113 are control signal pins b (pins shown as diagonal filled in the figure).

[0096] Overall, the pins of this Pinmap Pattern are arranged in a cross-shaped graphic unit, with the four data signal pins a placed at the four protruding ends of the cross-shaped graphic unit, and the control signal pin b placed in the center of the cross-shaped graphic unit. This allows the data signal pins a to be spaced apart from each other, and each data signal pin a has no adjacent data signal pins a that could form a crosstalk source, effectively avoiding the effects of electromagnetic crosstalk between adjacent data signal pins a. Based on this Pinmap solution, on the one hand, electromagnetic crosstalk between pins is effectively reduced, which can support higher parallel bus operating rates, such as but not limited to the DDR bus or the flash ONFI bus, for high-speed transmission of data and control signals. On the other hand, it can increase the density of the pin arrangement, save packaging area, and provide technical support for further improving product yield and reducing processing costs.

[0097] Here, in Figure 2 and the following figures, the dotted lines connecting the signal pins 11 are only used to illustrate the positional relationship of the pins, and the dotted lines surrounding the periphery of the signal pins 11 are only used to illustrate the arrangement area of ​​the basic graphic unit P. The corresponding dotted lines do not exist in the structure of the packaging substrate and do not constitute a limitation on the specific structure of the packaging substrate.

[0098] In other specific implementations, the multiple pin arrangement graphic units in the pin area of ​​the packaging substrate 1 can be configured as different pin arrangements according to actual functional requirements; for example, for a CPU chip, the multiple pin arrangement graphic units in its pin area can have a part of the basic graphic units P configured as the cross-shaped arrangement graphic units shown in the figure, so as to build a parallel bus channel; while another part of the pin arrangement graphic units can be configured to include graphic units with other arrangements (not shown in the figure) to achieve electrical connection with the corresponding external circuit; that is, the pin arrangement of the pin area of ​​the packaging substrate 1 can be obtained by combining and arranging several types of graphic units, rather than being limited to the situation where all the graphic units are configured as the cross-shaped arrangement as shown in FIG.

[0099] In this embodiment, the fifth pin 115 and the sixth pin 116 are arranged on the perpendicular bisector of the line connecting the second pin 112 and the third pin 113, that is, the distances from the second pin 112 and the third pin 113 to the line connecting the fifth pin 115 and the sixth pin 116 are equal, and the cross-shaped graphic unit is a centrally symmetrical structure.

[0100] In a specific implementation, the distances from the second pin 112 and the third pin 113 to the line connecting the fifth pin 115 and the sixth pin 116 can vary (not shown in the figure). In other words, the fifth pin 115 and the sixth pin 116 can be located on either side of the line connecting the second pin 112 and the third pin 113, which can still achieve a solution in which no adjacent data signal pins form a source of crosstalk. In addition, in other specific implementations, the line connecting the fifth pin 115 and the sixth pin 116 can intersect the line connecting the second pin 112 and the third pin 113 at other angles (not shown in the figure).

[0101] In comparison, the implementation method in which the fifth pin 115 and the sixth pin 116 are arranged on the perpendicular midline of the line connecting the second pin 112 and the third pin 113 can maximize the arrangement density of the pin area on the basis of effectively reducing the influence of electromagnetic crosstalk. Please also refer to Figure 3, which is a schematic diagram of the arrangement structure of the pin area of ​​the packaging substrate provided in an embodiment of the present application. As shown in Figure 3, the pins in the pin area of ​​the packaging substrate 1 are arranged in an array, and the pins between rows and columns are staggered. The staggered arrangement of the pins between rows and columns means that the pins in each row (X1~X15) and the pins in each column (Y1~Y9) are staggered with each other, and as many pins as possible can be arranged in a limited layout space. In other words, the pins in the pin area are arranged in a triangular grid, and the line connecting each pin and its two adjacent pins forms an equilateral triangle. In this way, the tight alternating arrangement of the cross-shaped arrangement graphic units can be achieved, thereby improving the pin arrangement density.

[0102] It should be noted that, for each pin in the pin area of ​​the packaging substrate 1, the pin and the other two adjacent pins are arranged in an equilateral triangle, including an equilateral triangle arrangement relationship with good shape and position tolerance control, and also includes a triangle arrangement relationship with dimensional tolerance affected by the processing accuracy. In other words, it also includes a situation where there is a certain deviation within the range of process accuracy limitations, and the pin is arranged in a roughly equilateral triangle that is not completely equilateral.

[0103] Furthermore, a ground (GND) pin can be provided around the six signal pins 11 of the cross-shaped graphic unit. Please also refer to FIG4 , which is a schematic diagram of the construction relationship of the basic graphic unit provided in an embodiment of the present application.

[0104] As shown in the figure, corresponding to the six signal pins 11 of the cross-shaped graphic unit, the basic graphic unit P is provided with fourteen ground pins 12 (pins c shown as single-line circles in the figure), with two control signal pins b as the center, and four data signal pins a are arranged at the upper, lower, left and right positions closest to the two control signal pins b, respectively. Finally, ground pins c are arranged on the periphery to form a return ground around each signal pin 11, thereby reducing electromagnetic interference with other pins.

[0105] As shown in FIG4 , the fourteen ground pins 12 surround the six signal pins 11 and are arranged in a spaced-apart pattern to form a tetradecagon. In the first direction X, the first ground pin 1201 is located next to the first pin 111, the eighth ground pin 1208 is located next to the fourth pin 114, and the second ground pin 1202, the third ground pin 1203, the fourth ground pin 1204, the fifth ground pin 1205, the sixth ground pin 1206, and the seventh ground pin 1207 are sequentially arranged between the first ground pin 1201 and the eighth ground pin 1208. The ninth ground pin 1209, the tenth ground pin 1210, the eleventh ground pin 1211, the twelfth ground pin 1212, the thirteenth ground pin 1213, and the fourteenth ground pin 1214 are sequentially arranged between the eighth ground pin 1208 and the first ground pin 1201.

[0106] The data signal pins a adjacent to two adjacent ground pins 12 and the line connecting the two adjacent ground pins 12 form an equilateral triangle S. Each data signal pin a is located on the perpendicular midline of the line connecting its two adjacent ground pins 12. To simplify the diagram, the first pin 111 is used as an example to illustrate its relative positional relationship with the two adjacent ground pins 12. This fully utilizes the pin area space where pins are staggered between rows and columns. A Pinmap unit is constructed according to the alternating arrangement rule, and the distance between any two adjacent pins is consistent. While providing a return ground function, it can also increase pin layout density and achieve a high signal-to-ground ratio. The "signal-to-ground ratio" here refers to the ratio of the number of signal pins 11 to the number of ground pins 12 per unit area. It is understood that in other specific implementations, the number of ground pins 12 can be determined as needed, and this embodiment of the present application does not limit this.

[0107] In a specific implementation, a basic graphics unit P can correspond to a nibbel (half-byte) signal pin. The data of each nibbel can be transmitted using four DQ data signals and a pair of DQS differential clock signals. Among them, the four data signal pins a of the six signal pins 11 are single-ended signal pins for transmitting DQ data signals; the two control signal pins b of the six signal pins 11 are differential signal pins for transmitting DQS signals.

[0108] When the two control signal pins (second pin 112 and third pin 113) transmit DQS differential clock signals, the polarity of the differential signal pair is opposite during transmission, meaning the amplitudes of the signals transmitted on the two pins of the differential signal pair are opposite. As a result, the interference in the second direction Y and its two upper and lower adjacent single-ended signal pins (fifth pin 115 and sixth pin 116) can be completely canceled out, and the crosstalk in the first direction X and its left and right single-ended signal pins (first pin 111 and fourth pin 114) can be partially canceled out, thereby reducing the total crosstalk experienced by the single-ended signal.

[0109] In DDR systems, based on the definition of DDR signals, data signals are typically divided into bytes. Each byte is transmitted using four DQ data signals and a pair of DQS differential clock signals. Based on the aforementioned basic graphic unit P, a combination of two basic graphic units P can be used to transmit a single byte of data. In other words, when designing a DDR Pinmap, a byte is typically used as the basic unit for layout.

[0110] Please refer to Figure 5, which is a schematic diagram of a basic graphic unit P combination method provided in an embodiment of the present application. The figure shows a combined unit formed by splicing two basic graphic units P, which can transmit data per byte. Based on the basic graphic unit P described in Figure 4, this combined unit is composed of two basic graphic units P spliced ​​together to form a pin arrangement combined unit corresponding to a byte unit. The adjacent sides of the first basic graphic unit P1 and the second basic graphic unit P2 share a ground pin.

[0111] As shown in Figure 5, the first basic graphical unit P1 and the second basic graphical unit P2 are mutually translated. That is, one of the two basic graphical units P is formed by translation relative to the other. The fifth pin 115 of the first basic graphical unit P1 is arranged in the same direction as the first pin 111, second pin 112, third pin 113, and fourth pin 114 of the second basic graphical unit P2. The first pin 111, second pin 112, third pin 113, and fourth pin 114 of the first basic graphical unit P1 are arranged in the same direction as the sixth pin 116 of the second basic graphical unit P2.

[0112] In this implementation, the first basic graphics unit P1 and the second basic graphics unit P2 share two ground pins 12, and these two shared ground pins 12 are located between the fourth pin 114 of the first basic graphics unit P1 and the first pin 111 of the second basic graphics unit P2. Specifically, the seventh ground pin 1207 of the first basic graphics unit P1 and the first ground pin 1201 of the second basic graphics unit P2 share a common ground pin, and the eighth ground pin 1208 of the first basic graphics unit P1 and the fourteenth ground pin 1214 of the second basic graphics unit P2 share a common ground pin. This effectively reduces electromagnetic crosstalk and achieves a more compact and reasonable pin layout density.

[0113] In a specific implementation, the eight data signal pins a of the two basic graphic units P can correspond to the eight data pins on the data bus: DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6 and DQ7, which respectively send or receive data from data bit 0 to data bit 7; the four control signal pins of the two basic graphic units P correspond to the four data clock signal pins on the data bus: DQS0, DQS1, DQS2 and DQS3, where DQS0 and DQS1 are a pair of differential pair pins, and DQS2 and DQS3 are a pair of differential pair pins, which are respectively used to time and synchronize data during data transmission.

[0114] Based on the staggered arrangement of pins between rows and columns in the pin area of ​​the package substrate 1, different pin arrangement combination units can be formed by translation or rotational translation followed by splicing. Please refer to Figures 6 to 10, which respectively illustrate five different basic graphic unit combinations. In the assembled units shown in Figures 6, 7, 8, and 10, one of the two basic graphic units P is formed by translation relative to the other. In the assembled unit shown in Figure 9, one of the two basic graphic units P is formed by rotation and translation relative to the other.

[0115] As shown in FIG6 , the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated graphics, wherein the fifth pin 115 and the sixth pin 116 of the first basic graphic unit P1 are arranged in the same direction as the fifth pin 115 and the sixth pin 116 of the second basic graphic unit P1.

[0116] In this implementation, two basic graphical units share two spaced-apart ground pins 12. These two shared ground pins 12 are located between the sixth pin 116 of the first basic graphical unit P1 and the fifth pin 115 of the second basic graphical unit P2. Specifically, the twelfth ground pin 1212 of the first basic graphical unit P1 and the fourth ground pin 1204 of the second basic graphical unit P2 share a common ground pin, while the eleventh ground pin 1211 of the first basic graphical unit P1 and the fifth ground pin 1205 of the second basic graphical unit P2 share a common ground pin.

[0117] As shown in Figure 7, the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated graphics, wherein the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the first basic graphic unit P1 are arranged in the same direction as the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the second basic graphic unit P2.

[0118] In this implementation, two basic graphic units share a ground pin 12, which is located between the fourth pin 114 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2. Specifically, the eighth ground pin 1208 of the first basic graphic unit P1 and the first ground pin 1201 of the second basic graphic unit P2 are shared ground pins.

[0119] As shown in Figure 8, the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated graphics, wherein the fifth pin 115 and the sixth pin 116 of the first basic graphic unit P1 are arranged in the same direction as the first pin 111 of the second basic graphic unit P2; the fourth pin 114 of the first basic graphic unit P1 is arranged in the same direction as the fifth pin 115 and the sixth pin 116 of the second basic graphic unit P2.

[0120] In this implementation, two basic graphical units share four ground pins 12 spaced apart from each other. Two of the shared ground pins 12 are located between the sixth pin 116 of the first basic graphical unit P1 and the first pin 111 of the second basic graphical unit P2, and the other two are located between the fourth pin 114 of the first basic graphical unit P1 and the fifth pin 115 of the second basic graphical unit P2. Specifically, the twelfth ground pin 1212 of the first basic graphical unit P1 and the second ground pin 1202 of the second basic graphical unit P2 share a ground pin; the eleventh ground pin 1211 of the first basic graphical unit P1 and the third ground pin 1203 of the second basic graphical unit P2 share a ground pin; the tenth ground pin 1210 of the first basic graphical unit P1 and the fourth ground pin 1204 of the second basic graphical unit P2 share a ground pin; and the ninth ground pin 1209 of the first basic graphical unit P1 and the fifth ground pin 1205 of the second basic graphical unit P2 share a ground pin.

[0121] As shown in Figure 9, the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated and rotated graphics, wherein the first pin 111 and the fifth pin 115 of the first basic graphic unit P1 are arranged in the same direction as the fifth pin 115 and the sixth pin 116 of the second basic graphic unit P2; the sixth pin 116 and the fourth pin 114 of the first basic graphic unit P1 are arranged in the same direction as the first pin 111 of the second basic graphic unit P2.

[0122] In this implementation, the two basic graphic units share four ground pins 12 that are spaced apart in sequence, wherein two of the shared ground pins 12 are located between the fifth pin 115 of the first basic graphic unit P1 and the fifth pin 115 of the second basic graphic unit P2, and the other two shared ground pins 12 are located between the fourth pin 114 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2. Specifically, the fifth ground pin 1205 of the first basic graphic unit P1 and the fifth ground pin 1205 of the second basic graphic unit P2 are a common ground pin, the sixth ground pin 1206 of the first basic graphic unit P1 and the fourth ground pin 1204 of the second basic graphic unit P2 are a common ground pin, the seventh ground pin 1207 of the first basic graphic unit P1 and the third ground pin 1203 of the second basic graphic unit P2 are a common ground pin, and the eighth ground pin 1208 of the first basic graphic unit P1 and the second ground pin 1202 of the second basic graphic unit P2 are a common ground pin.

[0123] As shown in Figure 10, the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated graphics, wherein the fourth pin 114 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2 are arranged in the same direction; the sixth pin 116 of the first basic graphic unit P and the fifth pin 115 of the second basic graphic unit P2 are arranged in the same direction.

[0124] The two devices share four ground pins 12 spaced apart from each other. Two of the shared ground pins 12 are located between the sixth pin 116 of the first basic graphical unit P1 and the first pin 111 of the second basic graphical unit P2. The other two shared ground pins 12 are located between the fourth pin 114 of the first basic graphical unit P1 and the fifth pin 115 of the second basic graphical unit P2. Specifically, the eleventh ground pin 1211 of the first basic graphical unit P1 and the first ground pin 1201 of the second basic graphical unit P are shared ground pins; the tenth ground pin 1210 of the first basic graphical unit P and the second ground pin 1202 of the second basic graphical unit P2 are shared ground pins; the ninth ground pin 1209 of the first basic graphical unit P and the third ground pin 1203 of the second basic graphical unit P are shared ground pins; and the eighth ground pin 1208 of the first basic graphical unit P and the fourth ground pin 1204 of the second basic graphical unit P2 are shared ground pins.

[0125] It can be understood that the package substrate configured with the basic graphics unit P described in Figures 2, 3 and 4, and the package substrate configured with the pin arrangement combination unit described in Figures 5 to 10 can be used to match chips such as CPU (central processing unit), GPU (graphics processing unit) or NPU (neural-network processing units), that is, the pinmap formed on the pin area of ​​the package substrate described in the above embodiment based on the basic graphics unit P can be used for the DDR interface on the CPU chip, NPU chip or GPU chip. For the CPU chip, the DDR signal can be connected to the memory chip (DIMM) on the memory stick DIMM through the signal pin 11 and the PCB trace.

[0126] The following briefly describes how the pin arrangement on the aforementioned package substrate matches the CPU chip.

[0127] Please refer to Figure 11, which is a schematic diagram of the hardware architecture of the CPU DDR interface provided in an embodiment of the present application.

[0128] As shown in Figure 11 , the CPU chip 21 includes multiple memory channels (DDR channels) 22, each of which can drive a corresponding memory bank 30. Without loss of generality, Figure 11 illustrates a CPU chip 21 with eight memory channels 22. It should be understood that in other implementations, the number of channels in the CPU and the number of memory banks connected to each channel can be set based on actual needs. This can be achieved based on existing technologies and is not further described herein.

[0129] Each memory channel 22 may include multiple DDR byte units 23, each byte including two nibbles 24. The memory bandwidth of a memory channel 22 is generally 32 bits or 64 bits. It is understood that a memory channel 22 with a 32-bit bandwidth may be composed of four byte units 23, and a memory channel 22 with a 64-bit bandwidth may be composed of eight byte units 23. This is not limited in the present embodiment.

[0130] Please also refer to Figure 12, which is a schematic diagram of the relationship between the CPU DDR interface and the basic graphics unit P provided in an embodiment of the present application.

[0131] As shown in Figure 12, each Nibble 24 contains six data signals: four DQ data signals and a pair of DQS differential clock signals. Here, the six data signals of each Nibble 24 and its surrounding GND pins can be arranged in the cross-shaped pin arrangement unit P described in the previous embodiment. In other words, each Byte 23 contains twelve data signals: eight DQ data signals and two pairs of DQS differential clock signals. Accordingly, the twelve data signals of each Byte 23 and its surrounding GND pins can be arranged in the pinmap pattern unit described in Figures 5 to 10 of the previous embodiment.

[0132] In a specific implementation, the pins corresponding to all memory channels 22 of the CPU chip 21 can be arranged based on a Nibble to implement a combination of signal pins and their peripheral ground pins, forming a complete DDR Channel Pinmap (DDR channel pin layout pattern). This allows the memory channel 22 area of ​​the CPU chip 21 to achieve a high pin arrangement density and minimize electromagnetic crosstalk between signal pins, thereby ensuring stable signal transmission between the CPU 21 and the memory module 30. In a specific implementation, the memory module 30 can be a dual-inline-memory-module (DIMM), which is not limited in this embodiment of the present application.

[0133] Please refer to Figure 13, which is a schematic diagram of two combinations of multiple basic graphic units provided in an embodiment of the present application. In the combination shown in Figure 13 (a), each basic graphic unit P is spliced ​​together by translation. For two adjacent columns of basic graphic units P, the fourth pins of each basic graphic unit P in the left column and the first pins of each basic graphic unit P in the right column are arranged in sequence along the second direction. In the combination shown in Figure 13 (b), some basic graphic units P are spliced ​​together by translation, while other basic graphic units P are spliced ​​together by rotation and translation.

[0134] As shown in Figure 13, based on the staggered arrangement of pins between rows and columns in the pin area of ​​package substrate 1, and using the basic graphic units provided in the embodiments of the present application to form a DDR Channel Pinmap, each group of adjacent basic graphic units P can share peripheral ground pins, resulting in a more compact and reasonable overall pin layout density. By leveraging the structural characteristics of the cross-shaped pin arrangement graphic units, the data signal pins a of the DDR Channel Pinmap are distanced from each other, and each data signal pin a is free from adjacent crosstalk sources, effectively mitigating the impact of electromagnetic crosstalk between adjacent data signal pins a.

[0135] The CDU chip described in the preceding embodiments can be used in different generations of DDR systems to implement data storage and reading. For example, but not limited to, DDR4 SDRAM (4th generation double data rate synchronous dynamic random access memory) and DDR5 SDRAM (5th generation double data rate synchronous dynamic random access memory). Based on the different DDR chip data bus widths, DDR4 SDRAM includes two types: x8 and x16, and DDR5 SDRAM includes three types: x4, x8, and x16. X4 devices have a chip bit width of 4 bits, X8 devices have a chip bit width of 8 bits, and X16 devices have a chip bit width of 16 bits.

[0136] For the control signal pin b of the basic graphics unit P, it is usually defined as a DQS signal pin on the CDU chip side. In other specific implementations, such as in the X8 scenario, if DM signals need to be transmitted, the DQS0~DQS3 pins can be configured as channels for multiplexing DM signals. The DM signal is used to indicate the validity of each DQ data signal to provide shielding and selective writing of each data bit. In the write operation (WR OP), the CPU sends the DM signal to the DRAM at the same time as the DQ signal and the DQS signal. At this time, the DM signal is sampled together with the DQ signal at the rising / falling edge of the DQS clock signal. When the control signal pin is used to transmit the DM signal, the electromagnetic crosstalk actually generated by the DM being sampled as a low level is low and will not affect the data transmission of the DQ data signal pin.

[0137] It should be noted that the aforementioned cross-shaped basic graphic unit P can be applied to the chip packaging structure design for information connection with DDR memory. In addition to CPU chips, GPU chips or NPU chips, it can also be applied to other chips or connectors based on DDR interface. Through good anti-crosstalk performance, it ensures correct signal transmission and data reading and writing, thereby providing technical guarantee for high-performance and reliable DDR systems.

[0138] Of course, for other parallel bus scenarios, the Pinmap formed by the aforementioned cross-shaped basic graphic units P is used for the corresponding physical line interface, such as but not limited to parallel cameras, parallel external storage devices or parallel printers, etc., which are input and output devices that transmit data and control signals through a parallel bus.

[0139] Based on the hardware architecture of the CPU DDR interface shown in Figure 11, the embodiment of the present application further provides a method for a CPU to read and send data. Please refer to Figure 14, which is a flow chart of a method for a CPU to read and send data provided in the embodiment of the present application.

[0140] As shown in FIG14 , the method includes the following steps:

[0141] Step 101: responding to a write instruction or a read instruction of a DDR signal;

[0142] In a specific implementation, when the CPU or another device needs to read data from memory, the memory controller sends a read command to the memory module, specifying the address to read. When the CPU or another device needs to write data to memory, the memory controller sends a write command to the memory module, specifying the data to be written and the target address. The memory controller, part of the CPU or a separate chip on the motherboard, controls read and write operations on the memory module and handles memory access requests from the CPU or other devices.

[0143] Step 102: Send data to the DDR memory through the DQ pin according to the write instruction, and output a data strobe signal through the DQS pin, that is, provide a data clock signal to the DDR memory so that the DDR memory can correctly receive and analyze the data sent by the CPU; or receive data from the DDR memory through the DQ pin according to the read instruction, and read the data strobe signal through the DQS pin, that is, provide a data clock signal to the CPU so that the CPU can correctly sample and analyze the data transmitted from the DDR memory;

[0144] Specifically, during data transmission, the DQS pin and the corresponding DQ pin have a corresponding timing relationship, and data sampling and transmission occur on the edge (rising or falling edge) of the data clock signal. When sending data, the memory module writes the data to the storage unit at the specified address after receiving the command. When reading data, the memory module receives the command and transmits the requested data to the CPU via the data bus.

[0145] Among them, the DQ pin (data signal pin) and DQS pin (data select signal pin) of the CPU chip are arranged in a basic graphic unit, which includes six signal pins: a first pin 111, a second pin 112, a third pin 113, a fourth pin 114, a fifth pin 115 and a sixth pin 116. Among them, the first pin 111, the fourth pin 114, the fifth pin 115 and the sixth pin 116 are DQ pins (pins shown by solid circles in the figure), and the second pin 111 and the third pin 113 are DQS pins (pins shown by diagonal lines in the figure). The six signal pins are arranged in a cross pattern, wherein the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 are spaced apart in sequence in the first direction X. The fifth pin 115 and the sixth pin 116 of the six pins are spaced apart in the second direction Y. The fifth pin 115 and the sixth pin 116 are arranged on a perpendicular line connecting the second pin 112 and the third pin 113, and are located on either side of the second pin 112 and the third pin 113, respectively.

[0146] Taking the pin arrangement combination unit corresponding to a byte unit as an example, its eight data signal pins: DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6 and DQ7 are used to send or receive data from data bit 0 to data bit 7 respectively; its four data clock signal pins: DQS0, DQS1, DQS2 and DQS3, DQS0 and DQS1 are a pair of differential pair pins, DQS2 and DQS3 are a pair of differential pair pins, which are respectively used to time and synchronize data during data transmission.

[0147] Please refer to Figure 15, which is a schematic diagram of pin configuration in a CPU application scenario provided in an embodiment of the present application.

[0148] For the X4 granularity scenario, the pin configuration can be as shown in Figure 15. During write and read operations (WR OP / RD OP), the specific behaviors of each signal pin are as follows:

[0149] Write operation: The CPU sends the DQ signal and DQS signal to the DRAM. The DQS signal is aligned with the center of the DQ signal. On the DRAM side, the DQ signal is sampled at the rising and falling edges of the DQS clock signal and the sampled signal is stored in the DRAM.

[0150] Read operation: DRAM sends DQ and DQS signals to the CPU. The DQS signal is edge-aligned with the DQ signal. The CPU side first adjusts the phase relationship between the DQS and DQ signals so that the DQS and DQ signal centers are aligned. It then samples and transmits the sampled signal to the backend for processing.

[0151] Please refer to Figure 16, which is a schematic diagram of pin configuration in another CPU application scenario provided in an embodiment of the present application.

[0152] For the X8 granularity scenario, the pin configuration is as shown in Figure 16. During write and read operations (WR OP / RD OP), the RFU pin in the figure is a protection pin (Reserved for Future Use). The specific behaviors of other signal pins are as follows:

[0153] Write operation: The CPU sends the DQ, DM, and DQS signals to the DRAM. The DQS signal is center-aligned with the DQ and DM signals. On the DRAM side, the DQ and DM signals are sampled at the rising and falling edges of DQS and stored in the DRAM. It should be understood that when the DM signal is sampled low, the DQ signal sampled along with it is masked and not written to the DRAM.

[0154] Read operation: DRAM sends DQ and DQS signals to the CPU. The DQS signal is edge-aligned with the DQ signal. The CPU side first adjusts the phase relationship between DQS and DQ so that the DQS and DQ signal centers are aligned. Then it samples and transmits the sampled signal to the back-end for processing.

[0155] In practical applications, the cross-shaped basic graphic unit can increase the density of pin arrangement, save packaging area, and effectively reduce electromagnetic crosstalk between pins, thereby supporting higher DDR operating rates.

[0156] It should be noted that, in a specific implementation, the above-mentioned signal pins may adopt different pin configurations and signal distribution methods, which may be determined based on the type and specifications of the CPU chip and DDR chip, as well as the control mechanism of the corresponding memory controller. This is not limited in the embodiments of the present application.

[0157] Please refer to Figure 17, which is a pin configuration diagram for another CPU application scenario provided by an embodiment of the present application. As shown in Figure 17, the pin arrangement combination unit formed by two basic graphic units P can support the mixing of DQ signals of different Nibbles / Bytes. Among them, the four data signal pins corresponding to Nibble0 are DQ0, DQ1, DQ2, and DQ3, and the four data signal pins corresponding to Nibble1 are DQ4, DQ5, DQ6, and DQ7, among which DQ0, DQ1, and DQ2 of Nibble0 and DQ4 of Nibble1 are configured in one basic graphic unit P, and DQ3 of Nibble0 and DQ5, DQ6, and DQ7 of Nibble1 are configured in another basic graphic unit P.

[0158] In addition, based on the chip 20 using a cross-shaped arrangement of basic graphic units described in the above embodiment, the embodiment of the present application also provides a signal transmission method applied to the chip, wherein the pin area of ​​the packaging substrate 4 of the chip 20 is provided with a plurality of pin arrangement graphic units; at least two of the plurality of pin arrangement graphic units are basic graphic units P, and the basic graphic unit P includes six signal pins 11; wherein the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the six signal pins 11 are arranged in sequence in a first direction X, and the fifth pin 115 and the sixth pin 116 of the six signal pins 11 are arranged in a second direction Y; the fifth pin 115 and the sixth pin 116 are respectively located on both sides of the connection line between the second pin 112 and the third pin 113; wherein the first pin 111, the fourth pin 114, The fifth pin 115 and the sixth pin 116 are data signal pins, and the second pin 112 and the third pin 113 are control signal pins. The first direction X is different from the second direction Y. In a specific implementation, the chip can be a CPU chip as described above, or other chips or connectors based on a DDR interface, which is not limited in this embodiment of the present application.

[0159] The signal transmission method includes the following steps: transmitting data signals via the first pin 111, the fourth pin 1114, the fifth pin 115, and the sixth pin 116; and transmitting control signals via the second pin 112 and the third pin 113. Based on the aforementioned cross-shaped arrangement of basic graphic units P, the chip ensures correct signal transmission through excellent anti-crosstalk performance, providing technical support for high-performance and reliable system applications.

[0160] The embodiment of the present application also provides an electronic device, please refer to Figure 18, which is a schematic diagram of the architecture of the electronic device provided in the embodiment of the present application. The electronic device 100a includes a housing 40a and a circuit board 10a and a CPU 20a arranged in the housing 40a. The CPU 20a is arranged on the circuit board 10a. The pin area on the package substrate of the CPU 20a may include the basic graphic unit P as described in Figures 2, 3 and 4 above, or may include the pin arrangement combination unit described in Figures 5 to 10. Based on the cross-shaped basic graphic unit provided in this embodiment, the arrangement of its pins can increase the density of the pin arrangement, save packaging area, and can reduce DDR memory signal crosstalk, thereby improving the computing performance of the computing device.

[0161] It should be understood that other functional components of the computing device are not the core invention of this application, so they will not be described in detail in this article.

[0162] The cross-shaped pin arrangement graphic unit provided in this embodiment is an important technical means of chip packaging technology and has broad application prospects. It will play an increasingly important role in different electronic devices, such as but not limited to servers, supercomputers, Ethernet switches and other computing devices, and can also be used in terminal devices such as automobiles, mobile phones, and laptops.

[0163] The ordinal numbers "first" and "second" used herein are only used to describe components or structures with the same function in the technical solution. It is understood that the use of the ordinal numbers "first" and "second" does not constitute an understanding of the technical solution claimed in this application.

[0164] The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip, characterized in that: It comprises a core particle and a packaging substrate, wherein the core particle is arranged on the packaging substrate, and a plurality of pin arrangement graphic units are arranged in a pin area of ​​the packaging substrate; Among the plurality of pin arrangement graphic units, at least two pin arrangement graphic units are basic graphic units including six signal pins; Among them, the first pin, the second pin, the third pin and the fourth pin of the six signal pins are arranged in sequence in the first direction, and the fifth pin and the sixth pin of the six signal pins are arranged in the second direction, and the fifth pin and the sixth pin are respectively located on both sides of the connection line between the second pin and the third pin; The first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, the second pin and the third pin are control signal pins; and the first direction is different from the second direction.

2. The chip according to claim 1, characterized in that: The fifth pin and the sixth pin are arranged on a perpendicular line of a line connecting the second pin and the third pin, and the first direction is perpendicular to the second direction.

3. The chip according to claim 2, characterized in that: The fifth pin and the sixth pin are arranged on the perpendicular midline of the line connecting the second pin and the third pin.

4. The chip according to any one of claims 1 to 3, characterized in that: The basic graphic unit is a centrally symmetrical structure or an axially symmetrical structure.

5. The chip according to any one of claims 1 to 4, characterized in that: The pins in the pin area are arranged in an array, and the pins between rows and columns are staggered.

6. The chip according to any one of claims 1 to 5, characterized in that: The pins in the pin area are arranged in a triangular grid, wherein a line connecting the pin and two adjacent pins forms an equilateral triangle.

7. The chip according to any one of claims 1 to 6, characterized in that: The basic graphic unit further includes a ground pin, and the ground pin is arranged around the six signal pins.

8. The chip according to claim 7, characterized in that: The basic graphic unit has fourteen ground pins, and the fourteen ground pins are sequentially arranged at intervals around the six signal pins; in a first direction, the first ground pin is located beside the first pin, the eighth ground pin is located beside the fourth pin, and the second ground pin, the third ground pin, the fourth ground pin, the fifth ground pin, the sixth ground pin and the seventh ground pin are sequentially arranged between the first ground pin and the eighth ground pin; A ninth ground pin, a tenth ground pin, an eleventh ground pin, a twelfth ground pin, a thirteenth ground pin and a fourteenth ground pin are sequentially arranged between the eighth ground pin and the first ground pin.

9. The chip according to claim 8, characterized in that: The two basic graphic units are arranged adjacent to each other, one is a first basic graphic unit, and the other is a second basic graphic unit, and adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin.

10. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the eighth ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins.

11. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the eleventh ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

12. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the seventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourteenth ground pin of the second basic graphic unit are common ground pins.

13. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the eleventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the ninth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

14. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the eleventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the ninth ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins.

15. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, the fifth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are a common ground pin, the sixth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are a common ground pin, the seventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are a common ground pin, and the eighth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are a common ground pin.

16. The chip according to any one of claims 8 to 15, characterized in that: In the basic graphic unit, the data signal pin adjacent to two adjacent ground pins and a line connecting the two adjacent ground pins form an equilateral triangle.

17. The chip according to any one of claims 1 to 16, characterized in that: The first pin, the fourth pin, the fifth pin and the sixth pin are single-ended signal pins, and the second pin and the third pin are a pair of differential signal pins.

18. The chip according to any one of claims 1 to 17, characterized in that: The chip is a central processing unit, which is configured with multiple memory channels. The memory channels include multiple byte units, each of which corresponds to two basic graphic units. The data signal pins in the basic graphic units are used to transmit data signals corresponding to the byte units.

19. An electronic device, characterized in that: It comprises a shell and a circuit board arranged in the shell, wherein a chip is arranged on the circuit board, and the chip is the chip according to claim 1 or 18, and a signal pin of the chip is electrically connected to the circuit board.

20. A chip manufacturing method, characterized in that: The chip manufacturing method comprises: placing a core particle on a packaging substrate, and assembling the core particle and the packaging substrate to form the chip; wherein a pin area of ​​the packaging substrate is provided with a plurality of pin arrangement graphic units; Among the plurality of pin arrangement graphic units, at least two pin arrangement graphic units are basic graphic units including six signal pins; Among them, the first pin, the second pin, the third pin and the fourth pin of the six signal pins are arranged in sequence in the first direction, and the fifth pin and the sixth pin of the six signal pins are arranged in the second direction, and the fifth pin and the sixth pin are respectively located on both sides of the connection line between the second pin and the third pin; The first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, the second pin and the third pin are control signal pins; and the first direction is different from the second direction.

21. The chip manufacturing method according to claim 20, characterized in that: The fifth pin and the sixth pin are arranged on a perpendicular line of a line connecting the second pin and the third pin, and the first direction is perpendicular to the second direction.

22. The chip manufacturing method according to claim 21, characterized in that: The fifth pin and the sixth pin are arranged on the perpendicular midline of the line connecting the second pin and the third pin, and the basic graphic unit is a central symmetrical structure or an axisymmetric structure.

23. The chip manufacturing method according to any one of claims 20 to 22, characterized in that: The pins in the pin area are arranged in an array, and the pins between rows and columns are staggered; the pins in the pin area are arranged in a triangular grid, wherein the line connecting the pin and two adjacent pins forms an equilateral triangle.

24. The chip manufacturing method according to any one of claims 20 to 23, characterized in that: The basic graphic unit further includes a ground pin, the ground pins are fourteen in number, and the fourteen ground pins are sequentially arranged at intervals around the six signal pins; In the first direction, the first ground pin is located beside the first ground pin, the eighth ground pin is located beside the fourth ground pin, and the second ground pin, the third ground pin, the fourth ground pin, the fifth ground pin, the sixth ground pin and the seventh ground pin are sequentially arranged between the first ground pin and the eighth ground pin; A ninth ground pin, a tenth ground pin, an eleventh ground pin, a twelfth ground pin, a thirteenth ground pin and a fourteenth ground pin are sequentially arranged between the eighth ground pin and the first ground pin.

25. The chip manufacturing method according to claim 24, characterized in that: The two basic graphic units are arranged adjacent to each other, one is a first basic graphic unit, and the other is a second basic graphic unit, and adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin.

26. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the eighth ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins.

27. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the eleventh ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

28. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the seventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourteenth ground pin of the second basic graphic unit are common ground pins.

29. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the eleventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the ninth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

30. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the eleventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the ninth ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins.

31. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, the fifth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are a common ground pin, the sixth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are a common ground pin, the seventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are a common ground pin, and the eighth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are a common ground pin.

32. A signal transmission method, characterized in that: The signal transmission method is applied to a chip, the chip includes a packaging substrate, a pin area of ​​the packaging substrate is provided with a plurality of pin arrangement graphic units; among the plurality of pin arrangement graphic units, at least two pin arrangement graphic units are basic graphic units including six signal pins; wherein the first pin, the second pin, the third pin and the fourth pin of the six signal pins are sequentially arranged at intervals in a first direction, and the fifth pin and the sixth pin of the six signal pins are arranged at intervals in a second direction; the fifth pin and the sixth pin are respectively located on both sides of a line connecting the second pin and the third pin; wherein the first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins; the first direction is different from the second direction; the method comprises the following steps: A data signal is transmitted through the first pin, the fourth pin, the fifth pin and the sixth pin, and a control signal is transmitted through the second pin and the third pin.

33. The signal transmission method according to claim 32, characterized in that: The fifth pin and the sixth pin are arranged on a perpendicular line of a line connecting the second pin and the third pin, and the first direction is perpendicular to the second direction.

34. The signal transmission method according to claim 33, characterized in that: The fifth pin and the sixth pin are arranged on the perpendicular midline of the line connecting the second pin and the third pin, and the basic graphic unit is a central symmetrical structure or an axisymmetric structure.

35. The signal transmission method according to any one of claims 32 to 34, characterized in that: The pins in the pin area are arranged in an array, and the pins between rows and columns are staggered; the pins in the pin area are arranged in a triangular grid, wherein the line connecting the pin and two adjacent pins forms an equilateral triangle.

36. The signal transmission method according to any one of claims 32 to 35, characterized in that: The basic graphic unit further includes a ground pin, the ground pins are fourteen in number, and the fourteen ground pins are sequentially arranged at intervals around the six signal pins; In the first direction, the first ground pin is located beside the first ground pin, the eighth ground pin is located beside the fourth ground pin, and the second ground pin, the third ground pin, the fourth ground pin, the fifth ground pin, the sixth ground pin and the seventh ground pin are sequentially arranged between the first ground pin and the eighth ground pin; A ninth ground pin, a tenth ground pin, an eleventh ground pin, a twelfth ground pin, a thirteenth ground pin and a fourteenth ground pin are sequentially arranged between the eighth ground pin and the first ground pin.

37. The signal transmission method according to claim 36, characterized in that: The two basic graphic units are arranged adjacent to each other, one is a first basic graphic unit, and the other is a second basic graphic unit, and adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin.

38. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the eighth ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins.

39. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the eleventh ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

40. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the seventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourteenth ground pin of the second basic graphic unit are common ground pins.

41. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the eleventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the ninth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

42. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the eleventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the ninth ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins.

43. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, the fifth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are a common ground pin, the sixth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are a common ground pin, the seventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are a common ground pin, and the eighth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are a common ground pin.

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